Driving substrate and display device

Abstract

The present application relates to a driving substrate and a display device; the driving substrate includes a plurality of pixel areas and a plurality of pixel driving circuits arranged corresponding to the plurality of pixel areas, the pixel driving circuit includes a switching transistor and a driving transistor connected to each other; wherein the switching transistor includes a switching active part, the driving transistor includes a driving active part, the material of the switching active part and the material of the driving active part are different, the switching active part and the driving active part are arranged in different layers, and the switching active part and the driving active part partially overlap along the thickness direction of the driving substrate; the present application can increase wiring space to increase the number of thin film transistors, which is beneficial to improving the performance and resolution of the driving substrate.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving substrate and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) display panels have the advantage of being able to be made into flexible devices and can be used in wearable devices such as smart bracelets, smart watches, virtual reality (VR) devices, mobile phones, e-books and e-newspapers, televisions, personal laptops and other fields.

[0003] Similar to VR devices, more devices (such as thin-film transistors) are needed to improve device performance or resolution; however, due to its small size and the limitations of photolithography process conditions, the number of devices in the display panel is difficult to increase. Summary of the Invention

[0004] Embodiments of the present application provide a driving substrate and a display device, which can increase wiring space in the driving substrate and increase the number of components in the driving substrate.

[0005] An embodiment of the present application provides a driving substrate, the driving substrate comprising a plurality of pixel areas and a plurality of pixel driving circuits arranged corresponding to the plurality of pixel areas, the pixel driving circuit comprising a switching transistor and a driving transistor connected to each other;

[0006] Among them, the switching transistor includes a switching active part, the driving transistor includes a driving active part, the material of the switching active part and the material of the driving active part are different, the switching active part and the driving active part are arranged in different layers, and the switching active part and the driving active part partially overlap along the thickness direction of the driving substrate.

[0007] In one embodiment of the present application, the plurality of pixel regions are arranged along a first direction and a second direction, and the first direction and the second direction intersect;

[0008] The driving substrate includes:

[0009] substrate;

[0010] A first semiconductor layer is provided on the substrate and includes the driving active portion;

[0011] a second semiconductor layer, disposed on a side of the first semiconductor layer away from the substrate, and including the switch active portion, wherein the material of the second semiconductor layer is different from that of the first semiconductor layer;

[0012] The switch active portion extends along the second direction, a portion of the driving active portion extends along the second direction, and the driving active portion extending along the second direction partially overlaps with the switch active portion along the thickness direction of the driving substrate.

[0013] In one embodiment of the present application, the pixel driving circuit further includes a first reset transistor connected to the driving transistor and a second reset transistor connected to the switching transistor;

[0014] The first semiconductor layer further includes a first reset active portion of the first reset transistor, the first reset active portion extending along the second direction and connected to the driving active portion;

[0015] The second semiconductor layer further includes a second reset active portion of the second reset transistor, the second reset active portion extending along the second direction and connected to the switch active portion.

[0016] In one embodiment of the present application, the driving substrate further includes:

[0017] a first gate layer, disposed between the first semiconductor layer and the second semiconductor layer, the first gate layer comprising a driving gate of the driving transistor and a first control signal line extending along the first direction;

[0018] The driving gate partially overlaps with the driving active portion along the thickness direction of the driving substrate, the switch active portion is connected to the driving gate, and the first control signal line overlaps with the first reset active portion along the thickness direction of the driving substrate.

[0019] In one embodiment of the present application, the driving substrate further includes:

[0020] a first metal layer, disposed between the first gate layer and the second semiconductor layer, the first metal layer comprising a power signal line and a first reset signal line extending along the first direction;

[0021] The power signal line is connected to a side of the driving active portion away from the first reset active portion, and the first reset signal line is connected to a side of the first reset active portion away from the driving active portion.

[0022] In one embodiment of the present application, the first semiconductor layers corresponding to the two adjacent pixel driving circuits along the second direction are arranged axially symmetrically, and the first reset active portion in one of the pixel driving circuits is connected to the first reset active portion in the other pixel driving circuit, and is connected to the same first reset signal line.

[0023] In one embodiment of the present application, the first metal layer further includes a capacitor plate, the capacitor plate partially overlaps with the driving gate along the thickness direction of the driving substrate, and the capacitor plate is connected to the driving active portion.

[0024] In one embodiment of the present application, the second semiconductor layer further includes a first adapter wire, and the first adapter wire is connected to the capacitor plate;

[0025] The driving substrate further includes:

[0026] a second metal layer, disposed on a side of the second semiconductor layer away from the first metal layer, the second metal layer comprising a second transfer line and a plurality of data lines arranged along the first direction;

[0027] The data line extends along the second direction, the data line is connected to the active portion of the switch, and the second adapter line is connected to the first adapter line.

[0028] In one embodiment of the present application, the driving substrate further includes:

[0029] a third metal layer, disposed on a side of the second metal layer away from the second semiconductor layer, the third metal layer comprising a third transfer line and a second reset signal line extending along the first direction;

[0030] The second metal layer further includes a signal transmission portion connected between the second reset signal line and the second reset active portion, and the third adapter line is connected to the second adapter line.

[0031] In one embodiment of the present application, the driving substrate further includes:

[0032] An anode layer is provided on a side of the third metal layer away from the second metal layer. The anode layer includes a plurality of anodes provided corresponding to the plurality of pixel areas. The anodes are connected to the third transfer line.

[0033] In one embodiment of the present application, the second semiconductor layers corresponding to two adjacent pixel driving circuits along the second direction are arranged axially symmetrically, and the second reset active portion in one pixel driving circuit is connected to the second reset active portion in the other pixel driving circuit;

[0034] Two second reset signal lines are arranged at the connection between two adjacent pixel driving circuits along the second direction, and the first end and the second end of the signal transmission part relatively arranged along the second direction are respectively connected to the two reset signal lines, and the part of the signal transmission part located between the first end and the second end is connected to the two second reset active parts.

[0035] In one embodiment of the present application, the orthographic projection of the capacitor plate on the substrate partially overlaps with the orthographic projection of the switch active part on the substrate, and the orthographic projection of the capacitor plate on the substrate partially overlaps with the orthographic projection of the second reset active part on the substrate.

[0036] In one embodiment of the present application, the driving substrate further includes:

[0037] a second gate layer, disposed on a side of the second semiconductor layer away from the first semiconductor layer, the second gate layer comprising a second control signal line extending along the first direction and a third control signal line extending along the first direction;

[0038] The second control signal line overlaps with the switch active portion along the thickness direction of the drive substrate, and the third control signal line overlaps with the second reset active portion along the thickness direction of the drive substrate.

[0039] In an embodiment of the present application, two adjacent pixel driving circuits along the second direction are arranged axially symmetrically.

[0040] In an embodiment of the present application, patterns of two adjacent pixel driving circuits along the first direction are the same.

[0041] In one embodiment of the present application, the material of the driving active part includes a polysilicon material, and the material of the switching active part includes a metal oxide material.

[0042] According to the above-mentioned purpose of the present application, an embodiment of the present application further provides a display device, which includes the driving substrate.

[0043] The present application provides a driving substrate and a display device. By arranging the driving active part of the driving transistor and the switching active part of the switching transistor in different layers, the space in the film layer can be increased to arrange a larger number of devices and wirings; in addition, the driving active part and the switching active part partially overlap along the thickness direction of the driving substrate, which can further increase the wiring space to increase the number of thin film transistors, which is beneficial to improving the performance and resolution of the driving substrate.

[0044] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0046] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same drawing numbers represent the same parts in the following description.

[0047] Figure 1 is a structural diagram of a pixel driving circuit of a display panel in an embodiment;

[0048] Figure 2 A schematic structural diagram of a drive substrate provided in an embodiment of the present application;

[0049] Figure 3 A structural diagram of a pixel driving circuit of a driving substrate provided in an embodiment of the present application;

[0050] Figure 4 A circuit diagram of a pixel driving circuit of a driving substrate provided in an embodiment of the present application;

[0051] Figure 5 A structural diagram of a portion of a pixel driving circuit of a driving substrate provided in an embodiment of the present application;

[0052] Figure 6 A structural diagram of another part of the pixel driving circuit of the driving substrate provided in an embodiment of the present application;

[0053] Figure 7 Provided in the embodiments of this application Figure 5 A circuit diagram corresponding to a portion of a pixel driving circuit;

[0054] Figure 8 Provided in the embodiments of this application Figure 6 A circuit diagram corresponding to another part of the pixel driving circuit;

[0055] Figure 9 A schematic structural diagram of the first semiconductor layer of the driving substrate provided in an embodiment of the present application;

[0056] Figure 10 A schematic structural diagram of a first gate layer of a driving substrate provided in an embodiment of the present application;

[0057] Figure 11 A schematic structural diagram of the first metal layer of the driving substrate provided in an embodiment of the present application;

[0058] Figure 12 A schematic structural diagram of a light shielding layer of a driving substrate provided in an embodiment of the present application;

[0059] Figure 13 A schematic structural diagram of the second semiconductor layer of the driving substrate provided in an embodiment of the present application;

[0060] Figure 14 A schematic structural diagram of the second gate layer of the driving substrate provided in an embodiment of the present application;

[0061] Figure 15 A schematic structural diagram of the second metal layer of the drive substrate provided in an embodiment of the present application;

[0062] Figure 16 A schematic structural diagram of the third metal layer of the driving substrate provided in an embodiment of the present application;

[0063] Figure 17 A schematic structural diagram of the anode layer of the driving substrate provided in an embodiment of the present application.

[0064] Description of reference numerals:

[0065] 10. Substrate; 101. Pixel area; 1101. Pixel driving circuit; 11. First connection point; 12. Second connection point; 13. Third connection point; 14. Fourth connection point; 15. Fifth connection point;

[0066] 21. First semiconductor layer; 211. Driving active portion; 212. First reset active portion; 22. Second semiconductor layer; 221. Switch active portion; 222. Second reset active portion; 223. First adapter wire;

[0067] 31, first gate layer; 311, driving gate; 312, first control signal line; 32, second gate layer; 321, second control signal line; 322, third control signal line;

[0068] 41. First metal layer; 411. Power signal line; 412. First reset signal line; 413. Capacitor plate; 414. Fourth adapter line; 42. Second metal layer; 421. Data line; 422. Second adapter line; 423. Signal transmission unit; 4231. First end; 4232. Second end; 43. Third metal layer; 431. Second reset signal line; 432. Third adapter line;

[0069] 51, light shielding layer; 511, first light shielding portion; 512, second light shielding portion; 52, anode layer; 521, anode;

[0070] 61. Buffer layer; 62. First gate insulating layer; 63. First insulating layer; 64. Second insulating layer; 65. Third insulating layer; 66. Second gate insulating layer; 67. Fourth insulating layer; 68. First planarizing layer;

[0071] 69. Second flat layer;

[0072] 70. Pixel definition layer. DETAILED DESCRIPTION

[0073] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0074] Please refer to Figure 1 , is a structural diagram of a pixel driving circuit of a display panel, which includes a first transistor T01, a second transistor T02, a third transistor T03, and a fourth transistor T04. The active layers of the first transistor T01, the second transistor T02, the third transistor T03, and the fourth transistor T04 are all located on the same layer, resulting in insufficient wiring space. This in turn limits the number of transistors in the pixel driving circuit, which is not conducive to improving the performance and resolution of the display panel.

[0075] Please combine Figure 2 、 Figure 3 as well as Figure 4 An embodiment of the present application provides a driving substrate, which includes a plurality of pixel areas 101 and a plurality of pixel driving circuits 1101 corresponding to the plurality of pixel areas 101. The pixel driving circuit 1101 includes a switching transistor T2 and a driving transistor T1 connected to each other.

[0076] Among them, the switching transistor T2 includes a switching active portion 221, and the driving transistor T1 includes a driving active portion 211. The material of the switching active portion 221 is different from the material of the driving active portion 211. The switching active portion 221 and the driving active portion 211 are arranged in different layers, and the switching active portion 221 and the driving active portion 211 partially overlap along the thickness direction of the driving substrate.

[0077] During the implementation and application process, the embodiment of the present application arranges the driving active portion 211 of the driving transistor T1 and the switching active portion 221 of the switching transistor T2 in different layers, thereby increasing the space in the film layer to arrange a larger number of devices and wirings; in addition, the driving active portion 211 and the switching active portion 221 partially overlap along the thickness direction of the driving substrate, thereby further increasing the wiring space to increase the number of thin film transistors, which is beneficial to improving the performance and resolution of the driving substrate.

[0078] Specifically, please combine Figure 2 、 Figure 3 as well as Figure 4 The driving substrate includes a display area and a non-display area adjacent to the display area, and the display area of ​​the driving substrate may include a plurality of pixel areas 101, and the plurality of pixel areas 101 may be arranged in an array along a first direction X and a second direction Y.

[0079] In some embodiments, the first direction X and the second direction Y are perpendicular to each other.

[0080] In some embodiments, the driving substrate further includes a plurality of pixel driving circuits 1101 arranged corresponding to the plurality of pixel regions 101 . For example, the plurality of pixel driving circuits 1101 are arranged in a one-to-one correspondence within the plurality of pixel regions 101 .

[0081] In some embodiments, the driving substrate also includes a substrate 10 and a device layer arranged on the substrate 10, and the devices and wirings in the pixel driving circuit 1101 can be arranged in the device layer; the pixel driving circuit 1101 can include multiple thin film transistors and wirings arranged in the device layer.

[0082] Furthermore, please combine Figures 2 to 17The device layer includes a buffer layer 61 disposed on the substrate 10, a first semiconductor layer 21 disposed on the buffer layer 61, a first gate insulating layer 62 disposed on the first semiconductor layer 21, a first gate layer 31 disposed on the first gate insulating layer 62, a first insulating layer 63 disposed on the first gate layer 31, a first metal layer 41 disposed on the first insulating layer 63, a second insulating layer 64 disposed on the first metal layer 41, a light shielding layer 51 disposed on the second insulating layer 64, a third insulating layer 65 disposed on the light shielding layer 51, and a first insulating layer 66 disposed on the third insulating layer 67. 5, a second semiconductor layer 22 disposed on the second semiconductor layer 22, a second gate insulating layer 66 disposed on the second gate insulating layer 66, a fourth insulating layer 67 disposed on the second gate layer 32, a second metal layer 42 disposed on the fourth insulating layer 67, a first planarizing layer 68 disposed on the second metal layer 42, a third metal layer 43 disposed on the first planarizing layer 68, a second planarizing layer 69 disposed on the third metal layer 43, an anode layer 52 disposed on the second planarizing layer 69, and a pixel definition layer 70 disposed on the anode layer 52.

[0083] In some embodiments, the pixel driving circuit 1101 includes a driving transistor T1 , a switch transistor T2 , a first reset transistor T3 , a second reset transistor T4 , and a storage capacitor Cst.

[0084] In which, the first semiconductor layer 21 includes the driving active part 211 of the driving transistor T1 and the first reset active part 212 of the first reset transistor T3, the first gate layer 31 includes the driving gate 311 of the driving transistor T1 and the first control signal line 312; the first metal layer 41 includes the power signal line 411, the first reset signal line 412 and the capacitor plate 413; the second semiconductor layer 22 includes the switching active part 221 of the switching transistor T2 and the second reset active part 222 of the second reset transistor T4; the second gate layer 32 includes the second control signal line 321 and the third control signal line 322; the second metal layer 42 includes the data line 421; the third metal layer 43 includes the second reset signal line 431; and the anode layer 52 includes the anode 521.

[0085] The driving gate 311 of the driving transistor T1 is connected to the first node A, the source of the driving transistor T1 is connected to the power signal line 411 , the drain of the driving transistor T1 is connected to the second node B, and the power signal VDD is inputted from the power signal line 411 .

[0086] The gate of the switching transistor T2 is connected to the second control signal line 321 and receives the second control signal Gn. The source of the switching transistor T2 is connected to the data line 421. The drain of the switching transistor T2 is connected to the first node A and receives the data signal Vdata from the data line 421.

[0087] The gate of the first reset transistor T3 is connected to the first control signal line 312 and is connected to the first control signal INI. The source of the first reset transistor T3 is connected to the first reset signal line 412. The drain of the first reset transistor T3 is connected to the second node B and is input with the first reset signal Vini by the first reset signal line 412.

[0088] The gate of the second reset transistor T4 is connected to the third control signal line 322 and receives the third control signal REF. The source of the second reset transistor T4 is connected to the second reset signal line 431. The drain of the second reset transistor T4 is the second node B, and the second reset signal Vref is output by the second reset signal line 431.

[0089] The storage capacitor Cst is formed by the driving gate 311 and the capacitor plate 413 , wherein the driving gate 311 is connected to the first node A, and the capacitor plate 413 is connected to the second node B.

[0090] Furthermore, the following Figure 2 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 as well as Figure 8 The connection structure of each film layer to the pixel driving circuit 1101 is described in detail.

[0091] Further integration Figure 9 The first semiconductor layer 21 is arranged on the side of the buffer layer 61 away from the substrate 10. The first semiconductor layer 21 includes the driving active portion 211 and the first reset active portion 212. The driving active portion 211 extends in a broken line, that is, part of the driving active portion 211 extends along the first direction X, and part of the driving active portion 211 extends along the second direction Y; the first reset active portion 212 extends along the second direction Y and is connected to the driving active portion 211.

[0092] In which, the first semiconductor layer 21 corresponding to the two adjacent pixel driving circuits 1101 along the second direction Y is arranged axially symmetrically, and the first reset active part 212 in one of the pixel driving circuits 1101 is connected to the first reset active part 212 in the other pixel driving circuit 1101, and the driving active part 211 in one of the pixel driving circuits 1101 is located on the side of the first reset active part 212 away from the other pixel driving circuit 1101.

[0093] Further integration Figure 10 The first gate layer 31 is disposed on a side of the first semiconductor layer 21 away from the buffer layer 61 , and the first gate layer 31 includes the driving gate 311 and the first control signal line 312 .

[0094] The orthographic projection of the driving active portion 211 on the substrate 10 partially overlaps with the orthographic projection of the driving gate 311 on the substrate 10, and the portion of the driving active portion 211 overlapping with the driving gate 311 is the channel of the driving active portion 211. The first control signal line 312 extends along the first direction X, and the first control signal line 312 overlaps with the first reset active portion 212 along the thickness direction of the driving substrate. The portion of the first reset active portion 212 overlapping with the first control signal line 312 is the channel of the first reset active portion 212, and the portion of the first control signal line 312 overlapping with the first reset active portion 212 is multiplexed as the gate of the first reset transistor T3.

[0095] Further integration Figure 11 The first metal layer 41 is arranged on the side of the first gate layer 31 away from the first semiconductor layer 21, and the first metal layer 41 includes the power signal line 411, the first reset signal line 412, the capacitor plate 413 and the fourth transfer line 414.

[0096] The power signal line 411 extends along the first direction X, the driving active portion 211 is connected to the power signal line 411 at the first connection point 11, and the portion of the driving active portion 211 connected to the power signal line 411 is reused as the source of the driving transistor T1 to input the power signal VDD; the driving active portion 211 is connected to the capacitor plate 413 at the second node B, and the portion of the driving active portion 211 connected to the capacitor plate 413 at the second node B is reused as the drain of the driving transistor T1. pole, and the capacitor plate 413 can be reused as a transfer line; the first reset signal line 412 extends along the first direction X, the first reset active part 212 is connected to the first reset signal line 412 at the second connection point 12, and the part of the first reset active part 212 connected to the first reset signal line 412 is reused as the source of the first reset transistor T3 to input the first reset signal Vini, and the part of the first reset active part 212 connected to the driving active part 211 is reused as the drain of the first reset transistor T3.

[0097] In some embodiments, the power signal line 411 is connected to a side of the driving active portion 211 away from the first reset active portion 212 , and the first reset signal line 412 is connected to a side of the first reset active portion 212 away from the driving active portion 211 .

[0098] In some embodiments, the first semiconductor layer 21 corresponding to the two adjacent pixel driving circuits 1101 along the second direction Y is axially symmetrically arranged, and the first reset active portion 212 in one of the pixel driving circuits 1101 is connected to the first reset active portion 212 in the other pixel driving circuit 1101, and is connected to the same first reset signal line 412, that is, the two adjacent pixel driving circuits 1101 along the second direction Y in the embodiment of the present application can share one first reset signal line 412, thereby increasing the wiring space, increasing the line spacing, and reducing the probability of short circuit in the wiring.

[0099] The fourth connecting line 414 is connected to the driving gate 311 at the first node A.

[0100] The capacitor plate 413 and the driving gate 311 partially overlap along the thickness direction of the driving substrate to form the storage capacitor Cst.

[0101] Further integration Figure 12The light-shielding layer 51 is arranged on a side of the first metal layer 41 away from the first gate layer 31, and the light-shielding layer 51 includes a first light-shielding portion 511 and a second light-shielding portion 512, and the first light-shielding portion 511 extends along the first direction X, and the second light-shielding portion 512 extends along the first direction X.

[0102] Further integration Figure 13 The second semiconductor layer 22 is arranged on a side of the light shielding layer 51 away from the first metal layer 41 , and the second semiconductor layer 22 includes the switch active portion 221 , the second reset active portion 222 and a first adapter line 223 .

[0103] In which, the switch active portion 221 extends along the second direction Y, the second reset active portion 222 extends along the second direction Y, and the switch active portion 221 is connected to the second reset active portion 222; the second semiconductor layer 22 corresponding to the two adjacent pixel driving circuits 1101 along the second direction Y is arranged in an axially symmetrical manner, the second reset active portion 222 in one of the pixel driving circuits 1101 is connected to the second reset active portion 222 in the other pixel driving circuit 1101, and the switch active portion 221 in one of the pixel driving circuits 1101 is located on the side of the second reset active portion 222 away from the other pixel driving circuit 1101.

[0104] The switch active portion 221 is connected to the fourth transfer line 414 at the first node A, and then the switch active portion 221 is connected to the driving gate 311 through the fourth transfer line 414 at the first node A, and the part of the switch active portion 221 connected to the fourth transfer line 414 at the first node A is multiplexed as the drain of the switching transistor T2, and the part of the second reset active portion 222 connected to the switch active portion 221 is multiplexed as the drain of the second reset transistor T4.

[0105] In some embodiments, the orthographic projection of the portion of the driving active portion 211 extending along the second direction Y on the substrate 10 partially overlaps with the orthographic projection of the switching active portion 221 on the substrate 10 .

[0106] Furthermore, the orthographic projection of the first light-shielding portion 511 on the substrate 10 partially overlaps with the orthographic projection of the switch active portion 221 on the substrate 10, and the orthographic projection of the second light-shielding portion 512 on the substrate 10 partially overlaps with the orthographic projection of the second reset active portion 222 on the substrate 10; thus, the first light-shielding portion 511 and the second light-shielding portion 512 play the role of blocking light and shielding interference, thereby improving the electrical properties of the switch active portion 221 and the second reset active portion 222.

[0107] In some embodiments, a portion of the capacitor plate 413 extends along the first direction X, and another portion extends along the second direction Y; wherein, the orthographic projection of the portion of the capacitor plate 413 extending along the first direction X on the substrate 10 partially overlaps with the orthographic projection of the switch active portion 221 on the substrate 10, and the orthographic projection of the portion of the capacitor plate 413 extending along the first direction X on the substrate 10 partially overlaps with the orthographic projection of the second reset active portion 222 on the substrate 10, thereby the capacitor plate 413 can also play a role in blocking light and shielding interference, so as to further improve the electrical properties of the switch active portion 221 and the second reset active portion 222.

[0108] Further integration Figure 14 The second gate layer 32 is located on a side of the second semiconductor layer 22 away from the light shielding layer 51 , and the second gate layer 32 includes a second control signal line 321 and a third control signal line 322 .

[0109] The second control signal line 321 extends along the first direction X, and the second control signal line 321 overlaps with the switch active portion 221 along the thickness direction of the drive substrate. The portion of the second control signal line 321 that overlaps with the switch active portion 221 is reused as the gate of the switch transistor T2.

[0110] The third control signal line 322 extends along the first direction X, and the third control signal line 322 overlaps with the second reset active portion 222 along the thickness direction of the drive substrate. The portion of the third control signal line 322 that overlaps with the second reset active portion 222 is reused as the gate of the second reset transistor T4.

[0111] Further integration Figure 15 The second metal layer 42 is arranged on a side of the second gate layer 32 away from the second semiconductor layer 22 , and the second metal layer 42 includes a plurality of data lines 421 , a second transfer line 422 and a signal transmission part 423 .

[0112] A plurality of data lines 421 are arranged along the first direction X, and the data lines 421 extend along the second direction Y. The data lines 421 are connected to the switch active portion 221 at the third connection point 13 to input the data line signal Vdata. The portion of the switch active portion 221 connected to the data line 421 is multiplexed as the source of the switch transistor T2, or the portion of the data line 421 connected to the switch active portion 221 is multiplexed as the source of the switch transistor T2.

[0113] In some embodiments, the orthographic projection of the data line 421 on the substrate 10 partially overlaps with the orthographic projection of the switch active portion 221 on the substrate, and the orthographic projection of the data line 421 on the substrate 10 partially overlaps with the orthographic projection of the second reset active portion 222 on the substrate.

[0114] The second adapter line 422 is connected to the first adapter line 223 at the second node B, and the second adapter line 422 is connected to the driving active part 211 and the first reset active part 212 at the second node B through the first adapter line 223 and the capacitor plate 413.

[0115] The signal transmission portion 423 is connected between the second reset signal line 431 and the second reset active portion 222. The signal transmission portion 423 includes a first end 4231 and a second end 4232 that are relatively arranged along the second direction Y. Since the second semiconductor layers 22 corresponding to the two adjacent pixel driving circuits 1101 along the second direction Y are axially symmetrically arranged, and the second reset active portion 222 in one of the pixel driving circuits 1101 is connected to the second reset active portion 222 in the other pixel driving circuit 1101, the portion of the signal transmission portion 423 located between the first end 4231 and the second end 4232 is connected to the two connected second reset active portions 222 at the fourth connection point 14, for transmitting signals to the two second reset active portions 222, and the portion of the second reset active portion 222 connected to the signal transmission portion 423 is reused as the source of the second reset transistor T4.

[0116] Further integration Figure 16 The third metal layer 43 is disposed on a side of the second metal layer 42 away from the second gate layer 32 , and the third metal layer 43 includes the second reset signal line 431 and a third transfer line 432 .

[0117] In which, the second reset signal line 431 extends along the first direction X, and the second reset signal line 431 is connected to the first end 4231 and the second end 4232 of the signal transmission part 423 at the fifth connection point 15; then the second reset signal line 431 transmits the second reset signal Vref to the second reset active part 222 through the signal transmission part 423.

[0118] In some embodiments, two second reset signal lines 431 are provided at the connection between two adjacent pixel driving circuits 1101 along the second direction Y, and the first end 4231 and the second end 4232 of the signal transmission part 423 relatively arranged along the second direction Y are respectively connected to the two second reset signal lines 431, that is, the embodiment of the present application simultaneously sets two second reset signal lines 431 to transmit signals to the two second reset active parts 222, thereby enhancing the transmission stability of the second reset signal Vref, reducing the probability of the second reset signal Vref being interfered with, and improving the performance and display effect of the driving substrate.

[0119] The third adapter line 432 is connected to the second adapter line 422 at the second node B, and is connected to the driving active part 211 and the first reset active part 212 at the second node B through the second adapter line 422, the first adapter line 223 and the capacitor plate 413.

[0120] Further integration Figure 17 The anode layer 52 is arranged on the side of the third metal layer 43 away from the second metal layer 42, and the anode layer 52 includes a plurality of anodes 521 arranged corresponding to the plurality of pixel areas 101, and the plurality of anodes 521 can be arranged one by one in the plurality of pixel areas 101.

[0121] In which, the anode 521 is connected to the third adapter line 432 at the second node B, and then at the second node B, the anode 521 is connected to the driving active part 211 through the third adapter line 432, the second adapter line 422, the first adapter line 223 and the capacitor plate 413 to realize signal transmission between the driving transistor T1 and the anode 521.

[0122] It can be understood that in the embodiment of the present application, since the distance between the driving transistor T1 and the anode 521 is large, and thus the depth of the overlapping hole is large, the embodiment of the present application can use the same layer material of the second semiconductor layer 22 to form the first adapter line 223 to achieve signal transmission, and improve the connection between the anode 521 and the driving active part 211, improve the stability of signal transmission, and do not require additional adapter lines, which can save process steps and reduce process costs; for example, when forming the second semiconductor layer 22, the channel portion of the second semiconductor layer 22 forming the switching active part 221 and the channel portion of the second reset active part 222 can be kept as semiconductors, and the remaining portions can be conductorized, so that the first adapter line 223 is a conductor material and can be used for signal transmission.

[0123] In some embodiments, the plurality of pixel regions 101 may include a red pixel region, a green pixel region, and a blue pixel region. The embodiment of the present application may set the area of ​​the anode 521 located in different pixel regions 101 to different sizes according to the different luminous efficiencies of the pixel regions 101 of different colors; for example, the area of ​​the anode 521 in the red pixel region is larger than the area of ​​the anode 521 in the green pixel region, and the area of ​​the anode 521 in the green pixel region is equal to the area of ​​the anode 521 in the blue pixel region.

[0124] It should be noted that, in the embodiment of the present application, the material of the driving active portion 211 is different from the material of the switching active portion 221 , that is, the material of the second semiconductor layer 22 is different from the material of the first semiconductor layer 21 .

[0125] In some embodiments, the driving active portion 211 is made of a polysilicon material, and the switching active portion 221 is made of a metal oxide material, such as indium gallium zinc oxide (IGZO).

[0126] In some embodiments, two adjacent pixel driving circuits 1101 along the second direction Y are arranged in an axisymmetric manner.

[0127] In some embodiments, the patterns of two adjacent pixel driving circuits 1101 along the first direction X are the same.

[0128] It should be noted that the structural diagram of the pixel driving circuit 1101 provided in the embodiment of the present application shows the structures within 6 adjacent pixel areas 101, and the structures in the pixel driving circuit 1101 in the remaining pixel areas 101 in the driving substrate can be set with reference to the above embodiment.

[0129] In summary, the embodiment of the present application arranges the driving active portion 211 of the driving transistor T1 and the switching active portion 221 of the switching transistor T2 in different layers, thereby increasing the space in the film layer to arrange a larger number of devices and wirings; in addition, the driving active portion 211 and the switching active portion 221 partially overlap along the thickness direction of the driving substrate, thereby further increasing the wiring space to increase the number of thin film transistors, which is beneficial to improving the performance and resolution of the driving substrate.

[0130] In addition, an embodiment of the present application further provides a display device, which includes the driving substrate described in the above embodiment.

[0131] It can be understood that, since the display device has the same driving substrate as that in the above embodiment, the display device has the same beneficial effects as the driving substrate, which will not be described in detail.

[0132] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0133] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0134] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0135] The above are merely preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A driving substrate, characterized in that: The driving substrate includes a plurality of pixel areas and a plurality of pixel driving circuits provided corresponding to the plurality of pixel areas, the plurality of pixel areas are arranged along a first direction and a second direction, the first direction and the second direction intersecting, the pixel driving circuit includes a switching transistor, a driving transistor, a first reset transistor connected to the driving transistor, and a second reset transistor connected to the switching transistor; The switching transistor includes a switching active portion, and the driving transistor includes a driving active portion. The switching active portion and the driving active portion are made of different materials. The switching active portion and the driving active portion are arranged in different layers. The switching active portion and the driving active portion partially overlap along the thickness direction of the driving substrate. The driving substrate includes: substrate; a first semiconductor layer disposed on the substrate and comprising the driving active portion and a first reset active portion of the first reset transistor, wherein the first reset active portion extends along the second direction and is connected to the driving active portion; a second semiconductor layer, disposed on a side of the first semiconductor layer away from the substrate, and comprising the switch active portion and a second reset active portion of the second reset transistor, wherein the second reset active portion extends along the second direction and is connected to the switch active portion, and a material of the second semiconductor layer is different from that of the first semiconductor layer; The switch active portion extends along the second direction, a portion of the driving active portion extends along the second direction, and the driving active portion extending along the second direction partially overlaps with the switch active portion along the thickness direction of the driving substrate.

2. The driving substrate according to claim 1, wherein: The driving substrate further includes: a first gate layer, disposed between the first semiconductor layer and the second semiconductor layer, the first gate layer comprising a driving gate of the driving transistor and a first control signal line extending along the first direction; The driving gate partially overlaps with the driving active portion along the thickness direction of the driving substrate, the switch active portion is connected to the driving gate, and the first control signal line overlaps with the first reset active portion along the thickness direction of the driving substrate.

3. The driving substrate according to claim 2, wherein: The driving substrate further includes: a first metal layer, disposed between the first gate layer and the second semiconductor layer, the first metal layer comprising a power signal line and a first reset signal line extending along the first direction; The power signal line is connected to a side of the driving active portion away from the first reset active portion, and the first reset signal line is connected to a side of the first reset active portion away from the driving active portion.

4. The driving substrate according to claim 3, wherein: The first semiconductor layers corresponding to the two adjacent pixel driving circuits along the second direction are arranged axially symmetrically, wherein the first reset active portion in one pixel driving circuit is connected to the first reset active portion in the other pixel driving circuit and is connected to the same first reset signal line.

5. The driving substrate according to claim 3, wherein: The first metal layer further includes a capacitor plate, the capacitor plate partially overlaps with the driving gate along the thickness direction of the driving substrate, and the capacitor plate is connected to the driving active portion.

6. The driving substrate according to claim 5, wherein: The second semiconductor layer further includes a first adapter wire, and the first adapter wire is connected to the capacitor plate; The driving substrate further includes: a second metal layer, disposed on a side of the second semiconductor layer away from the first metal layer, the second metal layer comprising a second adapter line and a plurality of data lines arranged along the first direction; The data line extends along the second direction, the data line is connected to the active portion of the switch, and the second adapter line is connected to the first adapter line.

7. The driving substrate according to claim 6, wherein: The driving substrate further includes: a third metal layer, disposed on a side of the second metal layer away from the second semiconductor layer, the third metal layer comprising a third transfer line and a second reset signal line extending along the first direction; The second metal layer further includes a signal transmission portion connected between the second reset signal line and the second reset active portion, and the third adapter line is connected to the second adapter line.

8. The driving substrate according to claim 7, wherein: The driving substrate further includes: An anode layer is provided on a side of the third metal layer away from the second metal layer. The anode layer includes a plurality of anodes provided corresponding to the plurality of pixel areas. The anodes are connected to the third transfer line.

9. The driving substrate according to claim 7, wherein: The second semiconductor layers corresponding to two adjacent pixel driving circuits along the second direction are arranged axially symmetrically, and the second reset active portion in one pixel driving circuit is connected to the second reset active portion in the other pixel driving circuit; Two second reset signal lines are arranged at the connection between two adjacent pixel driving circuits along the second direction, and the first end and the second end of the signal transmission part relatively arranged along the second direction are respectively connected to the two reset signal lines, and the part of the signal transmission part located between the first end and the second end is connected to the two second reset active parts.

10. The driving substrate according to claim 5, wherein: The orthographic projection of the capacitor plate on the substrate partially overlaps with the orthographic projection of the switch active part on the substrate, and the orthographic projection of the capacitor plate on the substrate partially overlaps with the orthographic projection of the second reset active part on the substrate.

11. The driving substrate according to claim 1, wherein: The driving substrate further includes: a second gate layer, disposed on a side of the second semiconductor layer away from the first semiconductor layer, the second gate layer comprising a second control signal line extending along the first direction and a third control signal line extending along the first direction; The second control signal line overlaps with the switch active portion along the thickness direction of the drive substrate, and the third control signal line overlaps with the second reset active portion along the thickness direction of the drive substrate.

12. The driving substrate according to any one of claims 1 to 11, characterized in that: The two adjacent pixel driving circuits along the second direction are arranged axially symmetrically.

13. The driving substrate according to any one of claims 1 to 11, characterized in that: The patterns of two adjacent pixel driving circuits along the first direction are the same.

14. The driving substrate according to any one of claims 1 to 11, characterized in that: The driving active portion is made of a polysilicon material, and the switching active portion is made of a metal oxide material.

15. A display device, characterized in that: The display device includes the drive substrate according to any one of claims 1 to 14.

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