Display panel and display device

Abstract

The invention provides a display panel and a display device, relates to the technical field of display, and aims to improve the pixel density. Each sub-pixel on the display panel substrate includes a first transistor, a second transistor, a capacitor, and a third transistor stacked. The capacitor comprises a first pole plate and a second pole plate, the second pole plate is arranged on the side, away from the substrate, of the first pole plate, the first pole plate is electrically connected with the first transistor and the second transistor, and the second pole plate is electrically connected with the first transistor and the third transistor. On this basis, the arrangement of the first pole plate and the second pole plate does not need to avoid a connecting via hole between the second transistor and the first transistor, the area can be fully utilized, and under the condition that the capacitance value of the capacitor meets the display requirement, the structure arrangement in the sub-pixel can be more compact, so that the area occupied by the pixel circuit on the substrate is reduced, and the display effect is improved. Therefore, the pixel density is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In recent years, with the diversification of VR application fields, the demand for VR products has grown rapidly. In VR products, the display panel is one of its core hardware. VR products require more pixel viewpoints to restore real scenes, and the pixel density requirements are getting higher and higher.

[0003] Since there are many thin-film transistor switches in organic light-emitting diode display panels, it has always been difficult to increase the pixel density. How to improve its pixel density is a key research direction in this field. Summary of the invention

[0004] The present application proposes a display panel, aiming to improve pixel density.

[0005] The display panel includes a substrate and a plurality of sub-pixels arranged on the substrate. The sub-pixels include a first stacking structure, a second stacking structure, a third stacking structure and a fourth stacking structure, wherein the first stacking structure includes a first transistor, the second stacking structure includes a second transistor, the third stacking structure includes a capacitor, and the fourth stacking structure includes a third transistor.

[0006] The capacitor includes a first plate and a second plate, the second plate is arranged on a side of the first plate away from the substrate, the first plate is electrically connected to the first transistor and the second transistor, and the second plate is electrically connected to the first transistor and the third transistor.

[0007] In some embodiments, the first stacked structure includes a stacked first active layer, a first gate insulating layer, a first gate conductive layer and a first buffer layer, the active layer of the first transistor is located in the first active layer, and the gate of the first transistor is located in the first gate conductive layer.

[0008] The second stacking structure is arranged on a side of the first buffer layer away from the substrate, and the second stacking structure includes a stacked second active layer, a second gate insulating layer, a second gate conductive layer and a third gate insulating layer. The active layer of the second transistor is located in the second active layer, and the gate of the second transistor is located in the second gate conductive layer.

[0009] The first electrode plate is arranged on a side of the third gate insulating layer away from the substrate, and a through first via hole is arranged in the third gate insulating layer, the second gate insulating layer and the first buffer layer. The first via hole exposes the gate of the first transistor and the active layer of the second transistor, and the first electrode plate is electrically connected to the gate of the first transistor and the active layer of the second transistor through the first via hole.

[0010] In some embodiments, a material of the active layer of the second transistor includes oxide, a material of the first buffer layer includes silicon oxide, and a material of the second gate insulating layer includes silicon oxide.

[0011] In some embodiments, the third stacking structure is arranged on a side of the third gate insulating layer away from the substrate, and the third stacking structure includes a stacked first contact layer, a fourth gate insulating layer and a third gate conductive layer, the first plate of the capacitor is located in the first contact layer, and the second plate of the capacitor is located in the third gate conductive layer.

[0012] The fourth stacking structure is arranged on the side of the third gate conductive layer away from the substrate, and the fourth stacking structure includes a stacked fifth gate insulating layer, a fourth gate conductive layer, a sixth gate insulating layer, a third active layer and a first source-drain conductive layer, the active layer of the third transistor is located in the third active layer, the gate of the third transistor is located in the fourth gate conductive layer, and the source and drain of the third transistor are located in the first source-drain conductive layer.

[0013] A second through hole is provided in the sixth gate insulating layer and the fifth gate insulating layer, the second through hole exposes the second electrode plate, and the drain of the third transistor is electrically connected to the second electrode plate through the second through hole.

[0014] In some embodiments, the subpixel also includes a first passivation layer disposed on a side of the first source-drain conductive layer away from the substrate, the material of the active layer of the third transistor includes oxide, the material of the sixth gate insulating layer includes silicon oxide, and the material of the first passivation layer includes silicon oxide.

[0015] In some embodiments, the sub-pixel further includes a first passivation layer, a second source-drain conductive layer, a second passivation layer, a second contact layer, a planarization layer, a third passivation layer, and an anode disposed on a side of the fourth stacked structure away from the substrate.

[0016] The sub-pixel further includes a sensing signal line arranged in the second source-drain conductive layer, and a switching structure arranged in the second contact layer.

[0017] A through third via is provided in the first passivation layer, the third via exposes the source of the third transistor, the sensing signal line is electrically connected to the source of the third transistor through the third via, a through fourth via is provided in the second passivation layer and the first passivation layer, the fourth via exposes the drain of the third transistor, the switching structure is electrically connected to the drain of the third transistor through the fourth via, a through fifth via is provided in the third passivation layer and the planarization layer, the fifth via exposes the switching structure, and the anode is electrically connected to the switching structure through the fifth via.

[0018] In some embodiments, the fourth stacked structure includes a fifth gate insulation layer, a third active layer, a sixth gate insulation layer, a fourth gate conductive layer, a first passivation layer, a first source-drain conductive layer, a second passivation layer, and a second source-drain conductive layer, the active layer of the third transistor is located in the third active layer, the gate of the third transistor is located in the fourth gate conductive layer, the source of the third transistor is located in the first source-drain conductive layer, and the drain of the third transistor is located in the second source-drain conductive layer.

[0019] The sub-pixel also includes a sensing signal line arranged in the first source-drain conductive layer, the sensing signal line is directly connected to the source of the third transistor, a seventh via hole is arranged through the first passivation layer and the sixth gate insulating layer, the seventh via hole exposes the active layer of the third transistor, and the source of the third transistor is electrically connected to the active layer of the third transistor through the seventh via hole.

[0020] An eighth via is provided through the second passivation layer, the first passivation layer, the sixth gate insulation layer and the fifth gate insulation layer, and the eighth via exposes the active layer of the third transistor and the second electrode plate of the capacitor, and the drain of the third transistor is electrically connected to the active layer of the third transistor and the second electrode plate of the capacitor through the eighth via.

[0021] In some embodiments, the sub-pixel further includes a planarization layer, a third passivation layer, and an anode disposed on a side of the second source-drain conductive layer away from the substrate. A ninth via hole is provided through the third passivation layer and the planarization layer, the ninth via hole exposes the drain of the third transistor, and the anode is electrically connected to the drain of the third transistor through the ninth via hole.

[0022] In some embodiments, the first stacked structure includes a stacked first active layer, a first gate insulating layer, a first gate conductive layer and a first buffer layer, the active layer of the first transistor is located in the first active layer, and the gate of the first transistor is located in the first gate conductive layer.

[0023] The second stacking structure is arranged on a side of the first buffer layer away from the substrate, and the second stacking structure includes a stacked second active layer, a second gate insulating layer, a second gate conductive layer and a third gate insulating layer. The active layer of the second transistor is located in the second active layer, and the gate of the second transistor is located in the second gate conductive layer.

[0024] The third stacking structure is arranged on a side of the third gate insulating layer away from the substrate, and the third stacking structure includes a stacked first contact layer, a fourth gate insulating layer and a third gate conductive layer, the first plate of the capacitor is located in the first contact layer, and the second plate of the capacitor is located in the third gate conductive layer.

[0025] The sub-pixel also includes a power signal line arranged in the third gate conductive layer, and a sixth via hole is arranged through the fourth gate insulating layer, the third gate insulating layer, the second gate insulating layer, the first buffer layer and the first gate insulating layer, the sixth via hole exposes the active layer of the first transistor, and the power signal line is electrically connected to the active layer of the first transistor through the sixth via hole.

[0026] In a second aspect, the present application further provides a display device, comprising the display panel improved in any one of the embodiments of the first aspect and a controller, wherein the controller is electrically connected to the display panel.

[0027] In the display panel provided in the embodiment of the present application, the pixel circuit of each sub-pixel includes three transistors and one capacitor, and the first stacking structure, the second stacking structure, the third stacking structure and the fourth stacking structure of each sub-pixel stack include a first transistor, a second transistor, a capacitor and a third transistor, respectively. That is, along the direction perpendicular to the substrate, the capacitor is located between the second transistor and the third transistor, and the capacitor is located above the first transistor and the second transistor.

[0028] The capacitor includes a first plate and a second plate, the second plate is arranged on a side of the first plate away from the substrate, that is, the first plate is a lower plate, the second plate is an upper plate, the first plate is electrically connected to the first transistor and the second transistor, and the second plate is electrically connected to the first transistor and the third transistor.

[0029] Based on the above stacked arrangement, the first plate and the second plate of the capacitor do not need to avoid the connection via between the second transistor and the first transistor, so that the area can be fully utilized. When the pixel circuit occupies the same substrate area, the area of ​​the first plate and the second plate of the capacitor can be increased, which is conducive to increasing the overlapping area of ​​the first plate and the second plate, thereby increasing the capacitance of the capacitor. Alternatively, when the capacitance of the capacitor meets the display requirements, the structural arrangement in the sub-pixel can be made more compact to reduce the area of ​​the substrate occupied by the pixel circuit, thereby achieving an increase in pixel density.

[0030] The display device has the same structure and beneficial technical effects as the above-mentioned display panel, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solution in the present application, the following is a brief introduction to the drawings required for use in some embodiments of the present application. Obviously, the drawings described below are only drawings of some embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, not the actual size of the product involved in the embodiments of the present application, or the actual process of the method.

[0032] Figure 1 is a structural schematic diagram of a display panel;

[0033] Figure 2 It is a circuit structure schematic diagram of a 3T1C pixel circuit;

[0034] Figure 3 for Figure 1 A cross-sectional view of the display panel along section line AA';

[0035] Figure 4 for Figure 1 The shown is a partial enlarged view of the display panel at position P;

[0036] Figure 5 A schematic diagram of a partial structure of a first display panel provided in an embodiment of the present application;

[0037] Figure 6 A schematic diagram of a layout of a display panel provided in an embodiment of the present application;

[0038] Figure 7 for Figure 6 The shown is a partial enlarged view of the display panel at Q;

[0039] Figure 8 A schematic diagram of a partial structure of a second display panel provided in an embodiment of the present application;

[0040] Fig. 9 A partial structural diagram of a third display panel provided in an embodiment of the present application

[0041] Fig.10 A schematic diagram of a partial structure of a fourth display panel provided in an embodiment of the present application;

[0042] Fig.11 A schematic diagram of a partial structure of a fifth display panel provided in an embodiment of the present application;

[0043] Fig.12 A schematic diagram of the structure of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0045] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0046] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0047] When describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connection" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0048] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0049] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0050] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0051] At present, due to the large number of thin film transistor switches in organic light emitting diode display panels, it is always difficult to increase the pixel density. Figure 1 to Figure 4 As shown, Figure 1 Schematic diagram of the structure of a display panel, the display panel 1 includes a plurality of sub-pixels 2, each of which includes a pixel circuit. Figure 2 As shown, Figure 2It is a circuit structure diagram of a 3T1C pixel circuit, that is, the pixel circuit of the sub-pixel 2 includes three transistors and a capacitor. The 3T1C pixel circuit is used to realize circuit compensation and accurately control the luminous brightness of the diode (LED) corresponding to each sub-pixel. Figure 3 for Figure 1 The partial cross-sectional view of the display panel along the section line AA' is shown. Figure 4 for Figure 1 The shown figure is a partial enlarged view of the display panel at position P.

[0052] like Figure 3 and Figure 4 As shown, along the direction Z perpendicular to the substrate, the first transistor T1, the capacitor C, the second transistor T2, and the third transistor T3 are stacked in sequence. The first plate C1 of the capacitor C is arranged in the same layer as the gate G1 of the first transistor T1, and the second plate C2 of the capacitor C is arranged in the same layer as the source-drain conductive layer SD1 of the first transistor T1. The larger the overlapping area of ​​the first plate C1 and the second plate C2, the larger the capacitance of the corresponding capacitor C.

[0053] However, to form Figure 2 In the circuit connection structure shown, a connection structure CM1 needs to be provided between the source-drain conductive layer SD2 of the second transistor T2 and the gate G1 of the first transistor T1. Accordingly, a via hole needs to be provided between the source-drain conductive layer SD2 and the film layer where the gate G1 is located to form the connection structure CM1. In order to avoid the via hole, as shown in FIG. Figure 4 As shown, the overlapping area of ​​the first electrode plate C1 and the second electrode plate C2 is greatly reduced, resulting in a further reduction in the capacitance of the capacitor C. In order to ensure the display effect, the capacitance of the capacitor C needs to be increased, that is, the occupied area of ​​the first electrode plate C1 and the second electrode plate C2 on the substrate needs to be increased, which will increase the occupied area of ​​the pixel circuit on the substrate, thereby making the pixel density lower.

[0054] In addition, the source-drain conductive layer SD3 of the third transistor T3 needs to be connected to the diode LED upward on the one hand, and needs to be connected to the source-drain conductive layer SD1 of the first transistor T1 downward on the other hand. Accordingly, a via hole needs to be set between the film layer where the source-drain conductive layer SD3 and the source-drain conductive layer SD1 are located. The via hole needs to avoid the connection structure CM1 between the source-drain conductive layer SD2 of the second transistor T2 and the gate G1 of the first transistor T1, which further leads to an increase in the area occupied by the pixel circuit on the substrate, thereby making the pixel density lower.

[0055] Based on the above problems, the present application provides a display panel, aiming to improve pixel density.

[0056] like Figure 5 As shown, Figure 5A schematic diagram of the partial structure of a first display panel provided in an embodiment of the present application.

[0057] The display panel 1 includes a substrate 10 and a plurality of sub-pixels disposed on the substrate 10. The sub-pixels include a first stacking structure 11, a second stacking structure 12, a third stacking structure 13 and a fourth stacking structure 14, wherein the first stacking structure 11 includes a first transistor T1, the second stacking structure 12 includes a second transistor T2, the third stacking structure 13 includes a capacitor C, and the fourth stacking structure 14 includes a third transistor T3.

[0058] The capacitor C includes a first plate C1 and a second plate C2. The second plate C2 is arranged on a side of the first plate C1 away from the substrate 10, that is, the first plate C1 is a lower plate and the second plate C2 is an upper plate. The first plate C1 is electrically connected to the first transistor T1 and the second transistor T2, and the second plate C2 is electrically connected to the first transistor T1 and the third transistor T3.

[0059] In the display panel 1 provided in the embodiment of the present application, the pixel circuit of each sub-pixel includes three transistors and one capacitor, and the three transistors and one capacitor are connected to form a Figure 2 The circuit shown is used to realize circuit compensation and accurately control the luminance of the diode corresponding to each sub-pixel. The first transistor T1, the second transistor T2, the capacitor C and the third transistor T3 are stacked to avoid the space limitation of transistors made on the same layer, thereby improving the pixel density of the display panel.

[0060] Furthermore, in the embodiment of the present application, the capacitor C is located between the second transistor T2 and the third transistor T3 along the direction Z perpendicular to the substrate 10. Based on the above stacked arrangement, the second transistor T2 and the first transistor T1 are both located below the first plate C1 of the capacitor C, so the overlapping portion of the first plate C1 and the second plate C2 of the capacitor C does not need to avoid the connecting via between the second transistor T2 and the first transistor T1, thereby achieving full utilization of the area. When the pixel circuit occupies the same substrate area, the area of ​​the first plate C1 and the second plate C2 of the capacitor C can be increased, which is conducive to increasing the overlapping area of ​​the first plate C1 and the second plate C2 of the capacitor C, thereby increasing the capacitance of the capacitor C.

[0061] like Figure 6-7 As shown, Figure 6 A schematic diagram of a layout of a display panel provided in an embodiment of the present application, wherein the pixel density of the display panel shown in the figure is 1800, and the portion circled in the dotted line frame in the figure corresponds to a sub-pixel.

[0062] Figure 7 for Figure 6 The partial enlarged view of the display panel at Q is shown in FIG. Figure 4 It can be seen from the comparison with the illustrated embodiment that the stacking method provided in the embodiment of the present application increases the overlapping area of ​​the first electrode plate C1 and the second electrode plate C2 of the capacitor C, and the substrate area is fully utilized.

[0063] Alternatively, when the capacitance of the capacitor C meets the display requirements, the structure arrangement in the sub-pixel can be made more compact, so as to correspondingly reduce the area of ​​the substrate occupied by the pixel circuit, thereby achieving an increase in pixel density.

[0064] In some embodiments, different transistors may adopt different structures, so that three transistors can be manufactured in layers, avoiding transistor space limitations and improving pixel density.

[0065] like Figure 5 As shown, the first stacked structure 11 includes a stacked first active layer 111, a first gate insulating layer 112, a first gate conductive layer 113 and a first buffer layer 114, the active layer ACT1 of the first transistor T1 is located in the first active layer 111, and the gate G1 of the first transistor T1 is located in the first gate conductive layer 113.

[0066] The second stacked structure 12 is arranged on a side of the first buffer layer 114 away from the substrate 10, and the second stacked structure 12 includes a stacked second active layer 121, a second gate insulating layer 122, a second gate conductive layer 123 and a third gate insulating layer 124. The active layer ACT2 of the second transistor T2 is located in the second active layer 121, and the gate G2 of the second transistor T2 is located in the second gate conductive layer 123.

[0067] The first electrode plate C1 is arranged on a side of the third gate insulating layer 124 away from the substrate 10, and a through first via hole K1 is arranged in the third gate insulating layer 124, the second gate insulating layer 122 and the first buffer layer 114. The first via hole K1 exposes the gate G1 of the first transistor T1 and the active layer ACT2 of the second transistor T2. The first electrode plate C1 is electrically connected to the gate G1 of the first transistor T1 and the active layer ACT2 of the second transistor T2 through the first via hole K1.

[0068] In the embodiment of the present application, the first transistor T1 adopts a top gate structure of low temperature polysilicon technology, and the material of its active layer ACT1 includes polysilicon, so that the first transistor T1 has a smaller leakage current as a driving transistor.

[0069] The first via K1 is a semi-overlap hole, a portion of which exposes the active layer ACT2 of the second transistor T2, and the other portion of which exposes the gate G1 of the first transistor T1. The first electrode C1 is electrically connected to the active layer ACT2 of the second transistor T2 through the first via K1. It can be understood that the first electrode C1 and the drain D of the second transistor T2 are arranged in the same layer and are directly electrically connected. The first via K1 penetrates the third gate insulating layer 124, the second gate insulating layer 122 and the first buffer layer 114, and is used to realize the electrical connection between the first electrode C1 (the drain D of the second transistor T2) and the gate G1 of the first transistor T1. The above electrical connection relationship forms the following: Figure 2 The connection relationship of node P1 in the circuit shown.

[0070] Since the third gate insulating layer 124 and the second gate insulating layer 122 are located in the second stacking structure 12, the first buffer layer 114 is located in the first stacking structure 11, the first stacking structure 11 and the second stacking structure 12 are both located on the side of the third stacking structure 13 close to the substrate 10, that is, the first via K1 is located on the side of the first electrode plate C1 of the capacitor C close to the substrate 10, and the second electrode plate C2 is arranged on the side of the first electrode plate C1 away from the substrate 10. Based on this, the overlapping design of the first electrode plate C1 and the second electrode plate C2 does not need to avoid the first via K1, so that full utilization of the area can be achieved.

[0071] When the pixel circuit occupies the same substrate area, the stacking arrangement in the embodiment of the present application can increase the area of ​​the first plate C1 and the second plate C2 of the capacitor C, which is conducive to increasing the overlapping area of ​​the first plate C1 and the second plate C2, thereby increasing the capacitance of the capacitor C. Alternatively, when the capacitance of the capacitor C meets the display requirements, the structure arrangement in the sub-pixel can be made more compact to reduce the area of ​​the substrate occupied by the pixel circuit, thereby achieving an increase in pixel density.

[0072] In addition, if Figure 5 As shown, in some embodiments, a first wiring layer 1001 and a shielding layer 1002 are further provided between the substrate 10 and the first stacking structure 11. The first wiring layer 1001 is used to realize the electrical connection between the data line Data and the second transistor T2, and the shielding layer 1002 is used to shield the influence of the data line Data on the first transistor T1 when it jumps. A portion of the first gate conductive layer 113 is used to set the gate G1 of the first transistor T1 to realize the electrical connection of the relevant circuit, and another portion is used to set the bridging plate CM0. Based on this bridging plate CM0, the data line Data is electrically connected to the source S of the second transistor T2, which can avoid the problem of a large depth-width ratio of the via hole, and further avoid the problem of the active layer ACT2 being pierced due to the deep via hole being over-engraved.

[0073] In some embodiments, Figure 5As shown, the material of the active layer ACT2 of the second transistor T2 includes oxide, the material of the first buffer layer 114 includes silicon oxide, and the material of the second gate insulating layer 122 includes silicon oxide.

[0074] The material of the fourth gate insulating layer 132 is generally silicon nitride, which is used as the dielectric of the capacitor C. In the embodiment of the present application, the second transistor T2 adopts an oxide top gate structure, and the material of its active layer ACT2 may include indium gallium zinc oxide (IGZO). In order to avoid the influence of silicon nitride material on the characteristics of the oxide transistor, the dielectric layer of the capacitor C cannot be directly adjacent to the active layer ACT2, and the materials of the first buffer layer 114 and the second gate insulating layer 122 adjacent to the active layer ACT2 can both be silicon oxide. For example, if the first buffer layer 114 includes a composite material film layer, such as silicon nitride and silicon oxide, it can be set that the material of the first buffer layer 114 close to the active layer ACT2 is silicon oxide, and the material of the first buffer layer 114 close to the substrate 10 is silicon nitride.

[0075] In some embodiments, Figure 5 As shown, the third stacking structure 13 is arranged on the side of the third gate insulating layer 124 away from the substrate 10, and the third stacking structure 13 includes a stacked first contact layer 131, a fourth gate insulating layer 132 and a third gate conductive layer 133, the first plate C1 of the capacitor C is located in the first contact layer 131, and the second plate C2 of the capacitor C is located in the third gate conductive layer 133.

[0076] The fourth stacking structure 14 is arranged on a side of the third gate conductive layer 133 away from the substrate 10, and the fourth stacking structure 14 includes a stacked fifth gate insulating layer 141, a fourth gate conductive layer 142, a sixth gate insulating layer 143, a third active layer 144 and a first source-drain conductive layer 145, the active layer ACT3 of the third transistor T3 is located in the third active layer 144, the gate G3 of the third transistor T3 is located in the fourth gate conductive layer 142, and the source S and the drain D of the third transistor T3 are located in the first source-drain conductive layer 145.

[0077] The sixth gate insulating layer 143 and the fifth gate insulating layer 141 are provided with a through second via hole K2 , the second via hole K2 exposes the second electrode plate C2 , and the drain electrode D of the third transistor T3 is electrically connected to the second electrode plate C2 through the second via hole K2 .

[0078] In the embodiment of the present application, the second via hole K2 penetrates the sixth gate insulating layer 143 and the fifth gate insulating layer 141, and is used to realize the electrical connection between the drain electrode D of the third transistor T3 and the second electrode plate C2, so as to form Figure 2 The connection relationship of node P2 in the circuit shown.

[0079] Based on the above stacked arrangement, the sixth gate insulating layer 143 and the fifth gate insulating layer 141 are both located on the side of the second electrode plate C2 away from the first electrode plate C1, and the second via hole K2 does not need to avoid the overlapping area between the first electrode plate C1 and the second electrode plate C2, and the second via hole K2 does not need to avoid the first via hole K1, thereby achieving full utilization of the area.

[0080] like Figure 3 In the stacked structure of the display panel shown, the electrical connection between the drain electrode D of the third transistor T3 and the second electrode plate C2 needs to avoid the connection structure CM1. In the embodiment of the present application, when the overlapping area of ​​the first electrode plate C1 and the second electrode plate C2 of the capacitor C remains unchanged, the electrical connection between the drain electrode D of the third transistor T3 and the second electrode plate C2 can make full use of the substrate area, and does not need to avoid other vias or connection structures. When the capacitance of the capacitor C meets the display requirements, the structural arrangement in the sub-pixel can be made more compact to reduce the area of ​​the substrate occupied by the pixel circuit, thereby achieving an increase in pixel density.

[0081] In some embodiments, Figure 5 As shown, the sub-pixel also includes a first passivation layer 151 arranged on the side of the first source-drain conductive layer 145 away from the substrate 10, the material of the active layer ACT3 of the third transistor T3 includes oxide, the material of the sixth gate insulating layer 143 includes silicon oxide, and the material of the first passivation layer 151 includes silicon oxide.

[0082] In the embodiment of the present application, the third transistor T3 adopts an oxide BCE structure, and the material of its active layer ACT3 may include indium gallium zinc oxide (IGZO). To avoid affecting the oxide characteristics, the materials of the sixth gate insulating layer 143 and the first passivation layer 151 adjacent thereto may both be silicon oxide. For example, if the first passivation layer 151 includes a composite material film layer, such as silicon nitride and silicon oxide, the material of the first passivation layer 151 close to the active layer ACT3 may be silicon oxide, and the material of the first passivation layer 151 away from the active layer ACT3 may be silicon nitride.

[0083] In other embodiments, Figure 8 As shown, Figure 8 The schematic diagram of the partial structure of the second display panel provided in the embodiment of the present application. The sub-pixel further includes a first passivation layer 151, a second source-drain conductive layer 152, a second passivation layer 153, a second contact layer 154, a planarization layer 155, a third passivation layer 156 and an anode 157 arranged on a side of the fourth stacked structure 14 away from the substrate 10.

[0084] The sub-pixel further includes a sensing signal line Sense disposed in the second source-drain conductive layer 152 , and a transfer structure CM2 disposed in the second contact layer 154 .

[0085] A through third via K3 is provided in the first passivation layer 151, and the third via K3 exposes the source S of the third transistor T3. The sensing signal line Sense is electrically connected to the source S of the third transistor T3 through the third via K3. A through fourth via K4 is provided in the second passivation layer 153 and the first passivation layer 151, and the fourth via K4 exposes the drain D of the third transistor T3. The transfer structure CM2 is electrically connected to the drain D of the third transistor T3 through the fourth via K4. A through fifth via K5 is provided in the third passivation layer 156 and the planarization layer 155, and the fifth via K5 exposes the transfer structure CM2. The anode 157 is electrically connected to the transfer structure CM2 through the fifth via K5.

[0086] In the embodiment of the present application, the second source-drain conductive layer 152 is used for routing the sensing signal line Sense, and the fourth via K4 and the fifth via K5 are used to realize the electrical connection between the drain electrode D of the third transistor T3 and the anode 157 via the transfer structure CM2. The anode 157 can be regarded as Figure 2 The node P2 is connected to one end of the diode LED. Based on this, the routing design of the sensing signal line Sense needs to avoid the fourth via K4.

[0087] and Figure 5 Compared with the embodiment shown, Figure 5 In the embodiment, the drain electrode D of the third transistor T3 and the anode 157 are not provided with a transfer structure CM2, but are directly electrically connected. To ensure the insulation performance, Figure 5 In the illustrated embodiment, a planarization layer 155 and a second passivation layer 153 are further provided between the second source-drain conductive layer 152 and the anode 157. Furthermore, in order to realize the electrical connection between the drain electrode D of the third transistor T3 and the anode 157, a through via hole needs to be provided in the second passivation layer 153, the planarization layer 155 and the first passivation layer 151. The via hole has a large depth. To ensure the reliability of the electrical connection, the via hole has a large width, which will compress the space for routing the sensing signal line Sense.

[0088] In the embodiment of the present application, Figure 8 As shown, the fourth via hole K4 passes through the second passivation layer 153 and the first passivation layer 151, and the depth of the fourth via hole K4 is relatively small. Under the premise of certain process accuracy and under the premise of ensuring the reliability of the electrical connection between the transfer structure CM2 and the drain D of the third transistor T3, the width of the fourth via hole K4 can be relatively small, which is beneficial to increase the space for routing the sensing signal line Sense and to reduce the area of ​​the substrate occupied by the pixel circuit, thereby achieving an increase in pixel density.

[0089] In the above embodiments, the third transistor T3 adopts a bottom gate design, which results in a larger thickness between the active layer ACT3 of the third transistor T3 and the second electrode plate C2.

[0090] In some other embodiments, the third transistor T3 adopts a top gate structure design, for example, Fig. 9 As shown, Fig. 9 A schematic diagram of the partial structure of a third display panel provided in an embodiment of the present application.

[0091] The fourth stacked structure 14 includes a fifth gate insulating layer 141, a third active layer 144, a sixth gate insulating layer 143, a fourth gate conductive layer 142, a first passivation layer 151, a first source-drain conductive layer 145, a second passivation layer 153 and a second source-drain conductive layer 152, the active layer ACT3 of the third transistor T3 is located in the third active layer 144, the gate G3 of the third transistor T3 is located in the fourth gate conductive layer 142, the source S of the third transistor T3 is located in the first source-drain conductive layer 145, and the drain D of the third transistor T3 is located in the second source-drain conductive layer 152.

[0092] The sub-pixel also includes a sensing signal line Sense arranged in the first source-drain conductive layer 145. The sensing signal line Sense and the source S of the third transistor T3 are both located in the first source-drain conductive layer 145, and the two are directly connected. A seventh via K7 is provided through the first passivation layer 151 and the sixth gate insulating layer 143. The seventh via K7 exposes the active layer ACT3 of the third transistor T3. The source S of the third transistor T3 is electrically connected to the active layer ACT3 of the third transistor T3 through the seventh via K7.

[0093] An eighth via hole K8 is provided through the second passivation layer 153, the first passivation layer 151, the sixth gate insulating layer 143 and the fifth gate insulating layer 141, and the eighth via hole K8 exposes the active layer ACT3 of the third transistor T3 and the second electrode plate C2 of the capacitor C, and the drain D of the third transistor T3 is electrically connected to the active layer ACT3 of the third transistor T3 and the second electrode plate C2 of the capacitor C through the eighth via hole K8.

[0094] In the embodiment of the present application, the third transistor T3 adopts a top gate structure design, and the drain electrode D of the third transistor T3 is connected to the second electrode plate C2 of the capacitor C by a half-overlap hole (eighth via K8). That is, a part of the eighth via K8 exposes the active layer ACT3 of the third transistor T3, and the other part exposes the second electrode plate C2 of the capacitor C. Since the third transistor T3 adopts a top gate structure design, the film thickness between the active layer ACT3 of the third transistor T3 and the second electrode plate C2 is reduced, and the depth of the half-overlap hole located in the film layer area is small.

[0095] For example, with Figure 8Compared with the second via hole K2 shown in FIG. 1 , the second via hole K2 needs to penetrate the sixth gate insulating layer 143 and the fifth gate insulating layer 141 to partially expose the active layer ACT3 and another part to expose the second electrode plate C2. In the embodiment of the present application, the part of the eighth via hole K8 that plays the same role only needs to penetrate the fifth gate insulating layer 141. The depth of this part of the eighth via hole K8 is smaller and the required width is smaller, which is conducive to reducing the area of ​​the substrate occupied by the pixel circuit, thereby improving the pixel density.

[0096] Furthermore, the sensing signal line Sense and the source electrode S of the third transistor T3 are both located in the first source-drain conductive layer 145, and the two are directly connected. Figure 8 Compared with the embodiment shown, one conductive layer design can be saved, and one passivation layer via design can be saved.

[0097] In some embodiments, Fig. 9 As shown, the sub-pixel further includes a planarization layer 155, a third passivation layer 156, and an anode 157, which are arranged on a side of the second source-drain conductive layer 152 away from the substrate 10. A ninth via hole K9 is provided through the third passivation layer 156 and the planarization layer 155, and the ninth via hole K9 exposes the drain electrode D of the third transistor T3. The anode 157 is electrically connected to the drain electrode D of the third transistor T3 through the ninth via hole K9.

[0098] Based on the above film layer setting, the depth of the ninth via hole K9 is relatively small, which is conducive to realizing the electrical connection between the drain electrode D of the third transistor T3 and the anode 157. When the capacitance of the capacitor meets the display requirements, the structure arrangement in the sub-pixel can be made more compact to reduce the area of ​​the substrate occupied by the pixel circuit, thereby realizing the improvement of pixel density.

[0099] In addition, to form Figure 2 In the circuit shown, the electrical connection between the power signal line VDD and the first transistor T1 also needs to be realized through a via hole. In some embodiments, in order to avoid the via hole having an excessively large aspect ratio, the position of the conductive layer where the power signal line VDD is located can be optimized. Figure 10-11 As shown, Fig.10 A schematic diagram of a partial structure of a fourth display panel provided in an embodiment of the present application, Fig.11 A schematic diagram of the partial structure of a fifth display panel provided in an embodiment of the present application.

[0100] For example, Fig.10 As shown, in some embodiments, the first stacked structure 11 includes a stacked first active layer 111, a first gate insulating layer 112, a first gate conductive layer 113 and a first buffer layer 114, the active layer ACT1 of the first transistor T1 is located in the first active layer 111, and the gate G1 of the first transistor T1 is located in the first gate conductive layer 113.

[0101] The second stacked structure 12 is arranged on a side of the first buffer layer 114 away from the substrate 10, and the second stacked structure 12 includes a stacked second active layer 121, a second gate insulating layer 122, a second gate conductive layer 123 and a third gate insulating layer 124. The active layer ACT2 of the second transistor T2 is located in the second active layer 121, and the gate G2 of the second transistor T2 is located in the second gate conductive layer 123.

[0102] The third stacking structure 13 is arranged on a side of the third gate insulating layer 124 away from the substrate 10, and the third stacking structure 13 includes a stacked first contact layer 131, a fourth gate insulating layer 132 and a third gate conductive layer 133. The first electrode C1 of the capacitor C is located in the first contact layer 131, and the second electrode C2 of the capacitor C is located in the third gate conductive layer 133.

[0103] The sub-pixel also includes a power signal line VDD arranged in the third gate conductive layer 133, and a sixth via hole K6 is arranged through the fourth gate insulating layer 132, the third gate insulating layer 124, the second gate insulating layer 122, the first buffer layer 114 and the first gate insulating layer 112, the sixth via hole K6 exposes the active layer ACT1 of the first transistor T1, and the power signal line VDD is electrically connected to the active layer ACT1 of the first transistor T1 through the sixth via hole K6.

[0104] In the embodiment of the present application, the power signal line VDD and the first plate C1 of the capacitor C are arranged in the same layer, and are both arranged in the third gate conductive layer 133, which is beneficial to reducing the aspect ratio of the sixth via K6. Under the premise of the same process accuracy and ensuring the reliability of electrical connection, the required width of the sixth via K6 is smaller, which is beneficial to reducing the area of ​​the substrate occupied by the pixel circuit, thereby achieving an increase in pixel density.

[0105] This improved method is also applicable in other embodiments, for example, Figure 8 and Fig.11 As shown, in Figure 8 In the embodiment shown, the power signal line VDD is arranged in the first source-drain conductive layer 145. To realize the electrical connection between the power signal line VDD and the active layer ACT1, the tenth via hole K10 needs to penetrate the sixth gate insulating layer 143, the fifth gate insulating layer 141, the fourth gate insulating layer 132, the third gate insulating layer 124, the second gate insulating layer 122, the first buffer layer 114 and the first gate insulating layer 112. The tenth via hole K10 has a large depth and a large width, which is not conducive to reducing the area of ​​the substrate occupied by the pixel circuit. Fig.11In the illustrated embodiment, the power signal line VDD is arranged on the same layer as the second electrode plate C2, and both are arranged on the third gate conductive layer 133. In order to realize the electrical connection between the power signal line VDD and the active layer ACT1, the eleventh via hole K11 needs to penetrate the fourth gate insulating layer 132, the third gate insulating layer 124, the second gate insulating layer 122, the first buffer layer 114 and the first gate insulating layer 112. The depth of the eleventh via hole K11 is relatively small, which is more conducive to reducing the area of ​​the substrate occupied by the pixel circuit, thereby realizing an increase in pixel density.

[0106] In a second aspect, the present application also provides a display device, such as Fig.12 As shown, Fig.12 A schematic diagram of the structure of a display device provided in an embodiment of the present application. The display device 2 comprises a display panel 1 and a controller 20 improved in any embodiment of the first aspect above, wherein the controller 20 is electrically connected to the display panel 1. The controller 20 is used to provide a control signal to the display panel 1 so that the display panel 1 displays a picture.

[0107] In the above-mentioned display panel 1, the pixel circuit of each sub-pixel includes three transistors and one capacitor, which are used to realize circuit compensation and accurately control the luminous brightness of the diode corresponding to each sub-pixel. In addition, along the direction Z perpendicular to the substrate 10, the first transistor T1, the second transistor T2, the capacitor C and the third transistor T3 are stacked. The capacitor C is located between the second transistor T2 and the third transistor T3, and the second transistor T2 and the first transistor T1 are both located below the first plate C1 of the capacitor C. Therefore, the overlapping part of the first plate C1 and the second plate C2 of the capacitor C does not need to avoid the connection via between the second transistor T2 and the first transistor T1, so that the area can be fully utilized. When the pixel circuit occupies the same substrate area, the overlapping area of ​​the first plate C1 and the second plate C2 of the capacitor C is increased, thereby increasing the capacitance of the capacitor C. Accordingly, under the premise of ensuring the display effect, the area occupied by the pixel circuit on the substrate can be correspondingly reduced, thereby achieving an increase in pixel density.

[0108] Based on this, the display device 2 provided in the embodiment of the present application may also have a higher pixel density, which is conducive to the application in fields such as virtual reality (VR) or augmented reality (AR).

[0109] Further, the display device 2 may be any device that displays images, whether in motion (e.g., video) or fixed (e.g., still images), and whether textual or graphic. More specifically, it is contemplated that the embodiments may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controls and / or displays, displays of camera views (e.g., displays of rear-view cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0110] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A display panel, characterized in that: It includes a substrate, and a plurality of sub-pixels arranged on the substrate; The sub-pixel includes a first stacking structure, a second stacking structure, a third stacking structure and a fourth stacking structure, wherein the first stacking structure includes a first transistor, the second stacking structure includes a second transistor, the third stacking structure includes a capacitor, and the fourth stacking structure includes a third transistor; The capacitor includes a first plate and a second plate, wherein the second plate is disposed on a side of the first plate away from the substrate; the first plate is electrically connected to the first transistor and the second transistor, and the second plate is electrically connected to the first transistor and the third transistor.

2. The display panel according to claim 1, characterized in that: The first stacked structure includes a stacked first active layer, a first gate insulating layer, a first gate conductive layer and a first buffer layer, the active layer of the first transistor is located in the first active layer, and the gate of the first transistor is located in the first gate conductive layer; The second stacked structure is arranged on a side of the first buffer layer away from the substrate, the second stacked structure comprises a stacked second active layer, a second gate insulating layer, a second gate conductive layer and a third gate insulating layer, the active layer of the second transistor is located in the second active layer, and the gate of the second transistor is located in the second gate conductive layer; The first electrode plate is arranged on a side of the third gate insulating layer away from the substrate; a first through hole is arranged in the third gate insulating layer, the second gate insulating layer and the first buffer layer, and the first via hole exposes the gate of the first transistor and the active layer of the second transistor; The first electrode plate is electrically connected to the gate of the first transistor and the active layer of the second transistor through the first via hole.

3. The display panel according to claim 2, characterized in that: The material of the active layer of the second transistor includes oxide; A material of the first buffer layer includes silicon oxide, and a material of the second gate insulating layer includes silicon oxide.

4. The display panel according to claim 2, characterized in that: The third stacked structure is arranged on a side of the third gate insulating layer away from the substrate, the third stacked structure comprises a stacked first contact layer, a fourth gate insulating layer and a third gate conductive layer, the first electrode plate of the capacitor is located on the first contact layer, and the second electrode plate of the capacitor is located on the third gate conductive layer; The fourth stacked structure is arranged on a side of the third gate conductive layer away from the substrate, the fourth stacked structure comprises a fifth gate insulating layer, a fourth gate conductive layer, a sixth gate insulating layer, a third active layer and a first source-drain conductive layer, the active layer of the third transistor is located in the third active layer, the gate of the third transistor is located in the fourth gate conductive layer, and the source and drain of the third transistor are located in the first source-drain conductive layer; A through second via hole is provided in the sixth gate insulating layer and the fifth gate insulating layer, and the second via hole exposes the second electrode plate; the drain of the third transistor is electrically connected to the second electrode plate through the second via hole.

5. The display panel according to claim 4, characterized in that: The sub-pixel further includes a first passivation layer disposed on a side of the first source-drain conductive layer away from the substrate; A material of the active layer of the third transistor includes oxide, a material of the sixth gate insulating layer includes silicon oxide, and a material of the first passivation layer includes silicon oxide.

6. The display panel according to claim 1, characterized in that: The sub-pixel further includes a first passivation layer, a second source-drain conductive layer, a second passivation layer, a second contact layer, a planarization layer, a third passivation layer and an anode, which are arranged on a side of the fourth stacked structure away from the substrate; The sub-pixel further includes a sensing signal line disposed in the second source-drain conductive layer, and a transfer structure disposed in the second contact layer; A third through hole is provided in the first passivation layer, the third through hole exposes the source of the third transistor, and the sensing signal line is electrically connected to the source of the third transistor through the third through hole; A fourth through-hole is provided in the second passivation layer and the first passivation layer, the fourth through-hole exposes the drain of the third transistor, and the transfer structure is electrically connected to the drain of the third transistor through the fourth through-hole; a fifth through-hole is provided in the third passivation layer and the planarization layer, the fifth through-hole exposes the transfer structure, and the anode is electrically connected to the transfer structure through the fifth through-hole.

7. The display panel according to claim 1, characterized in that: The fourth stacked structure includes a fifth gate insulating layer, a third active layer, a sixth gate insulating layer, a fourth gate conductive layer, a first passivation layer, a first source-drain conductive layer, a second passivation layer, and a second source-drain conductive layer, wherein the active layer of the third transistor is located in the third active layer, the gate of the third transistor is located in the fourth gate conductive layer, the source of the third transistor is located in the first source-drain conductive layer, and the drain of the third transistor is located in the second source-drain conductive layer; The sub-pixel further includes a sensing signal line disposed in the first source-drain conductive layer, the sensing signal line being directly connected to the source of the third transistor; a seventh via hole penetrating through the first passivation layer and the sixth gate insulating layer is disposed, the seventh via hole exposing the active layer of the third transistor, and the source of the third transistor is electrically connected to the active layer of the third transistor through the seventh via hole; An eighth via hole is provided through the second passivation layer, the first passivation layer, the sixth gate insulation layer and the fifth gate insulation layer, and the eighth via hole exposes the active layer of the third transistor and the second electrode plate of the capacitor; the drain of the third transistor is electrically connected to the active layer of the third transistor and the second electrode plate of the capacitor through the eighth via hole.

8. The display panel according to claim 7, characterized in that: The sub-pixel further includes a planarization layer, a third passivation layer and an anode arranged on a side of the second source-drain conductive layer away from the substrate; A ninth via hole is provided through the third passivation layer and the planarization layer, the ninth via hole exposes the drain of the third transistor, and the anode is electrically connected to the drain of the third transistor through the ninth via hole.

9. The display panel according to claim 1, characterized in that: The first stacked structure includes a stacked first active layer, a first gate insulating layer, a first gate conductive layer and a first buffer layer, the active layer of the first transistor is located in the first active layer, and the gate of the first transistor is located in the first gate conductive layer; The second stacked structure is arranged on a side of the first buffer layer away from the substrate, the second stacked structure comprises a stacked second active layer, a second gate insulating layer, a second gate conductive layer and a third gate insulating layer, the active layer of the second transistor is located in the second active layer, and the gate of the second transistor is located in the second gate conductive layer; The third stacked structure is arranged on a side of the third gate insulating layer away from the substrate, the third stacked structure comprises a stacked first contact layer, a fourth gate insulating layer and a third gate conductive layer, the first electrode plate of the capacitor is located on the first contact layer, and the second electrode plate of the capacitor is located on the third gate conductive layer; The sub-pixel also includes a power signal line arranged in the third gate conductive layer, and a sixth via hole is arranged through the fourth gate insulating layer, the third gate insulating layer, the second gate insulating layer, the first buffer layer and the first gate insulating layer, and the sixth via hole exposes the active layer of the first transistor; the power signal line is electrically connected to the active layer of the first transistor through the sixth via hole.

10. A display device, characterized in that: include: The display panel according to any one of claims 1 to 9; A controller is electrically connected to the display panel.

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