Display panel, preparation method thereof and display device

Abstract

The invention relates to the technical field of display, particularly provides a display panel and a preparation method thereof, and a display device, and aims to solve the problem that the color of the edge and the middle area of the display panel is not uniform due to an FIP scheme. To this end, the display panel of the present application comprises: a substrate; the plurality of functional layers on the substrate comprise a plurality of data lines which are arranged at intervals along a first direction and extend along a second direction crossed with the first direction, and the data lines comprise a first type of data lines and a second type of data lines; the connecting lines are located in the display area, and each connecting line comprises a first connecting part extending in the first direction and a second connecting part extending in the second direction; and the compensation structure is used for reducing the resistance and capacitance load difference on the second type of data lines and the first type of data lines. According to the display panel, the compensation structure is introduced to perform capacitance compensation on the non-FIP area, so that the resistance and capacitance load of the display panel is balanced, the color and the brightness of the display panel are uniform, and the display effect is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and specifically provides a display panel and a preparation method thereof, and a display device. Background Art

[0002] At present, with the development of OLED display technology, narrow border design has become the mainstream trend. In order to achieve a narrower product border, display panels usually adopt the FIP (Fanout in Panel) solution, that is, signal fan-out inside the panel. The FIP solution effectively reduces the need for external connections and further compresses the border width by adjusting the signal transmission path. Common FIP designs include dot (sub-pixel) 1-in-1 (1IN1), 2-in-1 (2IN1) or 4-in-1 (4IN1) designs. These designs provide more wiring space for FIP routing by compressing the horizontal and vertical dimensions of a single pixel.

[0003] When the Data signal is transmitted from the source driver to the edge area of ​​the screen through the FIP routing, it will inevitably cross multiple columns of pixels horizontally. This design leads to a significant uneven distribution of signal load (Source loading) in the edge FIP area and the signal load distribution in the middle area of ​​the screen without FIP ​​routing, and further leads to uneven color at the edge and middle areas of the display panel. Especially in pictures with high signal load, such as high contrast or large color blocks, color anomalies are prone to occur on both sides of the display panel, seriously affecting the display quality.

[0004] Accordingly, the art needs a new display panel solution to solve the above problems. Summary of the invention

[0005] The present application aims to solve the above-mentioned technical problem, that is, to solve the problem of uneven color at the edge and middle area of ​​the display panel caused by the existing FIP solution.

[0006] In a first aspect, the present application provides a display panel, comprising a display area and a peripheral area surrounding the display area, wherein the peripheral area includes a fan-out area arranged on one side of the display area, and the display panel comprises:

[0007] substrate;

[0008] Multiple functional layers on the substrate, including:

[0009] A plurality of data lines, the plurality of data lines are arranged at intervals along a first direction and extend along a second direction intersecting the first direction, wherein the plurality of data lines include first-type data lines and second-type data lines;

[0010] a plurality of connection lines located in the display area, each connection line comprising a first connection portion extending along the first direction and a second connection portion extending along the second direction, wherein a first end of the first connection portion is electrically connected to a first-type data line and a second end thereof is electrically connected to the first end of the second connection portion across at least one data line in the first direction, and a second end of the second connection portion extends in the second direction to the fan-out area;

[0011] A compensation structure is used to reduce the difference in resistance and capacitance loads between the second type of data lines and the first type of data lines.

[0012] In a technical solution of the above display panel, the compensation structure is a capacitor structure, including:

[0013] The capacitor structure is located on the other side of the display area relative to the fan-out area in the peripheral area, and the capacitor structure includes a first electrode plate and a relative electrode plate, wherein the first electrode plate is electrically connected to the second type of data line, the first electrode plate and the relative electrode plate are respectively located on different layers of the multiple functional layers, and the first electrode plate and the relative electrode plate are electrically insulated by an insulating layer in the functional layer.

[0014] In a technical solution of the above display panel, the display panel is an LTPS display panel, including a thin film transistor and a storage capacitor, wherein the thin film transistor includes a first gate metal, and the storage capacitor includes a first storage capacitor plate arranged in the same layer as the first gate metal and a second storage capacitor plate arranged opposite to the first storage capacitor plate in a direction away from the substrate;

[0015] The relative electrode plate is a second electrode plate, wherein the first electrode plate is disposed in the same layer as the first gate metal, and the second electrode plate is disposed in the same layer as the second storage capacitor electrode plate.

[0016] In a technical solution of the above display panel, the display panel is an LTPO display panel, comprising a first thin film transistor, a second thin film transistor and a storage capacitor, wherein the active layer materials of the first thin film transistor and the second thin film transistor are different, the first thin film transistor comprises a first gate metal, the second thin film transistor comprises a second gate metal, and the storage capacitor comprises a first storage capacitor plate arranged in the same layer as the first gate metal and a second storage capacitor plate arranged opposite to the first storage capacitor plate in a direction away from the substrate;

[0017] The relative electrode plate includes a second electrode plate and a third electrode plate, the first electrode plate is located between the second electrode plate and the third electrode plate, wherein the first electrode plate and the second storage capacitor electrode plate are arranged in the same layer, the second electrode plate and the first gate metal are arranged in the same layer, and the third electrode plate and the second gate metal are arranged in the same layer.

[0018] In one technical solution of the above display panel, the compensation structure includes:

[0019] a metal wiring extending along the first direction, wherein the metal wiring is electrically connected to the second type of data line;

[0020] The metal wiring crosses over at least one data line and forms a capacitor with at least the crossed data line.

[0021] In a technical solution of the above display panel, the metal wiring has the same length as the first connecting portion.

[0022] In a technical solution of the above display panel, the metal wiring is arranged in the same layer as the first connecting portion.

[0023] In a technical solution of the above display panel, one end point of the metal wiring is electrically connected to the second-type data line.

[0024] In a technical solution of the above display panel, the metal wiring is electrically connected to the second-type data line at a non-end point position.

[0025] In a technical solution of the above display panel, the functional layer includes a first metal layer and a second metal layer, wherein the second metal layer is farther away from the substrate than the first metal layer;

[0026] The data line is in a different layer from the metal wiring, and is respectively arranged in the same layer as one of the first metal layer and the second metal layer;

[0027] The metal wiring is connected to the second-type data line via.

[0028] In a technical solution of the above display panel, the display panel further comprises a plurality of auxiliary power lines electrically connected to the low-voltage power line of the display panel, wherein the plurality of auxiliary power lines at least comprise a first auxiliary power line arranged at intervals along the second direction and extending along the first direction;

[0029] At least one power auxiliary line is disposed between two adjacent metal wirings and penetrates the display area along a first direction.

[0030] In a technical solution of the above display panel, the plurality of auxiliary power lines further include second auxiliary power lines arranged at intervals along the first direction and extending along the second direction.

[0031] In a second aspect, the present application provides a display device, comprising the above-mentioned display panel.

[0032] In a third aspect, the present application provides a method for manufacturing a display panel, wherein the display panel comprises a display area and a peripheral area surrounding the display area, the peripheral area comprises a fan-out area arranged on one side of the display area, and the method comprises:

[0033] forming a plurality of data lines, wherein the plurality of data lines are arranged at intervals along a first direction and extend along a second direction intersecting the first direction, wherein the plurality of data lines include first-type data lines and second-type data lines;

[0034] forming a plurality of connection lines located in the display area, each connection line comprising a first connection portion extending along the first direction and a second connection portion extending along the second direction, wherein a first end of the first connection portion is electrically connected to a first-type data line and a second end thereof is electrically connected to the first end of the second connection portion across at least one data line in the first direction, and a second end of the second connection portion extends to the fan-out area in the second direction;

[0035] A compensation structure is formed, wherein the compensation structure is used to reduce the difference in resistance and capacitance loads on the second type of data line and the first type of data line.

[0036] When adopting the above technical solution, the present application can introduce a compensation structure to perform capacitance compensation on the non-FIP area to balance the resistance and capacitance load of the display panel, so that the color and brightness of the display panel are uniform, thereby improving the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The preferred embodiments of the present application are described below in conjunction with the accompanying drawings, in which:

[0038] Figure 1 is a schematic diagram of wiring of a display area of ​​a display panel according to an embodiment of the present application;

[0039] Figure 2 is a cross-sectional view of a display panel according to an embodiment of the present application;

[0040] Figure 3 to Figure 6 They are schematic diagrams of some metal routings according to an embodiment of the present application;

[0041] Figure 7A to Figure 7B : is a metal layer structure diagram illustrating FIP routing according to one embodiment of the present application, wherein Fig. 7A is a metal layer structure diagram of the first source and drain metal layer, Figure 7B is a metal layer structure diagram of a second source-drain metal layer; Figure 7Cis a metal layer structure diagram illustrating FIP routing according to another embodiment of the present application;

[0042] Figure 8 is a schematic diagram of display panel brightness according to the related art;

[0043] Fig.9A It is a capacitance variation trend diagram according to the FIP scheme of related technology; Fig. 9B It is a resistance change trend diagram of the FIP scheme according to the relevant technology;

[0044] Figures 10A-10D is a schematic diagram of a capacitor structure according to an embodiment of the present application; wherein Fig. 10A is the projection diagram of the capacitor structure on the XY plane, Fig. 10B For along Fig. 10A Sectional view of the AA' section; Fig. 10C For along Fig. 10A Sectional view of the section taken at BB'; Fig. 10D For along Fig. 10A Sectional view of the CC' section;

[0045] Fig.11 This is a metal layer structure diagram where the metal routing is located according to an embodiment of the present application. DETAILED DESCRIPTION

[0046] Some embodiments of the present application are described below with reference to the accompanying drawings. Those skilled in the art should understand that these embodiments are only used to explain the technical principles of the present application and are not intended to limit the protection scope of the present application.

[0047] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme of the embodiments of the present application will be clearly and completely described below in conjunction with the drawings of the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the described embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0048] Unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which this application belongs. "First", "second" and similar words used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0049] In the existing FIP solution, two source-drain metal layers are usually used for FIP routing. Taking a display panel with two source-drain metal layers as an example, the FIP routing is provided with a plurality of connecting lines, and the connecting lines include a first connecting portion provided in the first source-drain metal layer and a second connecting portion provided in the second source-drain metal layer.

[0050] For details, please refer to the attached Figure 7A to Figure 7B .

[0051] Figure 7A to Figure 7B This is a metal layer structure diagram illustrating a FIP routing in an embodiment of the present application. The FIP routing in this embodiment adopts a 4IN1 method, that is, one connecting line is inserted every four dots.

[0052] Fig. 7A 701 is a diagram of the metal layer structure of the first source-drain metal layer, wherein 701 is the first connection portion in the connection line. The unmarked parts in the figure are all metal layer structures arranged in the first source-drain metal layer. Each pixel includes two symmetrically arranged dots. Fig. 7A Only the first source-drain metal layer is shown, and 700 only shows the range of a pixel rather than a specific pixel structure.

[0053] Figure 7B It is a metal layer structure diagram of the second source-drain metal layer, wherein 702 is the second connection part in the connecting line; 703 is the data line of the display panel, and 704 is the working power line (VDD); the unmarked parts in the figure are other metal layer structures arranged in the second source-drain metal layer.

[0054] Further, for the connection method between the first connection part and the second connection part of the connecting wire in the FIP routing, please refer to Figure 7C .

[0055] Figure 7CThis is a metal layer structure diagram illustrating a FIP routing in another embodiment of the present application. The FIP routing in this embodiment adopts a 2IN1 method, that is, a connecting line is inserted every 2 dots.

[0056] Specifically, Figure 7C It is a schematic diagram of the stacking of the first source-drain metal layer and the second source-drain metal layer, wherein the first connecting portion 711 is arranged in the first source-drain metal layer, and the second connecting portion 712 is arranged in the second source-drain metal layer, and the two are connected through a via; 710 only shows the range of one pixel.

[0057] However, the FIP solution introduces different lengths of connecting wires, and there are no connecting wires in areas where FIP routing is not used, which will cause huge differences in resistance and capacitance loads at the edge and middle areas of the display panel, thereby causing uneven colors at the edge and middle areas of the display panel.

[0058] See also Figure 8 as well as Fig.9A , Fig. 9B .in, Figure 8 This is a schematic diagram of the brightness of a display panel according to the related art. The color of the edge and middle area of ​​the display panel is uneven, and the brightness of the two sides is lower than that of the middle area, resulting in uneven visual display effect.

[0059] Fig.9A It is a capacitance variation trend diagram according to the FIP scheme of related technology; Fig. 9B This is a resistance change trend diagram of the FIP solution according to the related technology. Fig.9A and Fig. 9B The horizontal axes are the numbers of the data lines. Fig.9A The vertical axis is the capacitance value, Fig. 9B The vertical axis is the voltage value. Specifically, the data lines in the display panel are numbered 1, 2, 3, etc. from left to right, and the capacitance value of each data line is measured respectively to form Fig.9A ; Measure the voltage value of each data line separately to form Fig. 9B .

[0060] Obviously, the capacitance and resistance of the data lines with FIP routing on both sides are greater than those in the middle area (the peak in the center is the capacitance and resistance fluctuation caused by factors such as the camera, which is not taken into consideration). In addition, compared with 1IN1, since the wiring of 2IN1 is relatively sparse, its connection lines will pass through more signal lines, and the parasitic capacitance connected to the circuit will also increase; the relative path length increases, resulting in higher signal propagation impedance, so its capacitance and resistance values ​​are also significantly greater than 1IN1. FIG. 9A to FIG. 9B This diagram illustrates the reason for the huge difference in resistance and capacitance loads between the edge and middle areas of the display panel.

[0061] In order to solve the problem of uneven color at the edge and middle area of ​​a display panel caused by the existing FIP solution, the present application provides a display panel, comprising a display area and a peripheral area surrounding the display area, wherein the peripheral area includes a fan-out area arranged on one side of the display area, and the display panel includes:

[0062] substrate;

[0063] Multiple functional layers on the substrate, including:

[0064] A plurality of data lines, the plurality of data lines are arranged at intervals along a first direction and extend along a second direction intersecting the first direction, wherein the plurality of data lines include first-type data lines and second-type data lines;

[0065] a plurality of connection lines located in the display area, each connection line comprising a first connection portion extending along the first direction and a second connection portion extending along the second direction, wherein a first end of the first connection portion is electrically connected to a first-type data line and a second end thereof is electrically connected to the first end of the second connection portion across at least one data line in the first direction, and a second end of the second connection portion extends in the second direction to the fan-out area;

[0066] A compensation structure is used to reduce the difference in resistance and capacitance loads between the second type of data lines and the first type of data lines.

[0067] In one embodiment, the first type of data lines are located in edge regions of the display area along the first direction, and the second type of data lines are located in a central region between the edge regions.

[0068] The compensation structure can take many forms. Figure 1 , Figure 1 This is a schematic diagram of partial wiring of the display area of ​​a display panel according to an embodiment of the present application.

[0069] The plurality of data lines DL include a first type of data line DL1 located in an edge region 101 of the display area along the first direction X and a second type of data line DL2 located in a central region 102; each of the connection lines 11 includes a first connection portion 111 extending along the first direction X and a second connection portion 112 extending along the second direction Y; the schematic position 103 is the fan-out region. In addition, Figure 1 Also shown is an auxiliary line 12 connected to a low voltage power line (VSS), including a first auxiliary line 121 and a second auxiliary line 122 . The first auxiliary line 121 and the second auxiliary line 122 are both separated from the connection line 11 and have no electrical conduction.

[0070] It is understandable that in Figure 1In order to distinguish the data line DL, the connection line 11 and the auxiliary line 12, solid lines, thick solid lines and dashed lines are used to represent the above lines. The thickness and dashedness of the lines do not represent the width of the lines themselves or the continuity of the extension, but are only used to distinguish different signal lines. In other figures of the present application, unless otherwise specified, the signal lines are drawn in a similar way.

[0071] In one embodiment of the present application, the compensation structure is a capacitor structure, comprising:

[0072] The capacitor structure 104 is located on the other side of the display area relative to the fan-out area 103 in the peripheral area, and the capacitor structure 104 includes a first electrode and a relative electrode, wherein the first electrode is electrically connected to the second-type data line 102, the first electrode and the relative electrode are respectively located on different layers of the multiple functional layers, and the first electrode and the relative electrode are electrically insulated by an insulating layer in the functional layer.

[0073] In one embodiment of the present application, the display panel is an LTPS (Low-TemperaturePolycrystalline Silicon) display panel, comprising a thin film transistor (TFT) and a storage capacitor, wherein the thin film transistor comprises a first gate metal, and the storage capacitor comprises a first storage capacitor plate arranged in the same layer as the first gate metal and a second storage capacitor plate arranged opposite to the first storage capacitor plate in a direction away from the substrate;

[0074] The relative electrode plate is a second electrode plate, wherein the first electrode plate is disposed in the same layer as the first gate metal, and the second electrode plate is disposed in the same layer as the second storage capacitor electrode plate.

[0075] LTPS is a semiconductor technology used for thin-film transistors in display panels, whose active layer is composed of polycrystalline silicon. Through low-temperature (about 400°C) preparation technology, LTPS display panels have higher electron mobility and are suitable for high-resolution displays such as AMOLED and TFT-LCD.

[0076] For the capacitor structure, the first electrode is electrically connected to the second type data line 102. In one embodiment of the present application, the second electrode is electrically connected to VDD. The capacitor structure connected to the circuit can perform capacitance compensation for the second type data line 102 in the central area to reduce the resistance and capacitance load difference between the central area and the edge area of ​​the FIP routing.

[0077] Please also read Figure 2 In a display panel using LTPS technology, the thin film transistor is as follows Figure 2As shown in TFT1, its active layer ACT1 is made of polycrystalline silicon.

[0078] In another embodiment of the present application, the display panel may also be an LTPO (LTPS+Oxide, low temperature polycrystalline silicon+oxide) display panel. LTPO is a display technology that combines LTPS and oxide. By introducing an oxide layer in the active layer, it can achieve a combination of high mobility and low power consumption, and is suitable for adaptive refresh rate displays such as smartphones and wearable devices.

[0079] In LTPO technology, TFTs generally include two types: LTPS-TFT and IGZO-TFT. The active layer of the IGZO-TFT is generally a composite active layer combining IGZO and LTPS, wherein IGZO is indium gallium zinc oxide composed of In, Ga, Zn and O; by optimizing material properties, the display speed and power consumption are balanced.

[0080] In another embodiment of the present application, the display panel is an LTPO display panel, comprising a first thin film transistor, a second thin film transistor and a storage capacitor, wherein the active layer materials of the first thin film transistor and the second thin film transistor are different, the first thin film transistor comprises a first gate metal, the second thin film transistor comprises a second gate metal, and the storage capacitor comprises a first storage capacitor plate arranged in the same layer as the first gate metal and a second storage capacitor plate arranged opposite to the first storage capacitor plate in a direction away from the substrate;

[0081] The relative electrode plate includes a second electrode plate and a third electrode plate, the first electrode plate is located between the second electrode plate and the third electrode plate, wherein the first electrode plate and the second storage capacitor electrode plate are arranged in the same layer, the second electrode plate and the first gate metal are arranged in the same layer, and the third electrode plate and the second gate metal are arranged in the same layer.

[0082] In this embodiment, the first thin film transistor is an LTPS-TFT, the second thin film transistor is an IGZO-TFT, the first active layer ACT1 is made of polysilicon, and the second active layer ACT2 is made of IGZO.

[0083] To illustrate the capacitor structure described in the above embodiment, please refer to Figure 2 , Figure 2 is a cross-sectional view of a display panel according to an embodiment of the present application. Specifically, Figure 2 It is a partial schematic diagram of the display area cut along the XZ plane.

[0084] For example, Figure 2As shown, the display panel includes a substrate 20, and the substrate 20 may be a rigid substrate or a flexible substrate, and may be made of glass, polyimide, polycarbonate, and the like;

[0085] And a plurality of functional layers on the substrate 20, specifically including a stacked structure arranged in sequence along a third direction Z away from the substrate 20:

[0086] The first active layer ACT1, the first insulating layer GI1, the first gate metal Gate1, the second insulating layer GI2, the first interlayer dielectric layer ILD1, the third gate metal Gate2, the buffer layer Buffer, the third insulating layer GI3, the second active layer ACT2, the second interlayer dielectric layer ILD2, the second gate metal Gate3, the first metal layer SD1, the first planarization layer PLN1, the second metal layer SD2, and the second planarization layer PLN2. The first metal layer SD1 is the source and drain metal layer of the first thin film transistor TFT1; the second metal layer SD2 is the source and drain metal layer of the first thin film transistor TFT2.

[0087] Furthermore, the display panel further comprises a light emitting device: comprising an anode layer ANO, a light emitting functional layer EL and a cathode layer CATH which are stacked. The cathode layers CATH of a plurality of light emitting devices are interconnected to form a continuous whole layer structure.

[0088] The display panel 1100 may further include a pixel defining layer PDL and an encapsulation layer, wherein the encapsulation layer includes a first protective layer CVD1 , an organic encapsulation layer IJP, and a second protective layer CVD2 .

[0089] Figure 2 The storage capacitor CST is included, wherein the first storage capacitor plate CST1 of the storage capacitor is arranged at the same layer as the first gate metal Gate1, and the second storage capacitor plate CST2 is arranged at the same layer as the third gate metal Gate2.

[0090] For LTPO-TFT, in addition to using a single-gate structure to set the second gate metal Gate3, a double-gate design can also be used, that is, a third gate metal Gate2 is set on the other side of the second gate metal Gate3 relative to the second active layer ACT2.

[0091] Furthermore, for the dual-gate LTPO-TFT, the capacitor structure is specifically configured as follows:

[0092] The first plate of the capacitor structure is arranged on the same layer as the second storage capacitor plate CST2, that is, on the same layer as the third gate metal Gate2; the second plate of the capacitor structure is arranged on the same layer as the first gate metal Gate1, and the third plate is arranged on the same layer as the second gate metal Gate3.

[0093] Since the capacitor structure is arranged in the peripheral area, it is not possible to Figure 2 As shown in the figure, please refer to the capacitor structure for further reference. Figures 10A-10D .

[0094] Figures 10A-10D Schematic diagram of a capacitor structure according to an embodiment of the present application. In order to illustrate the relationship between layers, Fig. 10A The symbols Gate1, Gate2, Gate3, SD1, and SD2 in the figure all refer to the metal layers where these structures are located. For example, Gate1 refers to the metal layer where the first gate metal Gate1 is located, hereinafter referred to as the Gate1 layer.

[0095] in Fig. 10A The projection diagram of the capacitor structure on the XY plane also illustrates the electrical connection relationship between each metal layer in the capacitor structure and other structures in the display panel. The capacitor structure is composed of the second electrode 1002, the first electrode 1001, and the third electrode 1003 from bottom to top in the Z direction.

[0096] Specifically, see FIG. 10B to FIG. 10D sectional view of .

[0097] Fig. 10B For along Fig. 10A A cross-sectional view taken along AA' in the figure, wherein the first electrode plate 1001 disposed on the Gate2 layer is connected to the second type data line 102 disposed on the SD2 layer via a via hole, and is padded with Pad1 when passing through the SD1 layer;

[0098] Fig. 10C For along Fig. 10A A cross-sectional view taken along BB', in which the third electrode plate 1003 disposed on the Gate3 layer is connected to the VDD line disposed on the SD2 layer via a via hole, and is padded with Pad3 when passing through the SD1 layer;

[0099] Fig. 10D For along Fig. 10A In the cross-sectional view taken along CC′, the second electrode plate 1002 disposed on the Gate1 layer is connected to the VDD line disposed on the SD2 layer through a via hole, and is padded with Pad2 when passing through the SD1 layer.

[0100] Among them, Pad1, Pad2 and Pad3 are metal sheets at the pad joints and are not electrically connected to other metal layer structures of the SD1 layer.

[0101] In one embodiment, the area of ​​the first electrode plate 1001 is smaller than that of the second electrode plate 1002 and the third electrode plate 1003, forming a sandwich structure with large ends and a small middle. Fig. 10A The figures shown are not the actual projected area ratios of the above-mentioned plates.

[0102] The capacitor structure connected to the circuit can perform capacitance compensation for the second type data line 102 in the central area to reduce the resistance and capacitance load difference between the central area and the edge area of ​​the FIP routing; the capacitor structure with a stacked design can obtain a larger capacitance value, further expanding the compensable range.

[0103] In another embodiment of the present application, the compensation structure may also use a metal wiring to form a parasitic capacitor with the existing metal layer structure in the display panel to achieve the function of compensating the resistance and capacitance load. The metal wiring forms a parasitic capacitor with the data line extending along the second direction Y across which it crosses, and may also form a parasitic capacitor with the gate line extending along the first direction X not shown in the figure.

[0104] See also Figure 3 to Figure 6 , Figure 3 to Figure 6 They are respectively schematic diagrams of some metal routings according to an embodiment of the present application.

[0105] like Figure 3 / Figure 4 As shown, in one embodiment of the present application, the compensation structure includes:

[0106] a metal wiring 320 / 420 extending along the first direction X, wherein the metal wiring 320 / 420 is electrically connected to the second-type data line 302 / 402;

[0107] The metal wiring 320 / 420 crosses over at least one data line and forms a capacitor with at least the crossed data line.

[0108] In one embodiment, the metal trace 320 / 420 and the first connection portion 311 / 411 have the same length.

[0109] Furthermore, the metal wiring 320 / 420 and the first connection portion 311 / 411 are arranged at the same layer. The first connection portion 311 / 411 and the second connection portion 312 / 412 are arranged at different layers.

[0110] In one embodiment, one end point of the metal wiring is electrically connected to the second type data line. Figure 3 As shown, the first end O of the metal wiring 320 is electrically connected to the second type data line 302; Figure 4 As shown, the second end P of the metal wiring 420 is electrically connected to the second-type data line 402 .

[0111] Specifically, the metal wiring 320 can be further referred to in Fig.11 .

[0112] Fig.11This is a metal layer structure diagram where a metal routing is located according to an embodiment of the present application, wherein the metal routing 320 is electrically connected to the second-type data line 302 and crosses multiple data lines in the first direction X.

[0113] Fig.11 The unmarked parts are other metal layer structures arranged on the first source-drain metal layer and the second source-drain metal layer.

[0114] In another embodiment of the present application, Figure 5 As shown, the metal wiring 520 is electrically connected to the second-type data line 502 at a non-end point. Exemplarily, the metal wiring 520 is electrically connected to the second-type data line 502 at a midpoint Q.

[0115] In the figure, 511 is the first connection part, and 512 is the second connection part.

[0116] In one embodiment, the functional layer includes a first metal layer and a second metal layer, wherein the second metal layer is further away from the substrate than the first metal layer;

[0117] The data line is in a different layer from the metal wiring, and is respectively arranged in the same layer as one of the first metal layer and the second metal layer;

[0118] The metal wiring is connected to the second-type data line via.

[0119] For a display panel having two source-drain metal layers, the first metal layer is the first source-drain metal layer SD1 , and the second metal layer is the second source-drain metal layer SD2 .

[0120] Furthermore, for a display panel having three source-drain metal layers, a source-drain metal layer is further included between the first metal layer and the second metal layer, and when the metal routing is connected to the second-type data line via, a pad connection can be used when passing through the source-drain metal layer.

[0121] In some implementations, an auxiliary power line connected to VSS is provided in the display area to balance the voltage drop of VSS, namely, SIP (VSS in panel) technology.

[0122] For a display panel using SIP technology, the metal wiring can be set up using part of the power auxiliary line. Specifically, the power auxiliary line is etched to obtain a metal wiring with the same length as the first connecting portion, and the etched redundant part electrically isolated from the metal wiring is still connected to VSS.

[0123] Furthermore, if Figure 6In one embodiment of the present application, the display panel further includes a plurality of auxiliary power lines electrically connected to the low-voltage power line VSS of the display panel, wherein the plurality of auxiliary power lines at least include a first auxiliary power line 621 arranged at intervals along the second direction and extending along the first direction;

[0124] At least one first power auxiliary line 621 is disposed between two adjacent metal wirings 620 and penetrates the display area along a first direction.

[0125] In the figure, 611 is the first connection part, and 612 is the second connection part. In some embodiments, FIP routing can be performed based on SIP technology. For example, the first connection part 611 is formed by etching the auxiliary power line.

[0126] In a technical solution of the above display panel, the plurality of auxiliary power lines further include second auxiliary power lines arranged at intervals along the first direction and extending along the second direction. Figure 1 , wherein the power auxiliary line 12 includes a first power auxiliary line 121 and a second power auxiliary line 122 .

[0127] By arranging the first power auxiliary line 621 and the metal wiring 620 at intervals, the capacitance compensation is further made more uniform, and at the same time, no interference is caused to the voltage dispersion of VSS.

[0128] Furthermore, the present application also provides a display device, comprising the above-mentioned display panel.

[0129] The display device described in the present application may have all the features and advantages of the aforementioned display panel, which will not be described in detail here. Those skilled in the art can understand that the display device described in the present application may include but is not limited to the aforementioned display panel, and may also include other components or combinations of components, such as a touch sensor, a drive circuit, etc.

[0130] In another aspect, the present application provides a method for manufacturing a display panel, wherein the display panel comprises a display area and a peripheral area surrounding the display area, the peripheral area comprises a fan-out area arranged on one side of the display area, and the method comprises:

[0131] forming a plurality of data lines, wherein the plurality of data lines are arranged at intervals along a first direction and extend along a second direction intersecting the first direction, wherein the plurality of data lines include first-type data lines and second-type data lines;

[0132] forming a plurality of connection lines located in the display area, each connection line comprising a first connection portion extending along the first direction and a second connection portion extending along the second direction, wherein a first end of the first connection portion is electrically connected to a first-type data line and a second end thereof is electrically connected to the first end of the second connection portion across at least one data line in the first direction, and a second end of the second connection portion extends to the fan-out area in the second direction;

[0133] A compensation structure is formed, wherein the compensation structure is used to reduce the difference in resistance and capacitance loads on the second type of data line and the first type of data line.

[0134] Based on the above steps, the display panel in the above technical solution can be prepared.

[0135] In the above technical solution, a compensation structure is introduced to perform capacitance compensation on the non-FIP area to balance the resistance and capacitance load of the display panel, so that the color and brightness of the display panel are uniform, thereby improving the display effect.

[0136] It should be pointed out that although the various steps in the above embodiments are described in a specific order, those skilled in the art can understand that in order to achieve the effect of the present application, different steps do not have to be executed in such an order. They can be executed simultaneously (in parallel) or in other orders. These changes are within the scope of protection of the present application.

[0137] All the above optional technical solutions can be arbitrarily combined to form optional embodiments of the present application, which will not be described one by one here.

[0138] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0139] So far, the technical solutions of the present application have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present application is obviously not limited to these specific embodiments. Without departing from the principles of the present application, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present application.

Claims

1. A display panel comprising a display area and a peripheral area surrounding the display area, wherein the peripheral area includes a fan-out area arranged on one side of the display area, characterized in that: The display panel comprises: substrate; Multiple functional layers on the substrate, including: A plurality of data lines, the plurality of data lines are arranged at intervals along a first direction and extend along a second direction intersecting the first direction, wherein the plurality of data lines include first-type data lines and second-type data lines; a plurality of connection lines located in the display area, each connection line comprising a first connection portion extending along the first direction and a second connection portion extending along the second direction, wherein a first end of the first connection portion is electrically connected to a first-type data line and a second end thereof is electrically connected to the first end of the second connection portion across at least one data line in the first direction, and a second end of the second connection portion extends in the second direction to the fan-out area; A compensation structure is used to reduce the difference in resistance and capacitance loads between the second type of data lines and the first type of data lines.

2. The display panel according to claim 1, characterized in that: The compensation structure is a capacitor structure, comprising: The capacitor structure is located on the other side of the display area relative to the fan-out area in the peripheral area, and the capacitor structure includes a first electrode plate and a relative electrode plate, wherein the first electrode plate is electrically connected to the second type of data line, the first electrode plate and the relative electrode plate are respectively located on different layers of the multiple functional layers, and the first electrode plate and the relative electrode plate are electrically insulated by an insulating layer in the functional layer.

3. The display panel according to claim 2, characterized in that: The display panel is an LTPS display panel, including a thin film transistor and a storage capacitor, wherein the thin film transistor includes a first gate metal, and the storage capacitor includes a first storage capacitor plate arranged in the same layer as the first gate metal and a second storage capacitor plate arranged opposite to the first storage capacitor plate in a direction away from the substrate; The relative electrode plate is a second electrode plate, wherein the first electrode plate is disposed in the same layer as the first gate metal, and the second electrode plate is disposed in the same layer as the second storage capacitor electrode plate.

4. The display panel according to claim 2, characterized in that: The display panel is an LTPO display panel, comprising a first thin film transistor, a second thin film transistor and a storage capacitor, wherein the active layer materials of the first thin film transistor and the second thin film transistor are different, the first thin film transistor comprises a first gate metal, the second thin film transistor comprises a second gate metal, and the storage capacitor comprises a first storage capacitor plate arranged in the same layer as the first gate metal and a second storage capacitor plate arranged opposite to the first storage capacitor plate in a direction away from the substrate; The relative electrode plate includes a second electrode plate and a third electrode plate, the first electrode plate is located between the second electrode plate and the third electrode plate, wherein the first electrode plate and the second storage capacitor electrode plate are arranged in the same layer, the second electrode plate and the first gate metal are arranged in the same layer, and the third electrode plate and the second gate metal are arranged in the same layer.

5. The display panel according to claim 1, characterized in that: The compensation structure includes: a metal wiring extending along the first direction, wherein the metal wiring is electrically connected to the second type of data line; The metal wiring crosses over at least one data line and forms a capacitor with at least the crossed data line.

6. The display panel according to claim 5, characterized in that: The metal wiring has the same length as the first connecting portion.

7. The display panel according to claim 5, characterized in that: The metal wiring is arranged in the same layer as the first connecting portion.

8. The display panel according to claim 5, characterized in that: One end point of the metal wiring is electrically connected to the second-type data line.

9. The display panel according to claim 5, characterized in that: The metal wiring is electrically connected to the second-type data line at a non-end point position.

10. The display panel according to claim 5, characterized in that: The functional layer comprises a first metal layer and a second metal layer, wherein the second metal layer is further away from the substrate than the first metal layer; The data line is in a different layer from the metal wiring, and is respectively arranged in the same layer as one of the first metal layer and the second metal layer; The metal wiring is connected to the second-type data line via.

11. The display panel according to any one of claims 5 to 10, characterized in that: The display panel further comprises a plurality of auxiliary power lines electrically connected to the low-voltage power line of the display panel, wherein the plurality of auxiliary power lines at least comprise first auxiliary power lines arranged at intervals along the second direction and extending along the first direction; At least one first power auxiliary line is disposed between two adjacent metal wirings and penetrates the display area along a first direction.

12. The display panel according to claim 11, characterized in that: The plurality of auxiliary power lines further include second auxiliary power lines arranged at intervals along the first direction and extending along the second direction.

13. A display device, characterized in that: A display panel comprising any one of claims 1-12.

14. A method for preparing a display panel, wherein the display panel comprises a display area and a peripheral area surrounding the display area, the peripheral area comprising a fan-out area arranged on one side of the display area, characterized in that: The method comprises: forming a plurality of data lines, wherein the plurality of data lines are arranged at intervals along a first direction and extend along a second direction intersecting the first direction, wherein the plurality of data lines include first-type data lines and second-type data lines; forming a plurality of connection lines located in the display area, each connection line comprising a first connection portion extending along the first direction and a second connection portion extending along the second direction, wherein a first end of the first connection portion is electrically connected to a first-type data line and a second end thereof is electrically connected to the first end of the second connection portion across at least one data line in the first direction, and a second end of the second connection portion extends to the fan-out area in the second direction; A compensation structure is formed, wherein the compensation structure is used to reduce the difference in resistance and capacitance loads on the second type of data line and the first type of data line.

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