A method for quantum chip packaging to eliminate the influence of quasiparticles

Abstract

The present invention discloses a quantum chip packaging device for eliminating the influence of quasiparticles, which includes a shielding barrel bottom plate, a substrate, a packaging upper plate, a PCB board, a connecting plate component, a cover plate component, and a shielding barrel body. The shielding barrel bottom plate is located at the bottom end of the shielding barrel body. The substrate is provided with a first square hole, a second square hole, a third square hole, a fourth square hole, and a chip square hole. The interior of the packaging upper plate is provided with a fifth square hole, a sixth square hole, a seventh square hole, an eighth square hole, and a central square hole. The connecting plate component includes a first connecting plate and a second connecting plate. The first connecting plate is placed on the PCB board; the second connecting plate is placed in the fifth square hole, the sixth square hole, the seventh square hole, and the eighth square hole. The cover plate component includes a first cover plate, a second cover plate, a third cover plate, and a central cover plate. The shielding barrel body is assembled with the shielding barrel bottom plate and the packaging upper plate. The present invention realizes high integration, magnetic shielding, and stable performance under extremely low temperature environments, can effectively reduce quasiparticle interference, and ensure high stability of quantum computing.

Description

Technical Field

[0001] The present invention relates to the technical field of quantum chip packaging, and particularly to a quantum chip packaging method for eliminating the influence of quasiparticles. Background Art

[0002] The research on quantum technology has become a major focus of current world scientific and technological research. Among them, the research on quantum computers is an important direction in the field of quantum technology. Quantum computers have far superior computing capabilities compared to classical computers, and the number and quality of their core components - qubits (quantum bits) directly determine the computing power of the computer. To further improve the computing power of quantum computers, it is necessary to continuously expand the number of qubits and integrate them onto high-density quantum chips. However, as the size of quantum chips continues to increase, the influence of their packaging structure on qubits becomes increasingly obvious.

[0003] In the field of quantum chip packaging technology, the influence of quasiparticles has become an important factor restricting the performance of qubits. Quasiparticles refer to excited-state particles generated by the destruction of Cooper pairs in superconducting materials at low temperatures. The transport and accumulation of these quasiparticles in quantum chips will cause energy relaxation of superconducting qubits, thereby shortening the coherence time of qubits and affecting the stability of quantum computing. Existing quantum chip packaging technologies usually use superconducting shielding layers or cryogenic treatments to suppress the influence of quasiparticles, but it is still difficult to effectively control the transport and accumulation of quasiparticles in the chip, resulting in the inability to further improve the coherence time of qubits. Summary of the Invention

[0004] The purpose of this part is to outline some aspects of the embodiments of the present invention and briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this part, as well as in the abstract and title of the specification of this application, to avoid obscuring the purpose of this part, the abstract, and the title. However, such simplifications or omissions cannot be used to limit the scope of the present invention.

[0005] To solve the above technical problems, the present invention provides the following technical solution: A quantum chip packaging device for eliminating the influence of quasiparticles, mainly including:

[0006] A shielding barrel bottom plate, which is located at the bottom end of the shielding barrel body and is provided with a first groove, a second groove, and a third groove thereon;

[0007] A substrate, which is provided with a first square hole, a second square hole, a third square hole, a fourth square hole for placing a connector, and a chip square hole for placing a quantum chip;

[0008] A packaging upper plate, which is of a cylindrical structure and internally provided with a fifth square hole, a sixth square hole, a seventh square hole, an eighth square hole, and a central square hole, and the central square hole is located at the center of the packaging upper plate;

[0009] A PCB board, and the PCB board is placed on a substrate;

[0010] A connecting plate component, which includes a first connecting plate and a second connecting plate. The first connecting plate is placed on the PCB board; the second connecting plate is placed in the fifth square hole, the sixth square hole, the seventh square hole and the eighth square hole;

[0011] A cover plate component, which includes a first cover plate, a second cover plate, a third cover plate and a center cover plate, and are respectively encapsulated at different positions to protect internal components;

[0012] The body of a shielding barrel, which is assembled with a shielding barrel bottom plate and a packaging upper plate to form the peripheral shielding structure of the packaging device.

[0013] As a preferred solution of the quantum chip packaging device for eliminating the influence of quasiparticles according to the present invention, wherein: the shielding barrel bottom plate includes a bottom plate outer wall and a bottom plate inner wall. Among them, the outer diameter of the bottom plate outer wall is greater than the outer diameter of the bottom plate inner wall, and the protruding thickness of the bottom plate outer wall relative to the bottom plate inner wall matches the wall thickness of the body of the shielding barrel.

[0014] As a preferred solution of the quantum chip packaging device for eliminating the influence of quasiparticles according to the present invention, wherein: the packaging upper plate includes an upper plate outer wall and an upper plate inner wall. The outer diameter of the upper plate outer wall is greater than the outer diameter of the upper plate inner wall, and the protruding thickness of the upper plate outer wall relative to the upper plate inner wall matches the wall thickness of the body of the shielding barrel; the positions of the fifth square hole, the sixth square hole, the seventh square hole and the eighth square hole are coaxially arranged with the positions of the first square hole, the second square hole, the third square hole and the fourth square hole on the substrate respectively.

[0015] As a preferred solution of the quantum chip packaging device for eliminating the influence of quasiparticles according to the present invention, wherein: the size of the first connecting plate is set according to the size and quantity of connectors, and the position of the first connecting plate corresponds to the first square hole, the second square hole, the third square hole and the fourth square hole on the substrate. The first connecting plate is provided with connecting holes for fixing connectors, and threaded holes are provided on the protruding parts on both sides of the first connecting plate. The first connecting plate, the PCB board and the substrate are fixedly connected by screws; the second connecting plate is provided with connecting holes for fixing connectors, and threaded holes are provided on the protruding parts on both sides of the second connecting plate. The packaging upper plate is provided with threaded holes coaxially corresponding to the second connecting plate. The second connecting plate and the substrate are fixedly connected by screws.

[0016] As a preferred solution of the quantum chip packaging device for eliminating the influence of quasiparticles according to the present invention, the following is provided: The first cover plate is packaged below the first square hole, the second square hole, the third square hole, and the fourth square hole, and the first cover plate is placed in the second groove. Both sides of the first cover plate are provided with arc protrusions, and the arc protrusions are placed in the third groove. A threaded hole is provided in the middle of the protruding arc. The first cover plate and the substrate are fixedly connected by screws; The second cover plate is packaged below the chip square hole. A groove is provided at the top of the second cover plate for chip wire bonding. The second cover plate is placed in the first groove and fixedly connected to the substrate by screws; The third cover plate is packaged above the chip and fixedly connected to the PCB board by screws; The third cover plate is embedded in the middle part surrounded by the first connecting plate, and the thickness of the third cover plate is the same as the thickness of the first connecting plate; The center cover plate is placed in the center square hole for packaging the center square hole. The center cover plate adopts a trapezoidal structure design, with the upper layer size larger than the lower layer size. The center cover plate and the packaging upper plate are fixedly connected by screws;

[0017] The inner wall of the shielding barrel body is coated with an infrared glue coating. The shielding barrel bottom plate, the substrate, the first connecting plate, the second connecting plate, the first cover plate, the center cover plate, the packaging upper plate, and the shielding barrel body are all made of oxygen-free copper. The second cover plate and the third cover plate are made of permalloy.

[0018] A packaging method applied to the above-mentioned quantum chip packaging device for eliminating the influence of quasiparticles, the method comprising:

[0019] Step 1: Deposit a superconducting material layer with a high critical temperature on the inner walls of the shielding barrel bottom plate, the shielding barrel body, and the packaging upper plate to form a superconducting layer intershielding structure, and coat an infrared glue coating inside the shielding barrel body;

[0020] Step 2: Coat a doped graphene superconductor low-energy state trap material layer on the surfaces of the substrate and the PCB board, especially increasing the coating thickness around the chip square hole, and optimizing the trap energy state distribution by low-temperature heat treatment to capture quasiparticles and confine them in local minimum potential wells;

[0021] Step 3: Deposit a quantum dot adsorption layer on the inner wall of the chip square hole and the surface of the inner center square hole of the packaging upper plate;

[0022] Step 4: Assemble the shielding barrel body, the shielding barrel bottom plate, the packaging upper plate, the substrate, the PCB board, the cover plate components, and the connecting plate components to form a complete packaging structure, and introduce a microstructural diversion layer into the first groove, the second groove, and the third groove to make the captured quasiparticles diffuse to the low-temperature region;

[0023] Step 5: Under a low-temperature environment, perform multi-dimensional performance tests on the packaging structure, and judge the quasiparticle suppression ability according to the multi-dimensional performance test results.

[0024] As a preferred solution of the method for packaging a quantum chip to eliminate the influence of quasiparticles according to the present invention, wherein: in step five, multi-dimensional performance testing is performed on the packaging structure, including the following steps:

[0025] Use cryogenic probe scanning technology or microwave resonance measurement to measure the quasiparticle density at different positions, record the number and distribution of quasiparticles, and calculate the change in quasiparticle density , and the calculation formula is:

[0026]

[0027] Wherein: is the number of quasiparticles per unit volume, is the volume of the measurement area;

[0028] Test the energy dissipation effect of quasiparticles through the quantum dot adsorption layer, use a nanoscale thermal probe to measure the kinetic energy conversion of quasiparticles in the adsorption layer, and calculate its energy dissipation efficiency according to the energy consumption efficiency of quasiparticles in the quantum dot layer , and compare it with the theoretical expected value to evaluate the quasiparticle dissipation ability of the adsorption layer. Among them, the energy dissipation efficiency The calculation formula of is:

[0029]

[0030] Wherein: represents the dissipated energy, represents the total energy of quasiparticles;

[0031] Test the qubits using the standard qubit coherence time measurement method, and record the coherence time of the qubits under different packaging schemes , and compare it with the benchmark value without any quasiparticle suppression scheme;

[0032] Adopt quantum current transmission measurement technology or microwave reflection measurement, and compare the quasiparticle transmittance of different layers , to obtain the effective shielding ability of each layer in the packaging structure; among them, the quasiparticle transmittance The calculation formula of is:

[0033]

[0034] Wherein, is the quasiparticle current intensity passing through the material, is the incident quasiparticle current intensity.

[0035] As a preferred embodiment of the quantum chip packaging method for eliminating the influence of quasiparticles according to the present invention, wherein: the quasiparticle suppression ability of the packaging structure is related to the change in quasiparticle density , energy dissipation efficiency , coherence time of qubits and quasiparticle transmittance ; the mathematical expression of the quasiparticle suppression ability is:

[0036]

[0037] Wherein:

[0038] is a comprehensive index used to quantify the suppression effect of different packaging schemes on quasiparticles;

[0039] change in quasiparticle density, representing the change in quasiparticle concentration at the position and time of the packaging material;

[0040] is the exponential decay factor, representing the decay effect of quasiparticles during propagation in space. As the distance increases, the quasiparticle density decays exponentially. Among them, is the attenuation coefficient of the material, reflecting the shielding ability of the material against quasiparticles;

[0041] is the energy dissipation efficiency function, which is the efficiency of converting quasiparticle kinetic energy into thermal energy or other forms of energy in quantum dots or other material layers;

[0042] is the Gaussian decay factor, describing the influence of quasiparticle kinetic energy on energy dissipation. As the quasiparticle kinetic energy increases, the energy dissipation efficiency shows a decaying trend, is the decay coefficient related to quasiparticle kinetic energy and material properties;

[0043] represents the spatial integration region for calculating the change in quasiparticle density over the entire packaging region;

[0044] represents the total effect of energy dissipation on all quasiparticles;

[0045] describes the combined effect of coherence time and transmittance. As the transmittance increases, the coherence time decreases, showing the effect of the packaging on quasiparticle suppression;

[0046] is a regulation factor, indicating the influence of the encapsulation design on the transmittance;

[0047] is the coherence time of the qubit, indicating the time that the qubit can maintain its quantum state without external interference;

[0048] is the quasiparticle transmittance, indicating the shielding effect of the encapsulation layer on quasiparticles and measuring the transmittance of different shielding layers to quasiparticles;

[0049] represents the volume of the encapsulation;

[0050] represents the surface area of the encapsulation;

[0051] Value range meaning:

[0052] When > 0.8, it indicates that the quasiparticle suppression effect of the encapsulation scheme is good and is suitable for long-term stable operation;

[0053] When 0.5 < ≤ 0.8, it indicates that the encapsulation scheme needs to be optimized;

[0054] When ≤ 0.5, it indicates that the quasiparticle suppression effect of the encapsulation scheme is poor and the materials and structure need to be redesigned.

[0055] As a preferred scheme of a quantum chip encapsulation method for eliminating the influence of quasiparticles according to the present invention, wherein: a dynamic quasiparticle transport control mechanism is introduced into the encapsulation structure, and through an adjustable microstructure channel, quasiparticles are guided to move towards the energy dissipation region to improve the quasiparticle suppression ability of the encapsulation.

[0056] As a preferred scheme of a quantum chip encapsulation method for eliminating the influence of quasiparticles according to the present invention, wherein: the dynamic quasiparticle transport control mechanism includes the following steps:

[0057] Integrate an adjustable microstructure channel inside the encapsulation layer, and the channel forms a periodic potential field through a superconducting microbridge or a quantum dot array to guide quasiparticles to diffuse towards the low-temperature region;

[0058] Adjust the transport characteristics of the microstructure channel through a low-temperature electric field or magnetic field to dynamically optimize the movement direction and distribution of quasiparticles;

[0059] Add a real-time monitoring system outside the encapsulation, combine microwave resonance measurement and nanoscale thermal probe to analyze the density distribution of quasiparticles, and adjust the opening and closing state of the microstructure channel according to the monitoring data to enhance the shielding ability of the encapsulation structure;

[0060] Combine the mathematical expression of quasiparticle suppression ability and dynamically adjust the exponential decay factor The coefficient in And the Gaussian decay factor The coefficient in To maximize the dissipation efficiency of quasiparticles and improve the shielding performance of the overall package.

[0061] Advantages of the present invention:

[0062] 1. The packaging device proposed in the present invention can achieve high integration, magnetic shielding, and still maintain good performance in an extremely low-temperature environment. In addition, the components of the entire device are simple, easy to assemble, and easy to mass-produce.

[0063] 2. The present invention reduces the interference of quasiparticles on qubits from multiple dimensions by introducing a high critical temperature superconducting material layer, a low-energy state trap material layer doped with graphene, and a quantum dot adsorption layer inside the packaging structure. Among them, the trap material layer can capture and confine quasiparticles in local potential wells, and the quantum dot adsorption layer can efficiently dissipate the energy of quasiparticles, thereby reducing its impact on the coherence time of qubits. At the same time, a microstructural diversion layer and a dynamic transport control mechanism are adopted to guide quasiparticles to diffuse towards the low-temperature energy dissipation area, further enhancing the shielding ability of the packaging structure, thereby significantly reducing the quasiparticle density, improving the coherence time of qubits, and ensuring the high stability and long life of quantum computing.

[0064] 3. The present invention integrates a dynamic quasiparticle transport control mechanism in the packaging structure, uses adjustable microstructural channels to guide quasiparticles to move towards specific dissipation regions, and adjusts the transport characteristics of the microstructural channels through a low-temperature electric field or magnetic field to improve the quasiparticle shielding effect. At the same time, the real-time monitoring system combines microwave resonance measurement and nanoscale thermal probe technology to dynamically adjust the material coefficients, enabling the packaging structure to maintain the best quasiparticle shielding ability in different environments. In addition, through the dynamic adjustment of the exponential decay factor and the Gaussian decay factor, the dissipation efficiency of quasiparticles is maximized, ensuring that the quantum chip package has long-term stable anti-interference ability and meets the quantum computing requirements under different temperature and environmental conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts. Among them:

[0066] Figure 1 It is a schematic diagram of the overall assembled structure of a quantum chip packaging device for eliminating the influence of quasiparticles of the present invention.

[0067] Figure 2 This is a schematic diagram of the disassembly of a quantum chip packaging device for eliminating the influence of quasiparticles according to the present invention.

[0068] Figure 3 This is a schematic diagram of the structure of the substrate of a quantum chip packaging device for eliminating the influence of quasiparticles according to the present invention.

[0069] Figure 4 This is a schematic diagram of the structure of the bottom plate of the shielding barrel of a quantum chip packaging device for eliminating the influence of quasiparticles according to the present invention.

[0070] Figure 5 This is a schematic diagram of the structure of the upper packaging plate of a quantum chip packaging device for eliminating the influence of quasiparticles according to the present invention.

[0071] In the figure: 1. Bottom plate of the shielding barrel; 101. First groove; 102. Second groove; 103. Third groove; 104. Inner wall of the bottom plate; 105. Outer wall of the bottom plate; 2. Substrate; 201. First square hole; 202. Second square hole; 203. Third square hole; 204. Fourth square hole; 205. Chip square hole; 3. Barrel body of the shielding barrel; 4. Upper packaging plate; 401. Fifth square hole; 402. Sixth square hole; 403. Seventh square hole; 404. Eighth square hole; 405. Central square hole; 406. Inner wall of the upper plate; 407. Outer wall of the upper plate; 5. PCB board; 6. First connecting plate; 7. First cover plate; 8. Second cover plate; 9. Third cover plate; 10. Second connecting plate; 11. Central cover plate. Specific embodiments

[0072] In order to make the above objects, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings of the specification.

[0073] In the following description, many specific details are set forth in order to fully understand the present invention. However, the present invention can also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the connotation of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.

[0074] Secondly, the so-called "one embodiment" or "embodiment" herein refers to a specific feature, structure or characteristic that can be included in at least one implementation manner of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments.

[0075] Next, the present invention will be described in detail with reference to the schematic diagrams. When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional views showing the device structure will be locally enlarged out of the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention herein. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0076] Embodiment 1

[0077] Referring to Figures 1-5 , an embodiment of the present invention provides a quantum chip packaging device for eliminating the influence of quasiparticles, including:

[0078] The shielding barrel bottom plate 1, as Figure 4 , the shielding barrel bottom plate 1 is a cylinder, supporting the entire assembly structure. The shielding barrel bottom plate 1 is located at the bottom end of the shielding barrel body 3, and is provided with a first groove 101, a second groove 102, and a third groove 103 thereon; in addition, the shielding barrel bottom plate 1 includes a bottom plate outer wall 105 and a bottom plate inner wall 104. Among them, the outer diameter of the bottom plate outer wall 105 is greater than the outer diameter of the bottom plate inner wall 104, and the protruding thickness of the bottom plate outer wall 105 relative to the bottom plate inner wall 104 matches the wall thickness of the shielding barrel body 3.

[0079] The substrate 2, as Figure 3 , the substrate 2 is provided with a first square hole 201, a second square hole 202, a third square hole 203, a fourth square hole 204 for placing connectors, and a chip square hole 205 for placing a quantum chip.

[0080] The packaging upper plate 4, the packaging upper plate 4 is a cylinder structure, and is internally provided with a fifth square hole 401, a sixth square hole 402, a seventh square hole 403, an eighth square hole 404, and a central square hole 405. The central square hole 405 is placed at the central position of the packaging upper plate 4.

[0081] The PCB board 5, the PCB board 5 is placed on the substrate 2.

[0082] The connecting plate component, the connecting plate component includes a first connecting plate 6 and a second connecting plate 10. The first connecting plate 6 is placed on the PCB board 5; the second connecting plate 10 is placed in the fifth square hole 401, the sixth square hole 402, the seventh square hole 403, and the eighth square hole 404.

[0083] The cover plate component, the cover plate component includes a first cover plate 7, a second cover plate 8, a third cover plate 9, and a central cover plate 11, which are respectively packaged at different positions to protect the internal components.

[0084] The shielding barrel body 3, the shielding barrel body 3 is assembled with the shielding barrel bottom plate 1 and the packaging upper plate 4 to form the peripheral shielding structure of the packaging device.

[0085] Specifically, as Figure 5, the upper encapsulation board 4 includes an outer wall 407 and an inner wall 406 of the upper board. The outer diameter of the outer wall 407 of the upper board is greater than the outer diameter of the inner wall 406 of the upper board, and the protruding thickness of the outer wall 407 of the upper board relative to the inner wall 406 of the upper board matches the wall thickness of the shielding barrel body 3. The positions of the fifth square hole 401, the sixth square hole 402, the seventh square hole 403, and the eighth square hole 404 are coaxially arranged with the positions of the first square hole 201, the second square hole 202, the third square hole 203, and the fourth square hole 204 on the substrate 2 respectively.

[0086] As Figure 2 , the size of the first connecting plate 6 is set according to the size and quantity of the connectors, and the position of the first connecting plate 6 corresponds to the first square hole 201, the second square hole 202, the third square hole 203, and the fourth square hole 204 on the substrate 2. The first connecting plate 6 is provided with connection holes for fixing the connectors, and threaded holes are provided on the protruding parts on both sides of the first connecting plate 6. The first connecting plate 6, the PCB board 5, and the substrate 2 are fixedly connected by screws.

[0087] The second connecting plate 10 is provided with connection holes for fixing the connectors, and threaded holes are provided on the protruding parts on both sides of the second connecting plate 10. The upper encapsulation board 4 is provided with threaded holes coaxially corresponding to the second connecting plate 10. The second connecting plate 10 and the substrate 2 are fixedly connected by screws.

[0088] As Figure 2 , the first cover plate 7 is encapsulated below the first square hole 201, the second square hole 202, the third square hole 203, and the fourth square hole 204, and the first cover plate 7 is placed in the second groove 102. Both sides of the first cover plate 7 are provided with arc protrusions, and the arc protrusions are placed in the third groove 103. A threaded hole is provided in the middle of the protruding arc. The first cover plate 7 and the substrate 2 are fixedly connected by screws.

[0089] The second cover plate 8 is encapsulated below the chip square hole 205. The top of the second cover plate 8 is provided with a groove for chip wire bonding. The second cover plate 8 is placed in the first groove 101 and is fixedly connected to the substrate 2 by screws.

[0090] The third cover plate 9 is embedded in the middle part surrounded by the first connecting plate 6, and the thickness of the third cover plate 9 is the same as the thickness of the first connecting plate 6. The third cover plate 9 is encapsulated above the chip and is fixedly connected to the PCB board 5 by screws.

[0091] The center cover plate 11 is placed in the center square hole 405 for encapsulating the center square hole 405. The center cover plate 11 adopts a trapezoidal structure design, with the upper layer size larger than the lower layer size. The center cover plate 11 is provided with threaded holes, and the corresponding positions on the upper encapsulation board 4 are provided with threaded holes coaxially corresponding to the center cover plate 11. The center cover plate 11 and the upper encapsulation board 4 are fixedly connected by screws.

[0092] The inner wall of the shielding barrel body 3 is coated with an infrared glue coating. The shielding barrel bottom plate 1, the substrate 2, the first connecting plate 6, the second connecting plate 10, the first cover plate 7, the central cover plate 11, the encapsulation upper plate 4, and the shielding barrel body 3 are all made of oxygen-free copper, and the second cover plate 8 and the third cover plate 9 are made of permalloy.

[0093] The oxygen-free copper material used in the present invention enables the quantum encapsulation design to still maintain good performance in an ultra-low temperature environment, achieving the effects of high integration, high thermal conductivity, and magnetic shielding, and can quickly dissipate the heat generated during the operation of the quantum chip. The overall structure of the device is very strong and reliable, and the components constituting the device are simple, easy to assemble, and mass-produced.

[0094] Using the encapsulation method of the above-mentioned quantum chip encapsulation device for eliminating the influence of quasiparticles, the method includes:

[0095] Step 1: Deposit a superconducting material layer with a high critical temperature on the inner walls of the shielding barrel bottom plate, the shielding barrel body, and the encapsulation upper plate to form a superconducting layer intershielding structure, and coat an infrared glue coating inside the shielding barrel body to enhance the heat radiation absorption and shielding effect and improve the low-temperature performance of the encapsulation system; among them, the superconducting layer intershielding structure adopts a multi-layer superconducting-insulator-superconductor (SIS) structure design, and the coverage uniformity is optimized by low-temperature plasma enhanced deposition (PECVD) technology, thereby forming an effective quasiparticle shielding barrier and reducing the diffusion of quasiparticles into the quantum chip area.

[0096] Step 2: Coat a low-energy trap material layer of a superconductor doped with graphene (such as NbSe2 + graphene) or alumina) on the surfaces of the substrate and the PCB board, especially increase the coating thickness around the chip square hole, and optimize the trap energy state distribution by low-temperature heat treatment to capture quasiparticles and confine them in local minimum potential wells to improve the quasiparticle dissipation ability. Among them, the minimum potential well refers to in the low-energy trap material layer of the superconductor doped with graphene, by adjusting the energy state distribution of the material and optimizing the treatment, so that quasiparticles (such as quasiparticle excited electrons in the superconducting system or single electrons after the Cooper pair breaks) are confined in a local low-energy region (i.e., the minimum potential well), thereby reducing their interference with the quantum chip.

[0097] Specifically, the minimum potential well has the following characteristics:

[0098] Local low-energy region: Due to the doping and low-temperature heat treatment of the material, the potential energy of some local regions is lower than that of the surrounding regions, forming a "trap" effect, making quasiparticles tend to stay in this region.

[0099] Quasiparticle capture ability: By adjusting the energy band structure of the superconductor material doped with graphene, the depth and density of these minimum potential wells can be adjusted, enabling them to effectively capture and confine quasiparticles and reduce their diffusion into the chip interior.

[0100] Step 3: Deposit a semiconductor quantum dot adsorption layer such as PbSe or InAs on the inner wall of the square hole of the chip and the surface of the central square hole inside the upper encapsulation board, so as to actively dissipate the kinetic energy of quasiparticles by using the local electron-phonon coupling effect, and ensure the uniform distribution of quantum dots through chemical vapor deposition (CVD) or spraying nanomaterials method, thereby enhancing the active consumption ability of the encapsulation system for quasiparticles.

[0101] Step 4: Assemble the shielding barrel body, shielding barrel bottom plate, upper encapsulation board, substrate, PCB board, cover plate component and connecting plate component to form a complete encapsulation structure, and introduce a microstructural diversion layer into the first groove, the second groove and the third groove, so that the captured quasiparticles diffuse towards the low-temperature region. At the same time, optimize the thickness and number of layers of the encapsulation material through low-temperature probe scanning (LT-SPM) or microwave resonance measurement to enhance the quasiparticle suppression effect.

[0102] Step 5: Under a low-temperature environment, conduct multi-dimensional performance tests on the encapsulation structure, and judge the quasiparticle suppression ability according to the results of the multi-dimensional performance tests.

[0103] Specifically, the multi-dimensional performance test of the encapsulation structure includes the following steps:

[0104] Use low-temperature probe scanning technology or microwave resonance measurement to measure the quasiparticle density at different positions, record the number and distribution of quasiparticles, and calculate the change in quasiparticle density , and the calculation formula is:

[0105]

[0106] where: is the number of quasiparticles per unit volume, is the volume of the measurement area;

[0107] Test the energy dissipation effect of quasiparticles by the quantum dot adsorption layer, use a nanoscale thermal probe to measure the kinetic energy conversion of quasiparticles in the adsorption layer, and calculate its energy dissipation efficiency according to the energy consumption efficiency of quasiparticles in the quantum dot layer , and compare it with the theoretical expected value to evaluate the quasiparticle dissipation ability of the adsorption layer. Among them, the energy dissipation efficiency has the following calculation formula:

[0108]

[0109] where: represents the dissipated energy, represents the total energy of quasiparticles;

[0110] Test the qubits using standard qubit coherence time measurement methods and record the coherence time of the qubits under different packaging schemes. And compare it with the benchmark value without any quasiparticle suppression scheme;

[0111] Adopt quantum current transmission measurement technology or microwave reflection measurement, and obtain the effective shielding ability of each layer in the packaging structure by comparing the quasiparticle transmission rates of different layers ; The calculation formula for the quasiparticle transmission rate is:

[0112]

[0113] Where, is the quasiparticle current intensity through the material, is the incident quasiparticle current intensity.

[0114] Further, the quasiparticle suppression ability of the packaging structure is related to the change in quasiparticle density , energy dissipation efficiency , qubit coherence time and quasiparticle transmission rate ; The mathematical expression for the quasiparticle suppression ability is:

[0115]

[0116] Where:

[0117] is a comprehensive index used to quantify the suppression effect of different packaging schemes on quasiparticles;

[0118] The change in quasiparticle density indicates the change in quasiparticle concentration at the position and time of the packaging material;

[0119] is the exponential decay factor, indicating the decay effect of quasiparticles when propagating in space. As the distance increases, the quasiparticle density will decay exponentially. Among them, is the attenuation coefficient of the material, reflecting the shielding ability of the material against quasiparticles, and the specific value is obtained by fitting experimental data;

[0120] is the energy dissipation efficiency function, which is the efficiency of converting quasiparticle kinetic energy into thermal energy or other forms of energy in quantum dots or other material layers;

[0121] is the Gaussian decay factor, which describes the kinetic energy of quasiparticles and its influence on energy dissipation. As the kinetic energy of quasiparticles increases, the energy dissipation efficiency shows a decaying trend. is the decay coefficient related to the kinetic energy of quasiparticles and material properties;

[0122] represents the spatial integration region used to calculate the change in quasiparticle density over the entire encapsulation area;

[0123] represents the total effect of energy dissipation for all quasiparticles;

[0124] describes the combined effect of the coherence time and the transmittance. As the transmittance increases, the coherence time decreases, showing the effect of the encapsulation on suppressing quasiparticles;

[0125] is the adjustment factor, indicating the influence of the encapsulation design on the transmittance;

[0126] is the qubit coherence time, which represents the time that a qubit can maintain its quantum state without external interference. is the adjustment factor under the influence of environmental factors (such as temperature, magnetic field, etc.);

[0127] is the quasiparticle transmittance, which represents the shielding effect of the encapsulation layer on quasiparticles and measures the degree of quasiparticle transmission through different shielding layers (such as superconducting layers, trap coatings);

[0128] represents the volume of the encapsulation;

[0129] represents the surface area of the encapsulation;

[0130] Value range meaning:

[0131] When > 0.8, it indicates that the quasiparticle suppression effect of the encapsulation scheme is good and suitable for long-term stable operation;

[0132] When 0.5 < ≤ 0.8, it indicates that the encapsulation scheme needs to be optimized, especially in terms of energy dissipation or coherence time;

[0133] When ≤ 0.5, it indicates that the quasiparticle suppression effect of the encapsulation scheme is poor and the materials and structure need to be redesigned.

[0134] This formula adopts a comprehensive integral form, combining the physical mechanisms of quasiparticle density, energy dissipation, qubit coherence time, and transmittance, reflecting the multi-dimensional impact of different packaging schemes on quasiparticle suppression.

[0135] Furthermore, a dynamic quasiparticle transport control mechanism is introduced into the packaging structure. Through adjustable microstructural channels, quasiparticles are guided to the energy dissipation region to improve the quasiparticle suppression ability of the packaging. The dynamic quasiparticle transport control mechanism includes the following steps:

[0136] Integrate adjustable microstructural channels inside the packaging layer. The channels form a periodic potential field through superconducting microbridges or quantum dot arrays to guide quasiparticles to diffuse to the low-temperature region;

[0137] Adjust the transport characteristics of the microstructural channels through a low-temperature electric field or magnetic field to dynamically optimize the motion direction and distribution of quasiparticles, so as to improve the overall energy dissipation efficiency;

[0138] Add a real-time monitoring system outside the packaging. Combine microwave resonance measurement and nanoscale thermal probes to analyze the density distribution of quasiparticles, and adjust the opening and closing states of the microstructural channels according to the monitoring data to enhance the shielding ability of the packaging structure;

[0139] Combine with the mathematical expression of the quasiparticle suppression ability and dynamically adjust the coefficient in the and the coefficient in the of the Gaussian decay factor to maximize the dissipation efficiency of quasiparticles and improve the overall shielding performance of the packaging.

[0140] In summary, by introducing a superconducting material layer with a high critical temperature, a low-energy state trap material layer doped with graphene, and a quantum dot adsorption layer inside the encapsulation structure, the present invention reduces the interference of quasiparticles to qubits from multiple dimensions. Among them, the trap material layer can capture and confine quasiparticles in local potential wells, and the quantum dot adsorption layer can efficiently dissipate the energy of quasiparticles, thereby reducing its impact on the coherence time of qubits. At the same time, a microstructural diversion layer and a dynamic transport control mechanism are adopted to guide quasiparticles to diffuse towards the low-temperature energy dissipation region, further enhancing the shielding ability of the encapsulation structure, thereby significantly reducing the quasiparticle density, increasing the coherence time of qubits, and ensuring the high stability and long lifespan of quantum computing. The present invention integrates a dynamic quasiparticle transport control mechanism in the encapsulation structure, uses adjustable microstructural channels to guide quasiparticles to move towards specific dissipation regions, and adjusts the transport characteristics of the microstructural channels through a low-temperature electric field or magnetic field to improve the quasiparticle shielding effect. At the same time, the real-time monitoring system combines microwave resonance measurement and nanoscale thermal probe technology to dynamically adjust the material coefficients, enabling the encapsulation structure to maintain the best quasiparticle shielding ability under different environments. In addition, by dynamically adjusting the exponential decay factor and the Gaussian decay factor, the dissipation efficiency of quasiparticles is maximized, ensuring that the quantum chip encapsulation has long-term stable anti-interference ability and adapts to the quantum computing requirements under different temperatures and environmental conditions.

[0141] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention, and they should all be covered within the scope of the claims of the present invention.

Claims

1. A quantum chip packaging method for eliminating the influence of quasiparticles, characterized in that, It includes the following steps: Step 1: Deposit a superconducting material layer with a high critical temperature on the bottom plate of the shielding barrel, the barrel body of the shielding barrel, and the inner wall of the encapsulation upper plate to form a superconducting layer - to - layer shielding structure, and coat an infrared glue coating inside the barrel body of the shielding barrel; Step 2: Coat a doped graphene superconductor low - energy state trap material layer on the surfaces of the substrate and the PCB board, especially increase the coating thickness around the chip square hole, and use low - temperature heat treatment to optimize the trap energy state distribution to capture quasiparticles and confine them in local minimum potential wells; Step 3: Deposit a quantum dot adsorption layer on the inner wall of the chip square hole and the surface of the central square hole inside the encapsulation upper plate; Step 4: Assemble the barrel body of the shielding barrel, the bottom plate of the shielding barrel, the encapsulation upper plate, the substrate, the PCB board, the cover plate component, and the connecting plate component to form a complete encapsulation structure, and introduce a micro - structure diversion layer into the first groove, the second groove, and the third groove to make the captured quasiparticles diffuse towards the low - temperature region; Step 5: Under a low - temperature environment, conduct multi - dimensional performance tests on the encapsulation structure, and judge the quasiparticle suppression ability according to the results of the multi - dimensional performance tests; The multi - dimensional performance tests on the encapsulation structure in Step 5 include the following steps: Measure the quasiparticle density at different positions using low-temperature probe scanning technology or microwave resonance measurement, record the number and distribution of quasiparticles, and calculate the change in quasiparticle density , and the calculation formula is as follows: Wherein: is the number of quasiparticles per unit volume, is the volume of the measurement region, is the position of the encapsulating material, is the time; Test the energy dissipation effect of quasiparticles through the quantum dot adsorption layer, measure the kinetic energy conversion of quasiparticles in the adsorption layer using a nanoscale thermal probe, and calculate its energy dissipation efficiency based on the energy consumption efficiency of quasiparticles in the quantum dot layer , and compare it with the theoretical expected value to evaluate the quasiparticle dissipation ability of the adsorption layer. Among them, the energy dissipation efficiency is calculated by the formula: Wherein: represents the dissipated energy, represents the total energy of quasiparticles, represents the quasiparticle kinetic energy; Test the qubits using standard qubit coherence time measurement methods and record the coherence times of the qubits under different packaging schemes and compare them with the benchmark values without any quasiparticle suppression scheme is the adjustment factor under the influence of environmental factors Adopt quantum current transmission measurement technology or microwave reflection measurement, and obtain the effective shielding ability of each layer in the encapsulation structure by comparing the quasiparticle transmission rates of different layers , and obtain the effective shielding ability of each layer in the encapsulation structure; where the calculation formula of the quasiparticle transmission rate is as follows: Among them, is the quasiparticle current intensity of the material, is the current intensity of the incident quasiparticles.

2. The method for packaging a quantum chip to eliminate the influence of quasiparticles according to claim 1, wherein: The quasiparticle suppression ability of the encapsulation structure and the change amount of the quasiparticle density , the energy dissipation efficiency , the coherence time of the qubit and the quasiparticle transmittance are related; the mathematical expression of the quasiparticle suppression ability is: Among them: is a comprehensive index used to quantify the suppression effect of different packaging schemes on quasiparticles; The change in quasiparticle density, indicating the change in the concentration of quasiparticles at the position and time of the encapsulation material and time of the encapsulation material; is the exponential decay factor, representing the decay effect of quasiparticles during propagation in space. As the distance increases, the quasiparticle density decays exponentially, where is the attenuation coefficient of the material, reflecting the screening ability of the material for quasiparticles; is the energy dissipation efficiency function, which is the efficiency at which the kinetic energy of quasiparticles is converted into thermal energy or other forms of energy in a quantum dot or other material layer; is the Gaussian decay factor, which describes the kinetic energy of quasiparticles on the influence of energy dissipation. As the kinetic energy of quasiparticles increases, the dissipation efficiency of energy shows a decaying trend is the decay coefficient related to the kinetic energy of quasiparticles and material properties; Denotes the spatial integration region, which is used to calculate the change in quasiparticle density over the entire encapsulation region; represents the total effect of the energy dissipation of all quasiparticles; Describes the combined effect of coherence time and transmittance. As the transmittance increases, the coherence time decreases, showing the effect of suppressing the packaging alignment particles; is a regulating factor, indicating the influence of the encapsulation design on the transmittance; It is the coherence time of a qubit, which represents the time during which a qubit can maintain its quantum state without being interfered by the external environment; The quasiparticle transmittance indicates the shielding effect of the encapsulation layer on quasiparticles and measures the degree of transmission of quasiparticles through different shielding layers; Indicates the volume of the package; Represents the surface area of the package; Range meaning: When > 0.8, it indicates that the quasiparticle suppression effect of the encapsulation scheme is good and suitable for long-term stable operation; When 0.5 < ≤ 0.8, it means that the encapsulation solution needs to be optimized; When ≤ 0.5, it indicates that the quasiparticle suppression effect of the encapsulation scheme is poor and the materials and structures need to be redesigned.

3. The method for packaging a quantum chip to eliminate the influence of quasiparticles according to claim 2, wherein: A dynamic quasiparticle transport control mechanism is introduced into the encapsulation structure. Through adjustable micro - structure channels, it guides quasiparticles to move towards the energy dissipation region to improve the quasiparticle suppression ability of the encapsulation.

4. The quantum chip packaging method for eliminating the influence of quasiparticles according to claim 3, characterized in that: The dynamic quasiparticle transport control mechanism includes the following steps: Integrate adjustable micro - structure channels inside the encapsulation layer. The channels form a periodic potential field through superconducting micro - bridges or quantum dot arrays to guide quasiparticles to diffuse towards the low - temperature region; Adjust the transport characteristics of the micro - structure channels through a low - temperature electric field or magnetic field to dynamically optimize the movement direction and distribution of quasiparticles; Add a real - time monitoring system outside the encapsulation. Combine microwave resonance measurement and nano - scale thermal probe to analyze the density distribution of quasiparticles, and adjust the opening and closing states of the micro - structure channels according to the monitoring data to enhance the shielding ability of the encapsulation structure; Dynamically adjust the exponential decay factor in combination with the mathematical expression of quasiparticle suppression ability Coefficient in And the Gaussian decay factor Coefficient in To maximize the dissipation efficiency of quasiparticles.

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