Pixel circuit, driving method thereof and display device

Abstract

The invention provides a pixel circuit, a driving method thereof and a display device, the pixel circuit comprises a driving circuit, a first compensation circuit, a light-emitting element, a second light-emitting control circuit and a reset control circuit, and the first compensation circuit comprises a first storage capacitor; the control end of the reset control circuit is configured to receive a reset control signal, the first end of the reset control circuit is electrically connected with the first end of the driving circuit, the second end of the reset control circuit is electrically connected with the reset signal end to receive a reset signal, and the third end of the reset control circuit is electrically connected with the first electrode of the light-emitting element. The reset control circuit is configured to respond to a reset control signal to apply a reset signal to the first electrode of the light-emitting element and / or the first end of the driving circuit, the reset control circuit is arranged between the driving circuit and the reset signal end in the pixel circuit, and the influence of fluctuation of the reset signal on the voltage of the first end of the driving circuit can be reduced. The risk of introducing noise to a pixel circuit is reduced.

Description

Pixel circuit, driving method thereof, and display device

[0001] This application claims priority to patent application No. PCT / CN2023 / 113514 filed on August 17, 2023, and the contents of the above patent application disclosure are hereby incorporated by reference in their entirety as a part of this application for all purposes. Technical Field

[0002] At least one embodiment of the present disclosure relates to a pixel circuit, a driving method thereof, and a display device. Background Art

[0003] With the continuous development of display technology, organic light-emitting diodes (OLED) and quantum-dot light-emitting diodes (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility and low cost.

[0004] Summary of the Invention

[0005] At least one embodiment of the present disclosure provides a pixel circuit, a driving method thereof, and a display device.

[0006] At least one embodiment of the present disclosure provides a pixel circuit, which includes a driving circuit, a first compensation circuit, a light-emitting element, a second light-emitting control circuit and a reset control circuit, wherein the driving circuit includes a control terminal, a first terminal and a second terminal, and is configured to control the magnitude of a driving current flowing through the first terminal and the second terminal; the first compensation circuit is configured to apply a reference signal to the control terminal of the driving circuit in response to a first compensation control signal, the first compensation circuit includes a first storage capacitor, a first electrode of the first storage capacitor is electrically connected to the control terminal of the driving circuit, and a second electrode of the first storage capacitor is electrically connected to the first terminal of the driving circuit; the light-emitting element is configured to emit light under the drive of the driving current, and the second electrode of the light-emitting element is electrically connected to the second voltage terminal to receive a second power supply voltage; the control terminal of the second light-emitting control circuit is configured to receive a second light-emitting element. a control signal, a first end of the second light-emitting control circuit is electrically connected to the first end of the drive circuit, a second end of the second light-emitting control circuit is electrically connected to the first electrode of the light-emitting element, and the second light-emitting control circuit is configured to apply the drive current to the light-emitting element in response to the second light-emitting control signal and allow the reset signal to be applied to the first end of the drive circuit; a control end of the reset control circuit is configured to receive a reset control signal, a first end of the reset control circuit is electrically connected to the first end of the drive circuit, a second end of the reset control circuit is electrically connected to the reset signal end to receive the reset signal, a third end of the reset control circuit is electrically connected to the first electrode of the light-emitting element, and the reset control circuit is configured to apply the reset signal to the first electrode of the light-emitting element and / or the first end of the drive circuit in response to the reset control signal.

[0007] For example, according to a pixel circuit provided by at least one embodiment of the present disclosure, the reset control circuit includes a second compensation circuit and a reset circuit, the second compensation circuit includes a second storage capacitor, wherein the second compensation circuit is electrically connected between the first end of the driving circuit and the reset signal end, the control end of the reset circuit serves as the control end of the reset control circuit and is configured to receive the reset control signal, the first end of the reset circuit serves as the third end of the reset control circuit and is electrically connected to the first electrode of the light-emitting element, and the second end of the reset circuit serves as the second end of the reset control circuit and is electrically connected to the reset signal end to receive the reset signal.

[0008] For example, in the pixel circuit provided by at least one embodiment of the present disclosure, the value of the reset signal is adjustable.

[0009] For example, in a pixel circuit provided according to at least one embodiment of the present disclosure, the reset signal includes at least a first reset signal and a second reset signal, the first reset signal corresponds to a first display temperature, the second reset signal corresponds to a second display temperature, the first display temperature is lower than the second display temperature, and the value of the first reset signal is smaller than the value of the second reset signal.

[0010] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the first reset signal is adjusted to the second reset signal during the reset signal adjustment period, the pixel circuit corresponds to multiple display frame cycles, and the reset signal adjustment period is located between two adjacent display frame cycles; or the reset signal adjustment period is located within a display frame cycle, and the display frame cycle at least includes a reset stage, a compensation stage, a data writing stage and a light-emitting stage, and the reset signal adjustment period at least partially overlaps with, or does not overlap with, any one of the reset stage, the compensation stage, the data writing stage and the light-emitting stage.

[0011] For example, in the pixel circuit provided by at least one embodiment of the present disclosure, the value of the reference signal is adjustable.

[0012] For example, in a pixel circuit provided according to at least one embodiment of the present disclosure, the first electrode of the second storage capacitor serves as the first end of the reset control circuit and is electrically connected to the first end of the driving circuit, and the second electrode of the second storage capacitor is electrically connected to the first end of the reset circuit.

[0013] For example, according to a pixel circuit provided in accordance with at least one embodiment of the present disclosure, the pixel circuit further includes a first light-emitting control circuit, wherein the control end of the first light-emitting control circuit is configured to receive a first light-emitting control signal, the first end of the first light-emitting control circuit is electrically connected to the second end of the driving circuit, the second end of the first light-emitting control circuit is electrically connected to the first voltage end to receive a first power supply voltage, and the first light-emitting control circuit is configured to apply the first power supply voltage to the second end of the driving circuit in response to the first light-emitting control signal.

[0014] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the first light-emitting control circuit includes a first light-emitting control transistor, the gate of the first light-emitting control transistor is electrically connected to the first light-emitting control end to receive the first light-emitting control signal, the first electrode of the first light-emitting control transistor is electrically connected to the second end of the driving circuit, and the second electrode of the first light-emitting control transistor is electrically connected to the first voltage end to receive the first power supply voltage.

[0015] For example, in a pixel circuit provided according to at least one embodiment of the present disclosure, the second terminal of the driving circuit is directly electrically connected to the first voltage terminal to receive the first power supply voltage.

[0016] For example, according to a pixel circuit provided by at least one embodiment of the present disclosure, the reset circuit includes a reset transistor, the gate of the reset transistor is electrically connected to the reset control terminal to receive the reset control signal, the first electrode of the reset transistor is electrically connected to the second electrode of the second storage capacitor and the first end of the driving circuit, and the second electrode of the reset transistor is electrically connected to the reset signal terminal to receive the reset signal.

[0017] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the second light-emitting control circuit includes a second light-emitting control transistor, the gate of the second light-emitting control transistor is electrically connected to the second light-emitting control end to receive the second light-emitting control signal, the first electrode of the second light-emitting control transistor is electrically connected to the first end of the driving circuit, and the second electrode of the second light-emitting control transistor is electrically connected to the first electrode of the light-emitting element.

[0018] For example, according to a pixel circuit provided in accordance with at least one embodiment of the present disclosure, the pixel circuit further includes an auxiliary compensation circuit, wherein the control end of the auxiliary compensation circuit is configured to receive an auxiliary compensation signal, the first end of the auxiliary compensation circuit is electrically connected to the second electrode of the second storage capacitor, and the second end of the auxiliary compensation circuit is electrically connected to the first electrode of the light-emitting element.

[0019] For example, in the pixel circuit provided according to at least one embodiment of the present disclosure, the first end of the auxiliary compensation circuit is also electrically connected to the second end of the second light emitting control circuit and the first end of the reset circuit.

[0020] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the auxiliary compensation circuit includes an auxiliary compensation transistor, the gate of the auxiliary compensation transistor serves as the control end of the auxiliary compensation circuit to receive the auxiliary compensation control signal, the first electrode of the auxiliary compensation transistor is electrically connected to the second electrode of the second compensation capacitor and the second electrode of the second light-emitting control transistor, and the second electrode of the auxiliary compensation transistor is electrically connected to the first electrode of the light-emitting element.

[0021] For example, in a pixel circuit provided according to at least one embodiment of the present disclosure, the first end of the auxiliary compensation circuit is also electrically connected to the first end of the reset circuit, and the second end of the auxiliary compensation circuit is also electrically connected to the second end of the second light-emitting control circuit.

[0022] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the auxiliary compensation circuit includes an auxiliary compensation transistor, the gate of the auxiliary compensation transistor is electrically connected to the auxiliary compensation control terminal to receive the auxiliary compensation control signal, the first electrode of the auxiliary compensation transistor is electrically connected to the second electrode of the second compensation capacitor and the first electrode of the reset transistor, and the second electrode of the auxiliary compensation transistor is electrically connected to the first electrode of the light-emitting element.

[0023] For example, in a pixel circuit provided according to at least one embodiment of the present disclosure, the gate of the auxiliary compensation transistor is electrically connected to the gate of the second light-emitting control transistor, the auxiliary compensation transistor and the second light-emitting control transistor share a gate, the second light-emitting control signal serves as the auxiliary compensation control signal, and the type of the auxiliary compensation transistor is the same as the type of the second light-emitting control transistor; or, the gate of the auxiliary compensation transistor and the gate of the second light-emitting control transistor are independent of each other and are not electrically connected.

[0024] For example, in a pixel circuit provided according to at least one embodiment of the present disclosure, the gate of the auxiliary compensation transistor is electrically connected to the gate of the reset transistor, the auxiliary compensation transistor and the reset transistor share a gate, the reset control signal serves as the auxiliary compensation control signal, and the type of the auxiliary compensation transistor is the same as the type of the reset transistor; or, the gate of the auxiliary compensation transistor and the gate of the reset transistor are independent of each other and not electrically connected.

[0025] For example, according to a pixel circuit provided in accordance with at least one embodiment of the present disclosure, the driving circuit includes a driving transistor, the gate of the driving transistor serves as the control end of the driving circuit and is electrically connected to the first node, the first electrode of the driving transistor serves as the first end of the driving circuit and is electrically connected to the first electrode of the second storage capacitor at the second node, the second electrode of the driving transistor serves as the second end of the driving circuit and is electrically connected to the first voltage end to receive a first power supply voltage; the pixel circuit also includes: a data writing circuit, the control end of the data writing circuit is configured to receive a data scanning signal, the first end of the data writing circuit is electrically connected to the data signal end to receive a data signal, the second end of the data writing circuit is electrically connected to the first node, and the data writing circuit is configured to write the data signal to the control end of the driving circuit in response to the data scanning signal.

[0026] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the control end of the first compensation circuit is configured to receive the first compensation control signal, the first end of the first compensation circuit is electrically connected to the reference signal end to receive the reference signal, and the second end of the first compensation circuit is electrically connected to the second node, wherein the first compensation circuit also includes a first compensation transistor, the gate of the first compensation transistor serves as the control end of the first compensation circuit and is electrically connected to the first compensation control signal end to receive the first compensation control signal, the first electrode of the first compensation transistor serves as the first end of the first compensation circuit and is electrically connected to the reference signal end to receive the reference signal, the second electrode of the first compensation transistor is electrically connected to the first node, the data write circuit includes a data write transistor, the gate of the data write transistor is electrically connected to the data scan signal end to receive the data scan signal, the first electrode of the data write transistor is electrically connected to the data signal end to receive the data signal, and the second electrode of the data write transistor is electrically connected to the first node.

[0027] For example, in the pixel circuit provided according to at least one embodiment of the present disclosure, the data writing transistor and the first compensation transistor are transistors controlled independently of each other, the data scanning signal terminal and the first compensation control signal terminal are different signal terminals independent of each other, and the data signal terminal and the reference signal terminal are different signal terminals independent of each other; or, the data writing transistor is multiplexed into the first compensation transistor, the data scanning signal is multiplexed into the first compensation control signal, the first electrode of the data writing transistor is also electrically connected to the reference signal terminal to receive the reference signal, the data signal terminal is multiplexed as the reference signal terminal, and is configured to provide the data signal or the reference signal respectively in different time periods.

[0028] At least one embodiment of the present disclosure further provides a display device, comprising any one of the pixel circuits described above.

[0029] At least one embodiment of the present disclosure also provides a driving method for a pixel circuit, which is applicable to the pixel circuit described in any one of the above items, and the driving method includes: making the reset control signal a turn-on signal so that the reset signal is applied to the first electrode of the light-emitting element and / or the first end of the driving circuit through the reset control circuit.

[0030] For example, according to a driving method of a pixel circuit provided by at least one embodiment of the present disclosure, the reset control circuit includes a second compensation circuit and a reset circuit, the second compensation circuit includes a second storage capacitor, wherein the first electrode of the second storage capacitor serves as the first end of the reset control circuit and is electrically connected to the first end of the driving circuit, and the second electrode of the second storage capacitor is electrically connected to the first end of the reset circuit; the control end of the reset circuit serves as the control end of the reset control circuit and is configured to receive the reset control signal, the first end of the reset circuit serves as the third end of the reset control circuit and is electrically connected to the first electrode of the light-emitting element, the second end of the reset circuit serves as the second end of the reset control circuit and is electrically connected to the reset signal end to receive the reset signal, and the driving method includes a reset stage stage, compensation stage, data writing stage and light-emitting stage, in the reset stage, the reset control signal is set to be an on signal in at least part of the time period so that the first end and the second end of the reset circuit are turned on, and the reset signal is sequentially applied to the second pole of the second storage capacitor, the first end of the drive circuit and the first electrode of the light-emitting element through the second end and the first end of the reset circuit; in the compensation stage and the data writing stage, the reset control signal is set to be an on signal, and the reset signal is sequentially applied to the second pole of the second storage capacitor and the first electrode of the light-emitting element through the second end and the first end of the reset circuit; in the light-emitting stage, the reset control signal is set to be an off signal in at least part of the time period so that the second pole of the second storage capacitor is disconnected from the reset signal end.

[0031] For example, according to a driving method of a pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit further includes a data writing circuit and a first light-emitting control circuit; the control end of the data writing circuit is configured to receive a data scanning signal, the first end of the data writing circuit is electrically connected to the data signal end to receive the data signal, and the second end of the data writing circuit is electrically connected to the control end of the driving circuit; the control end of the first light-emitting control circuit is configured to receive a first light-emitting control signal, the first end of the first light-emitting control circuit is electrically connected to the second end of the driving circuit, and the second end of the first light-emitting control circuit is electrically connected to the first voltage end so that the second end of the driving circuit Receive a first power supply voltage; in the light-emitting stage, the driving method includes sequentially executing the following steps S101 to S104: Step S101: set the data scanning signal to an off signal to turn off the data writing circuit; Step S102: set the second light-emitting control signal to an on signal to turn on the second light-emitting control circuit, and set the first light-emitting control signal to remain an off signal to turn off the first light-emitting control circuit; Step S104: set the first light-emitting control signal to an on signal to turn on the first light-emitting control circuit, so that the second end of the driving circuit receives the first power supply voltage from the first voltage end via the first light-emitting control circuit.

[0032] For example, according to a driving method of a pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit further includes a data writing circuit and a first light-emitting control circuit; the control end of the data writing circuit is configured to receive a data scanning signal, the first end of the data writing circuit is electrically connected to the data signal end to receive the data signal, and the second end of the data writing circuit is electrically connected to the control end of the driving circuit; the control end of the first light-emitting control circuit is configured to receive a first light-emitting control signal, the first end of the first light-emitting control circuit is electrically connected to the second end of the driving circuit, and the second end of the first light-emitting control circuit is electrically connected to the first voltage end so that the driving circuit The second end of the driving circuit receives the first power supply voltage; in the reset stage, the driving method includes sequentially performing the following steps S1010 to S1030: step S1010: disconnecting the second end of the driving circuit from the first voltage end; step S1020: setting the reset control signal to a turn-on signal to turn on the reset circuit; and step S1030: setting the first compensation control signal to a turn-on signal to turn on the first compensation circuit, and, in the reset stage, the data scanning signal remains as a turn-off signal to turn off the data writing circuit, and the second light-emitting control signal remains as a turn-on signal to turn on the second light-emitting control circuit.

[0033] For example, according to the driving method of the pixel circuit provided by at least one embodiment of the present disclosure, in the compensation stage, the driving method includes sequentially executing the following steps S2010 to S2020: Step S2010: setting the second light-emitting control signal to an off signal to turn off the second light-emitting control circuit, and setting the first light-emitting control signal to remain an off signal to turn off the first light-emitting control circuit; and Step S2020: setting the first light-emitting control signal to an on signal to turn on the first light-emitting control circuit, and setting the second light-emitting control signal to an off signal; and, in the compensation stage, the data scanning signal is maintained as an off signal to keep the data writing circuit turned off, and the first compensation control signal is maintained as an on signal to keep the first compensation circuit turned on.

[0034] For example, according to the driving method of the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit also includes a data writing circuit, the control end of the data writing circuit is configured to receive a data scanning signal, the first end of the data writing circuit is electrically connected to the data signal end to receive the data signal, and the second end of the data writing circuit is electrically connected to the control end of the driving circuit, wherein, in the data writing stage, the driving method includes sequentially performing the following steps S3010 to S3030: Step S3010: Set the first compensation control signal to a closed signal to turn off the first compensation circuit, and set the second end of the driving circuit to continue receiving the first power supply voltage; and Step S3030: Set the data scanning signal to a turned-on signal to turn on the data writing circuit, wherein, in the data writing stage, the second light-emitting control signal remains as a closed signal to keep the second light-emitting control circuit turned off.

[0035] For example, according to the driving method of the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit also includes a first light-emitting control circuit, the control end of the first light-emitting control circuit is configured to receive a first light-emitting control signal, the first end of the first light-emitting control circuit is electrically connected to the second end of the driving circuit, and the second end of the first light-emitting control circuit is electrically connected to the first voltage end so that the second end of the driving circuit receives the first power supply voltage; the step S3030 also includes: setting the first light-emitting control signal to a turn-on signal to turn on the first light-emitting control circuit, so that the second end of the driving circuit receives the first power supply voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0037] FIG1 is a schematic block diagram of a pixel circuit provided by at least one embodiment of the present disclosure.

[0038] FIG2 is a circuit diagram of an implementation example of the pixel circuit shown in FIG1 .

[0039] FIG3 is a signal timing diagram of a driving method provided by at least one embodiment of the present disclosure.

[0040] FIG. 4A is a schematic diagram of the pixel circuit in FIG. 2 in the third sub-reset phase.

[0041] FIG. 4B is a schematic diagram of the pixel circuit in FIG. 2 in the second sub-compensation stage.

[0042] FIG. 4C is a schematic diagram of the pixel circuit in FIG. 2 in the third sub-data writing phase.

[0043] FIG4D is a schematic diagram of the pixel circuit in FIG2 in the fourth sub-light emitting stage.

[0044] FIG. 4E is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure.

[0045] FIG5 is a schematic diagram of another pixel circuit provided by an embodiment of the present disclosure.

[0046] FIG. 6 is a signal timing diagram corresponding to the pixel circuit shown in FIG. 5 .

[0047] FIG. 7A is a schematic diagram of the pixel circuit in FIG. 5 in the third sub-reset phase.

[0048] FIG. 7B is a schematic diagram of the pixel circuit in FIG. 5 in the second sub-compensation stage.

[0049] FIG. 7C is a schematic diagram of the pixel circuit in FIG. 5 in the third sub-data writing phase.

[0050] FIG7D is a schematic diagram of the pixel circuit in FIG5 in the fourth sub-light emitting stage.

[0051] FIG8 is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure.

[0052] FIG9 is a circuit diagram of an implementation example of the pixel circuit shown in FIG8 .

[0053] FIG. 10 is a signal timing diagram corresponding to the pixel circuit shown in FIG. 9 .

[0054] FIG. 11A is a schematic diagram of the pixel circuit shown in FIG. 9 in the third sub-reset phase.

[0055] FIG. 11B is a schematic diagram of the pixel circuit shown in FIG. 9 in the second sub-compensation stage.

[0056] FIG11C is a schematic diagram of the pixel circuit shown in FIG9 in the third sub-data writing phase.

[0057] FIG11D is a schematic diagram of the pixel circuit shown in FIG9 in the fourth sub-light emitting stage.

[0058] FIG12 is a schematic diagram of another pixel circuit provided by an embodiment of the present disclosure.

[0059] FIG13 is a signal timing diagram corresponding to the pixel circuit shown in FIG12 .

[0060] FIG. 14A is a schematic diagram of the pixel circuit in FIG. 12 in the second sub-compensation stage.

[0061] FIG14B is a schematic diagram of the pixel circuit in FIG12 in the third sub-data writing phase.

[0062] FIG14C is a schematic diagram of the pixel circuit in FIG12 in the fourth sub-light emitting stage.

[0063] FIG15 is a schematic block diagram of yet another pixel circuit provided by at least one embodiment of the present disclosure.

[0064] FIG16 is a circuit diagram of an implementation example of the pixel circuit shown in FIG15 .

[0065] FIG17 is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure.

[0066] FIG18A is a schematic diagram of the pixel circuit shown in FIG15 in the third sub-reset phase.

[0067] FIG18B is a schematic diagram of the pixel circuit shown in FIG15 in the second sub-compensation stage.

[0068] FIG18C is a schematic diagram of the pixel circuit shown in FIG15 in the third sub-data writing phase.

[0069] FIG18D is a schematic diagram of the pixel circuit shown in FIG15 in the fourth sub-light emitting stage.

[0070] FIG19 is a schematic block diagram of yet another pixel circuit provided by at least one embodiment of the present disclosure.

[0071] FIG20 is a circuit diagram of an implementation example of the pixel circuit shown in FIG19 .

[0072] FIG21 is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure.

[0073] FIG. 22A is a schematic diagram of the pixel circuit in FIG. 20 in the third sub-reset phase.

[0074] FIG22B is a schematic diagram of the pixel circuit in FIG20 in the second sub-compensation stage.

[0075] FIG22C is a schematic diagram of the pixel circuit in FIG20 in the third sub-data writing phase.

[0076] FIG22D is a schematic diagram of the pixel circuit in FIG20 in the fourth sub-light emitting stage.

[0077] FIG23 is a schematic block diagram of yet another pixel circuit provided by at least one embodiment of the present disclosure.

[0078] FIG24 is a circuit diagram of an implementation example of the pixel circuit shown in FIG23 .

[0079] FIG25 is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure.

[0080] FIG26A is a schematic diagram of the pixel circuit in FIG24 in the third sub-reset phase.

[0081] FIG. 26B is a schematic diagram of the pixel circuit in FIG. 24 in the second sub-compensation stage.

[0082] FIG26C is a schematic diagram of the pixel circuit in FIG24 in the third sub-data writing phase.

[0083] FIG26D is a schematic diagram of the pixel circuit in FIG24 in the fourth sub-light emitting stage.

[0084] FIG. 27 is a schematic diagram illustrating how the reset voltage varies with temperature in at least one embodiment of the present disclosure.

[0085] FIG28 is a schematic diagram showing how the brightness of a light-emitting element varies with grayscale in at least one embodiment of the present disclosure.

[0086] FIG. 29 is a schematic diagram illustrating how the reset voltage varies with temperature in at least one embodiment of the present disclosure.

[0087] FIG30 is a schematic diagram illustrating how a reference voltage varies with temperature in at least one embodiment of the present disclosure.

[0088] FIG31 is a schematic structural diagram of another pixel driving circuit provided in an embodiment of the present disclosure.

[0089] FIG32 is an equivalent circuit diagram 1 including the third control sub-circuit shown in FIG31 .

[0090] FIG33 is a second equivalent circuit diagram including the third control sub-circuit shown in FIG31 .

[0091] FIG34 is a third equivalent circuit diagram including the third control sub-circuit shown in FIG31 .

[0092] FIG35 is a fourth equivalent circuit diagram including the third control sub-circuit shown in FIG31 .

[0093] FIG36 is a fifth equivalent circuit diagram including the third control sub-circuit shown in FIG31 .

[0094] FIG37 is an equivalent circuit diagram 6 including the third control sub-circuit shown in FIG31.

[0095] FIG38 is a partial equivalent circuit diagram of another pixel driving circuit provided in an embodiment of the present disclosure.

[0096] FIG39 is a first equivalent circuit diagram of the pixel driving circuit shown in FIG38 .

[0097] FIG40 is a second equivalent circuit diagram of the pixel driving circuit shown in FIG38 .

[0098] FIG41 is a third equivalent circuit diagram of the pixel driving circuit shown in FIG38 .

[0099] FIG42 is a fourth equivalent circuit diagram of the pixel driving circuit shown in FIG38.

[0100] FIG43 is a fifth equivalent circuit diagram of the pixel driving circuit shown in FIG38 .

[0101] FIG44 is a sixth equivalent circuit diagram of the pixel driving circuit shown in FIG38 .

[0102] FIG45 is an operation timing diagram of the pixel driving circuit provided in FIG39 and FIG40.

[0103] FIG46 is an operating timing diagram of the pixel driving circuit provided in FIG41 .

[0104] FIG47 is an operating timing diagram of the pixel driving circuit provided in FIG42 .

[0105] FIG48 is an operation timing diagram of the pixel driving circuit provided in FIG43 and FIG44 . DETAILED DESCRIPTION

[0106] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0107] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are simply used to distinguish different components. The words "include" or "comprising" and similar terms mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0108] The features "perpendicular," "parallel," and "identical" used in the embodiments of the present disclosure include the features "perpendicular," "parallel," and "identical" in the strict sense, as well as "approximately perpendicular," "approximately parallel," and "approximately identical" that include certain errors, taking into account the errors associated with the measurement of specific quantities (i.e., the limitations of the measurement system), and represent within the acceptable deviation range for the specific value determined by ordinary technicians in this field. The "center" in the embodiments of the present disclosure can include a position strictly at the geometric center and a position approximately at the center of a small area around the geometric center.

[0109] In some cases, a display device may experience short-term afterimages during display. This means that after displaying the same image for a period of time, when the display device switches to the next image, a portion of the original image will remain and appear in the next image. After a period of time, the afterimage disappears. The cause of the short-term afterimage may be the hysteresis effect of the driver transistor in the pixel circuit. The hysteresis effect is mainly caused by the threshold voltage (Vth) shift caused by mobile ions remaining in the holes. When the display device switches images, the Vgs (the voltage difference between the gate and source of the driver transistor) in the initialization phase of the driver transistor may be different, which may cause the threshold voltage of the driver transistor to shift.

[0110] For example, after a display device displays an initial image for a period of time, when the display device switches to a new image, the initial image may still partially remain for several hours, thereby affecting the display. Therefore, the problem of eliminating the threshold voltage (Vth) offset of the driving transistor needs to be solved urgently.

[0111] Pixel circuits using oxides have been increasingly used in display devices. The refresh rate of the pixel circuit is high and the process has high uniformity. In some pixel circuits, the first pole of the driving transistor is directly connected to the reset signal terminal, so that the fluctuation of the reset signal will affect the stability of the voltage of the first pole of the driving circuit. In other pixel circuits, the first pole of the driving transistor is electrically connected to the first light-emitting control transistor, the second pole of the driving transistor is electrically connected to the light-emitting element through the second light-emitting control transistor, the first pole of the storage capacitor is electrically connected to the first pole of the driving transistor, and the second pole of the storage capacitor is electrically connected to the constant signal terminal to receive a constant signal, for example, the constant signal can be a reset signal. When the above-mentioned constant signal is unstable, it is easy to cause the voltage of the second pole of the storage capacitor to fluctuate, thereby introducing external noise into the pixel circuit. For example, when the pixel circuit enters the light-emitting stage from the data writing stage, the reset signal needs to be switched from the on signal to the off signal, which is easy to increase the risk of introducing noise into the pixel circuit, thereby making the driving current unstable and affecting the display effect.

[0112] At least one embodiment of the present disclosure provides a pixel circuit, a driving method thereof, and a display device.

[0113] At least one embodiment of the present disclosure provides a pixel circuit including a driving circuit, a first compensation circuit, a light-emitting element, a second light-emitting control circuit, and a reset control circuit. The driving circuit includes a control terminal, a first terminal, and a second terminal, and is configured to control the magnitude of a driving current flowing through the first terminal and the second terminal. The first compensation circuit is configured to apply a reference signal to the control terminal of the driving circuit in response to a first compensation control signal. The first compensation circuit includes a first storage capacitor, a first electrode of the first storage capacitor is electrically connected to the control terminal of the driving circuit, and a second electrode of the first storage capacitor is electrically connected to the first terminal of the driving circuit. The light-emitting element is configured to emit light under the drive of the driving current, and a second electrode of the light-emitting element is electrically connected to the second voltage terminal to receive a second power supply voltage. The control terminal of the second light-emitting control circuit is configured to receive a second power supply voltage. The reset control circuit receives a second light-emitting control signal, a first end of the second light-emitting control circuit is electrically connected to the first end of the driving circuit, a second end of the second light-emitting control circuit is electrically connected to the first electrode of the light-emitting element, and the second light-emitting control circuit is configured to apply a driving current to the light-emitting element in response to the second light-emitting control signal and allow a reset signal to be applied to the first end of the driving circuit; the control end of the reset control circuit is configured to receive a reset control signal, a first end of the reset control circuit is electrically connected to the first end of the driving circuit, a second end of the reset control circuit is electrically connected to the reset signal end to receive the reset signal, a third end of the reset control circuit is electrically connected to the first electrode of the light-emitting element, and the reset control circuit is configured to apply a reset signal to the first electrode of the light-emitting element and / or the first end of the driving circuit in response to the reset control signal.

[0114] The pixel circuit provided in at least one embodiment of the present disclosure is provided with a reset control circuit, and the first end of the reset control circuit is electrically connected to the first end of the driving circuit, and the second end of the reset control circuit is electrically connected to the reset signal end. Therefore, the reset signal needs to pass through the reset control circuit before it can be applied to the first electrode of the light-emitting element and / or to the first end of the driving circuit, thereby reducing the impact of the fluctuation of the reset signal on the voltage of the first electrode of the light-emitting element and the first end of the driving circuit, and reducing the risk of introducing noise into the pixel circuit, thereby making the driving current more stable to improve the display effect.

[0115] The pixel circuit and its driving method, and the display device provided by the embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0116] FIG1 is a schematic block diagram of a pixel circuit provided by at least one embodiment of the present disclosure.

[0117] As shown in FIG. 1 , the pixel circuit 10 includes a driving circuit 100 , a first compensation circuit 300 , a second light emitting control circuit 500 , a light emitting element 600 , and a reset control circuit 780 .

[0118] As shown in FIG1 , the driving circuit 100 includes a control terminal 100m, a first terminal 100a, and a second terminal 100b. The control terminal 100m of the driving circuit 100 is electrically connected to a first node N1, the first terminal 100a of the driving circuit 100 is electrically connected to a second node N2, and the second terminal 100b of the driving circuit 100 is electrically connected to a third node N3. The driving circuit 100 is configured to control the magnitude of a driving current flowing through the first terminal 100a and the second terminal 100b. For example, the driving current can be used to drive the light-emitting element 600 to emit light. For example, in the light-emitting phase, the driving circuit 100 can provide a driving current to the light-emitting element 600 to drive the light-emitting element 600 to emit light.

[0119] As shown in FIG1 , the first compensation circuit 300 includes a control terminal 300m, a first terminal 300a, a second terminal 300b, and a third terminal 300c. The control terminal 300m of the first compensation circuit 300 is configured to receive a first compensation control signal G2. The first terminal 300a of the first compensation circuit 300 is electrically connected to the reference signal terminal REF to receive the reference signal REF. The second terminal 300b of the first compensation circuit 300 is electrically connected to the second node N2. The third terminal 300c of the first compensation circuit 300 is electrically connected to the first node N1. The first compensation circuit 300 is configured to apply the reference signal REF to the control terminal 100m of the driving circuit 100 in response to the first compensation control signal G2. For example, the first compensation circuit 300 may include a first storage capacitor C1 (see FIG2 ), wherein a first electrode of the first storage capacitor C1 is electrically connected to the control terminal 100m of the driving circuit 100, and a second electrode of the first storage capacitor C1 is electrically connected to the first terminal 100a of the driving circuit 100, but the embodiments of the present disclosure are not limited thereto.

[0120] For example, as shown in FIG1 , the second light-emitting control circuit 500 includes a control terminal 500m, a first terminal 500a, and a second terminal 500b. The control terminal 500m of the second light-emitting control circuit 500 is configured to receive a second light-emitting control signal EM2. The first terminal 500a of the second light-emitting control circuit 500 is electrically connected to the first terminal 100a of the driver circuit 100, and the second terminal 500b of the second light-emitting control circuit 500 is electrically connected to the first electrode 600a of the light-emitting element 600. The second light-emitting control circuit 500 is configured to apply a driving current to the light-emitting element 600 in response to the second light-emitting control signal EM2 and to allow the reset signal VINI to be applied to the first terminal 100a of the driver circuit 100. For example, during the light-emitting phase, the second light-emitting control circuit 500 is turned on in response to the second light-emitting control signal EM2, so that the driver circuit 100 can apply a driving current to the light-emitting element 600 through the second light-emitting control circuit 500 to cause the light-emitting element 600 to emit light.

[0121] For example, as shown in Figure 1, the light-emitting element 600 includes a first electrode 600a and a second electrode 600b. The first electrode 600a of the light-emitting element 600 is electrically connected to the first terminal 100a of the driving circuit 100, and the second electrode 600b of the light-emitting element 600 is electrically connected to the second voltage terminal VSS to receive the second power supply voltage VSS. The light-emitting element 600 is configured to emit light under the drive current. For example, the second voltage terminal VSS can be grounded, that is, the second power supply voltage VSS can be 0V. For example, the second power supply voltage VSS can be a negative voltage. For example, the light-emitting element 600 can adopt an organic light-emitting diode (OLED). In the embodiments described below, the light-emitting element 600 is taken as an OLED. For example, the light-emitting element 600 can also be other types of electroluminescent devices such as inorganic light-emitting diodes, quantum dot light-emitting elements, etc. The embodiments of the present disclosure do not limit the type of light-emitting element.

[0122] As shown in FIG1 , the reset control circuit 780 includes a control terminal 780m, a first terminal 780a, a second terminal 780b, and a third terminal 780c. The control terminal 780m of the reset control circuit 780 is configured to receive a reset control signal G3. The first terminal 780a of the reset control circuit 780 is electrically connected to the first terminal 100a of the driving circuit 100. The second terminal 780b of the reset control circuit 780 is electrically connected to the reset signal terminal VINI to receive the reset signal VINI. The third terminal 780c of the reset control circuit 780 is electrically connected to the first electrode 600a of the light-emitting element 600. The reset control circuit 780 is configured to apply the reset signal VINI to the first electrode 600a of the light-emitting element 600 and / or the first terminal 100a of the driving circuit 100 in response to the reset control signal G3. For example, during the reset phase, the second light-emitting control circuit 500 can be turned on in response to the second light-emitting control signal EM2, thereby allowing the reset signal VINI to be applied to the first terminal 100a of the driver circuit 100 in combination with other circuit elements (e.g., the reset circuit 700 described in the following embodiments), thereby achieving a reset operation and other operations for the driver circuit 100 and the light-emitting element 600. For example, during the compensation phase and the data writing phase, the second light-emitting control circuit 500 is turned off in response to the second light-emitting control signal EM2, and the reset signal VINI is applied to the first electrode of the light-emitting element 600. During this phase, the light-emitting element 600 can be prevented from emitting light, thereby meeting the display requirements of the display device. For example, the reset signal VINI can be a reset voltage VINI.

[0123] As shown in Figure 1, the first end 780a of the reset control circuit 780 is electrically connected to the first end 100a of the driving circuit 100, and the second end 780b of the reset control circuit 780 is electrically connected to the reset signal end VINI. Therefore, the reset signal from the reset signal end VINI needs to pass through the reset control circuit 780 before it can be applied to the first electrode 600a of the light-emitting element 600 and / or the first end of the driving circuit 100, thereby reducing the impact of the fluctuation of the reset signal on the voltage of the first electrode 600a of the light-emitting element 600 and the first end 100a of the driving circuit 100, and reducing the risk of introducing noise into the pixel circuit 10, thereby making the driving current more stable to improve the display effect.

[0124] For example, as shown in FIG1 , the reset control circuit 780 includes a reset circuit 700 and a second compensation circuit 800. The reset signal VINI is applied to the first electrode 600a of the light-emitting element 600 and / or the first terminal 100a of the driving circuit 100 via the reset circuit 700 and the second compensation circuit 800. For example, in some embodiments of the present disclosure, the reset control circuit 780 may further include other sub-circuits, and the embodiments of the present disclosure do not limit the specific structure of the reset control circuit 780.

[0125] For example, as shown in FIG1 , the second compensation circuit 800 includes a first terminal 800a and a second terminal 800b. The second compensation circuit 800 includes a second storage capacitor C2, and the second storage capacitor C2 is electrically connected between the first terminal 100a of the driving circuit 100 and the reset signal terminal VINI. For example, the reset circuit 700 includes a control terminal 700m, a first terminal 100a, and a second terminal 700b. The control terminal 700m of the reset circuit 700 serves as the control terminal 780m of the reset control circuit 780 and is configured to receive the reset control signal G3. The first terminal 100a of the reset circuit 700 serves as the third terminal 780c of the reset control circuit 780 and is electrically connected to the first electrode 600a of the light-emitting element 600. The second terminal 700b of the reset circuit 700 serves as the second terminal 780b of the reset control circuit 780 and is electrically connected to the reset signal terminal VINI to receive the reset signal VINI. For example, in combination with Figures 1 and 2, the first electrode of the second storage capacitor C2 serves as the first end 780a of the reset control circuit 780 and is electrically connected to the first end 100a of the driving circuit 100, and the second electrode of the second storage capacitor C2 is electrically connected to the first end 700a of the reset circuit 700. Therefore, under this scheme, the second electrode of the second storage capacitor C2 is indirectly electrically connected to the reset signal terminal VINI through the reset circuit 700.

[0126] Since the second electrode of the second storage capacitor C2 is connected to the first end 700a of the reset circuit 700 rather than the second end 700b of the reset circuit 700, the reset signal VINI needs to pass through the second end 700b and the first end 700a of the reset circuit 700 in sequence before it can be applied to the second electrode of the second storage capacitor C2 and the first electrode 600a of the light-emitting element 600, thereby reducing the risk of introducing noise into the pixel circuit 101 due to fluctuations in the reset signal VINI.

[0127] Of course, in other embodiments of the present disclosure, the second electrode of the second storage capacitor C2 may also be directly electrically connected to the reset signal terminal VINI to make the structural design of the pixel circuit more flexible, which is not limited in the embodiments of the present disclosure.

[0128] For example, as shown in FIG. 1 , the pixel circuit 10 further includes a data writing circuit 200 and a first light emitting control circuit 400 .

[0129] For example, as shown in FIG1 , the data write circuit 200 includes a control terminal 200m, a first terminal 200a, and a second terminal 200b. The control terminal 200m of the data write circuit 200 is configured to receive a data scan signal G1. The first terminal 200a of the data write circuit 200 is electrically connected to the data signal terminal DATA to receive the data signal DATA. The second terminal 200b of the data write circuit 200 is electrically connected to the first node N1. The data write circuit 200 is configured to write the data signal DATA to the control terminal 100m of the driving circuit 100 in response to the data scan signal G1. For example, during the data write phase, the data write circuit 200 is turned on in response to the data scan signal G1, so that the data signal DATA can be written to the control terminal 100m of the driving circuit 100 through the data write circuit 200.

[0130] As shown in FIG1 , the first light-emitting control circuit 400 includes a control terminal 400m, a first terminal 400a, and a second terminal 400b. The control terminal 400m of the first light-emitting control circuit 400 is configured to receive a first light-emitting control signal EM1. The first terminal 400a of the first light-emitting control circuit 400 is electrically connected to the second terminal 100b of the driver circuit 100. The second terminal 400b of the first light-emitting control circuit 400 is electrically connected to the first voltage terminal ELVDD to receive a first power supply voltage ELVDD. The first light-emitting control circuit 400 is configured to apply the first power supply voltage ELVDD to the second terminal 100b of the driver circuit 100 in response to the first light-emitting control signal EM1. For example, during the compensation phase, the first light-emitting control circuit 400 can be turned on in response to the first light-emitting control signal EM1, thereby applying the first power supply voltage ELVDD to the second terminal 100b of the driver circuit 100 via the first light-emitting control circuit 400. The second electrode 600 b of the light emitting element 600 receives the second power voltage VSS. For example, the first power voltage ELVDD may be a high voltage, and the second power voltage VSS may be a low voltage, but the embodiments of the present disclosure are not limited thereto.

[0131] FIG2 is a circuit diagram of an implementation example of the pixel circuit shown in FIG1 ; FIG3 is a signal timing diagram of a driving method provided by at least one embodiment of the present disclosure.

[0132] For example, the pixel circuit shown in FIG1 can be implemented as the pixel circuit structure shown in FIG2. As shown in FIG2, the pixel circuit 101 includes: a driving transistor DT, a data writing transistor T1, a first light-emitting control transistor T2, a first compensation transistor T3, a second light-emitting control transistor T4, a reset transistor T5, a first storage capacitor C1, a second storage capacitor C2, and a light-emitting element OLED. For example, the data writing transistor T1, the first light-emitting control transistor T2, the first compensation transistor T3, the second light-emitting control transistor T4, and the reset transistor T5 are used as switching transistors. For example, the light-emitting element is an OLED, which can be of various types, such as top emission, bottom emission, etc., and can emit red light, green light, blue light, or white light, etc., and the embodiments of the present disclosure are not limited to this.

[0133] As shown in Figures 1 and 2, the driving circuit 100 includes a driving transistor DT. The gate of the driving transistor DT serves as a control terminal 100m of the driving circuit 100 and is electrically connected to a first node N1. A first electrode of the driving transistor DT serves as a first terminal 100a of the driving circuit 100 and is electrically connected to a first electrode of a second storage capacitor C2 at a second node N2. A second electrode of the driving transistor DT serves as a second terminal 100b of the driving circuit 100 and is electrically connected to a first voltage terminal ELVDD to receive a first power supply voltage ELVDD.

[0134] As shown in Figures 1 and 2, the first compensation circuit 300 includes a first compensation transistor T3 and a first storage capacitor C1. The gate of the first compensation transistor T3 serves as a control terminal 300m of the first compensation circuit 300 and is electrically connected to the first compensation control signal terminal G2 to receive the first compensation control signal G2. The first electrode of the first compensation transistor T3 serves as a first terminal 300a of the first compensation circuit 300 and is electrically connected to the reference signal terminal REF to receive the reference signal REF. The second electrode of the first compensation transistor T3 is electrically connected to the first node N1. The first electrode of the first compensation capacitor C1 is electrically connected to the gate of the drive transistor DT, and the second electrode of the first storage capacitor C1 is electrically connected to the first electrode of the drive transistor DT.

[0135] For example, as shown in Figures 1 and 2, the second light emission control circuit 500 includes a second light emission control transistor T4. The gate of the second light emission control transistor T4 is electrically connected to the second light emission control terminal EM2 to receive the second light emission control signal EM2. A first electrode of the second light emission control transistor T4 is electrically connected to the first terminal 100a of the driving circuit 100. A second electrode of the second light emission control transistor T4 is electrically connected to the first electrode 600a of the light emitting element 600.

[0136] As shown in Figures 1 and 2, the reset circuit 700 includes a reset transistor T5, the gate of which is electrically connected to the reset control terminal G3 to receive the reset control signal G3. A first electrode of the reset transistor T5 is electrically connected to the second electrode of the second storage capacitor C2 and the first terminal 100a of the drive circuit 100, and a second electrode of the reset transistor T5 is electrically connected to the reset signal terminal VINI to receive the reset signal VINI.

[0137] As shown in Figures 1 and 2, in the pixel circuit provided by at least one embodiment of the present disclosure, the first electrode of the reset transistor T5 is indirectly electrically connected to the first end 100a of the driving circuit 100, that is, the first electrode of the reset transistor T5 is electrically connected to the first end 100a of the driving circuit 100 through the second light-emitting control transistor T4.

[0138] As shown in Figures 1 and 2, the reset signal from the reset signal terminal VINI needs to pass through the first electrode and the second electrode of the reset transistor T5 before it can be applied to the first electrode of the light-emitting element OLED and / or the first end of the driving circuit 100, thereby reducing the impact of the fluctuation of the reset signal on the voltage of the first electrode of the light-emitting element OLED and the first end 100a of the driving circuit 100, and reducing the risk of introducing noise into the pixel circuit 10, thereby making the driving current more stable to improve the display effect.

[0139] For example, as shown in Figures 1 and 2, the second compensation circuit 800 includes a second storage capacitor C2. The first electrode of the second storage capacitor C2 serves as the first terminal 800a of the second compensation circuit 800 and is electrically connected to the first terminal 100a of the driving circuit 100 (i.e., the first electrode of the driving transistor DT). The second electrode of the second storage capacitor C2 serves as the second terminal 800b of the second compensation circuit 800 and is electrically connected to the first terminal 700a of the reset circuit 700 (i.e., the first electrode of the reset transistor T5).

[0140] In the technical solution of this embodiment, since the second electrode of the second storage capacitor C2 is electrically connected to the first electrode of the reset transistor T5 rather than the second electrode of the reset transistor T5, the reset signal VINI is applied to the second electrode of the second storage capacitor C2 and the first electrode 600a of the light-emitting element 600 through the second electrode and the first electrode of the reset transistor T5 in sequence, thereby reducing the risk of introducing noise into the pixel circuit 101 due to fluctuations in the reset signal VINI.

[0141] For example, as shown in Figures 1 and 2, the data write circuit 200 includes a data write transistor T1, the gate of the data write transistor T1 is electrically connected to the data scan signal terminal G1 to receive the data scan signal G1, the first electrode of the data write transistor T1 is electrically connected to the data signal terminal DATA to receive the data signal DATA, and the second electrode of the data write transistor T1 is electrically connected to the first node N1.

[0142] For example, as shown in Figures 1 and 2, the first emission control circuit 400 includes a first emission control transistor T2. The gate of the first emission control transistor T2 is electrically connected to the first emission control terminal EM1 to receive the first emission control signal EM1. The first electrode of the first emission control transistor T2 is electrically connected to the second terminal 100b of the driving circuit 100. The second electrode of the first emission control transistor T2 is electrically connected to the first voltage terminal ELVDD to receive the first power supply voltage ELVDD.

[0143] It should be noted that in the description of the embodiments of the present disclosure, the first node N1, the second node N2, and the third node N3 do not necessarily represent actual components, but rather represent junction points of circuit connections in the circuit diagram. In the description of the embodiments of the present disclosure, the symbol DATA can represent both a data signal terminal and a data signal; similarly, the symbol G1 can represent both a data scan signal terminal and a data scan signal; the symbol REF can represent both a reference signal terminal and a reference signal; the symbol G2 can represent both a first compensation control signal terminal and a first compensation control signal; the symbol EM1 can represent both a first light-emitting control terminal and a first light-emitting control signal; the symbol ELVDD can represent both a first voltage terminal and a first power supply voltage; the symbol EM2 can represent both a second light-emitting control terminal and a second light-emitting control signal; the symbol G3 can represent both a reset control terminal and a reset control signal; the symbol VINI can represent both a reset signal terminal and a reset signal, and can also represent a reset voltage; and the symbol VSS can represent both a second voltage terminal and a second power supply voltage. The following embodiments are similar and will not be described in detail.

[0144] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics. The embodiments of the present disclosure are described using thin film transistors as examples. The source and drain of the transistors used here may be symmetrical in structure, so the source and drain may be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one pole is directly described as the first pole and the other pole is directly described as the second pole.

[0145] In addition, transistors can be divided into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages), and the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages). However, the embodiment of the present disclosure does not limit the type of transistor. When the type of transistor changes, the connection relationship in the circuit can be adjusted accordingly.

[0146] The working principle of the pixel circuit 101 shown in FIG2 is described below in conjunction with the signal timing diagram shown in FIG3. As shown in FIG3, the display process of each frame of image includes four stages, namely reset stage 1, compensation stage 2, data writing stage 3 and light emitting stage 4.

[0147] For example, in the pixel circuit 101 shown in FIG2 , the driving transistor DT, the data writing transistor T1, the first light emission control transistor T2, the first compensation transistor T3, the second light emission control transistor T4, and the reset transistor T5 are all N-type transistors, i.e., the gate of each transistor is turned on when a high-level signal is connected and turned off when a low-level signal is connected. Of course, in other embodiments, the above-mentioned transistors may also be P-type transistors. The embodiments of the present disclosure do not limit the type of each transistor, and the type can be selected as needed. Here, N-type transistors are used as an example.

[0148] As shown in Figures 1-3, an embodiment of the present disclosure provides a driving method, including: setting the reset control signal G3 to a turn-on signal, so that the reset signal VINI is applied to the first electrode 600a of the light-emitting element 600 and / or the first end 100a of the driving circuit 100 through the reset control circuit 780 in sequence.

[0149] 1-3 , the first terminal 100a of the driving circuit 100 is indirectly connected to the reset signal terminal VINI, that is, the two are electrically connected through the reset control circuit 780. For example, when the reset control signal G3 is a shutdown signal, the first terminal 100a of the driving circuit 100 is disconnected from the reset signal terminal VINI.

[0150] With this arrangement, the reset signal from the reset signal terminal needs to pass through the reset control circuit before it can be applied to the first electrode of the light-emitting element and / or the first end of the driving circuit, thereby reducing the impact of fluctuations in the reset signal on the voltage of the first electrode of the light-emitting element and the first end of the driving circuit, reducing the risk of introducing noise into the pixel circuit, and thus making the driving current more stable to improve the display effect.

[0151] For example, as shown in Figures 1-3, in reset phase 1, the driving method of the pixel circuit includes: setting the reset control signal G3 to an on signal during at least a portion of the time period so that the first terminal 700a and the second terminal 700b of the reset circuit 700 are conductive, and the reset signal VINI is sequentially applied to the second electrode of the second storage capacitor C2, the first terminal 100a of the driving circuit 100, and the first electrode 600a of the light-emitting element 600 through the second terminal 700b and the first terminal 700a of the reset circuit 700, thereby achieving a reset operation. For example, the above-mentioned at least a portion of the time period can be the entire time period of reset phase 1, or it can be a portion of the time period of reset phase 1, and the embodiments of the present disclosure are not limited in this regard.

[0152] Correspondingly, as shown in Figures 1-3, during reset phase 1, the reset control signal G3 is a high-level signal for at least a portion of the time period to turn on the reset transistor T5, thereby allowing the reset signal VINI to be applied to the second electrode of the second storage capacitor C2 and the first electrode 600a of the light-emitting element 600. During this phase, the second emission control signal EM2 is a high-level signal to turn on the second emission control transistor T4, and the reset signal VINI is then applied to the first terminal 100a of the driver circuit 100 via the second emission control transistor T4.

[0153] For example, as shown in Figure 1-3, in the compensation stage 2 and the data writing stage 3, the driving method of the pixel circuit includes: setting the reset control signal G3 as the turn-on signal, and applying the reset signal VINI to the second electrode of the second storage capacitor C2 and the first electrode 600a of the light-emitting element 600 through the second end 700b and the first end 700a of the reset circuit 700 in sequence.

[0154] Correspondingly, as shown in Figures 1-3, during compensation phase 2 and data writing phase 3, the reset control signal G3 is a high-level signal for at least a portion of the time period to turn on the reset transistor 5. For example, the second light-emission control signal EM2 is a low-level signal to turn off the second light-emission control transistor T4. Therefore, the voltage at the second electrode of the second storage capacitor C2 and the first electrode 600a of the light-emitting element 600 can be maintained at the reset voltage VINI.

[0155] For example, as shown in Figures 1-3, in light-emitting stage 4, the driving method of the pixel circuit includes: setting the reset control signal G3 to an off signal during at least a portion of the time period, so that the second electrode of the second storage capacitor C2 is disconnected from the reset signal terminal VINI. For example, the at least portion of the time period can be the entire time period of light-emitting stage 4, or it can be a portion of the time period of light-emitting stage 4, and the embodiments of the present disclosure are not limited to this.

[0156] Correspondingly, as shown in Figures 1-3, in the light-emitting stage 4, the reset control signal G3 is a low-level signal during at least part of the time period to turn off the reset transistor 5, so that the second electrode of the second storage capacitor C2 and the first electrode of the light-emitting element OLED are disconnected from the reset signal terminal VINI, so as to facilitate maintaining the voltage of the first electrode of the light-emitting element OLED at the voltage when the light-emitting element OLED is in the light-emitting state.

[0157] In this way, as shown in Figures 1-3, when the reset control signal G3 is an on signal, the reset signal VINI enters the interior of the pixel circuit 101 through the reset control circuit 780, for example, it is applied to the first electrode 600a of the light-emitting element 600 and the second pole of the second storage capacitor C2. When the reset control signal G3 is an off signal, the reset signal VINI is disconnected from the first electrode 600a of the light-emitting element 600, the second pole of the second storage capacitor C2, and the first end 100a of the drive circuit 100. While meeting the working requirements of each stage, the impact of the fluctuation of the reset signal VINI on the voltage of the first end 100a of the drive circuit 100 can be reduced, reducing the risk of introducing noise into the pixel circuit 101, thereby making the drive current more stable to improve the display effect.

[0158] For example, as shown in Figure 3, reset phase 1 includes a first sub-reset phase P1, a second sub-reset phase P2, and a third sub-reset phase P3, which are performed sequentially. For example, compensation phase 2 includes a first sub-compensation phase P4 and a second sub-compensation phase P5, which are performed sequentially. For example, data writing phase 3 includes a first sub-data writing phase P6, a second sub-data writing phase P7, and a third sub-data writing phase P8, which are performed sequentially. For example, light-emitting phase 4 includes a first sub-light-emitting phase P9, a second sub-light-emitting phase P10, a third sub-light-emitting phase P11, and a fourth sub-light-emitting phase P12, which are performed sequentially.

[0159] Figure 4A is a schematic diagram of the pixel circuit in Figure 2 during the third sub-reset phase; Figure 4B is a schematic diagram of the pixel circuit in Figure 2 during the second sub-compensation phase; Figure 4C is a schematic diagram of the pixel circuit in Figure 2 during the third sub-data write phase; and Figure 4D is a schematic diagram of the pixel circuit in Figure 2 during the fourth sub-light-emitting phase. Furthermore, transistors marked with dashed lines in Figures 4A through 4D are all in an off state during the corresponding phase.

[0160] Specifically, for example, as shown in FIG1 and FIG3 , in the reset phase 1, the driving method of the pixel circuit includes:

[0161] Step S1010: disconnecting the second terminal 100b of the driving circuit 100 from the first voltage terminal ELVDD;

[0162] Step S1020: setting the reset control signal G3 to an on signal to turn on the reset circuit 700; and

[0163] Step S1030 : Set the first compensation control signal G2 to a turn-on signal to turn on the first compensation circuit 300 .

[0164] During the reset phase, the data scan signal G1 remains as an off signal to turn off the data writing circuit 200 , and the second light emitting control signal EM2 remains as an on signal to turn on the second light emitting control circuit 500 .

[0165] For example, as shown in Figures 1 and 3, in the first sub-reset phase P1, the data scan signal G1 remains as an off signal to turn off the data writing circuit 200; the second light-emitting control signal EM2 remains as an on signal to turn on the second light-emitting control circuit 500; the first compensation control signal G2 and the reset control signal G3 are both maintained as off signals, so that the first compensation circuit 300 and the reset circuit 700 are both in the off state; in addition, corresponding to step S1010, the first light-emitting control signal EM1 is switched to an off signal to turn off the first light-emitting control circuit 400, thereby disconnecting the second end 100b of the driving circuit 100 from the first voltage end ELVDD.

[0166] For example, as shown in Figures 1 and 3, in the second sub-reset phase P2, the data scan signal G1 remains as a turn-off signal to turn off the data writing circuit 200; the second light-emitting control signal EM2 remains as a turn-on signal to turn on the second light-emitting control circuit 500; the first light-emitting control signal EM1 remains as a turn-off signal to turn off the first light-emitting control circuit 400; the first compensation control signal G2 remains as a turn-off signal to make the first compensation circuit 300 in an off state; in addition, corresponding to step S1020, the reset control signal G3 is switched to a turn-on signal to turn on the reset circuit 700, so that the reset signal VINI can be applied to the second pole of the second storage capacitor C2, the first electrode 600a of the light-emitting element 600 and the first end 100a of the driving circuit 100.

[0167] For example, as shown in Figures 1 and 3, in the third sub-reset phase P3, the data scan signal G1 remains as a turn-off signal to turn off the data writing circuit 200; the second light-emitting control signal EM2 remains as a turn-on signal to turn on the second light-emitting control circuit 500; the first light-emitting control signal EM1 remains as a turn-off signal to turn off the first light-emitting control circuit 400; the reset control signal G3 remains as a turn-on signal to turn on the reset circuit 700; in addition, corresponding to step S1030, the first compensation control signal G2 is switched to a turn-on signal to turn on the first compensation circuit 300, so that the reference signal REF can be applied to the control terminal 100m of the driving circuit 100.

[0168] For example, as shown in Figures 1 and 3, by turning on the reset circuit 700 when the first light-emitting control circuit 400 is turned off, that is, when the first light-emitting control circuit 400 is turned off in the first sub-reset stage P1, the reset circuit 700 is turned on in the second sub-reset stage P2. In this way, the first light-emitting control circuit 400 can be prevented from being turned on to the reset circuit 700 through the drive circuit 100 and the second light-emitting control circuit 500, thereby making the drive current more stable, which is beneficial to the safety of the device.

[0169] Correspondingly, as shown in Figures 2 and 3, in the first sub-reset phase P1, the data scan signal G1 remains at a low level signal to turn off the data writing transistor T1; the second light-emitting control signal EM2 remains at a high level signal to turn on the second light-emitting control transistor T4; the first compensation control signal G2 and the reset control signal G3 are both maintained at low level signals, so that the first compensation transistor T3 and the reset transistor T5 are both in the on state; in addition, corresponding to step S1010, the first light-emitting control signal EM1 is switched to a low level signal to turn off the first light-emitting control transistor T2, thereby disconnecting the second electrode of the driving transistor DT from the first voltage terminal ELVDD.

[0170] Correspondingly, as shown in Figures 2 and 3, in the second sub-reset phase P2, the data scan signal G1 remains at a low level signal to turn off the data write transistor T1; the second light-emitting control signal EM2 remains at a high level signal to turn on the second light-emitting control transistor T4; the first light-emitting control signal EM1 remains at a low level signal to turn off the first light-emitting control transistor T2; the first compensation control signal G2 remains at a low level signal to turn off the first compensation transistor T3; in addition, corresponding to step S1020, the reset control signal G3 is switched to a high level signal to turn on the reset transistor T5, so that the reset signal VINI can be applied to the second electrode of the second storage capacitor C2, the first electrode of the light-emitting element OLED and the first electrode of the driving transistor DT.

[0171] Correspondingly, as shown in Figures 3 and 4A, in the third sub-reset phase P3, the data scan signal G1 remains at a low level signal to turn off the data write transistor T1; the second light-emitting control signal EM2 remains at a high level signal to turn on the second light-emitting control transistor T4; the first light-emitting control signal EM1 remains at a low level signal to turn off the first light-emitting control transistor T2; the reset control signal G3 remains at a high level signal to turn on the reset transistor T5; in addition, corresponding to step S1030, the first compensation control signal G2 is switched to a high level signal to turn on the first compensation transistor T3, so that the reference signal REF can be applied to the gate of the driving transistor DT.

[0172] Therefore, as shown in Figures 3 and 4A, the reset transistor T5 is turned on when the first light-emitting control transistor T2 is turned off, thereby preventing the first light-emitting control transistor T2 from being turned on by the reset transistor T5 through the driving transistor DT and the second light-emitting control transistor T4, thereby making the driving current more stable, which is beneficial to the safety of the device.

[0173] For example, as shown in Figures 3 and 4A, the reference signal REF is a reference voltage, and its value is VREF; the reset signal VINI is a reset voltage, and its value is VINI. The difference between the voltage value of the gate of the driving transistor DT and the voltage value of its first electrode is the gate-source voltage Vgs. The threshold voltage of the driving transistor DT is Vth. After the steps in the first sub-reset phase P1, the second sub-reset phase P2, and the third sub-reset phase P3 are completed, Vgs ≥ Vth, that is, VREF - VINI ≥ Vth. For example, when Vgs > Vth, the driving transistor DT is in the on state.

[0174] It should be noted that the steps corresponding to the first sub-reset stage P1, the second sub-reset stage P2, and the third sub-reset stage P3 are performed sequentially to effectively control the drive current in the pixel circuit, but the embodiments of the present disclosure are not limited thereto. For example, in some embodiments, the steps corresponding to at least two of the first sub-reset stage P1, the second sub-reset stage P2, and the third sub-reset stage P3 may be performed simultaneously. For example, the steps corresponding to the first sub-reset stage P1, the second sub-reset stage P2, and the third sub-reset stage P3 may be performed simultaneously, but the embodiments of the present disclosure are not limited thereto.

[0175] For example, as shown in FIG1 and FIG3 , in compensation stage 2, the driving method of the pixel circuit includes:

[0176] Step S2010 : setting the second light control signal EM2 to a turn-off signal to turn off the second light control circuit 500 , and setting the first light control signal EM1 to a turn-off signal to turn off the first light control circuit 400 ; and

[0177] Step S2020 : Set the first light-emitting control signal EM1 to be a turn-on signal to turn on the first light-emitting control circuit 400 , and keep the second light-emitting control signal EM2 to be a turn-off signal.

[0178] For example, in compensation phase 2, the data scan signal G1 remains as a turn-off signal to keep the data write circuit 200 turned off, the first compensation control signal G2 remains as an turn-on signal to keep the first compensation circuit 300 turned on, and the reset control signal G3 is an turn-on signal to turn on the reset circuit 700.

[0179] For example, as shown in Figures 1 and 3, in the first sub-compensation stage P4, the data scan signal G1 remains as an off signal to turn off the data writing circuit 200; the first compensation control signal G2 and the reset control signal G3 are both maintained as on signals, so that the first compensation circuit 300 and the reset circuit 700 are both in the on state; the first light-emitting control signal EM1 remains as an off signal to turn off the first light-emitting control circuit 400; in addition, corresponding to step S2010, the second light-emitting control signal EM2 is switched to an off signal to turn off the second light-emitting control circuit 500.

[0180] For example, as shown in Figures 1 and 3, in the second sub-compensation stage P5, the data scan signal G1 remains as an off signal to turn off the data writing circuit 200; the first compensation control signal G2 and the reset control signal G3 are both maintained as on signals, so that the first compensation circuit 300 and the reset circuit 700 are both in the on state; the second light-emitting control signal EM2 remains as an off signal to turn off the second light-emitting control circuit 500; in addition, corresponding to step S2020, the first light-emitting control signal EM1 is switched to an on signal to turn on the first light-emitting control circuit 400.

[0181] For example, as shown in Figures 1 and 3, when the second light-emitting control circuit 500 is turned off in the first sub-compensation stage P4 and remains turned off in the second sub-compensation stage P5, the first light-emitting control circuit 400 is turned on in the second sub-compensation stage P5. Therefore, when the reset circuit 700 is in the on state, the first light-emitting control circuit 400 is prevented from being turned on to the reset circuit 700 through the driving circuit 100 and the second light-emitting control circuit 500, thereby making the driving current more stable, thereby benefiting the safety of the device.

[0182] Correspondingly, as shown in Figures 2 and 3, in the first sub-compensation stage P4, the data scanning signal G1 remains as an off signal to turn off the data writing transistor T1; the first compensation control signal G2 and the reset control signal G3 are both maintained as on signals, so that the first compensation transistor T3 and the reset transistor T5 are both in the on state; the first light-emitting control signal EM1 remains as an off signal to turn off the first light-emitting control transistor T2; in addition, corresponding to step S2010, the second light-emitting control signal EM2 is switched to an off signal to turn off the second light-emitting control transistor T4.

[0183] Correspondingly, as shown in Figures 3 and 4B, in the second sub-compensation stage P5, the data scanning signal G1 remains as an off signal to turn off the data writing transistor T1; the first compensation control signal G2 and the reset control signal G3 are both maintained as on signals, so that the first compensation transistor T3 and the reset transistor T5 are both in the on state; the second light-emitting control signal EM2 remains as an off signal to turn off the second light-emitting control transistor T4; in addition, corresponding to step S2020, the first light-emitting control signal EM1 is switched to an on signal to turn on the first light-emitting control transistor T2, so that the first power supply voltage ELVDD is applied to the second electrode of the driving transistor DT.

[0184] For example, as shown in Figures 2, 3 and 4B, when the second light-emitting control transistor T4 is turned off in the first sub-compensation stage P4 and remains turned off in the second sub-compensation stage P5, the first light-emitting control transistor T2 is turned on in the second sub-compensation stage P5. Therefore, when the reset transistor T5 is in the on state, the first light-emitting control transistor T2 is prevented from being turned on to the reset transistor T5 through the drive transistor DT and the second light-emitting control transistor T4, thereby making the driving current more stable, thereby facilitating device safety.

[0185] For example, as shown in FIG3 and FIG4B , at the beginning of compensation phase 2, the voltage value of the first electrode of the driving transistor DT is equal to the reset voltage value Vini, and Vgs-Vth>0. After the steps in the first sub-compensation phase P4 and the second sub-compensation phase P5 are completed, the voltage value of the gate of the driving transistor DT is VREF, and the voltage of the second electrode of the driving transistor DT is the first power supply voltage ELVDD. Since the value of the first power supply voltage ELVDD is greater than the voltage value of the first electrode of the driving transistor DT (i.e., Vini), the driving transistor DT can be charged by the first power supply voltage ELVDD until the driving transistor DT is turned off, so that the voltage value Vs of the first terminal of the driving transistor DT is equal to Vref-Vth.

[0186] It should be noted that the steps corresponding to the first sub-reset phase P4 and the second sub-compensation phase P5 are performed sequentially to ensure good control of the drive current in the pixel circuit, but the embodiments of the present disclosure are not limited thereto. For example, in some embodiments, the steps corresponding to the first sub-reset phase P4 and the second sub-compensation phase P5 may also be performed simultaneously, which is not a limitation of the embodiments of the present disclosure.

[0187] For example, as shown in FIG1 and FIG3 , in the data writing phase 3, the driving method of the pixel circuit includes:

[0188] Step S3010: setting the first compensation control signal G2 to a shutdown signal to turn off the first compensation circuit 300, and allowing the second end of the driving circuit 100 to continue receiving the first power voltage ELVDD;

[0189] Step S3020: setting the first light emitting control signal EM1 to a turn-off signal to turn off the first light emitting control circuit 400 , so that the second terminal of the driving circuit 100 is disconnected from the first voltage terminal ELVDD; and

[0190] Step S3030 : Set the data scanning signal G1 to a turn-on signal to turn on the data writing circuit 200 .

[0191] In the data writing phase 2, the second light emitting control signal EM2 is kept as an off signal to keep the second light emitting control circuit 500 turned off, and the reset control signal G3 is kept as an on signal to keep the reset circuit 700 turned on.

[0192] For example, as shown in Figures 1 and 3, in the first sub-data writing phase P6, the data scanning signal G1 remains as a turn-off signal to turn off the data writing circuit 200; the first light-emitting control signal EM1 remains as an on signal to turn on the first light-emitting control circuit 400, so that the second end of the driving circuit 100 continues to receive the first power supply voltage ELVDD; the second light-emitting control signal EM2 remains as a turn-off signal to turn off the second light-emitting control circuit 500; the reset control signal G3 remains as an on signal, so that the reset circuit 700 is in an on state; in addition, corresponding to step S3010, the first compensation control signal G2 is switched to a turn-off signal to turn off the first compensation circuit 300, so that the reference signal REF stops being applied to the control electrode 100m of the driving circuit 100.

[0193] For example, as shown in Figures 1 and 3, in the second sub-data writing phase P7, the data scanning signal G1 remains as a turn-off signal to turn off the data writing circuit 200; the second light-emitting control signal EM2 remains as a turn-off signal to turn off the second light-emitting control circuit 500; the reset control signal G3 remains as an on signal to make the reset circuit 700 in an on state; the first compensation control signal G2 is a turn-off signal to turn off the first compensation circuit 300; in addition, corresponding to step S3020, the first light-emitting control signal EM1 is switched to a turn-off signal to turn off the first light-emitting control circuit 400, so that the second end of the driving circuit 100 stops receiving the first power supply voltage ELVDD.

[0194] For example, as shown in Figures 1 and 3, in the third sub-data writing stage P8, the second light-emitting control signal EM2 remains as a turn-off signal to turn off the second light-emitting control circuit 500; the reset control signal G3 remains as a turn-on signal, so that the reset circuit 700 is in an on state; the first compensation control signal G2 is a turn-off signal to turn off the first compensation circuit 300; the first light-emitting control signal EM1 remains as a turn-off signal to turn off the first light-emitting control circuit 400; in addition, corresponding to step S3030, the data scanning signal G1 is switched to a turn-on signal to turn on the data writing circuit 200, so that the data signal DATA is applied to the control electrode 100m of the driving circuit 100.

[0195] For example, as shown in Figures 1 and 3, the steps corresponding to the third sub-data writing phase P8 are performed after the steps corresponding to the first sub-data writing phase P6. That is, after the first compensation circuit 300 is turned off, the data writing circuit 200 is turned on. This driving method can avoid the situation where the first compensation circuit 300 applies the reference signal REF to the control terminal 100m of the driving circuit 100 while the data writing circuit 200 applies the data signal DATA to the control terminal 100m of the driving circuit 100. This makes the control method of the driving circuit more reliable and the driving current more stable.

[0196] Correspondingly, as shown in Figures 2 and 3, in the first sub-data writing phase P6, the data scanning signal G1 remains as an off signal to turn off the data writing transistor T1; the first light-emitting control signal EM1 remains as an on signal to turn on the first light-emitting control transistor T2, so that the second electrode of the driving transistor DT continues to receive the first power supply voltage ELVDD; the second light-emitting control signal EM2 remains as an off signal to turn off the second light-emitting control transistor T4; the reset control signal G3 remains as an on signal, so that the reset transistor T5 is in the on state; in addition, corresponding to step S3010, the first compensation control signal G2 is switched to an off signal to turn off the first compensation transistor T3.

[0197] Correspondingly, as shown in Figures 2 and 3, during the second sub-data writing phase P7, the data scanning signal G1 remains an off signal to turn off the data writing transistor T1; the second emission control signal EM2 remains an off signal to turn off the second emission control transistor T4; the reset control signal G3 remains an on signal to turn on the reset transistor T5; and the first compensation control signal G2 remains an off signal to turn off the first compensation transistor T3. Furthermore, corresponding to step S3020, the first emission control signal EM1 switches to an off signal to turn off the first emission control transistor T2, thereby disconnecting the second electrode of the driving transistor DT from the first power supply voltage terminal ELVDD.

[0198] Correspondingly, as shown in Figures 3 and 4C , during the third sub-data writing phase P8, the second emission control signal EM2 remains an off signal to turn off the second emission control transistor T4; the reset control signal G3 remains an on signal to turn on the reset transistor T5; the first compensation control signal G2 remains an off signal to turn off the first compensation transistor T3; and the first emission control signal EM1 remains an off signal to turn off the first emission control transistor T2, thereby disconnecting the second electrode of the drive transistor DT from the first power supply voltage terminal ELVDD. Furthermore, corresponding to step S3030, the data scanning signal G1 switches to an on signal to turn on the data writing transistor T1, thereby writing the data signal DATA to the gate of the drive transistor DT.

[0199] For example, as shown in Figures 2, 3, and 4C, after the first compensation transistor T3 is turned off in the first sub-data writing phase P6, the data writing transistor T1 is turned on. This driving method can prevent the first compensation transistor T3 from applying the reference signal REF to the gate of the driving transistor DT while the data writing transistor T1 is applying the data signal DATA to the gate of the driving transistor DT. This makes the control method of the driving circuit more reliable and the driving current more stable.

[0200] For example, as shown in Figures 3 and 4C, when the steps in the above-mentioned first sub-data writing stage P6, the second sub-data writing stage P7 and the third sub-data writing stage P8 are completed, the voltage value of the gate of the driving transistor DT and the voltage value of the first electrode of the first storage capacitor C1 are equal to the value Vdata of the data voltage DATA, and the voltage value of the first end of the driving transistor DT is Vref-Vth+C1 / (C1+C2)×(Vdata-Vref). Here, for clarity, the capacitance value of the first storage capacitor and the first storage capacitor are labeled the same as C1, and the capacitance value of the second storage capacitor and the second storage capacitor are labeled the same as C2.

[0201] It should be noted that the steps corresponding to the first sub-data writing phase P6, the second sub-data writing phase P7, and the third sub-data writing phase P8 are performed sequentially to enable good control of the drive current in the pixel circuit, but the embodiments of the present disclosure are not limited thereto. For example, in some embodiments, the steps corresponding to at least two of the first sub-data writing phase P6, the second sub-data writing phase P7, and the third sub-data writing phase P8 may be performed simultaneously. For example, the steps corresponding to the first sub-data writing phase P6, the second sub-data writing phase P7, and the third sub-data writing phase P8 may be performed simultaneously, but the embodiments of the present disclosure are not limited thereto.

[0202] For example, as shown in FIG2 and FIG3 , in the light emitting stage 4, the driving method of the pixel circuit includes:

[0203] Step S101: setting the data scanning signal G1 to an off signal to turn off the data writing circuit 200;

[0204] Step S102 : setting the second light emitting control signal EM2 to an on signal to turn on the second light emitting control circuit 500 , and setting the first light emitting control signal EM1 to an off signal to turn off the first light emitting control circuit 400 ;

[0205] Step S103: setting the reset control signal G3 to a shutdown signal to turn off the reset circuit 700;

[0206] Step S104 : setting the first light emitting control signal EM1 to a start signal to turn on the first light emitting control circuit 400 , so that the second terminal 100 b of the driving circuit 100 receives the first power voltage ELVDD via the first light emitting control circuit 400 .

[0207] In the light emitting stage 4 , the first compensation control signal G2 is maintained as an off signal to turn off the first compensation circuit 300 .

[0208] For example, as shown in Figures 1 and 3, in the first sub-emission phase P9, the first emission control signal EM1 is an off signal to turn off the first emission control circuit 400; the second emission control signal EM2 is an off signal to turn off the second emission control circuit 500; the first compensation control signal G2 is an off signal to turn off the first compensation circuit 300; and the reset control signal G3 is an on signal to turn on the reset circuit 700. Furthermore, corresponding to step S101, the data scanning signal G1 is switched to an off signal to turn off the data write circuit 200, causing the data write circuit 200 to stop applying the data signal DATA to the control terminal 100m of the driver circuit 100.

[0209] For example, as shown in Figures 1 and 3, in the second sub-emission phase P10, the first emission control signal EM1 is an off signal to turn off the first emission control circuit 400; the first compensation control signal G2 is an off signal to turn off the first compensation circuit 300; the reset control signal G3 is an on signal to turn on the reset circuit 700; and the data scanning signal G1 is an off signal to turn off the data writing circuit 200. Furthermore, corresponding to step S102, the second emission control signal EM2 is switched to an on signal to turn on the second emission control circuit 500.

[0210] For example, as shown in Figures 1 and 3, in the third sub-lighting phase P11, the first light-emitting control signal EM1 is an off signal to turn off the first light-emitting control circuit 400; the first compensation control signal G2 is an off signal to turn off the first compensation circuit 300; the data scanning signal G1 is an off signal to turn off the data writing circuit 200; and the second light-emitting control signal EM2 is an on signal to turn on the second light-emitting control circuit 500. Furthermore, corresponding to step S103, the reset control signal G3 is switched to an off signal to turn off the reset circuit 700.

[0211] For example, as shown in Figures 1 and 3, in the fourth sub-emission phase P12, the first compensation control signal G2 is an off signal to turn off the first compensation circuit 300; the data scanning signal G1 is an off signal to turn off the data writing circuit 200; the second emission control signal EM2 is an on signal to turn on the second emission control circuit 500; and the reset control signal G3 is an off signal to turn off the reset circuit 700. Furthermore, corresponding to step S104, the first emission control signal EM1 is switched to an on signal to turn on the first emission control circuit 400.

[0212] For example, as shown in Figures 1 and 3, the steps corresponding to the fourth sub-light-emitting stage P12 are performed after the steps corresponding to the second sub-light-emitting stage P10. For example, when the second light-emitting control circuit 500 is turned on, so that the voltage at the first terminal 100a of the driver circuit 100, the voltage at the first electrode 600a of the light-emitting element 600, and the voltage at the second terminal of the second storage capacitor C2 are all reset voltage VINI, the voltage value at the first terminal 100a of the driver circuit 100 has a first change, and the voltage at the first terminal of the first storage capacitor C1 also has the first change. Since the voltage across the first storage capacitor C1 does not change suddenly, the voltage at the second terminal of the first storage capacitor C1 (i.e., the voltage at the control terminal 100m of the driver circuit 100) also produces the above-mentioned first change. As a result, the gate-source voltage Vgs of the driver transistor DT (as shown in Figure 4D) in the driver circuit 100 remains unchanged. Then, in the fourth sub-light-emitting stage P12, the first light-emitting control circuit 400 is turned on to cause the light-emitting element 600 to emit light. By adopting this driving method, the voltage difference between the first terminal 100a of the driving circuit 100 and the first electrode 600a of the light emitting element 600 can be eliminated when the light emitting element 600 emits light, thereby reducing the risk of voltage jump at the first terminal 100a of the driving circuit 100.

[0213] Correspondingly, as shown in Figures 2 and 3, during the first sub-emission phase P9, the first emission control signal EM1 is an off signal to turn off the first emission control transistor T2; the second emission control signal EM2 is an off signal to turn off the second emission control transistor T4; the first compensation control signal G2 is an off signal to turn off the first compensation transistor T3; and the reset control signal G3 is an on signal to turn on the reset transistor T5. Furthermore, corresponding to step S101, the data scan signal G1 is switched to an off signal to turn off the data write transistor T1, thereby stopping the data signal DATA from being applied to the control terminal 100m of the driver circuit 100.

[0214] Correspondingly, as shown in Figures 2 and 3, during the second sub-emission phase P10, the first emission control signal EM1 is an off signal, turning off the first emission control transistor T2; the first compensation control signal G2 is an off signal, turning off the first compensation transistor T3; the reset control signal G3 is an on signal, turning on the reset transistor T5; and the data scanning signal G1 is an off signal, turning off the data writing transistor T1. Furthermore, corresponding to step S102, the second emission control signal EM2 is switched to an on signal, turning on the second emission control transistor T4.

[0215] Correspondingly, as shown in Figures 2 and 3, in the third sub-emission phase P11, the first emission control signal EM1 is an off signal to turn off the first emission control transistor T2; the first compensation control signal G2 is an off signal to turn off the first compensation transistor T3; the data scan signal G1 is an off signal to turn off the data write transistor T1; and the second emission control signal EM2 is an on signal to turn on the second emission control transistor T4. Furthermore, corresponding to step S103, the reset control signal G3 is switched to an off signal to turn off the reset transistor T5.

[0216] Correspondingly, as shown in Figures 3 and 4D , in the fourth sub-emission phase P12, the first compensation control signal G2 is an off signal to turn off the first emission control transistor T3; the data scan signal G1 is an off signal to turn off the data write transistor T1; the second emission control signal EM2 is an on signal to turn on the second emission control transistor T4; and the reset control signal G3 is an off signal to turn off the reset transistor T5. Furthermore, corresponding to step S104, the first emission control signal EM1 is switched to an on signal to turn on the first emission control transistor T2.

[0217] For example, as shown in Figures 2, 3, and 4D, the steps corresponding to the fourth sub-light-emitting stage P12 are performed after the steps corresponding to the second sub-light-emitting stage P10. For example, when the second light-emitting control transistor T4 is turned on, so that the voltage of the first electrode of the driving transistor DT, the voltage of the first electrode of the light-emitting element OLED, and the voltage of the second electrode of the second storage capacitor C2 are all reset voltage VINI, the voltage value of the first electrode of the driving transistor DT has a first change, and the voltage of the first electrode of the first storage capacitor C1 also has the first change, and then the voltage of the second electrode of the first storage capacitor C1 (that is, the voltage of the gate of the driving transistor DT) also produces the above-mentioned first change accordingly, so that the gate-source voltage Vgs of the driving transistor DT remains unchanged. Then, in the fourth sub-light-emitting stage P12, the first light-emitting control transistor T3 is turned on to cause the light-emitting element OLED to emit light. Using this driving method, when the light-emitting element OLED is caused to emit light, the voltage difference between the first electrode of the driving transistor DT and the first electrode of the light-emitting element OLED can be eliminated, thereby reducing the risk of voltage jumps at the first electrode of the driving transistor DT.

[0218] For example, as shown in Figures 3 and 4D, after the steps in the first sub-light-emitting stage P9, the second sub-light-emitting stage P10, the third sub-light-emitting stage P11 and the fourth sub-light-emitting stage P12 are completed, since the voltage value of the first electrode of the driving transistor DT is Vini, its change ΔV=Vini-[Vref-Vth+(Vdata-Vref)×C1 / (C1+C2)], so that the voltage value of the gate of the driving transistor DT and the voltage value of the first electrode of the first storage capacitor C1 are both equal to Vdata-[Vref-Vth+C1 / (C1+C2)×(Vdata-Vref)-Vini], and the gate-source voltage Vgs of the driving transistor DT is Vdata-Vref+Vth-C1 / (C1+C2)×(Vdata-Vref).

[0219] The value of the driving current I flowing through the light-emitting element can be obtained according to the following formula:

[0220] I=K×(Vgs-Vth) 2 , K is the conductivity coefficient of the driving transistor DT. That is: I=K×[(Vdata-Vref)×C2 / (C1+C2)] 2

[0221] According to the above formula, the value I of the driving current flowing through the light-emitting element is no longer related to the threshold voltage Vth of the driving transistor. This can compensate for the pixel circuit, solve the problem of threshold voltage Vth drift of the driving transistor due to process technology and long-term operation, and eliminate its influence on the driving current, thereby improving the display effect of the display device using this pixel circuit.

[0222] Figure 5 is a schematic diagram of another pixel circuit provided by an embodiment of the present disclosure; Figure 6 is a signal timing diagram corresponding to the pixel circuit shown in Figure 5; Figure 7A is a schematic diagram of the pixel circuit in Figure 5 in the third sub-reset phase; Figure 7B is a schematic diagram of the pixel circuit in Figure 5 in the second sub-compensation phase; Figure 7C is a schematic diagram of the pixel circuit in Figure 5 in the third sub-data write phase; and Figure 7D is a schematic diagram of the pixel circuit in Figure 5 in the fourth sub-light-emitting phase. In addition, transistors marked with dashed lines in Figures 7A to 7D indicate that they are in an off state during the corresponding phase.

[0223] For example, as shown in FIG5 , the difference between the pixel circuit 102 and the pixel circuit 101 shown in FIG2 lies in the different structures of the data transistor T1 and the first compensation transistor T3. For other structures in the pixel circuit 102, please refer to the relevant description of FIG2 in the above embodiment, which will not be repeated here.

[0224] For example, in the pixel circuit 101 shown in FIG2 , the data write transistor T1 and the first compensation transistor T3 are independently controlled transistors, the data scan signal terminal G1 and the first compensation control signal terminal G2 are independent and different signal terminals, and the data signal terminal DATA and the reference signal terminal REF are independent and different signal terminals. For example, the data write transistor T1 is turned on or off under the control of the data scan signal G1, and the first compensation transistor T3 is turned on or off under the control of the first compensation control signal G2. The data write transistor T1 and the first compensation transistor T3 are independently controlled.

[0225] For example, as shown in Figure 5, the data write transistor T1 is multiplexed as the first compensation transistor T3, the data scan signal G1 is multiplexed as the first compensation control signal G2, the first electrode of the data write transistor T1 is also electrically connected to the reference signal terminal REF to receive the reference signal REF, the data signal terminal DATA is multiplexed as the reference signal terminal REF, and is configured to provide the data signal DATA or the reference signal REF in different time periods.

[0226] For example, as shown in FIG6 , during the driving process of the pixel circuit 102, the operating state (e.g., on state or off state) of each transistor is the same as that of the pixel circuit 101 shown in FIG2 . Compared to the timing diagram shown in FIG3 , the timing states of the first light-emitting control signal EM1, the second light-emitting control signal EM2, and the reset control signal G3 in the timing diagram of FIG6 remain unchanged. The difference is that the timing distribution of the first compensation control signal G2 is eliminated, and the timing state of the data scanning signal G1 is different.

[0227] For example, as shown in Figures 6 and 7A, in the first sub-reset phase P1 and the second sub-reset phase P2, the data scanning signal G1 is an off signal, so that the data writing transistor T1 is in the off state. In the third sub-reset phase P3, the data scanning signal G1 is an on signal, so that the data writing transistor T1 is in the on state. The first electrode of the data writing transistor T1 is electrically connected to the reference signal terminal REF to receive the reference signal REF, and the reference signal REF is applied to the gate of the driving transistor DT.

[0228] For example, as shown in Figures 6 and 7B, in the first sub-compensation stage P4 and the second sub-compensation stage P5, the data scanning signal G1 remains as an on signal so that the data writing transistor T1 is in an on state, and the first electrode of the data writing transistor T1 is electrically connected to the reference signal terminal REF to receive the reference signal REF, and the reference signal REF is applied to the gate of the driving transistor DT.

[0229] For example, as shown in Figures 6 and 7C, in the first sub-data writing phase P6 and the second sub-data writing phase P7, the data scanning signal G1 is an off signal so that the data writing transistor T1 is in an off state. In the third sub-data writing phase P8, the data scanning signal G1 is an on signal so that the data writing transistor T1 is turned on. The first electrode of the data writing transistor T1 is electrically connected to the data signal terminal DATA to receive the data signal DATA, and the data signal DATA is applied to the gate of the driving transistor DT.

[0230] For example, as shown in FIG6 and FIG7D , in the light emitting phase 4 , the data scanning signal G1 is an off signal so that the data writing transistor T1 is in an off state.

[0231] As described above, by multiplexing the data writing transistor as the first compensation transistor, the data signal terminal can receive different signals in different working stages, so as to simplify the structure of the pixel circuit and make its control method more flexible while meeting the working needs of the pixel circuit.

[0232] FIG8 is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure.

[0233] For example, as shown in Figure 8, compared with the pixel circuit 10 shown in Figure 1, the difference between the pixel circuit 20 is that the first light-emitting control circuit 400 is removed. For other structures in the pixel circuit 20, please refer to the relevant description of Figure 1 in the above embodiment, and no repetitive description will be given here.

[0234] For example, as shown in Figure 8, the second end of the driving circuit 100 is directly electrically connected to the first voltage end ELVDD to receive the first power supply voltage ELVDD, that is, no other elements such as transistors or capacitors are set between the second end of the driving circuit 100 and the first voltage end ELVDD, and the second end of the driving circuit 100 is electrically connected to the first voltage end ELVDD through a wire.

[0235] Figure 9 is a circuit diagram of an exemplary implementation of the pixel circuit shown in Figure 8; Figure 10 is a signal timing diagram corresponding to the pixel circuit shown in Figure 9; Figure 11A is a schematic diagram of the pixel circuit shown in Figure 9 in the third sub-reset phase; Figure 11B is a schematic diagram of the pixel circuit shown in Figure 9 in the second sub-compensation phase; Figure 11C is a schematic diagram of the pixel circuit shown in Figure 9 in the third sub-data write phase; and Figure 11D is a schematic diagram of the pixel circuit shown in Figure 9 in the fourth sub-light-emitting phase. In addition, transistors marked with dashed lines in Figures 11A to 11D are all in an off state during the corresponding phase.

[0236] For example, as shown in FIG9 , the pixel circuit 103 differs from the pixel circuit 101 shown in FIG1 in that the first light emission control transistor T2 is eliminated, and the rest of the structures are the same.

[0237] For example, as shown in Figures 9 and 10, during the driving process of the pixel circuit 103, the operating state (e.g., on state or off state) of each transistor is the same as that of the pixel circuit 101 shown in Figure 2. Compared with the timing diagram shown in Figure 3, the timing distribution corresponding to the first light-emitting control signal EM1 is eliminated in the timing diagram shown in Figure 10.

[0238] For example, as shown in Figures 10 and 11A, in the third sub-reset phase P3, the data scan signal G1 remains low to turn off the data write transistor T1; the second light-emitting control signal EM2 is high to turn on the second light-emitting control transistor T4; the reset control signal G3 is high to turn on the reset transistor T5; and the first compensation control signal G2 is high to turn on the first compensation transistor T3. Since the gate-source voltage Vgs of the drive transistor DT is greater than its threshold voltage Vth during this phase, the drive transistor DT is in the on state. Furthermore, the second terminal of the drive transistor DT receives the first power supply voltage ELVDD, thereby charging the drive transistor DT.

[0239] For example, as shown in Figures 10 and 11B, in the second sub-compensation phase P5, the data scanning signal G1 remains an off signal to turn off the data writing circuit 200; the first compensation control signal G2 and the reset control signal G3 are both on signals, so that the first compensation circuit 300 and the reset circuit 700 are both in an on state; and the second light-emitting control signal EM2 remains an off signal to turn off the second light-emitting control circuit 500. The first power supply voltage ELVDD charges the driving transistor DT until the driving transistor DT is turned off, and the voltage Vs at the first terminal of the driving transistor DT is equal to Vref-Vth.

[0240] For example, as shown in Figures 10 and 11C, in the third sub-data writing phase P8, the second light-emitting control signal EM2 is an off signal to turn off the second light-emitting control transistor T4; the reset control signal G3 is an on signal to turn on the reset transistor T5; the first compensation control signal G2 is an off signal to turn off the first compensation transistor T3; the data scanning signal G1 is switched to an on signal to turn on the data writing transistor T1, thereby writing the data signal DATA to the gate of the driving transistor DT. In addition, the second terminal of the driving transistor DT receives the first power supply voltage ELVDD, thereby charging the driving transistor DT.

[0241] For example, as shown in Figures 10 and 11D, in the fourth sub-light-emitting stage P12, the first compensation control signal G2 is an off signal to turn off the first light-emitting control transistor T3; the data scan signal G1 is an off signal to turn off the data writing transistor T1; the second light-emitting control signal EM2 is an on signal to turn on the second light-emitting control transistor T4; the reset control signal G3 is an off signal to turn off the reset transistor T5; and the second end of the driving transistor DT continues to receive the first power supply voltage ELVDD, so that the light-emitting element OLED emits light.

[0242] For example, as shown in Figures 10 and 11C, the mobility of the driving transistor is positively correlated with temperature, that is, when the temperature increases, the mobility increases; and the driving current is positively correlated with the gate-source voltage Vgs of the driving circuit. In the third sub-data writing phase P8, when the data signal DATA is written to the gate of the driving transistor DT and the driving transistor DT is charged, for example, when the temperature of the pixel circuit 103 is high, the mobility is large. Accordingly, the voltage at the first terminal of the driving transistor DT can be made high within a certain charging time, thereby making the gate-source voltage Vgs of the driving transistor DT small, thereby preventing the driving current from being too large. For example, when the temperature of the pixel circuit 103 is low, the mobility is small. Accordingly, the voltage at the first terminal of the driving transistor DT can be made low within a certain charging time, thereby making the gate-source voltage Vgs of the driving transistor DT large, thereby preventing the driving current from being too small.

[0243] Therefore, in the third sub-data writing stage P8, by removing the first light-emitting control transistor T2 (that is, removing the first light-emitting control circuit) so that the second end of the driving transistor DT continues to receive the first power supply voltage ELVDD, the mobility of the driving transistor DT at different temperatures can be compensated to reduce the impact of temperature changes on the driving current in the pixel circuit.

[0244] FIG4E is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure. For example, the difference between the signal timing diagram shown in FIG4E and the signal timing diagram shown in FIG3 is that the timing distribution of the first light-emitting control signal EM1 during the third sub-data writing phase P8 is different, while the timing distributions of the remaining signals are the same.

[0245] For example, for some pixel circuits provided in the embodiments of the present disclosure, such as the pixel circuits in Figures 2 and 5 above, step S3030 in the driving method of the pixel circuit also includes: setting the first light-emitting control signal to a turn-on signal to turn on the first light-emitting control circuit, so that the second end of the driving circuit receives the first power supply voltage.

[0246] For example, as shown in Figures 1 and 4E, in the third sub-data writing phase P8, when the data scanning signal G1 is a turn-on signal to turn on the data writing circuit 200, the first light-emitting control signal EM1 is a turn-on signal to turn on the first light-emitting control circuit 400, so that the second end 100b of the driving circuit 100 receives the first power supply voltage ELVDD; the second light-emitting control signal EM2 remains as a turn-off signal to turn off the second light-emitting control circuit 500; the reset control signal G3 remains as a turn-on signal, so that the reset circuit 700 is in the turn-on state; and the first compensation control signal G2 is a turn-off signal to turn off the first compensation circuit 300.

[0247] Accordingly, as shown in Figures 4C and 4E, in the third sub-data writing phase, the data scanning signal G1 is switched to a turn-on signal to turn on the data writing transistor T1, so that the data signal DATA is written to the gate of the driving transistor DT; the first light-emitting control signal EM1 is switched to a turn-on signal to turn on the first light-emitting control transistor T2, and the first power supply voltage ELVDD is applied to the second end 100b of the driving circuit 100; and the second light-emitting control signal EM2 is maintained as a turn-off signal to turn off the second light-emitting control transistor T4; the reset control signal G3 is maintained as a turn-on signal, so that the reset transistor T5 is in the turn-on state; and the first compensation control signal G2 is maintained as a turn-off signal to turn off the first compensation transistor T3.

[0248] With this arrangement, when the temperature of the pixel circuit is high, the mobility is high, and accordingly, the voltage at the first terminal of the driving transistor can be high, thereby reducing the gate-source voltage Vgs of the driving transistor DT, thereby preventing the driving current from being too large. Conversely, when the temperature of the pixel circuit is low, the mobility is low, and accordingly, the voltage at the first terminal of the driving transistor can be low, thereby reducing the gate-source voltage Vgs of the driving transistor, thereby preventing the driving current from being too small.

[0249] Therefore, in the third sub-data writing stage, by canceling the first light-emitting control transistor T2 and allowing the second end of the driving transistor to continue to receive the first power supply voltage, the mobility of the driving transistor DT at different temperatures can be compensated to reduce the impact of temperature changes on the driving current in the pixel circuit.

[0250] Figure 12 is a schematic diagram of another pixel circuit provided by an embodiment of the present disclosure; Figure 13 is a signal timing diagram corresponding to the pixel circuit shown in Figure 12; Figure 14A is a schematic diagram of the pixel circuit in Figure 12 in the second sub-compensation phase; Figure 14B is a schematic diagram of the pixel circuit in Figure 12 in the third sub-data writing phase; and Figure 14C is a schematic diagram of the pixel circuit in Figure 12 in the fourth sub-light-emitting phase. In addition, transistors marked with dashed lines in Figures 14A to 14C are all in the off state during the corresponding phase.

[0251] For example, as shown in FIG12 , the difference between the pixel circuit 104 and the pixel circuit 103 shown in FIG9 is that the structures of the data transistor T1 and the first compensation transistor T3 are different. For other structures in the pixel circuit 104 , please refer to the relevant description of FIG9 in the above embodiment, and no repetitive description is given here.

[0252] For example, in the pixel circuit 103 shown in FIG9 , the data write transistor T1 and the first compensation transistor T3 are independently controlled transistors, the data scan signal terminal G1 and the first compensation control signal terminal G2 are independent and different signal terminals, and the data signal terminal DATA and the reference signal terminal REF are independent and different signal terminals. For example, the data write transistor T1 is turned on or off under the control of the data scan signal G1, and the first compensation transistor T3 is turned on or off under the control of the first compensation control signal G2. The data write transistor T1 and the first compensation transistor T3 are independently controlled.

[0253] For example, as shown in Figure 12, the data write transistor T1 is multiplexed as the first compensation transistor T3, the data scan signal G1 is multiplexed as the first compensation control signal G2 (see Figure 9), and the first electrode of the data write transistor T1 is also electrically connected to the reference signal terminal REF to receive the reference signal REF. The data signal terminal DATA is multiplexed as the reference signal terminal REF and is configured to provide the data signal DATA or the reference signal REF in different time periods.

[0254] For example, as shown in FIG13 , during the driving process of the pixel circuit 104, the operating state (e.g., on state or off state) of each transistor is the same as that of the pixel circuit 103 shown in FIG9 . Compared to the timing diagram shown in FIG10 , the timing states of the second light emitting control signal EM2 and the reset control signal G3 in the timing diagram of FIG13 remain unchanged, the difference being that the timing distribution of the first compensation control signal G2 is eliminated, and the timing state of the data scanning signal G1 is different.

[0255] For example, as shown in Figures 13 and 12, in the first sub-reset phase P1 and the second sub-reset phase P2, the data scanning signal G1 is an off signal so that the data writing transistor T1 is in an off state. In the third sub-reset phase P3, the data scanning signal G1 is an on signal so that the data writing transistor T1 is in an on state. The first electrode of the data writing transistor T1 is electrically connected to the reference signal terminal REF to receive the reference signal REF, and the reference signal REF is applied to the gate of the driving transistor DT.

[0256] For example, as shown in Figures 13 and 14A, in the first sub-compensation stage P4 and the second sub-compensation stage P5, the data scanning signal G1 remains as an on signal so that the data writing transistor T1 is in an on state, and the first electrode of the data writing transistor T1 is electrically connected to the reference signal terminal REF to receive the reference signal REF, and the reference signal REF is applied to the gate of the driving transistor DT.

[0257] For example, as shown in Figures 13 and 14B, in the first sub-data writing phase P6 and the second sub-data writing phase P7, the data scanning signal G1 is an off signal so that the data writing transistor T1 is in an off state. In the third sub-data writing phase P8, the data scanning signal G1 is an on signal so that the data writing transistor T1 is turned on. The first electrode of the data writing transistor T1 is electrically connected to the data signal terminal DATA to receive the data signal DATA, and the data signal DATA is applied to the gate of the driving transistor DT.

[0258] For example, as shown in FIG. 13 and FIG. 14C , in the light emitting stage 4 , the data scanning signal G1 is an off signal so that the data writing transistor T1 is in a turned-off state.

[0259] As described above, by multiplexing the data writing transistor as the first compensation transistor, the data signal terminal can receive different signals in different working stages, thereby simplifying the structure of the pixel circuit while meeting the working requirements of the pixel circuit and making its control method more flexible. For other structures and technical effects of the pixel circuit 104 shown in Figure 12, please refer to the relevant description of Figure 9 in the above embodiment, and will not be repeated here.

[0260] FIG15 is a schematic block diagram of yet another pixel circuit provided by at least one embodiment of the present disclosure.

[0261] For example, as shown in FIG15 , compared with the pixel circuit 10 shown in FIG1 , the difference of the pixel circuit 30 is that an auxiliary compensation circuit 900 is added. For other structures in the pixel circuit 30 , please refer to the relevant description of FIG1 in the above embodiment, and no repetition will be made here.

[0262] For example, as shown in Figures 15 and 18A, the pixel circuit 30 includes an auxiliary compensation circuit 900, the control end 900m of the auxiliary compensation circuit 900 is configured to receive the auxiliary compensation signal EM3, the first end 900a of the auxiliary compensation circuit 900 is electrically connected to the second electrode of the second storage capacitor C2, the second end 500b of the second light-emitting control circuit 500 and the first end 700a of the reset circuit 700, and the second end of the auxiliary compensation circuit 900 is electrically connected to the first electrode 600a of the light-emitting element 600.

[0263] Figure 16 is a circuit diagram of an implementation example of the pixel circuit shown in Figure 15; Figure 17 is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure; Figure 18A is a schematic diagram of the pixel circuit shown in Figure 15 when it is in the third sub-reset stage; Figure 18B is a schematic diagram of the pixel circuit shown in Figure 15 when it is in the second sub-compensation stage; Figure 18C is a schematic diagram of the pixel circuit shown in Figure 15 when it is in the third sub-data writing stage; Figure 18D is a schematic diagram of the pixel circuit shown in Figure 15 when it is in the fourth sub-light-emitting stage. In addition, the transistors marked with dotted lines in Figures 18A to 18D all indicate that they are in the off state in the corresponding stage.

[0264] For example, as shown in FIG16 , the difference between the pixel circuit 105 and the pixel circuit 101 shown in FIG2 is that an auxiliary compensation transistor T6 is added. For other structures and technical effects in the pixel circuit 105 , please refer to the relevant description of FIG2 in the above embodiment, and no repetition is given here.

[0265] For example, as shown in FIG16 , the auxiliary compensation circuit 900 (see FIG15 ) includes an auxiliary compensation transistor T6. The gate of the auxiliary compensation transistor T6 is electrically connected to the auxiliary compensation control terminal EM3 to receive the auxiliary compensation control signal EM3. The first electrode of the auxiliary compensation transistor T6 is electrically connected to the second electrode of the second compensation capacitor C2 and the second electrode of the second emission control transistor T4. The second electrode of the auxiliary compensation transistor T6 is electrically connected to the first electrode 600a of the light-emitting element 600. For example, the gate of the auxiliary compensation transistor T6 is independent of and not electrically connected to the gate of the second emission control transistor T4. For example, the auxiliary compensation transistor T6 is turned on or off under the control of the auxiliary compensation control signal EM3. The auxiliary compensation control terminal EM3 is an independent control terminal, and the auxiliary compensation control signal EM3 and the second emission control signal EM2 are different signals. For example, the auxiliary compensation transistor T6 can be an N-type transistor, and its type can be the same as or different from the type of other transistors in the pixel circuit 105. This is not limited in the embodiments of the present disclosure.

[0266] For example, as shown in FIG17 , during the driving process of the pixel circuit 105, the operating state (e.g., on state or off state) of each transistor is the same as that of the pixel circuit 101 shown in FIG2 . Compared to the timing diagram shown in FIG3 , the timing diagram in FIG17 adds the timing distribution of the auxiliary compensation control signal EM3.

[0267] For example, as shown in Figures 17-18D , during reset phase 1, compensation phase 2, and light-emitting phase 4, the auxiliary compensation control signal EM3 is an on signal, thereby turning on the auxiliary compensation transistor T6. For example, during the first sub-data writing phase P6 and the second sub-data writing phase P7, the auxiliary compensation control signal EM3 is an on signal, but the embodiments of the present disclosure are not limited thereto. For example, in some embodiments, during the first sub-data writing phase P6 and the second sub-data writing phase P7, the auxiliary compensation control signal EM3 may also be an off signal.

[0268] For example, as shown in Figures 17 and 18C, during the third sub-data writing phase P8, the auxiliary compensation control signal EM3 is an off signal, so that the auxiliary compensation transistor T6 is in an off state. Since the light-emitting element OLED has a capacitor, when the auxiliary compensation transistor T6 is turned on, the capacitor in the light-emitting element OLED is connected in series with the second compensation capacitor C2.

[0269] Therefore, as shown in Figures 17 and 18C, in the third sub-data writing stage P8, when the data writing transistor T1 is turned on and the data signal DATA is written to the gate of the driving transistor DT, the auxiliary compensation transistor T6 is turned off, so that the influence of the capacitance in the light-emitting element OLED on the voltage of the second end of the second compensation capacitor C2 can be reduced, so that the voltage value of the second end of the second compensation capacitor C2 is equal to the reset voltage value Vini, and the voltage of the first end of the driving transistor DT can be made more stable.

[0270] Figure 19 is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure. Figure 20 is a circuit diagram of an implementation example of the pixel circuit shown in Figure 19. Figure 21 is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure.

[0271] For example, as shown in FIG19 , compared with the pixel circuit 30 shown in FIG15 , the difference between the pixel circuit 40 is that the connection method of the control electrode 900m of the auxiliary compensation circuit 900 is different. For other structures in the pixel circuit 40, please refer to the relevant description of FIG15 in the above embodiment, and no repetitive description will be given here.

[0272] For example, as shown in FIG20 , the gate of the auxiliary compensation transistor T6 is electrically connected to the gate of the second emission control transistor T4. The auxiliary compensation transistor T6 and the second emission control transistor T4 share a common gate. The second emission control signal EM2 serves as the auxiliary compensation control signal EM3, and the type of the auxiliary compensation transistor T6 is the same as that of the second emission control transistor T4. Therefore, when the second emission control signal EM2 is an on signal, the auxiliary compensation transistor T6 and the second emission control transistor T4 are both turned on in response to the second emission control signal EM2. When the second emission control signal EM2 is an off signal, the auxiliary compensation transistor T6 and the second emission control transistor T4 are both turned off in response to the second emission control signal EM2.

[0273] Figure 22A is a schematic diagram of the pixel circuit in Figure 20 when it is in the third sub-reset stage; Figure 22B is a schematic diagram of the pixel circuit in Figure 20 when it is in the second sub-compensation stage; Figure 22C is a schematic diagram of the pixel circuit in Figure 20 when it is in the third sub-data writing stage; Figure 22D is a schematic diagram of the pixel circuit in Figure 20 when it is in the fourth sub-light-emitting stage.

[0274] For example, as shown in Figures 21 and 22A, in the reset stage 1, the second light-emitting control signal EM2 is a high-level signal, and the auxiliary compensation transistor T6 and the second light-emitting control transistor T4 are both in the on state, so that the reset signal VINI can be applied to the first end of the light-emitting element OLED through the auxiliary compensation transistor T6.

[0275] For example, as shown in FIG. 21 and FIG. 22B , in compensation stage 2 , the second light emitting control signal EM2 is a low level signal, and the auxiliary compensation transistor T6 and the second light emitting control transistor T4 are both in the off state to prevent the light emitting element OLED from emitting light in this stage.

[0276] For example, as shown in Figures 21 and 22C, in the data writing stage 3, the second light-emitting control signal EM2 is a low-level signal, the auxiliary compensation transistor T6 and the second light-emitting control transistor T4 are both in the off state, and the voltage value of the second end of the second compensation capacitor C2 is equal to the reset voltage value Vini, thereby making the voltage of the first end of the driving transistor DT more stable.

[0277] For example, as shown in Figures 21 and 22D, in the first sub-light-emitting phase P9, the data scanning signal G1 switches from a high-level signal during the third sub-data writing phase P8 to a low-level signal, and the data writing transistor T1 switches from an on state during the third sub-data writing phase P8 to an off state, so that the gate of the driving transistor DT stops receiving the data signal DATA. The second light-emitting control signal EM2 remains a low-level signal, and the auxiliary compensation transistor T6 and the second light-emitting control transistor T4 are both in the off state.

[0278] This arrangement allows both the auxiliary compensation transistor T6 and the second emission control transistor T4 to be controlled by the second emission control signal EM2, simplifying the pixel structure and making the driving method more convenient. Furthermore, it reduces the risk of the auxiliary compensation transistor T6 being in the on state during the process of the data writing transistor T1 being switched off, thereby ensuring good voltage stability at the second end of the second compensation capacitor C2.

[0279] Figure 23 is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure. Figure 24 is a circuit diagram of an implementation example of the pixel circuit shown in Figure 23. Figure 25 is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure.

[0280] For example, as shown in Figure 23, compared with the pixel circuit 30 shown in Figure 15, the difference between the pixel circuit 50 is that the connection method of the auxiliary compensation circuit 900 is different. For other structures of the pixel circuit 50, please refer to the relevant description of Figure 15 in the above embodiment, and no repetitive description will be given here.

[0281] For example, as shown in FIG23 , the pixel circuit 50 includes an auxiliary compensation circuit 900. A control terminal 900m of the auxiliary compensation circuit 900 is configured to receive an auxiliary compensation signal EM3. A first terminal 900a of the auxiliary compensation circuit 900 is electrically connected to the second electrode of the second storage capacitor C2 and the first terminal 700a of the reset circuit 700. A second terminal 900b of the auxiliary compensation circuit 900 is electrically connected to the first electrode 600a of the light-emitting element 600 and the second terminal 500b of the second light-emitting control circuit 500. For example, the control terminal 900m of the auxiliary compensation circuit 900 may be an independent control terminal, and the auxiliary compensation signal EM3 may be an independent control signal for controlling the on / off switching of the auxiliary compensation circuit 900. However, the embodiments of the present disclosure are not limited thereto.

[0282] For example, as shown in Figures 23 and 24, the difference between the pixel circuit 107 and the pixel circuit 105 shown in Figure 16 is that the connection method of the auxiliary compensation transistor T6 is different. For the remaining structures and technical effects, please refer to the relevant description of the above embodiments and will not be repeated here.

[0283] For example, as shown in Figures 23 and 24, the auxiliary compensation circuit 900 includes an auxiliary compensation transistor T6, the gate of the auxiliary compensation transistor T6 is electrically connected to the auxiliary compensation control terminal EM3 to receive the auxiliary compensation control signal EM3, the first electrode of the auxiliary compensation transistor T6 is electrically connected to the second electrode of the second compensation capacitor C2 and the first electrode of the reset transistor T5, and the second electrode of the auxiliary compensation transistor T6 is electrically connected to the first electrode 600a of the light-emitting element 600 and the second electrode of the second light-emitting control transistor T4.

[0284] For example, as shown in FIG24 , the gate of the auxiliary compensation transistor T6 is electrically connected to the gate of the reset transistor T5. The auxiliary compensation transistor T6 and the reset transistor T5 share a common gate. The reset control signal G3 serves as the auxiliary compensation control signal EM3. The type of the auxiliary compensation transistor T6 is the same as that of the reset transistor T5. For example, when the reset control signal G3 is an on signal, the auxiliary compensation transistor T6 and the reset transistor T5 are both turned on in response to the reset control signal G3. When the reset control signal G3 is an off signal, the auxiliary compensation transistor T6 and the reset transistor T5 are both turned off in response to the reset control signal G3.

[0285] Figure 26A is a schematic diagram of the pixel circuit in Figure 24 when it is in the third sub-reset stage; Figure 26B is a schematic diagram of the pixel circuit in Figure 24 when it is in the second sub-compensation stage; Figure 26C is a schematic diagram of the pixel circuit in Figure 24 when it is in the third sub-data writing stage; Figure 26D is a schematic diagram of the pixel circuit in Figure 24 when it is in the fourth sub-light-emitting stage.

[0286] For example, as shown in Figures 25 and 26A, in the first sub-reset phase P1, the first emission control signal EM1 switches from a high-level signal during the fourth sub-emission phase P12 to a low-level signal, and the reset control signal G3 remains at a low-level signal. Thus, during this phase, the risk of a current path being formed from the second end of the drive transistor DT through the second emission control transistor T4 and the auxiliary compensation transistor T6, and then to the second end of the reset transistor T5, can be avoided, thereby improving the safety of the devices in the drive circuit 107. In the second sub-reset phase P2 and the third sub-reset phase P3, the reset control signal G3 switches to a high-level signal to turn on the auxiliary compensation transistor T6 and the reset transistor T5, thereby applying a reset voltage to the first electrode of the light-emitting element OLED.

[0287] For example, as shown in Figures 25, 26B and 26C, in the compensation stage 2 and the data writing stage 3, the reset control signal G3 remains a high-level signal, so that the auxiliary compensation transistor T6 and the reset transistor T5 are both in the on state, thereby keeping the voltage at the second end of the second compensation capacitor C2 at the reset voltage.

[0288] For example, as shown in Figures 25 and 26D, during the first and second light-emitting sub-stages P9 and P10, the reset control signal G3 remains high, turning on both the auxiliary compensation transistor T6 and the reset transistor T5. During the third and fourth light-emitting sub-stages P11 and P12, the reset control signal G3 is low, turning off both the auxiliary compensation transistor T6 and the reset transistor T5. During the first, second, and third light-emitting sub-stages P9, P10, and P11, the first light-emitting control signal EM1 is low, turning off the first light-emitting control transistor T2. During the fourth light-emitting sub-stage P12, the first light-emitting control signal EM1 is high, applying the first power supply voltage ELVDD to the second terminal of the driving transistor DT, and the light-emitting element OLED is in a light-emitting state.

[0289] By providing an auxiliary compensation transistor between the first electrode of the light-emitting element and the second electrode of the second storage capacitor, the influence of the capacitance of the light-emitting element on the voltage of the second electrode of the second storage capacitor can be reduced, so that the voltage of the second electrode of the second storage capacitor is more stable, and the voltage of the first electrode of the driving transistor is further stabilized.

[0290] For example, in some embodiments, when the first electrode of the auxiliary compensation transistor T6 is electrically connected to the second electrode of the second compensation capacitor C2 and the first electrode of the reset transistor T5, and the second electrode of the auxiliary compensation transistor T6 is electrically connected to the first electrode 600a of the light-emitting element 600 and the second electrode of the second light-emission control transistor T4, the gate of the auxiliary compensation transistor T6 and the gate of the reset transistor T5 may also be independent of each other and not electrically connected. For example, the auxiliary compensation transistor T6 may also share a gate with the second light-emission control transistor T4. In this configuration, when the data write transistor T1 is turned on and the data signal DATA is written to the gate of the drive transistor DT, the auxiliary compensation transistor T6 is turned off, thereby reducing the effect of the capacitance in the light-emitting element OLED on the voltage at the second end of the second compensation capacitor C2, so that the voltage value at the second end of the second compensation capacitor C2 is equal to the reset voltage value Vini, thereby further stabilizing the voltage at the first end of the drive transistor DT.

[0291] For example, in some embodiments of the present disclosure, when the first electrode of the auxiliary compensation transistor T6 is electrically connected to the second electrode of the second compensation capacitor C2 and the first electrode of the reset transistor T5, and the second electrode of the auxiliary compensation transistor T6 is electrically connected to the first electrode 600a of the light-emitting element 600 and the second electrode of the second light-emitting control transistor T4, the gate of the auxiliary compensation transistor T6 can be an independent electrode, and the embodiments of the present disclosure do not limit the setting method of the gate of the auxiliary compensation transistor T6.

[0292] The embodiments of the present disclosure also provide a method for reducing the influence of temperature change on the magnitude of driving current.

[0293] For example, as shown in Figures 3 and 4A, after the reset phase 1 is completed, the voltage at the first electrode of the driving transistor DT is the reset voltage VINI when entering the compensation phase 2. In the compensation phase 2, for example, in the second sub-compensation phase P5, the first light-emitting control transistor T2 is turned on, thereby charging the driving transistor DT until the driving transistor DT is turned off, thereby making the gate-source voltage Vgs of the driving transistor DT equal to its threshold voltage Vth, that is, making the voltage Vs at the first electrode of the driving transistor DT = Vref - Vth.

[0294] However, in some cases, as shown in Figures 3 and 4A, the pixel circuit may be interfered with by some factors during actual operation. For example, the charging time of the driving transistor DT may be insufficient, which may cause the driving transistor DT to not be completely turned off, and the voltage Vs of the first electrode of the driving transistor DT to be less than the theoretical value Vref-Vth derived above, resulting in a smaller driving current during the light-emitting phase. In addition, for pixel circuits using oxide materials, the brightness of the light-emitting element may be affected by temperature changes, mainly because the mobility of the oxide transistor changes with temperature. For example, when the temperature rises, the mobility of the oxide transistor will increase, which will cause the driving current to increase; conversely, when the temperature drops, the mobility of the oxide transistor will decrease, which will cause the driving current to increase. Therefore, when the compensation phase is completed, the voltage value of the first electrode of the driving transistor DT is crucial to the brightness of the light-emitting element.

[0295] It should be noted that the method for reducing the influence of temperature change on driving current provided in the embodiments of the present disclosure is applicable to the pixel circuit provided in the embodiments of the present disclosure, and is described below using the pixel circuit 101 shown in FIG. 2 as an example.

[0296] FIG. 27 is a schematic diagram illustrating how the reset voltage varies with temperature in at least one embodiment of the present disclosure.

[0297] For example, in at least one embodiment of the present disclosure, the value of the reset signal is adjustable. For example, the reset signal is a non-constant signal that can be adjusted according to the operating requirements of the pixel circuit. For example, the reset signal can be a DC signal or a non-DC signal.

[0298] For example, as shown in FIG4A , the reset signal VINI is a reset voltage. The method for reducing the influence of temperature change on the driving current provided by the embodiment of the present disclosure includes: increasing the reset voltage Vini as the ambient temperature of the pixel circuit increases.

[0299] For example, the reset signal VINI includes at least a first reset signal and a second reset signal, the first reset signal corresponds to a first display temperature, the second reset signal corresponds to a second display temperature, the first display temperature is lower than the second display temperature, and the value of the first reset signal is lower than the value of the second reset signal. For example, when the temperature of the pixel circuit increases from the first display temperature to the second display temperature, the value of the reset signal increases from the value of the first reset signal to the value of the second reset signal.

[0300] For example, as shown in FIG4A and FIG27 , the value of the first reset signal may be Vini1, the value of the second reset signal may be Vini2, the first display temperature may be 30° C., and the second display temperature may be 60° C. For example, when the temperature of the pixel circuit 102 increases, for example, from the first display temperature to the second display temperature, the value of the reset voltage may increase accordingly, that is, from Vini1 to Vini2. Therefore, when the reset phase is completed, the voltage value of the first electrode of the driving transistor DT may be increased to Vini2 accordingly.

[0301] For example, as shown in FIG4B , before charging, when the initial value of the voltage at the first electrode of the driving transistor DT is Vini1, after the charging time D has passed, the voltage value at the first electrode of the driving transistor DT is Vs1. For example, when the initial value of the voltage at the first electrode of the driving transistor DT is Vini2, after the charging time D has passed, the voltage value at the first electrode of the driving transistor DT is Vs2, and Vs2 is greater than Vs1. Furthermore, when the compensation phase is completed and the driving transistor DT is not completely turned off (for example, due to the aforementioned insufficient charging time, etc.), the voltage values ​​at the first electrode of the driving transistor DT (i.e., Vs1 and Vs2) are less than Vref-Vth.

[0302] For example, as shown in FIG4C , when the data writing phase is completed, the voltage value of the first electrode of the driving transistor DT increases from Vs1+(Vdata-Vref)×C1 / (C1+C2) to Vs2+(Vdata-Vref)×C1 / (C1+C2). Thus, as shown in FIG4D , when entering the light-emitting phase, since the voltage value of the gate of the driving transistor DT is Vdata, the gate-source voltage Vgs of the driving transistor DT decreases from Vdata-[Vs1+(Vdata-Vref)×C1 / (C1+C2)] to Vdata-[Vs2+(Vdata-Vref)×C1 / (C1+C2)].

[0303] The value of the driving current I flowing through the light-emitting element can be obtained according to the following formula:

[0304] I=K×(Vgs-Vth) 2, K is the conductivity coefficient of the driving transistor DT.

[0305] That is, when the gate-source voltage Vgs of the driving transistor DT decreases, the value I of the driving current decreases.

[0306] Therefore, when the temperature of the pixel circuit rises, the mobility of the driving transistor will increase, thereby increasing the driving current. By increasing the reset voltage, the increase in the driving current can be suppressed, and the size of the driving current in the pixel circuit can be within a reasonable range, thereby making the driving current more stable.

[0307] Table 1 shows the data distribution between the reset voltage and the drive current in the embodiment of the present disclosure. For example, as shown in Table 1, in the compensation stage, when the charging time of the driving transistor is 50μs, when the reset voltage increases from 1.2V to 1.4V, the voltage value Vs of the second end of the driving transistor increases from 1.711V to 1.739V, and the stable drive current in the light-emitting stage decreases from 72.4nA to 70.3nA. When the reset voltage increases from 1.4V to 1.6V, the voltage value of the second end of the driving transistor increases from 1.739V to 1.784V, and the stable drive current in the light-emitting stage decreases from 70.3nA to 67.3nA. It can be seen that increasing the reset voltage can effectively suppress the increase of the drive current in the light-emitting stage.

[0308] Table 1

[0309] FIG28 is a schematic diagram showing how the brightness of a light-emitting element varies with grayscale in at least one embodiment of the present disclosure.

[0310] For example, as shown in Figure 28, curve L1 represents the change curve between the brightness and grayscale of the light-emitting element at 300C; curve L2 and curve L3 represent the change curve between the brightness and grayscale of the light-emitting element at 500C, and the reset voltage values ​​corresponding to curve L1 and curve L2 are equal, and both are smaller than the reset voltage value corresponding to curve L3.

[0311] For example, as shown in FIG28 , by comparing curves L1 and L2, it can be seen that when the temperature of the pixel circuit increases from 300°C to 500°C, at the same grayscale, the brightness of the light-emitting element exhibits a significant deviation, that is, the brightness of the light-emitting element at 500°C is greater than that at 300°C. Comparing curves L1 and L3, it can be seen that when the temperature of the pixel circuit increases from 300°C to 500°C, increasing the reset voltage can reduce the brightness deviation of the pixel circuit at 300°C and 500°C, thereby ensuring good brightness uniformity of the light-emitting element.

[0312] For example, when the temperature or driving current of the pixel circuit is monitored to change through detection means, the driving current can be adjusted to a reasonable value by changing the magnitude of the reset signal to reduce the impact of the temperature change.

[0313] For example, the pixel circuit corresponds to a plurality of display frame cycles, and each display frame cycle includes at least the reset phase, compensation phase, data writing phase, and light emitting phase described in the embodiments of the present disclosure. For example, in some embodiments, a display frame cycle may include at least one refresh frame, for example, may include multiple refresh frames, but the embodiments of the present disclosure are not limited thereto. For example, the reset phase, compensation phase, data writing phase, and light emitting phase in the embodiments of the present disclosure are all located within the refresh frame. For example, in other embodiments, a display frame cycle may include at least one refresh frame and at least one hold frame. For example, the hold frame may include a hold reset phase, a hold stress application phase, and a hold light emitting phase.

[0314] For example, when the display frame period has only multiple refresh frames but no hold frame, the driving mode of the display panel using the pixel circuit is a high refresh driving mode, for example, its refresh frequency is above 120 Hz. For example, when the display frame period has multiple refresh frames and at least one hold frame, the multiple refresh frames and the at least one hold frame are alternately arranged, and the driving mode of the display panel using the pixel circuit is a low refresh driving mode. For example, the duration of the hold frame can be 1 / 2, 1 / 3, 1 / 10, 1 / 20, 1 / 30 or 1 / 60 of the duration of the refresh frame, and the embodiments of the present disclosure are not limited to this.

[0315] For example, in at least one embodiment of the present disclosure, the first reset signal is adjusted to the second reset signal during the reset signal adjustment period. For example, the reset signal adjustment period may be located between two adjacent display frame periods, so that the second reset signal can be written before the start of the next display frame period, and the value of the second reset signal remains at Vini2 during the next display frame period. After a certain charging time, the voltage value of the first electrode of the driving transistor is Vs2, and Vs2 is greater than the voltage value Vs1 of the first electrode of the driving transistor corresponding to the first reset signal.

[0316] For example, in at least one embodiment of the present disclosure, the reset signal adjustment period is within a display frame cycle, and the reset signal adjustment period may at least partially overlap with any one of the reset phase, the compensation phase, the data writing phase, and the light-emitting phase. For example, within a display frame cycle, the reset signal adjustment period may at least partially overlap with the reset phase. For example, during a portion of the reset phase (e.g., the second sub-reset phase in the aforementioned embodiment), the value of the reset signal is equal to the value Vini1 of the first reset signal, and during another portion of the reset phase (e.g., the third sub-reset phase in the aforementioned embodiment), the reset signal is adjusted to a second reset signal, whose value is equal to the value Vini2 of the second reset signal. Thus, after the reset signal adjustment period, the voltage value of the first pole of the driving transistor is adjusted from Vs1 to Vs2, and Vs2 is greater than Vs1.

[0317] For example, in at least one embodiment of the present disclosure, the reset signal adjustment period is within a display frame cycle, and the reset signal adjustment period does not overlap with any of the reset phase, compensation phase, data writing phase, and light-emitting phase. For example, the reset adjustment period can be between the reset phase and the compensation phase. For example, during a portion of the reset phase (e.g., the third sub-reset phase in the aforementioned embodiment), the value of the reset signal is equal to the value Vini1 of the first reset signal. During a portion of the compensation phase (e.g., the first sub-compensation phase in the aforementioned embodiment), the reset signal is adjusted to a second reset signal, whose value is equal to the value Vini2 of the second reset signal. Thus, after the reset signal adjustment period, the voltage value of the first electrode of the driving transistor is adjusted from Vs1 to Vs2, and Vs2 is greater than Vs1.

[0318] FIG. 29 is a schematic diagram illustrating how the reset voltage varies with temperature in at least one embodiment of the present disclosure.

[0319] For example, in some embodiments of the present disclosure, when the area of ​​the light-emitting area of ​​the light-emitting element is different, the parasitic capacitance of the light-emitting element itself is different. For example, when the light-emitting area of ​​the light-emitting element is larger, the parasitic capacitance of the light-emitting element itself is larger. For example, for some display panels, the display panel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, the first sub-pixel is configured to emit red light, the second sub-pixel is configured to emit green light, and the third sub-pixel is configured to emit blue light. The light-emitting area of ​​the light-emitting element of the first sub-pixel has a first light-emitting area, the light-emitting area of ​​the light-emitting element of the second sub-pixel has a second light-emitting area, the light-emitting area of ​​the light-emitting element of the third sub-pixel has a third light-emitting area, and the first light-emitting area is smaller than the second light-emitting area, and the second light-emitting area is smaller than the third light-emitting area. The first parasitic capacitance of the light-emitting element of the first sub-pixel itself is smaller than the second parasitic capacitance of the light-emitting element of the second sub-pixel itself, and the second parasitic capacitance of the light-emitting element of the second sub-pixel itself is smaller than the third parasitic capacitance of the light-emitting element of the third sub-pixel itself.

[0320] For example, when the reset voltages of the first, second, and third subpixels during the reset phase are all equal to the value of the first reset signal Vini1, and when the driving currents are all the same, when the temperature of the pixel circuits of the three subpixels increases from the first display temperature to the second display temperature, a first voltage increase occurs between the first electrode and the second electrode of the light-emitting element of the first subpixel, a second voltage increase occurs between the first electrode and the second electrode of the light-emitting element of the second subpixel, and a third voltage increase occurs between the first electrode and the second electrode of the light-emitting element of the third subpixel, and the first voltage increase is greater than the second voltage increase, and the second voltage increase is greater than the third voltage increase. As a result, a first current increase in the driving current of the light-emitting element of the first subpixel is greater than a second current increase in the driving current of the light-emitting element of the second subpixel, and the second current increase in the driving current of the light-emitting element of the second subpixel is greater than an increase in the driving current of the light-emitting element of the third subpixel.

[0321] To balance the effect of temperature increase on the drive current, the values ​​of the reset signals received by the first, second, and third subpixels need to be increased, respectively. The amount of reset signal increase corresponding to the first subpixel is greater than the amount of reset signal increase corresponding to the second subpixel, and the amount of reset signal increase corresponding to the second subpixel is greater than the amount of reset signal increase corresponding to the third subpixel. This ensures that the gate-source voltage decrease in the pixel circuit of the first subpixel is greater than the gate-source voltage decrease in the pixel circuit of the second subpixel, and the gate-source voltage decrease in the pixel circuit of the second subpixel is greater than the gate-source voltage decrease in the pixel circuit of the third subpixel. Accordingly, the drive current decrease in the first subpixel is greater than the drive current decrease in the second subpixel, and the drive current decrease in the second subpixel is greater than the drive current decrease in the third subpixel. This ensures that the drive current of each subpixel is in a stable state.

[0322] Therefore, when the light-emitting areas of the light-emitting elements of multiple pixel circuits are different, and when the temperature of the pixel current increases, the impact of the temperature increase on the driving current can be balanced by increasing the value of the reset signal corresponding to the light-emitting element with a smaller light-emitting area.

[0323] For example, in some other embodiments of the present disclosure, for some display panels, the display panel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, the first sub-pixel is configured to emit red light, the second sub-pixel is configured to emit green light, and the third sub-pixel is configured to emit blue light. The light-emitting element of the first sub-pixel has a first luminous efficiency, the light-emitting element of the second sub-pixel has a second luminous efficiency, and the light-emitting element of the third sub-pixel has a third luminous efficiency, and the first luminous efficiency is greater than the second luminous efficiency, and the second luminous efficiency is greater than the third luminous efficiency.

[0324] For example, when the reset voltages of the first, second, and third subpixels during the reset phase are all equal to the value of the first reset signal, Vini1, and when the drive currents are the same, when the temperature of the pixel circuits of the three subpixels increases from the first display temperature to the second display temperature, in order to ensure constant luminous brightness, the voltage increase required for the light-emitting element of the first subpixel is smaller than the voltage increase required for the light-emitting element of the second subpixel, and the voltage increase required for the light-emitting element of the second subpixel is smaller than the voltage increase required for the light-emitting element of the third subpixel. Consequently, the increase in the drive current of the light-emitting element of the first subpixel is smaller than the increase in the drive current of the light-emitting element of the second subpixel, and the increase in the drive current of the light-emitting element of the second subpixel is smaller than the increase in the drive current of the light-emitting element of the third subpixel.

[0325] To balance the effect of temperature increase on the drive current, the values ​​of the reset signals received by the first, second, and third subpixels need to be increased, respectively. The amount of reset signal increase corresponding to the first subpixel is smaller than the amount of reset signal increase corresponding to the second subpixel, and the amount of reset signal increase corresponding to the second subpixel is smaller than the amount of reset signal increase corresponding to the third subpixel. This ensures that the gate-source voltage decrease in the pixel circuit of the first subpixel is smaller than the gate-source voltage decrease in the pixel circuit of the second subpixel, and the gate-source voltage decrease in the pixel circuit of the second subpixel is smaller than the gate-source voltage decrease in the pixel circuit of the third subpixel. Accordingly, the drive current decrease in the first subpixel is smaller than the drive current decrease in the second subpixel, and the drive current decrease in the second subpixel is smaller than the drive current decrease in the third subpixel. This ensures that the drive current of each subpixel remains stable.

[0326] Therefore, when the luminous efficiencies of the light-emitting elements of multiple pixel circuits are different, and when the temperature at which the pixel current is located increases, the effect of the temperature increase on the driving current can be balanced by making the increment of the reset signal value corresponding to the light-emitting element with lower luminous efficiency larger.

[0327] For example, as shown in FIG29 , in some embodiments of the present disclosure, the first subpixel corresponds to curve R, the second subpixel corresponds to curve G, and the third subpixel corresponds to curve B. On the one hand, because the first light-emitting area corresponding to the first subpixel is smaller than the second light-emitting area of ​​the second subpixel, and the second light-emitting area of ​​the second subpixel is smaller than the third light-emitting area, when the temperature increases, for example, from 30°C to 60°C, the reset voltage of the first subpixel increases more than the reset voltages of the second and third subpixels. On the other hand, because the luminous efficiency of the light-emitting element of the third subpixel is lower than that of the light-emitting element of the second subpixel, and the luminous efficiency of the light-emitting element of the first subpixel is substantially the same as that of the light-emitting element of the second subpixel, when the temperature increases, the reset voltage of the third subpixel increases more than the reset voltage of the second subpixel, thereby ensuring that the drive currents of subpixels emitting different colors remain stable.

[0328] For example, in some embodiments of the present disclosure, referring to FIG. 29 , since the reset voltages of the first color sub-pixel and the third color sub-pixel are relatively close, the first color sub-pixel and the third color sub-pixel can correspond to the same reset voltage, and the second color sub-pixel can correspond to a reset voltage alone, thereby reducing the difficulty of adjustment.

[0329] FIG30 is a schematic diagram illustrating how a reference voltage varies with temperature in at least one embodiment of the present disclosure.

[0330] For example, as shown in FIG4A , the value of the reference signal REF may also be adjustable, and may be a DC signal or a non-DC signal. For example, the reference signal REF may be a reference voltage Vref. The method for reducing the effect of temperature changes on luminous brightness provided by the embodiments of the present disclosure includes decreasing the reference voltage Vref as the ambient temperature of the pixel circuit increases.

[0331] For example, as shown in FIG4A and FIG27, when the temperature of the pixel circuit increases, for example, from 0°C to 30°C, or from 30°C to 60°C, the reference voltage Vref may be increased accordingly, for example, decreased from Vref1 to Vref2. For example, when the reset phase is completed, the driving transistor DT approaches the cut-off state. Therefore, the voltage value of the first electrode of the driving transistor DT decreases from approximately Vref1-Vth to Vref2-Vth, thereby reducing the gate-source voltage Vgs of the driving transistor DT and reducing the driving current during the light-emitting phase.

[0332] Since when the temperature of the pixel circuit increases, the mobility of the driving transistor will increase and the driving current will become larger, therefore, by reducing the reference voltage, the increase of the driving current can be suppressed, and the size of the driving current in the pixel circuit can be within a reasonable range, thereby making the driving current more stable.

[0333] For example, in at least one embodiment of the present disclosure, the first power supply voltage may be a constant voltage or a non-constant voltage. For example, the value of the first power supply voltage may be adjustable. For example, while meeting the operating requirements of the pixel circuit, power consumption may be reduced by lowering the first power supply voltage.

[0334] For example, in at least one embodiment of the present disclosure, the second power supply voltage may be a constant voltage or a non-constant voltage. For example, the value of the second power supply voltage may be adjustable. For example, the brightness of the light-emitting element may be adjusted by adjusting the second power supply voltage while meeting the operating requirements of the pixel circuit.

[0335] At least one embodiment of the present disclosure further provides a pixel circuit. Referring to FIG1 , the pixel circuit 10 includes a driving circuit 100, a first compensation circuit 300, a light-emitting element 600, and a reset control circuit 780. That is, the pixel circuit may not include the second light-emitting control circuit of the pixel circuit in the above embodiment. For other structures and driving methods of the pixel circuit, please refer to the relevant description of the above embodiment and will not be elaborated here.

[0336] As shown in FIG1 , the driving circuit 100 includes a control terminal 100m, a first terminal 100a, and a second terminal 100b. The control terminal 100m of the driving circuit 100 is electrically connected to a first node N1, the first terminal 100a of the driving circuit 100 is electrically connected to a second node N2, and the second terminal 100b of the driving circuit 100 is electrically connected to a third node N3. The driving circuit 100 is configured to control the magnitude of a driving current flowing through the first terminal 100a and the second terminal 100b. For example, the driving current can be used to drive the light-emitting element 600 to emit light. For example, in the light-emitting phase, the driving circuit 100 can provide a driving current to the light-emitting element 600 to drive the light-emitting element 600 to emit light.

[0337] As shown in FIG1 , the first compensation circuit 300 includes a control terminal 300m, a first terminal 300a, a second terminal 300b, and a third terminal 300c. The control terminal 300m of the first compensation circuit 300 is configured to receive a first compensation control signal G2. The first terminal 300a of the first compensation circuit 300 is electrically connected to the reference signal terminal REF to receive the reference signal REF. The second terminal 300b of the first compensation circuit 300 is electrically connected to the second node N2. The third terminal 300c of the first compensation circuit 300 is electrically connected to the first node N1. The first compensation circuit 300 is configured to apply the reference signal REF to the control terminal 100m of the driving circuit 100 in response to the first compensation control signal G2. For example, the first compensation circuit 300 may include a first storage capacitor C1 (see FIG2 ), wherein a first electrode of the first storage capacitor C1 is electrically connected to the control terminal 100m of the driving circuit 100, and a second electrode of the first storage capacitor C1 is electrically connected to the first terminal 100a of the driving circuit 100, but the embodiments of the present disclosure are not limited thereto.

[0338] For example, as shown in Figure 1, the light-emitting element 600 includes a first electrode 600a and a second electrode 600b, the first electrode 600a of the light-emitting element 600 is electrically connected to the first end 100a of the driving circuit 100, and the second electrode 600b of the light-emitting element 600 is electrically connected to the second voltage terminal VSS to receive the second power supply voltage VSS, and the light-emitting element 600 is configured to emit light under the drive current. For example, the second voltage terminal VSS can be grounded, that is, the second power supply voltage VSS can be 0V. For example, the second power supply voltage VSS can be a negative voltage. For example, the light-emitting element 600 can adopt an organic light-emitting diode (OLED). For example, the light-emitting element 600 can also be other types of electroluminescent devices such as inorganic light-emitting diodes, quantum dot light-emitting elements, etc. The embodiment of the present disclosure does not limit the type of light-emitting element.

[0339] As shown in FIG1 , the reset control circuit 780 includes a control terminal 780m, a first terminal 780a, a second terminal 780b, and a third terminal 780c. The control terminal 780m of the reset control circuit 780 is configured to receive a reset control signal G3. The first terminal 780a of the reset control circuit 780 is electrically connected to the first terminal 100a of the driving circuit 100. The second terminal 780b of the reset control circuit 780 is electrically connected to the reset signal terminal VINI to receive the reset signal VINI. The third terminal 780c of the reset control circuit 780 is electrically connected to the first electrode 600a of the light-emitting element 600. The reset control circuit 780 is configured to apply the reset signal VINI to the first electrode 600a of the light-emitting element 600 and / or the first terminal 100a of the driving circuit 100 in response to the reset control signal G3.

[0340] As shown in Figure 1, the first end 780a of the reset control circuit 780 is electrically connected to the first end 100a of the driving circuit 100, and the second end 780b of the reset control circuit 780 is electrically connected to the reset signal end VINI. Therefore, the reset signal from the reset signal end VINI needs to pass through the reset control circuit 780 before it can be applied to the first electrode 600a of the light-emitting element 600 and / or the first end of the driving circuit 100, thereby reducing the impact of the fluctuation of the reset signal on the voltage of the first electrode 600a of the light-emitting element 600 and the first end 100a of the driving circuit 100, and reducing the risk of introducing noise into the pixel circuit 10, thereby making the driving current more stable to improve the display effect.

[0341] With the development of OLED display technology, oxide processes are often used in OLED display products due to their high uniformity. However, the coupling effect of some capacitors in pixel driver circuits made using oxide processes can introduce noise during the display phase, making the output drive current of the pixel driver circuit unstable and affecting its reliability.

[0342] 31 to 48 are schematic diagrams of other implementation examples of the pixel circuit shown in FIG. 1 .

[0343] Figure 31 is a schematic diagram of the structure of another pixel driving circuit provided by an embodiment of the present disclosure. As shown in Figure 31, the pixel driving circuit provided by an embodiment of the present disclosure may include: a driving subcircuit, a first control subcircuit, a second control subcircuit, a third control subcircuit, and a storage subcircuit.

[0344] For example, in some embodiments of the present disclosure, the driving circuit and the connection relationship in Figure 1 correspond to the driving sub-circuit in Figure 31 and subsequent embodiments; the data writing circuit and the first compensation circuit and the connection relationship in Figure 1 correspond to the first control sub-circuit and the storage sub-circuit in Figure 31 and subsequent embodiments; the first light-emitting control circuit and the second light-emitting control circuit in Figure 1 correspond to the second control sub-circuit in Figure 31 and subsequent embodiments; the light-emitting element in Figure 1 corresponds to the light-emitting device in Figure 31 and subsequent embodiments; the reset control circuit and the connection relationship in Figure 1 correspond to the third control sub-circuit in Figure 31 and subsequent embodiments.

[0345] As shown in FIG31 , the driving subcircuit is electrically connected to the first node N1, the second node N2 and the third node N3, respectively, and is configured to provide a driving current to the third node N3 under the control of the signals of the first node N1 and the second node N2; the first control subcircuit is electrically connected to the first scan signal line G1, the second scan signal line G2, the data signal line Data, the reference signal line REF and the first node N1, respectively, and is configured to provide a signal of the data signal line Data or the reference signal line REF to the first node N1 under the control of the signals of the first scan signal line G1 and the second scan signal line G2; the second control subcircuit is electrically connected to the first light-emitting signal line EM1, the second light-emitting signal line EM2, the first power line VDD, the second power line VDD and the third node N3, respectively. The second node N2, the third node N3 and the fourth node N4 are electrically connected, and are configured to provide the signal of the first power line VDD to the second node N2 and the signal of the third node N3 to the fourth node N4 under the control of the signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2; the third control sub-circuit is electrically connected to the first reset signal line Reset1, the auxiliary signal line VX and the third node N3, respectively, and is configured to control the signal of the third node N3 under the control of the signal of the first reset signal line Reset1 and the drive of the signal of the auxiliary signal line VX; the storage sub-circuit is electrically connected to the first node N1 and the third node N3, respectively, and is configured to store the voltage difference of the signal between the first node N1 and the third node N3.

[0346] In an exemplary embodiment, as shown in FIG. 31 , the pixel driving circuit is electrically connected to the light emitting device L through the fourth node N4 .

[0347] In an exemplary embodiment, the light emitting device L may include a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode). Exemplarily, the anode of the light emitting device L is electrically connected to the fourth node N4, and the cathode of the light emitting device L is electrically connected to the second power line VSS.

[0348] In an exemplary embodiment, the light-emitting device L may include a current-driven device, and may be a current-driven light-emitting diode, such as a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum dot light-emitting diode (QLED). A typical size (e.g., length) of a Micro LED may be less than 100 μm, for example, 10 μm to 50 μm. A typical size (e.g., length) of a Mini LED may be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0349] In an exemplary embodiment, the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, and the hole blocking layers of all sub-pixels may be a common layer connected together. The light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0350] In an exemplary embodiment, the first power line VDD continuously provides a high-level signal, and the signal of the first power line VDD is a DC signal.

[0351] In an exemplary embodiment, the second power line VSS continuously provides a low-level signal, and the signal of the second power line VSS is a DC signal.

[0352] In an exemplary embodiment, the reference signal line REF continuously provides a low-level signal. The signal of the reference signal line REF is a DC signal. Exemplarily, the voltage of the signal of the reference signal line REF may be 0V.

[0353] In an exemplary embodiment, the pixel driving circuit is located in a display substrate, and the content displayed by the display substrate includes multiple display frames. In any display frame, the signal of the first scanning signal line G1 is a pulse signal, and the signal of the second scanning signal line G2 is a pulse signal. The time period in which the second scanning signal line G2 is a valid level signal occurs before the time period in which the first scanning signal line G1 is a valid level signal.

[0354] The embodiment of the present disclosure provides a pixel driving circuit, comprising: a driving subcircuit, a first control subcircuit, a second control subcircuit, a third control subcircuit, and a storage subcircuit; the driving subcircuit is electrically connected to a first node, a second node, and a third node, respectively, and is configured to provide a driving current to the third node under the control of signals from the first node and the second node; the first control subcircuit is electrically connected to a first scan signal line, a second scan signal line, a data signal line, a reference signal line, and a first node, respectively, and is configured to provide a signal from a data signal line or a reference signal line to the first node under the control of signals from the first scan signal line and the second scan signal line; the second control subcircuit is electrically connected to a first scan signal line, a second scan signal line, a data signal line, a reference signal line, and a first node, respectively, and is configured to provide a signal from a data signal line or a reference signal line to the first node under the control of signals from the first scan signal line and the second scan signal line; The circuit is electrically connected to the first light-emitting signal line, the second light-emitting signal line, the first power line, the second node, the third node and the fourth node, respectively, and is configured to provide the signal of the first power line to the second node and the signal of the third node to the fourth node under the control of the signals of the first light-emitting signal line and the second light-emitting signal line; the third control subcircuit is electrically connected to the first reset signal line, the auxiliary signal line and the third node, respectively, and is configured to control the signal of the third node under the control of the signal of the first reset signal line and the drive of the signal of the auxiliary signal line; the storage subcircuit is electrically connected to the first node and the third node, respectively, and is configured to store the voltage difference of the signal between the first node and the third node. The present disclosure can control the signal of the third node through the signals of the first reset signal line and the auxiliary signal line by setting the third control subcircuit, thereby avoiding the introduction of noise in the display stage, maintaining the stability of the driving current output by the pixel driving circuit, and improving the reliability of the pixel driving circuit.

[0355] In an exemplary embodiment, the operation process of the pixel driving circuit includes a display phase, which includes a write phase and a light-emitting phase. The light-emitting phase occurs after the write phase, and the signal of the first scanning signal line G1 is an active-level signal during the write phase. The signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are both active-level signals during the light-emitting phase, and the time during which the write phase occurs is a write time period.

[0356] FIG32 is an equivalent circuit diagram 1 including the third control subcircuit shown in FIG31 . As shown in FIG32 , in an exemplary embodiment, the third control subcircuit may also be electrically connected to the third reset signal line Reset3 and the initial signal line INIT, respectively, and configured to provide the initial signal line signal to the fourth node N4 under control of the signal of the third reset signal line Reset3. Exemplarily, the third control subcircuit may include: a sixth transistor T6, an eighth transistor T8, and a second capacitor C2. The control electrode of the sixth transistor T6 is electrically connected to the first reset signal line Reset1, the first electrode of the sixth transistor T6 is electrically connected to the auxiliary signal line VX, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5; the first end of the second capacitor C2 is electrically connected to the fifth node N5, and the second end of the second capacitor C2 is electrically connected to the third node N3; the first electrode of the eighth transistor T8 is electrically connected to the initial signal line INIT, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4.

[0357] In an exemplary embodiment, as shown in FIG. 32 , the signal of the auxiliary signal line VX is a non-DC signal and is electrically connected to the fourth node N4 .

[0358] For example, in some embodiments, as shown in FIG32 , the signal value of the initialization signal line INIT is adjustable to reduce the impact of temperature changes on the magnitude of the drive current. For details on how to adjust the signal value of the initialization signal line INIT, refer to the method for adjusting the value of the reset signal in the above embodiment, and will not be repeated here.

[0359] In an exemplary embodiment, as shown in FIG32 , the present disclosure ensures display uniformity of the pixel driving circuit by resetting the third node N3 and the fourth node N4 before the write period by ensuring that the signal on the second light-emitting signal line EM2 is at an active level for at least a portion of the time period during which the signal on the third reset signal line Reset3 is at an active level. Furthermore, by ensuring that the signals on the first reset signal line Reset1 and the second light-emitting signal line EM2 are at an active level for at least a portion of the time period after the write period, the present disclosure ensures that the voltage values ​​of the signals across the second capacitor C2 during the light-emitting phase are the same. This prevents the second capacitor C2 from affecting the third node N3 during the light-emitting phase, prevents noise from being introduced into the third node N3, maintains the stability of the drive current output by the pixel driving circuit, and improves the reliability of the pixel driving circuit.

[0360] FIG33 is a second equivalent circuit diagram including the third control subcircuit shown in FIG31 . As shown in FIG33 , in an exemplary embodiment, the third control subcircuit may also be electrically connected to the second reset signal line Reset2 and configured to provide a signal from the fifth node N5 to the third node N3 under control of the signal from the second reset signal line Reset2. Exemplarily, the third control subcircuit may include a sixth transistor T6, a seventh transistor T7, and a second capacitor C2. A first electrode of the sixth transistor T6 is electrically connected to the auxiliary signal line VX, and a second electrode of the sixth transistor T6 is electrically connected to the fifth node N5. A control electrode of the seventh transistor T7 is electrically connected to the second reset signal line Reset3, a first electrode of the seventh transistor T7 is electrically connected to the fifth node N5, and a second electrode of the seventh transistor T7 is electrically connected to the third node N3. A first end of the second capacitor C2 is electrically connected to the fifth node N5, and a second end of the second capacitor C2 is electrically connected to the third node N3.

[0361] In an exemplary embodiment, as shown in FIG. 33 , the signal of the auxiliary signal line VX may be a DC signal and may be the same as the signal of any one of the initial signal line INIT, the reference signal line REF, and the first power line VDD.

[0362] For example, in some embodiments, as shown in FIG33 , the signal value of the auxiliary signal line VX is adjustable to reduce the impact of temperature changes on the magnitude of the drive current. For details on how to adjust the signal value of the auxiliary signal line VX, refer to the method for adjusting the reset signal value in the above embodiment and are not repeated here.

[0363] In an exemplary embodiment, as shown in FIG33 , the present disclosure ensures display uniformity of the pixel driver circuit by resetting the third node N3 and the fourth node N4 before the write period by ensuring that the second reset signal line Reset2 and the second emission signal line EM2 are active level signals during a portion of the time period when the first reset signal line Reset1 is an active level signal. By ensuring that the second reset signal line Reset2 is an active level signal for at least a portion of the time period after the write period, the present disclosure ensures that the voltage values ​​of the signals across the second capacitor C2 during the light-emitting phase are the same, thereby preventing the second capacitor C2 from affecting the third node N3 during the light-emitting phase and thus preventing noise from being introduced during the display phase. This maintains the stability of the drive current output by the pixel driver circuit and improves the reliability of the pixel driver circuit.

[0364] Figure 34 is a third equivalent circuit diagram including the third control subcircuit shown in Figure 31, and Figure 35 is a fourth equivalent circuit diagram including the third control subcircuit shown in Figure 31. In exemplary embodiments, as shown in Figures 34 and 35, the third control subcircuit may also be electrically connected to a third reset signal line Reset3 and an initial signal line INIT, respectively, and configured to provide a signal of the initial signal line to a fourth node N4 under control of a signal of the third reset signal line Reset3. Exemplarily, the third control subcircuit may further include an eighth transistor T8, wherein a control electrode of the eighth transistor T8 is electrically connected to the third reset signal line Reset3, a first electrode of the eighth transistor T8 is electrically connected to the initial signal line, and a second electrode of the eighth transistor T8 is electrically connected to the fourth node N4.

[0365] In an exemplary embodiment, the signal on the auxiliary signal line VX is a DC signal, and the signal on the auxiliary signal line VX is the same as the signal on any one of the initial signal line, the reference signal line REF, and the first power line VDD. Alternatively, the signal on the auxiliary signal line VX is a non-DC signal, and the signal on the auxiliary signal line VX is electrically connected to the fourth node N4. FIG34 illustrates the auxiliary signal line VX as a DC signal, while FIG35 illustrates the auxiliary signal line VX as a non-DC signal.

[0366] For example, in some embodiments, as shown in FIG34 , the signal value of the auxiliary signal line VX is the same as the signal value of the initial signal line VINI, and the signal value of the initial signal line VINI is adjustable to reduce the impact of temperature changes on the magnitude of the drive current. Regarding the method for adjusting the signal value of the initial signal line VINI, please refer to the method for adjusting the value of the reset signal in the above embodiment, and will not be repeated here.

[0367] For example, in some embodiments, as shown in FIG35 , the signal value of the initial signal line VINI is adjustable to reduce the impact of temperature changes on the magnitude of the drive current. For details on how to adjust the signal value of the initial signal line VINI, please refer to the method for adjusting the reset signal value in the above embodiment, and will not be repeated here.

[0368] In an exemplary embodiment, as shown in Figures 34 and 35, when the signal on the first reset signal line Reset1 is an active level signal, the signal on the third reset signal line is an active level signal, and the signal on the second reset signal line is an inactive level signal. When the signal on the second reset signal line is an active level signal, the signal on the first reset signal line is an inactive level signal. The present disclosure resets the third node N3 and the fourth node N4 before the write period by ensuring that the signal on the second light-emitting signal line EM2 is an active level signal during a portion of the time period when the signal on the third reset signal line Reset3 is an active level signal. This ensures display uniformity of the pixel driving circuit. By ensuring that the second reset signal line Reset2 is an active level signal during at least a portion of the time period after the write period, the voltage values ​​of the signals at both ends of the second capacitor C2 during the light-emitting phase are the same, thereby avoiding the influence of the second capacitor C2 on the third node N3 during the light-emitting phase and preventing the introduction of noise during the display phase. This maintains the stability of the drive current output by the pixel driving circuit and improves the reliability of the pixel driving circuit.

[0369] Figure 36 is a fifth equivalent circuit diagram including the third control sub-circuit shown in Figure 31, and Figure 37 is a sixth equivalent circuit diagram including the third control sub-circuit shown in Figure 31. In exemplary embodiments, as shown in Figures 36 and 37, the third control sub-circuit may also be electrically connected to a third reset signal line Reset3 and an initial signal line INIT, respectively, and configured to provide a signal of the initial signal line to a fourth node N4 under control of a signal on the third reset signal line Reset3. Exemplarily, the third control sub-circuit may further include a sixth transistor T6, an eighth transistor T8, and a second capacitor C2. Among them, the control electrode of the sixth transistor T6 is electrically connected to the first reset signal line Reset1, the first electrode of the sixth transistor T6 is electrically connected to the fifth node N5, and the second electrode of the sixth transistor T6 is electrically connected to the third node N3; the control electrode of the eighth transistor T8 is electrically connected to the third reset signal line Reset3, the first electrode of the eighth transistor T8 is electrically connected to the initial signal line INIT, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; the first end of the second capacitor C2 is electrically connected to the auxiliary signal line VX, and the second end of the second capacitor C2 is electrically connected to the fifth node N5.

[0370] In an exemplary embodiment, the signal on the auxiliary signal line VX is a DC signal, and the signal on the auxiliary signal line VX is the same as the signal on any one of the initial signal line, the reference signal line REF, and the first power line VDD. Alternatively, the signal on the auxiliary signal line VX is a non-DC signal, and the signal on the auxiliary signal line VX is electrically connected to the fourth node N4. FIG36 illustrates the auxiliary signal line VX as a DC signal, while FIG37 illustrates the auxiliary signal line VX as a non-DC signal.

[0371] For example, in some embodiments, as shown in FIG36 , the signal value of the auxiliary signal line VX is the same as the signal value of the initial signal line VINI, and the signal value of the initial signal line VINI is adjustable to reduce the impact of temperature changes on the magnitude of the drive current. Regarding the method for adjusting the signal value of the initial signal line VINI, please refer to the method for adjusting the value of the reset signal in the above embodiment, and will not be repeated here.

[0372] For example, in some embodiments, as shown in FIG37 , the signal value of the initial signal line VINI is adjustable to reduce the impact of temperature changes on the magnitude of the drive current. For details on how to adjust the signal value of the initial signal line VINI, please refer to the method for adjusting the reset signal value in the above embodiment, and will not be repeated here.

[0373] In exemplary embodiments, as shown in Figures 36 and 37 , the present disclosure resets the third node N3 and the fourth node N4 before the write period by maintaining the second light-emitting signal line EM2 at a valid level during a portion of the time period when the third reset signal line Reset3 is at a valid level, thereby ensuring display uniformity of the pixel driver circuit. By maintaining the first reset signal line Reset1 at an inactive level during the period after the write period, the present disclosure prevents the second capacitor C2 from affecting the third node N3, thereby avoiding the introduction of noise during the display phase, maintaining the stability of the drive current output by the pixel driver circuit, and improving the reliability of the pixel driver circuit.

[0374] In an exemplary embodiment, the initial signal line INIT continuously provides a low-level signal, and the signal of the initial signal line INIT is a DC signal.

[0375] In an exemplary embodiment, the voltage value of the signal of the initial signal line INIT may be lower than the voltage value of the signal of the second power line VSS, which may prevent the light emitting device L from emitting light inadvertently and improve the reliability of the pixel driving circuit.

[0376] FIG32 to FIG37 only show six exemplary structures of the third control sub-circuit. Those skilled in the art will readily appreciate that the implementation of the third control sub-circuit is not limited thereto.

[0377] Figure 38 is a partial equivalent circuit diagram of another pixel driving circuit provided by an embodiment of the present disclosure. As shown in Figure 38, in an exemplary embodiment, the first control subcircuit may include: a first transistor T1 and a second transistor T2, the driving subcircuit may include: a third transistor T3, the second control subcircuit may include: a fourth transistor T4 and a fifth transistor T5, and the storage subcircuit may include: a first capacitor C1. Among them, the control electrode of the first transistor T1 is electrically connected to the first scanning signal line G1, the first electrode of the first transistor T1 is electrically connected to the data signal line Data, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second scanning signal line G2, the first electrode of the second transistor T2 is electrically connected to the reference signal line REF, and the second electrode of the second transistor T2 is electrically connected to the first node N1; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the The second electrode is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first light-emitting signal line EM1, the first electrode of the fourth transistor T4 is electrically connected to the first power supply line VDD, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the second light-emitting signal line EM2, the first electrode of the fifth transistor T5 is electrically connected to the third node N3, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; the first end of the first capacitor C1 is electrically connected to the first node N1, and the second end of the first capacitor C1 is electrically connected to the third node N3.

[0378] Figure 38 only shows an exemplary structure of the driving sub-circuit, the first control sub-circuit, the second control sub-circuit and the storage sub-circuit. Those skilled in the art can easily understand that the implementation of the driving sub-circuit, the first control sub-circuit, the second control sub-circuit and the storage sub-circuit is not limited to this.

[0379] In an exemplary embodiment, FIG39 is an equivalent circuit diagram 1 of the pixel driving circuit shown in FIG38 , FIG40 is an equivalent circuit diagram 2 of the pixel driving circuit shown in FIG38 , FIG41 is an equivalent circuit diagram 3 of the pixel driving circuit shown in FIG38 , and FIG42 is an equivalent circuit diagram 4 of the pixel driving circuit shown in FIG38 . As shown in FIG39 to FIG42 , in an exemplary embodiment, a first control subcircuit in the pixel driving circuit includes a first transistor T1 and a second transistor T2 , a driving subcircuit includes a third transistor T3 , a second control subcircuit includes a fourth transistor T4 and a fifth transistor T5 , a storage subcircuit includes a first capacitor C1 , a third control subcircuit includes a second capacitor C2 and a sixth transistor T6 , and the third control subcircuit further includes at least one of a seventh transistor T7 and an eighth transistor T8 . Among them, the control electrode of the first transistor T1 is electrically connected to the first scan signal line G1, the first electrode of the first transistor T1 is electrically connected to the data signal line Data, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second scan signal line G2, the first electrode of the second transistor T2 is electrically connected to the reference signal line REF, and the second electrode of the second transistor T2 is electrically connected to the first node N1; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first light-emitting signal line EM1, the first electrode of the fourth transistor T4 is electrically connected to the first power supply line VDD, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the second light-emitting signal line EM2, and the first electrode of the fifth transistor T5 is electrically connected to the third node N3 a first terminal of the first capacitor C1 is electrically connected to the first node N1, and a second terminal of the first capacitor C1 is electrically connected to the third node N3; a first terminal of the second capacitor C2 is electrically connected to the fifth node N5, and a second terminal of the second capacitor C2 is electrically connected to the third node N3; a second terminal of the second capacitor C2 is electrically connected to the fifth node N5, and a second terminal of the second capacitor C2 is electrically connected to the third node N3; a second terminal of the second capacitor C2 is electrically connected to the fifth node N5, and a second terminal of the second capacitor C2 is electrically connected to the third node N3; a first terminal of the second capacitor C2 is electrically connected to the fifth node N5, and a second terminal of the second capacitor C2 is electrically connected to the third node N3.Figures 39 and 40 are explained by taking the example that the third control sub-circuit also includes: a seventh transistor T7 and an eighth transistor T8, Figure 41 is explained by taking the example that the third control sub-circuit also includes: a seventh transistor T7, and Figure 42 is explained by taking the example that the third control sub-circuit also includes: an eighth transistor T8.

[0380] In an exemplary embodiment, as shown in Figures 39 and 40, the third control sub-circuit further includes: the signal of the auxiliary signal line VX in the pixel driving circuit of the seventh transistor T7 and the eighth transistor T8 can be a DC signal, or can be a non-DC signal. Figure 39 is explained by taking the example that the signal of the auxiliary signal line VX in the pixel driving circuit is a DC signal and is the same as the signal of any one of the initial signal line INIT, the reference signal line REF and the first power line VDD. Figure 40 is explained by taking the example that the signal of the auxiliary signal line VX in the pixel driving circuit is a non-DC signal and is electrically connected to the fourth node N4.

[0381] In an exemplary embodiment, as shown in FIG41 , the third control subcircuit further includes a pixel driving circuit in which the signal of the auxiliary signal line VX in the seventh transistor T7 is a DC signal and is the same as the signal of any one of the initial signal line, the reference signal line, and the first power line.

[0382] In an exemplary embodiment, as shown in FIG42 , the signal of the auxiliary signal line VX in the pixel driving circuit in which the third control subcircuit further includes an eighth transistor T8 is a non-DC signal and is electrically connected to the fourth node N4 .

[0383] In an exemplary embodiment, any of the first to eighth transistors T1 to T8 may be an oxide thin film transistor, the active layer of which is made of an oxide semiconductor (Oxide), which has advantages such as low leakage current.

[0384] In an exemplary embodiment, any one of the first to eighth transistors T1 to T8 is an N-type transistor.

[0385] In an exemplary embodiment, FIG43 is a fifth equivalent circuit diagram of the pixel driving circuit shown in FIG38, and FIG44 is a sixth equivalent circuit diagram of the pixel driving circuit shown in FIG38. As shown in FIG43 and FIG44, in the pixel driving circuit, the first control subcircuit may include a first transistor T1 and a second transistor T2, the driving subcircuit may include a third transistor T3, the second control subcircuit may include a fourth transistor T4 and a fifth transistor T5, the storage subcircuit may include a first capacitor C1, and the third control subcircuit may include a second capacitor C2, a sixth transistor T6, and an eighth transistor T8. Among them, the control electrode of the first transistor T1 is electrically connected to the first scan signal line G1, the first electrode of the first transistor T1 is electrically connected to the data signal line Data, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second scan signal line G2, the first electrode of the second transistor T2 is electrically connected to the reference signal line REF, and the second electrode of the second transistor T2 is electrically connected to the first node N1; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first light emitting signal line EM1, the first electrode of the fourth transistor T4 is electrically connected to the first power supply line VDD, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The control electrode of the sixth transistor T6 is electrically connected to the first reset signal line Reset1, the first electrode of the sixth transistor T6 is electrically connected to the fifth node N5, and the second electrode of the sixth transistor T6 is electrically connected to the third node N3; the control electrode of the eighth transistor T8 is electrically connected to the third reset signal line Reset3, the first electrode of the eighth transistor T8 is electrically connected to the initial signal line INIT, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; the first end of the first capacitor C1 is electrically connected to the first node N1, and the second end of the first capacitor C1 is electrically connected to the third node N3; the first end of the second capacitor C2 is electrically connected to the auxiliary signal line VX, and the second end of the second capacitor C2 is electrically connected to the fifth node N5.

[0386] In an exemplary embodiment, as shown in Figures 43 and 44, the third control subcircuit includes: the signal of the auxiliary signal line VX in the pixel driving circuit of the sixth transistor T6, the eighth transistor T8 and the second capacitor C2 can be a DC signal, or can be a non-DC signal. Figure 43 is explained by taking the example that the signal of the auxiliary signal line VX in the pixel driving circuit is a DC signal and is the same as the signal of any one of the initial signal line INIT, the reference signal line REF and the first power line VDD. Figure 44 is explained by taking the example that the signal of the auxiliary signal line VX in the pixel driving circuit is a non-DC signal and is electrically connected to the fourth node N4.

[0387] In an exemplary embodiment, any of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 may be an oxide thin film transistor. The active layer of the oxide thin film transistor is made of an oxide semiconductor. Oxide thin film transistors have advantages such as low leakage current.

[0388] In an exemplary embodiment, any one of the first transistor T1 , the second transistor T2 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , and the eighth transistor T8 is an N-type transistor.

[0389] In an exemplary embodiment, in the pixel driving circuits provided in FIG. 39 to FIG. 44 , the number of the first transistor T1 , the second transistor T2 , and the fourth transistor T4 may be at least one.

[0390] In an exemplary embodiment, when the number of the first transistors T1 may be at least two, the control electrodes of all the first transistors are electrically connected to the first scan signal line, at least two first transistors are arranged in series, the first electrode of the first first transistor is electrically connected to the data signal line, and the second electrode of the last first transistor is electrically connected to the first node N1.

[0391] In an exemplary embodiment, when the number of the second transistors T2 may be at least two, the control electrodes of all the second transistors T2 are electrically connected to the second scan signal line, at least two second transistors are arranged in series, the first electrode of the first second transistor is electrically connected to the reference signal line, and the second electrode of the last second transistor is electrically connected to the second node N2.

[0392] FIG45 is an operating timing diagram of the pixel driving circuit provided in FIG39 and FIG40. The following describes exemplary embodiments of the present disclosure using the operating process of the pixel driving circuit illustrated in FIG39 and FIG40. The pixel driving circuit in FIG39 and FIG40 includes eight transistors (first transistor T1 to eighth transistor T8) and two capacitors (first capacitor C1 and second capacitor C2). All eight transistors are N-type transistors.

[0393] In an exemplary embodiment, the operation process of the pixel driving circuit provided in FIG. 39 and FIG. 40 may include:

[0394] The first phase P1 is called the first reset phase. The signals on the second scan signal line G2, the second luminescence signal line EM2, the first reset signal line Reset1, and the third reset signal line Reset3 are high-level signals, while the signals on the first scan signal line G1, the first luminescence signal line EM1, and the second reset signal line Reset2 are low-level signals. The signal on the second scan signal line G2 is high-level, the second transistor T2 is turned on, and the signal on the reference signal line REF is written to the second node N2, initializing (resetting) the signal on the second node N2 and clearing the existing charge on the second node N2. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is written to the fifth node N5, initializing (resetting) the signal on the fifth node N5 and clearing the existing charge on the fifth node N5. The signals on the second light-emitting signal line EM2 and the third reset signal line Reset3 are high-level signals, the fifth transistor T5 and the eighth transistor T8 are turned on, and the signal on the initial signal line INIT is written to the third node N3 and the fourth node N4, respectively. Since the voltage values ​​of the signals on the first node N1 and the third node N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on, and the signal on the initial signal line INIT is written to the second node N2, initializing (resetting) the signals on the second node N2, the third node N3, and the fourth node N4, clearing the existing charges on the second node N2, the third node N3, and the fourth node N4. The signals on the first scanning signal line G1, the first light-emitting signal line EM1, and the second reset signal line Reset2 are low-level signals, and the first transistor T1, the fourth transistor T4, and the seventh transistor T7 are turned off. At this stage, the light-emitting device L does not emit light.

[0395] In the second phase P2, i.e., the threshold compensation phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2, and the first light-emitting signal line EM1 are high-level signals, while the signals on the second reset signal line Reset2, the first scan signal line G1, and the second light-emitting signal line EM2 are low-level signals. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is continuously written to the fifth node N5, continuously initializing (resetting) the signal on the fifth node N5. The signal on the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal on the initialization signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the second scan signal line G2 is high, the second transistor T2 is turned on, the signal on the reference signal line REF is continuously supplied to the second node N2, the signal on the first light-emitting signal line EM1 is high, the fourth transistor T4 is turned on, and the signal on the first power line VDD is written to the third node N3 via the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage V3 of the signal on the third node N3 reaches Vref - Vth, where Vref is the voltage value of the signal on the initial signal line REF and Vth is the threshold voltage of the third transistor T3. At this point, the first capacitor C1 stores the voltage difference Vth between the signals on the first node N1 and the third node N3. The signals on the second reset signal line Reset2, the first scan signal line G1, and the second light-emitting signal line EM2 are low, and the first transistor T1, the fifth transistor T5, and the seventh transistor are turned off. During this phase, the light-emitting device L does not emit light.

[0396] In the third phase P3, the data writing phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, and the first scan signal line G1 are high-level signals, while the signals on the second reset signal line Reset2, the second scan signal line G2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low-level signals. The data signal line Data outputs a data voltage. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is continuously written to the fifth node N5, continuously initializing (resetting) the signal on the fifth node N5. The signal on the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal on the initialization signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the first scan signal line G1 is high, turning on the first transistor T1. The data voltage on the data signal line Data is written to the first node N1. At this point, the voltage V1 of the first node N1 equals Vdata, where Vdata is the data voltage on the data signal line. The signal on the first node N1 changes from its current voltage value to its previous voltage value. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal on the third node N3 also changes. At this point, the voltage V3 of the signal on the third node N3 equals Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2), where C1 is the capacitance of the first capacitor and C2 is the capacitance of the second capacitor. The signals on the second reset signal line Reset2, the second scan signal line G2, the first emission signal line EM1, and the second emission signal line EM2 are low. The second transistor T2, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are turned off. In this stage, the light-emitting device L does not emit light.

[0397] In the fourth phase P4, referred to as the second reset phase, the second reset signal line Reset2, the third reset signal line Reset3, and the second light-emitting signal line EM2 are high-level signals, while the signals on the first reset signal line Reset1, the first light-emitting signal line EM1, the first scanning signal line G1, and the second scanning signal line G2 are low-level signals. The signal on the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal on the initialization signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the second light-emitting signal line EM2 is high, the fifth transistor T5 is turned on, and the voltage V3 of the signal on the third node N3 is equal to Vinit, where Vinit is the voltage value of the signal on the initial signal line. At this time, the first node N1 is pulled low by the first capacitor C1, so that the voltage V1 of the signal on the first node N1 is equal to Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]+Vinit. The signal on the second reset signal line Reset2 is high, the seventh transistor T7 is turned on, and the voltages of the signals on the third node N3 and the fifth node N5 remain consistent. The signals on the first reset signal line Reset1, the first light-emitting signal line EM1, the first scan signal line G1, and the second scan signal line G2 are low, and the first transistor T1, the second transistor T2, the fourth transistor T4, and the sixth transistor T6 are turned off. In this stage, the light-emitting device L does not emit light.

[0398] In the fifth phase P5, i.e., the light-emitting phase, the signals on the second reset signal line Reset2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals, while the signals on the first reset signal line Reset1, the third reset signal line Reset3, and the first scan signal line G1 and the second scan signal line G2 are low-level signals. The signals on the first light-emitting signal line EM1 and the second light-emitting signal line Reset2 are high-level signals. The fourth transistor T4 and the fifth transistor T5 are turned on. The power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T4, third transistor T3, and fifth transistor T5, driving the light-emitting device L to emit light. The signal on the second reset signal line Reset2 is high-level, the seventh transistor T7 is turned on, and the voltages of the signals on the third node N3 and the fifth node N5 remain consistent. The signals on the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals. The first transistor T1, the second transistor T2, the sixth transistor T6, and the eighth transistor T8 are turned off. In this phase, the light-emitting device L emits light.

[0399] During the pixel driving circuit's driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and the second electrode (also the third node N3). Since the voltage value of the signal at the first node V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, and the voltage value of the signal at the third node N3 V3 = Vinit, the driving current of the third transistor T3 is: I = K * (Vgs - Vth) 2 =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]- Vth] 2 =K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0400] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0401] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0402] FIG46 is an operating timing diagram of the pixel driving circuit shown in FIG41. The following describes exemplary embodiments of the present disclosure using the operating process of the pixel driving circuit shown in FIG41. The pixel driving circuit in FIG41 includes seven transistors (first transistor T1 to seventh transistor T7) and two capacitors (first capacitor C1 and second capacitor C2). All seven transistors are N-type transistors.

[0403] In an exemplary embodiment, the operation process of the pixel driving circuit provided in FIG41 may include:

[0404] The first phase P1, referred to as the first reset phase, is characterized by high-level signals on the second scan signal line G2, the second light-emitting signal line EM2, the first reset signal line Reset1, and the second reset signal line Reset2. The signals on the first scan signal line G1 and the first light-emitting signal line EM1 are low-level signals. The signal on the second scan signal line G2 is high-level, the second transistor T2 is turned on, and the signal on the reference signal line REF is written to the second node N2, initializing (resetting) the signal on the second node N2 and clearing the existing charge on the second node N2. The signals on the first reset signal line Reset1, the second reset signal line Reset2, and the second light-emitting signal line EM2 are high-level signals. The fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned on, and the signal on the auxiliary signal line VX is sequentially written to the fifth node N5, the third node N3, and the fourth node N4. This initializes (resets) the signals on the third node N3, the fourth node N4, and the fifth node N5, clearing the existing charge on the third node N3, the fourth node N4, and the fifth node N5. The signals of the first scanning signal line G1 and the first light emitting signal line EM1 are low level signals, and the first transistor T1 and the fourth transistor T4 are turned off. In this stage, the light emitting device L does not emit light.

[0405] In the second phase P2, i.e., the threshold compensation phase, the signals on the first reset signal line Reset1, the second scan signal line G2, and the first light-emitting signal line EM1 are high-level signals, while the signals on the second reset signal line Reset2, the first scan signal line G1, and the second light-emitting signal line EM2 are low-level signals. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is continuously written to the fifth node N5, continuously initializing (resetting) the signal on the fifth node N5. The signal on the second scan signal line G2 is high, the second transistor T2 is turned on, the signal on the reference signal line REF is continuously supplied to the second node N2, the signal on the first light-emitting signal line EM1 is high, the fourth transistor T4 is turned on, and the signal on the first power line VDD is written to the third node N3 via the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage V3 of the signal on the third node N3 reaches Vref - Vth, where Vref is the voltage value of the signal on the initial signal line REF and Vth is the threshold voltage of the third transistor T3. At this point, the first capacitor C1 stores the voltage difference Vth between the signals on the first node N1 and the third node N3. The signals on the second reset signal line Reset2, the first scan signal line G1, and the second light-emitting signal line EM2 are low, and the first transistor T1, the fifth transistor T5, and the seventh transistor are turned off. During this phase, the light-emitting device L does not emit light.

[0406] In the third phase P3, the data writing phase, the signals on the first reset signal line Reset1 and the first scan signal line G1 are high-level signals, the signals on the second reset signal line Reset2, the second scan signal line G2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low-level signals, and the data signal line Data outputs a data voltage. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is continuously written to the fifth node N5, continuously initializing (resetting) the signal on the fifth node N5. The signal on the first scan signal line G1 is high, turning on the first transistor T1. The data voltage on the data signal line Data is written to the first node N1. At this point, the voltage V1 of the first node N1 equals Vdata, where Vdata is the data voltage on the data signal line. The signal on the first node N1 changes from its current voltage value to its previous voltage value. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal on the third node N3 also changes. At this point, the voltage V3 of the signal on the third node N3 equals Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2), where C1 is the capacitance of the first capacitor and C2 is the capacitance of the second capacitor. The signals on the second reset signal line Reset2, the second scan signal line G2, the first emission signal line EM1, and the second emission signal line EM2 are low. The second transistor T2, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are turned off. In this stage, the light-emitting device L does not emit light.

[0407] In the fourth phase P4, referred to as the second reset phase, the second reset signal line Reset2 and the second light-emitting signal line EM2 are high-level signals, while the signals on the first reset signal line Reset1, the first light-emitting signal line EM1, the first scanning signal line G1, and the second scanning signal line G2 are low-level signals. The signal on the second light-emitting signal line EM2 is high-level, the fifth transistor T5 is turned on, and the voltage V3 of the signal on the third node N3 is equal to Vinit, where Vinit is the voltage value of the signal on the initial signal line. At this time, the first node N1 is pulled low by the first capacitor C1, such that the voltage V1 of the signal on the first node N1 is equal to Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]+Vinit. The signal on the second reset signal line Reset2 is high-level, the seventh transistor T7 is turned on, and the voltages of the signals on the third node N3 and the fifth node N5 remain consistent. The signals of the first reset signal line Reset1, the first light emitting signal line EM1, the first scanning signal line G1 and the second scanning signal line G2 are low level signals, and the first transistor T1, the second transistor T2, the fourth transistor T4 and the sixth transistor T6 are turned off. In this stage, the light emitting device L does not emit light.

[0408] In the fifth phase P5, i.e., the light-emitting phase, the signals on the second reset signal line Reset2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals, while the signals on the first reset signal line Reset1, the first scan signal line G1, and the second scan signal line G2 are low-level signals. The signals on the first light-emitting signal line EM1 and the second light-emitting signal line Reset2 are high-level signals. The fourth transistor T4 and the fifth transistor T5 are turned on. The power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T4, the third transistor T3, and the fifth transistor T5, driving the light-emitting device L to emit light. The signal on the second reset signal line Reset2 is high-level, the seventh transistor T7 is turned on, and the voltages of the signals on the third node N3 and the fifth node N5 remain consistent. The signals on the first reset signal line Reset1, the first scan signal line G1, and the second scan signal line G2 are low-level signals. The first transistor T1, the second transistor T2, and the sixth transistor T6 are turned off. In this phase, the light-emitting device L emits light.

[0409] During the pixel driving circuit's driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and the second electrode (also the third node N3). Since the voltage value of the signal at the first node V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, and the voltage value of the signal at the third node N3 V3 = Vinit, the driving current of the third transistor T3 is: I = K * (Vgs - Vth) 2 =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]- Vth] 2 =K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0410] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0411] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0412] FIG47 is an operating timing diagram of the pixel driving circuit shown in FIG42. The following describes exemplary embodiments of the present disclosure using the operating process of the pixel driving circuit shown in FIG42. The pixel driving circuit in FIG42 includes seven transistors (first transistor T1 to sixth transistor T6, and eighth transistor T8) and two capacitors (first capacitor C1 and second capacitor C2). All seven transistors are N-type transistors.

[0413] In an exemplary embodiment, the operation process of the pixel driving circuit provided in FIG42 may include:

[0414] The first phase P1 is called the first reset phase. The signals on the second scan signal line G2, the second light-emitting signal line EM2, the first reset signal line Reset1, and the third reset signal line Reset3 are high-level signals, while the signals on the first scan signal line G1 and the first light-emitting signal line EM1 are low-level signals. The signal on the second scan signal line G2 is high-level, the second transistor T2 is turned on, and the signal on the reference signal line REF is written to the second node N2, initializing (resetting) the signal on the second node N2 and clearing the existing charge on the second node N2. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is written to the fifth node N5, initializing (resetting) the signal on the fifth node N5 and clearing the existing charge on the fifth node N5. The signals on the second light-emitting signal line EM2 and the third reset signal line Reset3 are high-level signals, the fifth transistor T5 and the eighth transistor T8 are turned on, and the signal on the initial signal line INIT is written to the third node N3 and the fourth node N4, respectively. Since the voltage values ​​of the signals on the first node N1 and the third node N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on, and the signal on the initial signal line INIT is written to the second node N2, initializing (resetting) the signals on the second node N2, the third node N3, and the fourth node N4, clearing the existing charges on the second node N2, the third node N3, and the fourth node N4. The signals on the first scanning signal line G1 and the first light-emitting signal line EM1 are low-level signals, and the first transistor T1 and the fourth transistor T4 are turned off. At this stage, the light-emitting device L does not emit light.

[0415] In the second phase P2, i.e., the threshold compensation phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2, and the first light-emitting signal line EM1 are high-level signals, while the signals on the first scan signal line G1 and the second light-emitting signal line EM2 are low-level signals. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is continuously written to the fifth node N5, continuously initializing (resetting) the signal on the fifth node N5. The signal on the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal on the initialization signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the second scan signal line G2 is high, the second transistor T2 is turned on, the signal on the reference signal line REF is continuously supplied to the second node N2, the signal on the first light-emitting signal line EM1 is high, the fourth transistor T4 is turned on, and the signal on the first power line VDD is written to the third node N3 via the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage V3 of the signal on the third node N3 reaches Vref - Vth, where Vref is the voltage value of the initial signal line REF and Vth is the threshold voltage of the third transistor T3. At this point, the first capacitor C1 stores the voltage difference Vth between the signals on the first node N1 and the third node N3. The signals on the first scan signal line G1 and the second light-emitting signal line EM2 are low, and the first transistor T1 and the fifth transistor T5 are turned off. During this stage, the light-emitting device L does not emit light.

[0416] In the third phase P3, the data writing phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, and the first scan signal line G1 are high-level signals, the signals on the second scan signal line G2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low-level signals, and the data signal line Data outputs a data voltage. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is continuously written to the fifth node N5, continuously initializing (resetting) the signal on the fifth node N5. The signal on the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal on the initialization signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the first scan signal line G1 is high, turning on the first transistor T1. The data voltage on the data signal line Data is written to the first node N1. At this point, the voltage V1 of the first node N1 equals Vdata, where Vdata is the data voltage on the data signal line. The signal on the first node N1 changes from its current voltage value to its previous voltage value. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal on the third node N3 also changes. At this point, the voltage V3 of the signal on the third node N3 equals Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2), where C1 is the capacitance of the first capacitor and C2 is the capacitance of the second capacitor. The signals on the second scan signal line G2, the first emission signal line EM1, and the second emission signal line EM2 are low, turning off the second transistor T2, the fourth transistor T4, and the fifth transistor T5. In this stage, the light-emitting device L does not emit light.

[0417] In the fourth phase P4, referred to as the second reset phase, the first reset signal line Reset1, the third reset signal line Reset3, and the second light-emitting signal line EM2 are high-level signals, while the signals on the first light-emitting signal line EM1, the first scanning signal line G1, and the second scanning signal line G2 are low-level signals. The signal on the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal on the initialization signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the second light-emitting signal line EM2 is high-level, the fifth transistor T5 is turned on, and the voltage V3 of the signal on the third node N3 is equal to Vinit, where Vinit is the voltage value of the signal on the initialization signal line. At this time, the first node N1 is pulled down by the first capacitor C1, so that the voltage V1 of the signal on the first node N1 is equal to Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]+Vinit. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the voltages of the signals on the third node N3 and the fifth node N5 are kept consistent. The signals of the first reset signal line Reset1, the first light emitting signal line EM1, the first scanning signal line G1 and the second scanning signal line G2 are low level signals, and the first transistor T1, the second transistor T2 and the fourth transistor T4 are turned off. In this stage, the light emitting device L does not emit light.

[0418] In the fifth phase P5, i.e., the light-emitting phase, the signals on the first reset signal line Reset1, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals, while the signals on the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals. The signals on the first light-emitting signal line EM1 and the second light-emitting signal line Reset2 are high-level signals. The fourth transistor T4 and the fifth transistor T5 are turned on. The power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T4, third transistor T3, and fifth transistor T5, driving the light-emitting device L to emit light. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the voltages of the signals on the third node N3 and the fifth node N5 remain consistent. The signals on the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals. The first transistor T1, the second transistor T2, and the eighth transistor T8 are turned off. In this phase, the light-emitting device L emits light.

[0419] During the pixel driving circuit's driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and the second electrode (also the third node N3). Since the voltage value of the signal at the first node V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, and the voltage value of the signal at the third node N3 V3 = Vinit, the driving current of the third transistor T3 is: I = K * (Vgs - Vth) 2 =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]-Vth] 2 = K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0420] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0421] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0422] For the pixel driving circuit provided in Figures 39 to 42, in the fourth and fifth stages, the signals of the third node N3 and the fifth node N5 at both ends of the second capacitor C2 remain consistent, so that the third node of the pixel driving circuit will not be affected by the coupling effect of the second capacitor C2 in the fifth stage, which can improve the stability of the driving current of the pixel driving circuit and improve the reliability of the pixel driving circuit.

[0423] FIG48 is an operating timing diagram of the pixel driving circuit provided in FIG43 and FIG44. The following describes an exemplary embodiment of the present disclosure using the operating process of the pixel driving circuit illustrated in FIG43 and FIG44. The pixel driving circuit in FIG43 and FIG44 includes seven transistors (first transistor T1 to sixth transistor T6, and eighth transistor T8) and two capacitors (first capacitor C1 and second capacitor C2). All seven transistors are N-type transistors.

[0424] In an exemplary embodiment, the operation process of the pixel driving circuit provided in FIG. 43 and FIG. 44 may include:

[0425] The first phase P1 is called the first reset phase. The signals on the second scan signal line G2, the second light-emitting signal line EM2, the first reset signal line Reset1, and the third reset signal line Reset3 are high-level signals, while the signals on the first scan signal line G1 and the first light-emitting signal line EM1 are low-level signals. The signal on the second scan signal line G2 is high-level, the second transistor T2 is turned on, and the signal on the reference signal line REF is written to the second node N2, initializing (resetting) the signal on the second node N2 and clearing the existing charge on the second node N2. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is written to the fifth node N5, initializing (resetting) the signal on the fifth node N5 and clearing the existing charge on the fifth node N5. The signals on the second light-emitting signal line EM2 and the third reset signal line Reset3 are high-level signals, the fifth transistor T5 and the eighth transistor T8 are turned on, and the signal on the initial signal line INIT is written to the third node N3 and the fourth node N4, respectively. Since the voltage values ​​of the signals on the first node N1 and the third node N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on, and the signal on the initial signal line INIT is written to the second node N2, initializing (resetting) the signals on the second node N2, the third node N3, and the fourth node N4, clearing the existing charges on the second node N2, the third node N3, and the fourth node N4. The signals on the first scanning signal line G1 and the first light-emitting signal line EM1 are low-level signals, and the first transistor T1 and the fourth transistor T4 are turned off. At this stage, the light-emitting device L does not emit light.

[0426] In the second phase P2, i.e., the threshold compensation phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2, and the first light-emitting signal line EM1 are high-level signals, while the signals on the first scan signal line G1 and the second light-emitting signal line EM2 are low-level signals. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is continuously written to the fifth node N5, continuously initializing (resetting) the signal on the fifth node N5. The signal on the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal on the initialization signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the second scan signal line G2 is high, the second transistor T2 is turned on, the signal on the reference signal line REF is continuously supplied to the second node N2, the signal on the first light-emitting signal line EM1 is high, the fourth transistor T4 is turned on, and the signal on the first power line VDD is written to the third node N3 via the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage V3 of the signal on the third node N3 reaches Vref - Vth, where Vref is the voltage value of the initial signal line REF and Vth is the threshold voltage of the third transistor T3. At this point, the first capacitor C1 stores the voltage difference Vth between the signals on the first node N1 and the third node N3. The signals on the first scan signal line G1 and the second light-emitting signal line EM2 are low, and the first transistor T1 and the fifth transistor T5 are turned off. During this stage, the light-emitting device L does not emit light.

[0427] In the third phase P3, the data writing phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, and the first scan signal line G1 are high-level signals, the signals on the second scan signal line G2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low-level signals, and the data signal line Data outputs a data voltage. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is continuously written to the fifth node N5, continuously initializing (resetting) the signal on the fifth node N5. The signal on the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal on the initialization signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the first scan signal line G1 is high, turning on the first transistor T1. The data voltage on the data signal line Data is written to the first node N1. At this point, the voltage V1 at the first node N1 equals Vdata, where Vdata is the data voltage on the data signal line. The signal on the first node N1 changes from its current voltage value to its previous voltage value. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal on the third node N3 also changes. At this point, the voltage V3 at the third node N3 equals Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2), where C1 is the capacitance of the first capacitor and C2 is the capacitance of the second capacitor. The signals on the second scan signal line G2, the first emission signal line EM1, and the second emission signal line EM2 are low, turning off the second transistor T2, the fourth transistor T4, and the fifth transistor T5. In this stage, the light-emitting device L does not emit light.

[0428] The fourth phase P4, referred to as the second reset phase, is characterized by the high-level signals of the third reset signal line Reset3 and the second light-emitting signal line EM2, while the signals of the first reset signal line Reset1, the first light-emitting signal line EM1, the first scanning signal line G1, and the second scanning signal line G2 are low-level signals. The signal of the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal of the initialization signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal of the fourth node N4. The signal of the second light-emitting signal line EM2 is high-level, the fifth transistor T5 is turned on, and the voltage V3 of the signal at the third node N3 is equal to Vinit, where Vinit is the voltage value of the signal of the initialization signal line. At this time, the first node N1 is pulled low by the action of the first capacitor C1, so that the voltage V1 of the signal at the first node N1 is equal to Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]+Vinit. The signals of the first reset signal line Reset1, the first light emitting signal line EM1, the first scanning signal line G1 and the second scanning signal line G2 are low level signals, and the first transistor T1, the second transistor T2, the fourth transistor T4 and the sixth transistor T6 are turned off. In this stage, the light emitting device L does not emit light.

[0429] In the fifth phase P5, i.e., the light-emitting phase, the signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals, while the signals on the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals. The signals on the first light-emitting signal line EM1 and the second light-emitting signal line Reset2 are high-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, and the power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T4, the third transistor T3, and the fifth transistor T5, driving the light-emitting device L to emit light. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the voltages of the signals on the third node N3 and the fifth node N5 remain consistent. The signals on the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals. The first transistor T1, the second transistor T2, the sixth transistor T6, and the eighth transistor T8 are turned off. In this phase, the light-emitting device L emits light.

[0430] During the pixel driving circuit's driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and the second electrode (also the third node N3). Since the voltage value of the signal at the first node V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, the voltage value of the signal at the third node N3 V3 = Vinit, so the driving current of the third transistor T3 is: I = K * (Vgs - Vth) 2 =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]-Vth] 2 = K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0431] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0432] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0433] For the pixel driving circuit provided in Figures 43 and 44, in the fourth and fifth stages, the sixth transistor T6 whose second capacitor C2 is disconnected from the third node N3 is disconnected, so that the third node of the pixel driving circuit will not be affected by the coupling effect of the second capacitor C2 in the fifth stage, which can improve the stability of the driving current of the pixel driving circuit and improve the reliability of the pixel driving circuit.

[0434] The embodiment of the present disclosure further provides a driving method of a pixel driving circuit, which is configured to drive the pixel driving circuit. The driving method of the pixel driving circuit may include:

[0435] Step 100: The driving sub-circuit provides a driving current to the third node under the control of the signals at the first node and the second node.

[0436] Step 200 : The first control sub-circuit provides a signal of a data signal line or a reference signal line to a first node N1 under the control of signals of a first scan signal line and a second scan signal line.

[0437] Step 300: Under the control of the signals of the first light-emitting signal line and the second light-emitting signal line, the second control subcircuit provides the signal of the first power line to the second node and provides the signal of the third node to the fourth node.

[0438] Step 400: The third control sub-circuit controls the signal of the third node under the control of the signal of the first reset signal line and the drive of the signal of the auxiliary signal line.

[0439] Step 500: The storage sub-circuit stores a voltage difference of a signal between a first node and a third node.

[0440] The present disclosure also provides a driving method for a pixel driving circuit, which is configured to drive the pixel driving circuit shown in FIG41. The operation process of the pixel driving circuit includes: a first stage to a fifth stage. The driving method for the pixel driving circuit shown in FIG41 may include:

[0441] Step 110. In the first stage, valid level signals are provided to the signals of the second scanning signal line, the second light-emitting signal line, the first reset signal line, and the second reset signal line, the first control sub-circuit provides the signal of the reference signal line to the first node, the third control sub-circuit provides the signal of the auxiliary signal line to the fifth node, and provides the signal of the fifth node to the third node, and the second control sub-circuit provides the signal of the fourth node to the third node.

[0442] Step 120. In the second stage, a valid level signal is provided to the first reset signal line, the second scan signal line and the first light-emitting signal line, the first control subcircuit provides a signal of the reference signal line to the first node, the third control subcircuit provides a signal of the auxiliary signal line to the fifth node, the second control subcircuit provides a signal of the first power line to the second node to charge the first node, and the storage subcircuit stores the voltage difference of the signal between the first node and the third node.

[0443] Step 130 , in the third stage, the signals to the first reset signal line and the first scan signal line are high level signals, the first control subcircuit provides the signal of the data signal line to the first node, and the third control subcircuit provides the signal of the auxiliary signal line to the fifth node.

[0444] Step 140: In the fourth stage, provide an effective level signal to the second reset signal line and the second light-emitting signal line, the third control subcircuit provides the signal of the third node to the fifth node, and the second control subcircuit provides the signal of the fourth node to the third node.

[0445] Step 150. In the fifth stage, a valid level signal is provided to the second reset signal line, the first light-emitting signal line, and the second light-emitting signal line, the second control subcircuit provides the signal of the first power line to the second node, and provides the signal of the third node to the fourth node, the driving subcircuit provides a driving current to the third node under the control of the signals of the first node and the second node, and the third control subcircuit provides the signal of the third node to the fifth node.

[0446] The present disclosure also provides a driving method for a pixel driving circuit, which is configured to drive the pixel driving circuit shown in FIG42. The operation process of the pixel driving circuit includes: a first stage to a fifth stage. The driving method for the pixel driving circuit shown in FIG42 may include:

[0447] Step 210: In the first stage, valid level signals are provided to the second scan signal line, the second light-emitting signal line, the first reset signal line, and the third reset signal line; the first control subcircuit provides a signal of the reference signal line to the first node; the third control subcircuit provides a signal of the auxiliary signal line to the fifth node and provides a signal of the initial signal line to the fourth node; and the second control subcircuit provides a signal of the fourth node to the third node.

[0448] Step 220. In the second stage, valid level signals are provided to the first reset signal line, the third reset signal line, the second scan signal line and the first light-emitting signal line, the first control subcircuit provides a signal of the reference signal line to the first node, the third control subcircuit provides a signal of the auxiliary signal line to the fifth node, and provides a signal of the initial signal line to the fourth node, the second control subcircuit provides a signal of the first power line to the second node to charge the first node, and the storage subcircuit stores the voltage difference of the signal between the first node and the third node.

[0449] Step 230. In the third stage, the signals to the first reset signal line, the third reset signal line and the first scan signal line are high-level signals, the first control subcircuit provides the signal of the data signal line to the first node, the third control subcircuit provides the signal of the auxiliary signal line to the fifth node, and provides the signal of the initial signal line to the fourth node.

[0450] Step 240. In the fourth stage, a valid level signal is provided to the first reset signal line, the third reset signal line and the second light-emitting signal line, the third control subcircuit provides the signal of the initial signal line to the fourth node, provides the signal of the auxiliary signal line to the fifth node, and the second control subcircuit provides the signal of the fourth node to the third node.

[0451] Step 250. In the fifth stage, a valid level signal is provided to the first reset signal line, the first light-emitting signal line, and the second light-emitting signal line, the second control subcircuit provides a signal of the first power line to the second node, and provides a signal of the third node to the fourth node, the driving subcircuit provides a driving current to the third node under the control of the signals of the first node and the second node, and the third control subcircuit provides a signal of the auxiliary signal line to the fifth node.

[0452] The present disclosure also provides a driving method for a pixel driving circuit, which is configured to drive the pixel driving circuits shown in FIG39 and FIG40. The operation process of the pixel driving circuit includes: a first stage to a fifth stage. The driving method for the pixel driving circuits shown in FIG39 and FIG40 may include:

[0453] Step 310. In the first stage, valid level signals are provided to the signals of the second scanning signal line, the second light-emitting signal line, the first reset signal line and the third reset signal line, the first control subcircuit provides the signal of the reference signal line to the first node, the third control subcircuit provides the signal of the auxiliary signal line to the fifth node, and provides the signal of the initial signal line to the fourth node, and the second control subcircuit provides the signal of the fourth node to the third node.

[0454] Step 320. In the second stage, valid level signals are provided to the first reset signal line, the third reset signal line, the second scan signal line and the first light-emitting signal line, the first control subcircuit provides a signal of the reference signal line to the first node, the third control subcircuit provides a signal of the auxiliary signal line to the fifth node, and provides a signal of the initial signal line to the fourth node, the second control subcircuit provides a signal of the first power line to the second node to charge the first node, and the storage subcircuit stores the voltage difference of the signal between the first node and the third node.

[0455] Step 330. In the third stage, the signals to the first reset signal line, the third reset signal line and the first scan signal line are high-level signals, the first control subcircuit provides the signal of the data signal line to the first node, the third control subcircuit provides the signal of the auxiliary signal line to the fifth node, and provides the signal of the initial signal line to the fourth node.

[0456] Step 340. In the fourth stage, a valid level signal is provided to the second reset signal line, the third reset signal line and the second light-emitting signal line, the third control subcircuit provides the signal of the initial signal line to the fourth node, provides the signal of the third node to the fifth node, and the second control subcircuit provides the signal of the fourth node to the third node.

[0457] Step 350. In the fifth stage, a valid level signal is provided to the second reset signal line, the first light-emitting signal line, and the second light-emitting signal line, the second control subcircuit provides the signal of the first power line to the second node, and provides the signal of the third node to the fourth node, the driving subcircuit provides a driving current to the third node under the control of the signals of the first node and the second node, and the third control subcircuit provides the signal of the third node to the fifth node.

[0458] The present disclosure also provides a driving method for a pixel driving circuit, which is configured to drive the pixel driving circuits shown in FIG. 43 and FIG. 44 . The operation process of the pixel driving circuit includes: a first stage to a fifth stage. The driving method for the pixel driving circuits shown in FIG. 43 and FIG. 44 may include:

[0459] Step 410. In the first stage, valid level signals are provided to the signals of the second scanning signal line, the second light-emitting signal line, the first reset signal line and the third reset signal line, the first control subcircuit provides the signal of the reference signal line to the first node, the third control subcircuit provides the signal of the third node to the fifth node, and provides the signal of the initial signal line to the fourth node, and the second control subcircuit provides the signal of the fourth node to the third node.

[0460] Step 420. In the second stage, valid level signals are provided to the first reset signal line, the third reset signal line, the second scan signal line and the first light-emitting signal line, the first control subcircuit provides the signal of the reference signal line to the first node, the third control subcircuit provides the signal of the third node to the fifth node, and provides the signal of the initial signal line to the fourth node, the second control subcircuit provides the signal of the first power line to the second node to charge the first node, and the storage subcircuit stores the voltage difference of the signal between the first node and the third node.

[0461] Step 430. In the third stage, the signals to the first reset signal line, the third reset signal line and the first scan signal line are high-level signals, the first control subcircuit provides the signal of the data signal line to the first node, the third control subcircuit provides the signal of the initial signal line to the fourth node, and provides the signal of the third node to the fifth node.

[0462] Step 440: In the fourth stage, provide an effective level signal to the third reset signal line and the second light-emitting signal line, the third control subcircuit provides the signal of the initial signal line to the fourth node, and the second control subcircuit provides the signal of the fourth node to the third node.

[0463] Step 450. In the fifth stage, a valid level signal is provided to the first light-emitting signal line and the second light-emitting signal line, the second control subcircuit provides the signal of the first power line to the second node, and provides the signal of the third node to the fourth node, and the driving subcircuit provides a driving current to the third node under the control of the signals of the first node and the second node.

[0464] At least one embodiment of the present disclosure further provides a display device, comprising the pixel circuit provided by any embodiment of the present disclosure. The display device may be, for example, an organic light-emitting diode display device, a quantum dot light-emitting diode display device, or other device with display functionality. The embodiments of the present disclosure are not limited thereto.

[0465] The other structures and functions of the display device provided by the embodiment of the present disclosure can be implemented with reference to conventional technologies, and the embodiment of the present disclosure does not limit this. The technical effects of the display device provided by the embodiment of the present disclosure can be referred to the above description of the technical effects of the pixel circuit provided by the embodiment of the present disclosure, and will not be repeated here.

[0466] For example, the display device provided in at least one embodiment of the present disclosure may be any product or component with a display function, such as a display panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator, and the embodiments of the present disclosure are not limited thereto.

[0467] For example, the display device provided by the embodiment of the present disclosure has a display area, and the display area is provided with a plurality of pixel driving circuits.

[0468] In an exemplary embodiment, a display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array, wherein the timing controller is connected to the data driver, the scan driver, and the light-emitting driver, respectively. The data driver is connected to a plurality of data signal lines, respectively. The scan driver is connected to a plurality of scan signal lines, respectively. The light-emitting driver is connected to a plurality of light-emitting signal lines, respectively. The pixel array may include a plurality of sub-pixels, at least one of which may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit, and the pixel driving circuit may be connected to the scan signal lines, the light-emitting signal lines, and the data signal lines, respectively.

[0469] The scanning signal lines include: a first scanning signal line, a second scanning signal line, a first reset signal line, a second reset signal line and a third reset signal line. The light emitting signal lines include: a first light emitting signal line and a second light emitting signal line.

[0470] In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, can provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and can provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver.

[0471] In an exemplary embodiment, the data driver may generate a data voltage to be supplied to the data signal line using a grayscale value and a control signal received from the timing controller. For example, the data driver may sample the grayscale value using a clock signal and apply a data voltage corresponding to the grayscale value to the data signal line in units of pixel rows.

[0472] In an exemplary embodiment, the scan driver may generate a scan signal to be provided to the scan signal line by receiving a clock signal, a scan start signal, etc. from a timing controller. For example, the scan driver may sequentially provide a scan signal having an on-level pulse to the scan signal line. For example, the scan driver may be configured in the form of a shift register and may generate the scan signal by sequentially transmitting the scan start signal provided in the form of an on-level pulse to the next stage circuit under the control of a clock signal.

[0473] In an exemplary embodiment, the light emitting driver may generate an emission signal to be provided to the light emitting signal line by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the light emitting driver may sequentially provide emission signals having an off-level pulse to the light emitting signal line. For example, the light emitting driver may be configured in the form of a shift register and may generate emission signals by sequentially transmitting the emission stop signal provided in the form of an off-level pulse to the next stage circuit under the control of a clock signal.

[0474] In an exemplary embodiment, a display substrate may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first subpixel that emits light of a first color, a second subpixel that emits light of a second color, and a third subpixel that emits light of a third color. The first, second, and third subpixels each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first, second, and third subpixels are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line and output a corresponding current to the light-emitting device. The light-emitting devices in the first, second, and third subpixels are respectively connected to the pixel driving circuits of their respective subpixels. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuits of their respective subpixels.

[0475] In an exemplary embodiment, the first sub-pixel may be a red sub-pixel (R) that emits red light, the second sub-pixel may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel may be a green sub-pixel (G) that emits green light. In an exemplary embodiment, the shape of the sub-pixels may be rectangular, diamond, pentagonal, or hexagonal.

[0476] In an exemplary embodiment, a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a triangular arrangement, which is not limited in the present disclosure.

[0477] In an exemplary embodiment, a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, etc., which is not limited in the present disclosure.

[0478] In a plane perpendicular to the display substrate, the display substrate may include a driving structure layer disposed on a base, a light-emitting structure layer disposed on a side of the driving structure layer away from the base, and an encapsulation structure layer disposed on a side of the light-emitting structure layer away from the base. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited in this disclosure.

[0479] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and conductive foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0480] In an exemplary embodiment, the driving structure layer may include multiple transistors and storage capacitors that constitute a pixel driving circuit, and the light-emitting structure layer may include an anode, a pixel definition layer, an organic light-emitting layer and a cathode. The anode is connected to the drain electrode of the transistor therein through a via, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of corresponding color under the drive of the anode and the cathode.

[0481] In an exemplary embodiment, the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0482] In an exemplary embodiment, the touch structure layer may include a first touch insulation layer arranged on the packaging structure layer, a first touch metal layer arranged on the first touch insulation layer, a second touch insulation layer covering the first touch metal layer, a second touch metal layer arranged on the second touch insulation layer, and a touch protection layer covering the second touch metal layer. The first touch metal layer may include a plurality of bridging electrodes, the second touch metal layer may include a plurality of first touch electrodes and second touch electrodes, and the first touch electrode or the second touch electrode may be connected to the bridging electrode through a via.

[0483] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

[0484] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0485] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0486] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0487] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0488] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0489] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0490] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0491] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0492] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

[0493] There are a few points to note:

[0494] (1) The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can refer to general designs.

[0495] (2) In the absence of conflict, features in the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0496] The foregoing description is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure, which is determined by the appended claims.

Claims

1. A pixel circuit, comprising: A driving circuit, comprising a control terminal, a first terminal and a second terminal, and configured to control the magnitude of a driving current flowing through the first terminal and the second terminal; a first compensation circuit, configured to apply a reference signal to the control terminal of the driving circuit in response to a first compensation control signal, the first compensation circuit comprising a first storage capacitor, a first electrode of the first storage capacitor being electrically connected to the control terminal of the driving circuit, and a second electrode of the first storage capacitor being electrically connected to the first terminal of the driving circuit; a light emitting element configured to emit light under the driving of the driving current, wherein a second electrode of the light emitting element is electrically connected to a second voltage terminal to receive a second power supply voltage; a second light emitting control circuit, wherein a control end of the second light emitting control circuit is configured to receive a second light emitting control signal, a first end of the second light emitting control circuit is electrically connected to a first end of the driving circuit, a second end of the second light emitting control circuit is electrically connected to a first electrode of the light emitting element, and the second light emitting control circuit is configured to apply the driving current to the light emitting element in response to the second light emitting control signal and allow the reset signal to be applied to the first end of the driving circuit; as well as A reset control circuit, wherein a control end of the reset control circuit is configured to receive a reset control signal, a first end of the reset control circuit is electrically connected to a first end of the drive circuit, a second end of the reset control circuit is electrically connected to a reset signal end to receive a reset signal, a third end of the reset control circuit is electrically connected to a first electrode of the light-emitting element, and the reset control circuit is configured to apply the reset signal to the first electrode of the light-emitting element and / or the first end of the drive circuit in response to the reset control signal.

2. The pixel circuit according to claim 1, wherein: The reset control circuit comprises: A second compensation circuit, comprising a second storage capacitor, wherein the second compensation capacitor is electrically connected between the first terminal of the driving circuit and the reset signal terminal; and a reset circuit, wherein the control end of the reset circuit serves as the control end of the reset control circuit and is configured to receive the reset control signal, the first end of the reset circuit serves as the third end of the reset control circuit and is electrically connected to the first electrode of the light emitting element, and the second end of the reset circuit serves as the second end of the reset control circuit and is electrically connected to the reset signal end to receive the reset signal Number.

3. The pixel circuit according to claim 1 or 2, wherein: The value of the reset signal is adjustable.

4. The pixel circuit according to claim 3, wherein: The reset signal includes at least a first reset signal and a second reset signal, the first reset signal corresponds to a first display temperature, the second reset signal corresponds to a second display temperature, the first display temperature is lower than the second display temperature, and the value of the first reset signal is smaller than the value of the second reset signal.

5. The pixel circuit according to claim 4, wherein: The first reset signal is adjusted to the second reset signal during a reset signal adjustment period, and the pixel circuit corresponds to a plurality of display frame periods. The reset signal adjustment period is located between two adjacent display frame periods; or, The reset signal adjustment period is within a display frame cycle, and the display frame cycle at least includes a reset phase, a compensation phase, a data writing phase, and a light-emitting phase. The reset signal adjustment period at least partially overlaps with, or does not overlap with, any of the reset phase, the compensation phase, the data writing phase, and the light-emitting phase.

6. The pixel circuit according to any one of claims 1 to 5, wherein: The value of the reference signal is adjustable.

7. The pixel circuit according to claim 2, wherein: The first electrode of the second storage capacitor serves as the first end of the reset control circuit and is electrically connected to the first end of the drive circuit, and the second electrode of the second storage capacitor is electrically connected to the first end of the reset circuit.

8. The pixel circuit according to claim 7 further includes a first light-emitting control circuit, wherein the control end of the first light-emitting control circuit is configured to receive a first light-emitting control signal, the first end of the first light-emitting control circuit is electrically connected to the second end of the driving circuit, the second end of the first light-emitting control circuit is electrically connected to the first voltage end to receive a first power supply voltage, and the first light-emitting control circuit is configured to apply the first power supply voltage to the second end of the driving circuit in response to the first light-emitting control signal.

9. The pixel circuit according to claim 8, wherein: The first light-emitting control circuit includes a first light-emitting control transistor, a gate of the first light-emitting control transistor is electrically connected to a first light-emitting control terminal to receive the first light-emitting control signal, a first electrode of the first light-emitting control transistor is electrically connected to a second terminal of the driving circuit, and a second electrode of the first light-emitting control transistor is electrically connected to the first voltage terminal to receive the first power supply voltage.

10. The pixel circuit according to any one of claims 2 to 7, wherein: The second terminal of the driving circuit is directly electrically connected to the first voltage terminal to receive a first power supply voltage.

11. The pixel circuit according to any one of claims 7 to 10, wherein: The reset circuit includes a reset transistor, a gate of the reset transistor is electrically connected to a reset control terminal to receive the reset control signal, a first electrode of the reset transistor is electrically connected to a second electrode of the second storage capacitor and a first terminal of the drive circuit, and a second electrode of the reset transistor is electrically connected to the reset signal terminal to receive the reset signal.

12. The pixel circuit according to any one of claims 7 to 10, wherein: The second light-emitting control circuit includes a second light-emitting control transistor, a gate of the second light-emitting control transistor is electrically connected to the second light-emitting control terminal to receive the second light-emitting control signal, a first electrode of the second light-emitting control transistor is electrically connected to the first terminal of the driving circuit, and a second electrode of the second light-emitting control transistor is electrically connected to the first electrode of the light-emitting element.

13. The pixel circuit according to claim 12, wherein: The pixel circuit also includes an auxiliary compensation circuit, a control end of the auxiliary compensation circuit is configured to receive an auxiliary compensation signal, a first end of the auxiliary compensation circuit is electrically connected to the second electrode of the second storage capacitor, and a second end of the auxiliary compensation circuit is electrically connected to the first electrode of the light-emitting element.

14. The pixel circuit according to claim 13, wherein: The first end of the auxiliary compensation circuit is also electrically connected to the second end of the second light emitting control circuit and the first end of the reset circuit.

15. The pixel circuit according to claim 14, wherein: The auxiliary compensation circuit includes an auxiliary compensation transistor, the gate of the auxiliary compensation transistor serves as the control end of the auxiliary compensation circuit to receive the auxiliary compensation control signal, the first electrode of the auxiliary compensation transistor is electrically connected to the second electrode of the second compensation capacitor and the second electrode of the second light-emitting control transistor, and the second electrode of the auxiliary compensation transistor is electrically connected to the first electrode of the light-emitting element.

16. The pixel circuit according to claim 13, wherein: The first end of the auxiliary compensation circuit is also electrically connected to the first end of the reset circuit, and the second end of the auxiliary compensation circuit is also electrically connected to the second end of the second light emitting control circuit.

17. The pixel circuit according to claim 16, wherein: The auxiliary compensation circuit includes an auxiliary compensation transistor, a gate of the auxiliary compensation transistor is electrically connected to the auxiliary compensation control terminal to receive the auxiliary compensation control signal, a first electrode of the auxiliary compensation transistor is electrically connected to the second electrode of the second compensation capacitor and the first electrode of the reset transistor, and a second electrode of the auxiliary compensation transistor is electrically connected to the first electrode of the light-emitting element.

18. The pixel circuit according to claim 15 or 17, wherein: The gate of the auxiliary compensation transistor is electrically connected to the gate of the second light emission control transistor, the auxiliary compensation transistor and the second light emission control transistor share a gate, the second light emission control signal serves as the auxiliary compensation control signal, and the type of the auxiliary compensation transistor is the same as that of the second light emission control transistor; or, The gate of the auxiliary compensation transistor and the gate of the second light emission control transistor are independent of each other and are not electrically connected.

19. The pixel circuit according to claim 17, wherein: The gate of the auxiliary compensation transistor is electrically connected to the gate of the reset transistor, the auxiliary compensation transistor and the reset transistor share a gate, the reset control signal serves as the auxiliary compensation control signal, and the type of the auxiliary compensation transistor is the same as the type of the reset transistor; or, The gate of the auxiliary compensation transistor and the gate of the reset transistor are independent of each other and are not electrically connected.

20. The pixel circuit according to any one of claims 2 to 19, wherein: The driving circuit includes a driving transistor, a gate of the driving transistor serving as a control terminal of the driving circuit and being electrically connected to a first node, a first electrode of the driving transistor serving as a first terminal of the driving circuit and being electrically connected to a first electrode of the second storage capacitor at a second node, and a second electrode of the driving transistor serving as a second terminal of the driving circuit and being electrically connected to a first voltage terminal to receive a first power supply voltage; The pixel circuit also includes: a data writing circuit, wherein the control end of the data writing circuit is configured to receive a data scanning signal, a first end of the data writing circuit is electrically connected to the data signal end to receive the data signal, a second end of the data writing circuit is electrically connected to the first node, and the data writing circuit is configured to write the data signal to the control end of the driving circuit in response to the data scanning signal.

21. The pixel circuit according to claim 16, wherein: The control end of the first compensation circuit is configured to receive the first compensation control signal, the first end of the first compensation circuit is electrically connected to the reference signal end to receive the reference signal, and the second end of the first compensation circuit is electrically connected to the second node. The first compensation circuit further includes a first compensation transistor, a gate of the first compensation transistor serving as a control terminal of the first compensation circuit and being electrically connected to a first compensation control signal terminal to receive the first compensation control signal, a first electrode of the first compensation transistor serving as a first terminal of the first compensation circuit and being electrically connected to the reference signal terminal to receive the reference signal, and a second electrode of the first compensation transistor being electrically connected to the first node. The data write circuit includes a data write transistor, a gate of the data write transistor is electrically connected to a data scan signal terminal to receive the data scan signal, a first electrode of the data write transistor is electrically connected to the data signal terminal to receive the data signal, and a second electrode of the data write transistor is electrically connected to the first node.

22. The pixel circuit according to claim 21, wherein: The data writing transistor and the first compensation transistor are transistors controlled independently of each other, the data scanning signal terminal and the first compensation control signal terminal are different signal terminals independent of each other, and the data signal terminal and the reference signal terminal are different signal terminals independent of each other; or The data write transistor is multiplexed as the first compensation transistor, the data scan signal is multiplexed as the first compensation control signal, the first electrode of the data write transistor is also electrically connected to the reference signal terminal to receive the reference signal, the data signal terminal is multiplexed as the reference signal terminal, and is configured to provide the data signal or the reference signal respectively in different time periods.

23. A display device comprising the pixel circuit according to any one of claims 1 to 22.

24. A driving method for a pixel circuit, applicable to the pixel circuit according to any one of claims 1 to 22, the driving method comprising: The reset control signal is set to be a start signal so that the reset signal is applied to the first electrode of the light emitting element and / or the first end of the driving circuit through the reset control circuit.

25. The driving method of the pixel circuit according to claim 24, wherein: The reset control circuit includes a second compensation circuit and a reset circuit, wherein the second compensation circuit includes a second storage capacitor, wherein the first electrode of the second storage capacitor serves as the first end of the reset control circuit and is electrically connected to the first end of the drive circuit, and the second electrode of the second storage capacitor is electrically connected to the first end of the reset circuit; the control end of the reset circuit serves as the control end of the reset control circuit and is configured to receive the reset control signal, the first end of the reset circuit serves as the third end of the reset control circuit and is electrically connected to the first electrode of the light-emitting element, and the second end of the reset circuit serves as the second end of the reset control circuit and is electrically connected to the reset signal end to receive the reset signal, The driving method includes a reset phase, a compensation phase, a data writing phase and a light emitting phase. In the reset stage, the reset control signal is set to be an on signal in at least a part of the time period so that the first end and the second end of the reset circuit are turned on, and the reset signal is sequentially applied to the second electrode of the second storage capacitor, the first end of the drive circuit, and the first electrode of the light-emitting element through the second end and the first end of the reset circuit; In the compensation phase and the data writing phase, the reset control signal is set to be a start signal, and the reset signal is sequentially applied to the second electrode of the second storage capacitor and the first electrode of the light-emitting element through the second end and the first end of the reset circuit; In the light emitting stage, the reset control signal is set to be a shutdown signal in at least a part of the time period, so that the second electrode of the second storage capacitor is disconnected from the reset signal terminal.

26. The driving method of the pixel circuit according to claim 25, wherein: The pixel circuit further includes a data writing circuit and a first light emitting control circuit; the control end of the data writing circuit is configured to receive a data scanning signal, the first end of the data writing circuit is electrically connected to the data signal end to receive the data signal, and the second end of the data writing circuit is electrically connected to the control end of the driving circuit; the control end of the first light emitting control circuit is configured to receive a first light emitting control signal, the first end of the first light emitting control circuit is electrically connected to the second end of the driving circuit, and the second end of the first light emitting control circuit is electrically connected to the first voltage end so that the second end of the driving circuit receives a first power supply voltage; In the light-emitting stage, the driving method includes sequentially performing the following steps S101 to S104: Step S101: setting the data scanning signal to a shutdown signal to shut down the data writing circuit; Step S102: setting the second light-emitting control signal to an on signal to turn on the second light-emitting control circuit, and setting the first light-emitting control signal to an off signal to turn off the first light-emitting control circuit; Step S104: setting the first light-emitting control signal to be a start signal to turn on the first light-emitting control circuit, so that the second end of the driving circuit receives the first power supply voltage from the first voltage end via the first light-emitting control circuit.

27. The driving method of a pixel circuit according to any one of claims 25 to 26, wherein: The pixel circuit further includes a data writing circuit and a first light emitting control circuit; the control end of the data writing circuit is configured to receive a data scanning signal, the first end of the data writing circuit is electrically connected to the data signal end to receive the data signal, and the second end of the data writing circuit is electrically connected to the control end of the driving circuit; the control end of the first light emitting control circuit is configured to receive a first light emitting control signal, the first end of the first light emitting control circuit is electrically connected to the second end of the driving circuit, and the second end of the first light emitting control circuit is electrically connected to the first voltage end so that the second end of the driving circuit receives a first power supply voltage; In the reset stage, the driving method includes sequentially performing the following steps S1010 to S1030: Step S1010: disconnecting the second terminal of the driving circuit from the first voltage terminal; Step S1020: setting the reset control signal to be an on signal to turn on the reset circuit; as well as Step S1030: Set the first compensation control signal to be an on signal to turn on the first compensation Circuit, Furthermore, in the reset phase, the data scanning signal is maintained as a turn-off signal to turn off the data writing circuit, and the second light emitting control signal is maintained as an turn-on signal to turn on the second light emitting control circuit.

28. The driving method of a pixel circuit according to any one of claims 26 to 27, wherein: In the compensation stage, the driving method includes sequentially performing the following steps S2010 to S2020: Step S2010: setting the second light-emitting control signal to be a turn-off signal to turn off the second light-emitting control circuit, and keeping the first light-emitting control signal to be a turn-off signal to turn off the first light-emitting control circuit; as well as Step S2020: setting the first light-emitting control signal to be an on signal to turn on the first light-emitting control circuit, and keeping the second light-emitting control signal to be an off signal; Furthermore, during the compensation phase, the data scanning signal is maintained as a turn-off signal to keep the data writing circuit turned off, and the first compensation control signal is maintained as an turn-on signal to keep the first compensation circuit turned on.

29. The driving method of a pixel circuit according to any one of claims 25 to 28, wherein: The pixel circuit further includes a data writing circuit, wherein a control end of the data writing circuit is configured to receive a data scanning signal, a first end of the data writing circuit is electrically connected to a data signal end to receive a data signal, and a second end of the data writing circuit is electrically connected to a control end of the driving circuit. Wherein, in the data writing stage, the driving method includes sequentially performing the following steps S3010 to S3030: Step S3010: setting the first compensation control signal to be a shutdown signal to turn off the first compensation circuit, and allowing the second end of the driving circuit to continue to receive the first power supply voltage; and Step S3030: setting the data scanning signal to be a start signal to turn on the data writing circuit. Wherein, during the data writing phase, the second light emitting control signal is maintained as a shutdown signal to keep the second light emitting control circuit turned off.

30. The driving method of the pixel circuit according to claim 29, wherein: The pixel circuit further includes a first light emitting control circuit, wherein a control terminal of the first light emitting control circuit is configured to receive a first light emitting control signal, a first terminal of the first light emitting control circuit is electrically connected to a second terminal of the driving circuit, and a second terminal of the first light emitting control circuit is electrically connected to a first voltage terminal so that the second terminal of the driving circuit receives a first power supply voltage; The step S3030 further includes: setting the first light-emitting control signal to be a start signal to turn on the first light-emitting control circuit, so that the second end of the driving circuit receives the first power supply voltage.

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