Apparatus and method for configurable ECC mode

Abstract

Devices, systems, and methods for enhanced ECC mode. The memory array comprises a plurality of data column planes and additional column planes. When the memory device is set in an enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one column plane other than the subset of the data column planes or one of the additional column planes. In this way, depending on the selected mode, the memory may be able to perform single error correction or single error correction with dual error detection (SECDED).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 383,865, filed on November 15, 2022. This application is incorporated herein by reference in its entirety and for all purposes. Background Art

[0003] The present disclosure relates generally to semiconductor devices, and more particularly to semiconductor memory devices. In particular, the present disclosure relates to volatile memory, such as dynamic random access memory (DRAM). Information may be stored as physical signals (e.g., charge on a capacitive element) on individual memory cells of the memory. During an access operation, an access command may be received along with address information specifying which memory cells should be accessed.

[0004] There is increasing interest in enabling memories to store information associated with data segments in arrays. For example, error correction information may be stored in an array along with its associated data. It may be desirable to ensure that this information can be accessed along with the specified data without unduly affecting the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0006] Figure 2 is a block diagram of a memory device according to some embodiments of the present invention.

[0007] Figure 3 is a block diagram showing an example of a read operation of a memory according to some example embodiments of the present disclosure.

[0008] Figure 4 is a schematic diagram of a portion of a memory bank according to some embodiments of the present disclosure.

[0009] Figure 5 is a flow chart of a method for performing enhanced ECC operations according to some embodiments of the present disclosure.

[0010] Figure 6 is a flow chart of a method for writing an error correction code (ECC) mode to a mode register of a memory device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0011] The following description of certain embodiments is merely exemplary in nature and is by no means intended to limit the scope of the present disclosure or its application or use. In the following detailed description of the embodiments of the present system and method, reference is made to the accompanying drawings that form a part thereof, and the accompanying drawings are shown by illustrative specific embodiments in which the description system and method can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the currently disclosed system and method, and it should be understood that other embodiments may be utilized and that structural and logical changes may be made without departing from the spirit and scope of the present disclosure. In addition, for the purpose of clarity, the detailed description of certain features will not be discussed when it is obvious to those skilled in the art, so as not to obscure the description of the embodiments of the present disclosure. Therefore, the following detailed description should not be understood in a limiting sense, and the scope of the present disclosure is defined only by the appended claims.

[0012] The memory array may generally include a number of memory cells arranged at the intersection of word lines (rows) and bit lines / digit lines (columns). The columns may be grouped together into column planes, and a column select (CS) signal may be used to select a set of columns within each active column plane to provide data. When an access command is received, the memory may pre-fetch a codeword (e.g., a number of bits of data) and one or more associated bits from the memory and replace the pre-fetched data with new data (e.g., as part of a write operation) or provide the pre-fetched data from the memory device (e.g., as part of a read operation). Some memory modes may involve providing less than all of the pre-fetched data from the memory device. For example, in a conventional memory device, in certain modes, half of the pre-fetched data may be provided from the device, and the remainder may be ignored.

[0013] The memory device may store additional information associated with each codeword. For example, the additional information may include parity bits used as part of an error correction scheme. However, the maximum number of bits that can be retrieved as part of a single access pass may be limited by the architecture of the memory, and this number may generally be based on the maximum number of data bits in the codeword plus a certain number of additional bits (e.g., 128 data bits + 8 additional bits). Some memories may include a set of data column planes, plus an additional column plane storing additional information. However, for various applications, it may be desirable to include additional information of more number bits than can be retrieved from the additional column plane (e.g., to include a lower data bit to parity bit ratio, etc.). Some memory devices may use a 'two-pass' architecture, in which at least some of the additional bits are first retrieved, stored, and then the codeword data bits are retrieved in a second access pass. However, this may result in a penalty for the delay of any given access operation. A one-pass or single-pass architecture for storing extended additional information that enables codewords and additional bits to be retrieved as part of a single access pass to the memory array may provide performance benefits superior to two-pass architectures.

[0014] As used herein, the term data may represent any information bit that the controller wishes to store and / or retrieve from the memory. Data represents information written to the memory by the controller and then also read from the memory by the controller. The term parity may represent any bit generated by the error correction circuit of the memory based on data, metadata, or a combination thereof. Parity may typically reside within the memory. In some embodiments, the amount of data retrieved as part of a single access operation may represent a group of bits that are a small portion of a larger information segment. For example, data bits (e.g., 64 bits) retrieved as part of a single access operation may not have any meaning by themselves, but may have meaning when combined with several groups of data bits retrieved as part of other access operations (e.g., to other memory arrays and / or to the same array at different times).

[0015] The present disclosure relates to apparatus, systems and methods for single-pass access of ECC information from one of an additional column plane or a data column plane with an associated codeword, for example, to implement single error correction (SEC) double error detection (DED). Some memory devices may operate in a mode in which less than all data bits that can be pre-fetched are provided from the device. For example, a memory device may pre-fetch 128 data bits as part of a codeword in x8 or x16 mode, whereas a 64-bit codeword is provided at the data terminal of the device in x4 memory mode. The data bits of the codeword in x4 memory mode are stored in some but not all (e.g., half of the column plane) in the data column plane. The selectable half of the data column plane may be based on a column address. Additional bits associated with the data (e.g., parity bits) may be stored in either an additional column plane or in a data column plane that is not selected by the column address as part of the current access.

[0016] According to some embodiments of the present disclosure, an example memory device may include a set of data column planes and an additional column plane. By storing some of the ECC data together with its associated data in the data column plane and storing some of the ECC data in the additional column plane, the memory can be set to a mode that enables SECDED. SECDED requires a lower codeword bit to ECC bit ratio. That is, 8 ECC parity bits per 128 bits of data may only be able to perform single error detection (SED) within the data. However, 8 parity bits per 64 bits of data can enable SECDED. In some instances, the additional column plane may be smaller than the data column plane, and therefore, it may not be possible to store a sufficient number of ECC bits for each column address access to implement SECDED for a 64-bit codeword architecture.

[0017] To provide additional ECC storage, some ECC data may be stored in the data column plane. When performing an access operation, a column select signal having a first value is provided to columns in the first portion of the data column plane and the additional column plane, and a column select signal having a second value is provided to one or more columns not in the first portion of the data column plane. The memory may store data in the first portion of the data column plane, and may store ECC data in the additional column plane and / or in accessed columns not in the first portion of the data column plane. In this way, data and ECC information for a codeword may be pre-fetched together as part of a single access pass without pre-fetching additional data bits to facilitate SECDED ECC operations.

[0018] In some embodiments, the mode register may be used to switch between behaviors of the memory device. For example, if the enhanced ECC mode is disabled (e.g., SEC enabled), the memory may have a first x4 operating mode in which the memory may store data bits at a first portion of the data column plane and a second portion of the data column plane, and pre-fetch ECC parity information from an additional column plane. In this x4 operating mode, the ECC circuitry of the memory may correct single bit errors in the pre-fetched data bits based on the pre-fetched parity bits, and then provide data bits (e.g., bits from the first portion) from the memory.

[0019] When enhanced ECC is enabled (e.g., SECDED is enabled), as part of an access operation, the memory may pre-fetch data bits from a first portion of the data column plane and pre-fetch ECC parity bits from one of the additional column planes or from a column plane in a second portion of the data column plane (e.g., determined based on a column address). The ECC circuit may correct errors in the data based on the parity bits, and the corrected data may be transmitted from the device. Thus, in a second mode (e.g., SECDED enabled mode), the ECC may pre-fetch and process fewer bits than in a first mode (e.g., SEC enabled mode). In the second mode, SECDED is achieved via a lower codeword bit to parity bit ratio.

[0020] Figure 1 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure. The semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip. The device may be operated by a controller 150 (eg, a processor).

[0021] The semiconductor device 100 includes a memory array 118. The memory array 118 is shown as including a plurality of memory banks. Figure 1In the embodiment of the present invention, the memory array 118 is shown as including eight memory banks BANK0 to BANK7. More or fewer memory banks may be included in the memory array 118 of other embodiments. As explained in more detail herein, each memory bank may be further divided into two or more sub-memory banks. Although this article generally describes an embodiment in which each memory bank includes two sub-memory banks, other embodiments may include more sub-memory banks per memory bank.

[0022] Each memory sub-bank includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL. The selection of the word line WL is performed by the row decoder 108, and the selection of the bit line BL is performed by the column decoder 110. Figure 1 In some embodiments, row decoder 108 includes a respective row decoder for each memory bank, and column decoder 110 includes a respective column decoder for each memory bank. In some embodiments, components such as row and column decoders and refresh control circuit 116 that are repeated bank by bank may also include components that are repeated sub-bank. For example, refresh control circuit 116 may exist for each sub-bank.

[0023] The bit lines BL are coupled to corresponding sense amplifiers (SAMPs). Read data from the bit lines BL are amplified by the sense amplifiers SAMPs and transmitted to the ECC circuit 120 through the local data line (LIO), the transfer gate (TG), and the global data line (GIO). Conversely, write data output from the ECC circuit 120 is transmitted to the sense amplifiers SAMPs through the complementary main data line GIO, the transfer gate TG, and the complementary local data line LIO, and is written in the memory cells MC coupled to the bit lines BL.

[0024] The semiconductor device 100 may employ a plurality of external terminals (e.g., pads), including a command and address terminal coupled to a command and address (C / A) bus to receive commands and addresses, a clock terminal for receiving clocks CK and / CK, a data terminal DQ coupled to a data bus to provide data, and a power supply terminal for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ.

[0025] The clock terminal is supplied with external clocks CK and / CK provided to the input circuit 112. The external clocks may be complementary. The input circuit 112 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is provided to the command decoder 106 and the internal clock generator 114. The internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used to time the operation of various internal circuits. The internal data clock LCLK is provided to the input / output circuit 122 to time the operation of the circuit included in the input / output circuit 122, for example, to the data receiver to time the reception of write data. The input / output circuit 122 may include several interface connections, each of which may be coupled to one of the DQ pads (e.g., pads that may serve as external connections to the device 100).

[0026] The C / A terminal may be supplied with a memory address. The memory address supplied to the C / A terminal is transmitted to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the address and supplies the decoded row address XADD to the row decoder 108, and supplies the decoded column address YADD to the column decoder 110. The decoded row address XADD can be used to determine which row should be turned on, which can result in data along the bit line being read out along the bit line. The column decoder 110 can provide a column select signal CS, which can be used to determine which sense amplifiers provide data to the LIO. The address decoder 104 can also supply a decoded memory bank address BADD, which can indicate the memory bank of the memory array 118 containing the decoded row address XADD and the column address YADD.

[0027] The C / A terminal may be supplied with commands. Command examples include timing commands for controlling the timing of various operations, access commands for accessing memory (e.g., read commands for performing read operations and write commands for performing write operations), and other commands and operations. The access command may be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD to indicate the memory cell(s) to be accessed.

[0028] The command may be provided as an internal command signal via the command / address input circuit 102 to the command decoder 106. The command decoder 106 includes circuitry for decoding the internal command signal to generate various internal signals and commands for performing an operation. For example, the command decoder 106 may provide a signal indicating whether data is to be read, written, etc.

[0029] The device 100 may receive an access command as a read command. When the read command is received and the bank address, row address, and column address are stored in time with the read command, read data is read from the memory cell corresponding to the row address and column address in the memory array 118. The read command is received by the command decoder 106, and the command decoder 106 provides an internal command so that the data read from the memory array 118 is provided to the ECC circuit 120. The ECC circuit 120 receives the data bits and parity bits from the memory array 118, and detects and / or corrects errors in the data bits. Correct read data is provided along the data bus and output to the outside from the data terminal DQ via the input / output circuit 122.

[0030] The device 100 may receive an access command as a write command. When the write command is received and the bank address, row address, and column address are supplied in time with the write command, the write data supplied to the data terminal DQ is provided along the data bus and written to the memory cell corresponding to the row address and the column address in the memory array 118. The write command is received by the command decoder 106, and the command decoder 106 provides an internal command so that the write data is received by the data receiver in the input / output circuit 122. The write data is supplied to the ECC circuit 120 via the input / output circuit 122. The ECC circuit generates a parity bit based on the received data and the received data and the parity are provided by the ECC circuit 120 to the memory array 118 to be written into the memory cell MC.

[0031] The device 100 includes refresh control circuits 116, each of which is associated with a bank of the memory array 118. Each refresh control circuit 116 can determine when to perform a refresh operation on the associated bank. The refresh control circuit 116 provides a refresh address RXADD (along with one or more refresh signals, Figure 1 1. The row decoder 108 performs a refresh operation on one or more word lines associated with RXADD. The refresh control circuit 116 may perform a variety of types of refresh operations, which may determine how to generate the address RXADD, and other details such as how many word lines are associated with the address RXADD.

[0032] The ECC circuit 120 may detect and / or correct errors in the accessed data. As part of a write operation, the ECC circuit 120 may receive bits from the IO circuit 122 and generate parity bits based on those received bits. The received bits and parity bits are written to the memory array 118. During an example read operation, the ECC circuit 120 receives a set of bits and their associated parity bits from the array 118 and uses them to locate and / or correct errors. For example, in a single error correction (SEC) scheme, up to one bit error may be located and detected. In a single error correction double error detection (SECDED) scheme, up to one bit error may be corrected, but two errors may be detected (although the bits causing those errors are not individually located and therefore cannot be corrected). The ECC circuit 120 may correct the information and then provide the corrected information (and / or a signal indicating a detected error) to the IO circuit 122. The parity bits may not typically be provided to the IO circuit 122.

[0033] Mode register 130 may include various settings and may be used to enable an enhanced ECC mode of memory 100. When the enhanced ECC mode is enabled, device 100 may store ECC data associated with the data in an additional column plane or in a designated data column plane determined based on a column address.

[0034] The memory 100 may operate in various modes based on the number of DQ pads used. The mode may determine how many DQ pads the controller 150 expects to send / receive data along, as well as the format and / or number of bits that the controller 150 expects as part of a single access command. For example, a memory may have 16 physical DQ pads. In x16 mode, all 16 DQ pads are used. In x8 mode, eight DQ pads are used, and in x4 mode, four DQ pads are used. The mode may also determine the burst length at each DQ terminal as part of the DQ operation. The burst length represents the number of serial bits at each DQ terminal during an access operation.

[0035] For example, in x8 mode, the memory may send or receive 128 data bits along 8 DQ terminals, each with a burst length of 16. In an example x4 mode, a burst length of 16 may also be used, and thus 64 bits may be sent or received as part of an access operation. The present disclosure will generally be described with respect to an example embodiment in which a codeword of 64 data bits is accessed as part of the x4 mode, and the ECC circuit 120 uses 8-bit ECC parity. Other example embodiments may use different numbers of data and parity.

[0036] The device 100 includes a mode register 130 that can be used to control various optional modes of the memory. For example, the mode register 130 may include settings that determine whether the enhanced ECC mode is enabled. If the enhanced ECC mode is enabled, the mode register 130 may set a one-pass x4 mode of operation. The controller 150 may perform a mode register write (MRW) operation to set the value in the mode register 130, or may perform a mode register read (MRR) operation to check what the value in the mode register 130 is. The mode register 130 includes several registers, each of which can store one or more bits corresponding to a setting or segment of information about the memory.

[0037] The controller 150 may provide the command and the row and column addresses as part of the access operation.In the x4 mode of operation, in response to the address and read command, the memory may retrieve data and parity as part of a single access pass to the memory array.

[0038] The power supply terminal is supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VARY and the like based on the power supply potentials VDD and VSS supplied to the power supply terminal.

[0039] The power supply terminal is also supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 122. In an embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminal may be the same potential as the power supply potentials VDD and VSS supplied to the power supply terminal. In another embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminal may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminal. The power supply potentials VDDQ and VSSQ supplied to the power supply terminal are used for the input / output circuit 122 so that the power supply noise generated by the input / output circuit 122 does not propagate to other circuit blocks.

[0040] Figure 2 is a block diagram of a memory device according to some embodiments of the present disclosure. In some embodiments, the memory device 200 may represent Figure 1 A portion of the memory device 100. Figure 2 The view display may be a memory storage body (e.g., Figure 1 1 and 2. The memory array 118 of FIG. 1 may further include a portion of the memory arrays 210 to 214 and 220 to 224 of the memory array 118 of FIG. 1 along with selected circuits used in the data path, such as the ECC circuit 232 (eg, Figure 1120) and IO circuit 234 (e.g., Figure 1 122). For clarity, Figure 2 Certain circuits and signals are omitted from the illustration.

[0041] The memory device 200 is organized into several column planes 210 to 214. Each of the column planes represents a portion of a memory bank. Each column plane 210 to 214 includes several memory cells at the intersection of a word line WL and a bit line. The bit lines can be grouped together into groups activated by the value of a CS signal. For clarity, only a single vertical line is used to represent the bit lines of each column selection group, however, there may be multiple columns accessed by the value of CS. For example, each line may represent 8 bit lines, all of which are accessed together by the value of CS. As used herein, the 'value' of CS may refer to a decoded signal provided to a bit line group. Therefore, a first value may represent a first value of a multi-bit CS signal, or be valid after decoding a signal line associated with that value. A word line may extend across multiple column planes 210 to 214.

[0042] The memory 200 includes a set of data column planes 210 and an additional column plane 212. The additional column plane 212 may be used to store additional information, such as ECC parity bits.

[0043] In some embodiments, the memory 200 may also include an optional global column redundancy (GCR) column plane 214. In some embodiments, the GCR plane 214 may have fewer memory cells (e.g., fewer column select groups) than the data column plane 210. The GCR CP 214 includes several redundant columns that may be used as part of a repair operation. If the value of the CS signal is identified as including a defective memory cell in one of the data column planes 210, the memory may be remapped so that the data that would have been stored in that column plane for that value of CS is instead stored in the GCR CP 214.

[0044] For example, in some embodiments, the memory 210 may include 16 data column planes 210(0) to 210(15). Each of those data column planes 210 includes 64 groups of bit lines activated by the value of the column select signal, and each group of bit lines includes 8 bit lines. Therefore, when the word line is turned on in response to the row address, and the column select signal is provided to each of the 16 column planes, then 8 bits are accessed from each of the 16 column planes, for a total of 128 bits. The column select signal is also provided to the additional column plane 212, but the column select signal may be a different value than the column select signal provided to the additional 8-bit data column plane 210. If a repair has been performed, the GCR CP 214 may also be accessed, and the value on the GCR LIO may be used, while ignoring the LIO of the column plane it is replacing. Therefore, the maximum number of bits that can be retrieved as part of an access pass is 128 bits from the data column plane 210 (8 bits replaced from the GCR CP 214 if a repair already exists) together with 8 additional bits from the extra CP 212.

[0045] The memory may operate in x4 mode, where fewer than the maximum number of bits are provided to an external device. The column address may indicate which of the column planes 210 (0) through (M) is used to store data accessed in x4 mode. For example, the CP select bit of the column address (e.g., bit 10 of the column address, C10) may select data from an even column plane or an odd column plane, or from the first half of the column plane or the second half of the column plane. Other schemes may be used in other example embodiments.

[0046] Figure 2 Mode registers not shown in Figure 1 210 (0) through (M) . The mode register 130 of FIG. 130 may be used to enable enhanced ECC on the device. If enhanced ECC is disabled, then the ECC data is limited to data in the additional column plane 212. If enhanced ECC is enabled, then the mode register may have settings that place the memory device in a one-pass x4 mode of operation and facilitate storage of some additional ECC data in two or more of the column planes 210 (0) through (M). The overall information received / sent to the external device is the same in both modes of operation. For example, a controller of the memory (e.g., Figure 1 150) may expect 64 bits of data for each access to the memory 200 in either mode, however, the operating mode may determine how the memory array is accessed, the power consumption of the access operation, the size of the pre-fetched information, the behavior of the ECC circuit 232, and which information is stored in which column planes 210(0) to (M).

[0047] In an example read command in the enhanced ECC mode of operation, the column, row, and bank addresses are received from the controller. The row decoder (e.g., Figure 1The row decoder 108 of the embodiment of the present invention opens the selected word line based on the row address. The column decoder generates a column select signal based on the column address. As part of a single access pass, a column select value having a first value is provided to a first portion of the column planes, and a column select signal having a second value may be provided to at least one column plane that is not in the first portion of the column planes. In addition, a third column select signal (which may or may not have the same value as the first or second column select signal) may be provided to an additional column plane 212. Which columns are in the first portion may be based on the CP select bit (e.g., C10) of the column address. The data column planes of the first portion provide the data bits of the codeword, and one of the data column planes not in the first portion or the additional column plane 212 provides the ECC parity bits. During the enhanced ECC mode, since only a portion of the column planes 210 (0) to (M) are accessed, only the data bits (and ECC bits) provided from the device are accessed. The ECC circuit 232 receives the data together with the parity bits and locates and / or corrects (several) errors in the codeword data. The (corrected) data is provided to the IO circuit 234, which provides the data to the DQ terminals.

[0048] This one-pass enhanced ECC mode architecture may provide performance improvements over a two-pass architecture that requires an additional access to retrieve some of the ECC data required to enable SECDED ECC operation. For example, there may be a delay time tCCD_L_WR that is part of the design specification of the memory. The time tCCD_L_WR represents the minimum amount of time that must elapse before a group of memory banks can be accessed again. The time tCCD_L_WR may be a long column-to-column (long column-to-column) or command (long column-to-command) delay cycle. During a write operation, the two-pass architecture may incur a delay of 2x tCCD_L_WR because each access pass requires a delay of tCCD_L_WR before the memory bank can be accessed again. The additional tCCD_L_WR is incurred because in order to generate parity bits based on all pre-fetched data in the two-pass architecture, half of the pre-fetched data bits that have not been written must still be pre-fetched (e.g., read) so that they can be added to the write bits received from the controller. The one-pass x4 mode of operation may eliminate the need for a read-modify-write since only the accessed data bits are prefetched.

[0049] In an example write command in enhanced ECC mode, column, row, and bank addresses are received from the controller along with codeword data. The codeword data is provided to the ECC circuit through the IO circuit, which generates ECC parity bits based on the codeword data and then writes the codeword data and parity to the column plane accessed in a manner similar to that described for read operations.

[0050] In enhanced ECC mode, each of the data column planes 210 (0) to (M) may store a mix of data and ECC parity bits, and additional ECC data is stored in the additional column plane 212. When the enhanced ECC mode is disabled, the ECC data may then be restricted to the additional column plane 212. In enhanced ECC mode, the ECC circuit 232 locates and corrects single errors and also has the ability to detect additional errors in the data. In non-enhanced ECC mode, the ECC circuit 232 may only correct one error in the data because the number of parity bits may not be sufficient to detect additional errors.

[0051] In addition, accesses in the enhanced ECC mode may consume less power than accesses in the non-enhanced ECC architecture. In the non-enhanced ECC architecture, all column planes may be activated, and data read from their sense amplifiers 220 are driven along the LIO to the ECC circuit 232, except for the sense amplifiers 222 and LIO associated with the additional column planes 212 (and the sense amplifiers 224 and LIO of the GCR 214 if a repair has been present). However, in the enhanced ECC architecture, only a selected portion (e.g., half) of the data column planes 210 (0) to (M) may be activated, and thus less than all of the data LIOs are driven by the corresponding sense amplifiers 220. Similarly, various switches, signal lines, etc. may not be used in each access in the enhanced ECC mode. Thus, less power is consumed in the enhanced ECC mode.

[0052] Figure 3 is a block diagram showing an example of a read operation of a memory according to some example embodiments of the present disclosure. Figure 3 A view of a memory array 300 is shown showing which portions of the memory array are set aside for representation of different types of information. Figure 3 The blocks shown in represent portions of a memory array, but do not necessarily represent the spatial layout of locations in the memory array where information is stored. In some embodiments, the memory array 300 may be Figure 1 The memory array 118 and / or Figure 2 Implementation of column planes 210 to 214 in an enhanced ECC mode of operation as described herein.

[0053] Figure 3 The example memory is described with respect to an example embodiment in which there are 16 data column planes, each of which provides 8 bits when activated by a column select signal, and additional column planes that also provide 8 bits when activated by their respective column select values. The example memory operates in x4 mode in which 64 data bits are accessed by the controller (e.g., Figure 1 The CP select bit C10 of the column address is used to determine which column planes provide data.

[0054] During an example read operation in which C10 is in a low logic state (e.g., C10=0), eight column planes are accessed in the first portion 301 of the memory array 300, each of which provides eight bits for a total of 64 data bits. A second column select signal is provided to a single column plane and / or an additional column plane 308 in the second portion 302 to retrieve a total of eight ECC parity bits. In some examples, the eight ECC parity bits may be stored exclusively in a single column plane or in the additional column plane 308. In other examples, half of the eight parity bits may be stored exclusively in a single column plane and the other half may be stored in the additional column plane 308. In this example, half of the bits retrieved from the additional column plane 308 used out of the eight ECC parity bits may be determined based on the C10 bit. The ECC circuit 310 (e.g., Figure 2 232) receives 64 data bits along with 8 parity bits and uses SECDED to provide corrected 64 data bits.

[0055] In another example read operation where C10 has an opposite value (eg, C10=1), 64 data bits may then be accessed from the second portion 302 and 8 ECC bits from the first portion 301 and / or from the additional column plane 308 .

[0056] In an example write operation, when only four ECC parity bits are stored in each data column plane and half are stored in the extra column plane 308, the extra ECC 4 parity bits in each data column plane may be protected. For example, the memory 300 may employ a read-modify-write (or RMW) strategy where all 8 parity bits in the extra column plane 308 and the data column plane are pre-fetched, and then four of those bits are located in each position (as needed) based on the newly written parity bits, and then all 8 parity bits are written back. This may protect the extra four bits (so they are not inadvertently changed by a direct write operation since no data is written to those cells) at the expense of additional latency (e.g., tCCD_L_WR required for an extra read as part of the RMW).

[0057] The blocks in the first portion 301 and the second portion 302 represent portions of those column planes that may be set aside for different storage, and do not necessarily represent the physical arrangement of where information is stored in the portions of the column planes or the spatial relationship of the column planes in each portion to each other. For example, the first portion 301 may represent even column planes while the second portion 302 represents odd column planes, and the columns set aside for storing ECC bits may be distributed throughout the data column planes. Figure 3In the example of , since 8 bits of ECC are required for every 64 bits of data, each of the first portion 301 and the second portion 302 may use 93.75% of its total memory space for data and 6.25% for ECC bits when the enhanced ECC mode is enabled. In other words, from the controller's perspective, only 93.75% of the memory array may be addressed because the remainder is set aside for ECC data that is expected to come with the data. In non-enhanced ECC mode, 100% of the array may be set aside for data, but then the number of ECC parity bits is diluted to 8 ECC parity bits per 128 data bits, which is insufficient for SECDED ECC calculations.

[0058] Table 1 is a summary of different operations in two different x4 modes according to some embodiments of the present disclosure.

[0059]

[0060] Table 1. Example comparison of enhanced ECC and normal ECC operating modes

[0061] In Table 1, the symbols d and p are used to represent data bits and parity bits, respectively. For example, the first row uses the symbol 64d+8p to represent that in enhanced ECC mode, 64 data bits and 8 parity bits are extracted. The mode register may also have a setting to disable enhanced ECC mode.

[0062] In the non-enhanced ECC mode, the ECC circuit 232 uses 128-bit data and 8 parity bits, while in the enhanced ECC mode, the ECC circuit 232 uses 64-bit data and 8-bit ECC parity. In the non-enhanced ECC mode, the ECC circuit 232 may implement the SEC scheme, while in the enhanced ECC mode, the SECDED scheme may be used. That is, since a higher ECC parity to data bit ratio is used in the enhanced ECC mode, more robust error protection may be provided.

[0063] The enhanced ECC mode may consume less power than the non-enhanced ECC mode. In the enhanced ECC mode, the CS signal may be provided to only the selected half of the column planes (based on C10). Therefore, only half of the column planes need to activate their switches, drive voltages along the LIO lines, etc. This can reduce the power consumption of a single access operation. For example, in the non-enhanced ECC mode, 17 different CS signals (16 data column planes and 1 additional column plane) and their associated LIO / GIO, etc. are activated, while in the enhanced ECC mode, 9 different CS signals and their associated LIO / GIO, etc. are activated.

[0064] Figure 4is a schematic diagram of a portion of a memory bank according to some embodiments of the present disclosure. In some embodiments, the memory bank 400 may include Figure 1 Memory 100, 200 of FIG. 20 and / or Figure 3 300. Memory bank 400 shows a simplified schematic diagram of a layout of a memory bank and example signals that may be used to activate various columns in a column plane as part of a second x4 operating mode (eg, a one-pass x4 operating mode).

[0065] Similar to Figure 3 , regarding the description of the example embodiments Figure 4 , where there are 16 data column planes, each data column plane includes 64 groups of bit lines (e.g., 64 values ​​of CS signals), each bit line providing 8 bits of data when activated by a corresponding CS signal. It should be understood that this is an example implementation of the present disclosure, and other arrangements (e.g., more or fewer CS groups per CP, more or fewer CPs per memory bank, etc.) may be used in other example embodiments.

[0066] Memory bank 400 is shown organized into sixteen column planes 412-448 (eg, Figure 2 210 and / or Figure 3 301 to 302), each column plane is associated with a DQ pad 410 to 440. Thus, a first DQ pad DQ3 410 is associated with column planes 412 to 418, a second DQ pad DQ2 420 is associated with column planes 422 to 428, a third DQ pad DQ1 430 is associated with column planes 432 to 438, and a fourth DQ pad DQ0 440 is associated with column planes 442 to 448. Figure 4 In the example x4 mode of 400, each of the four DQ pads DQ3 410, DQ2 420, DQ1 430, and DQ4 440 handles 16 data bits for a total of 64 data bits as part of an access operation. In addition to the four DQ pads 410, 420, 430, and 440, the memory bank 400 may be associated with an ECC terminal 450 that may be used to send / receive ECC parity data as part of an access operation. The ECC terminal 450 may be associated with an additional column plane 452 (e.g., Figure 1 Additional row planes 212 and / or Figure 3 The additional column plane 308 is associated with Figure 4 In a simplified view of FIG. 4 , a single word line WL and a global row decoder 402 driving the word line are shown. Similarly, for the bit lines, only the selected lines are shown, and each bit line represents a group of bit lines activated by a common CS signal in that CP. When activated, the bit line is coupled to the corresponding LIO line.

[0067] Memory banks 400 are organized such that the cells of the memory array are between two sense amplifier regions 404. The sense amplifier regions 404 may be elongated in the same direction as the word lines WL. Column planes 412 to 448 are separated by sub-word line (SWL) drivers 406. Each column plane is adjacent to another column plane and the SWL drivers 406. For example, column plane 412 is adjacent to SWL drivers 406 on one side and to column plane 414 on the other side. Column plane 414 is adjacent to column plane 412 on a first side and to a second SWL driver 406 on the opposite side. On the opposite side of that SWL driver 406 is another column plane 416, and so on.

[0068] Thus, each data terminal is associated with four column planes, namely two pairs of column planes that are adjacent to each other and separated from another pair by a SWL driver. Each pair is associated with a different value of the column plane select bit C10. For example, the first DQ pad 410 is associated with column planes 412 and 414, both of which are activated by C10 at a high logic level, and is associated with column planes 416 and 418, both of which are activated by C10 at a low logic level. Therefore, column planes 412, 414, 422, 424, 432, 434, 442, and 444 all contain data accessed when C10=1, and column planes 416, 418, 426, 428, 436, 438, 446, and 448 all contain data accessed when C10=0. No matter which group of column planes C10 selects, one or more column planes of the other group can be used to store ECC parity bits.

[0069] Figure 4 An example access operation in enhanced ECC mode is shown. The memory device receives a column address that includes C10=0 and has a value decoded to the first column select signal CS0. Therefore, CS0 is provided by the column decoder to column planes 416, 418, 426, 428, 436, 438, 446, and 448, and the bit lines associated with CS0 in each of those column planes each provide 8 bits of data. The column decoder also provides CS0 to an additional column plane 452 and / or generates an additional CS signal to provide it to one of the column planes not selected by the value of C10 to retrieve ECC parity data. In this example embodiment, a value CS56 is provided to column plane 444. Therefore, column plane 444 provides 8 bits of ECC parity. Thus, from a single access pass, 64 bits of data (8 bits each from column planes 416, 418, 426, 428, 436, 438, 446, and 448) and 8 bits of parity (from column plane 444) are accessed. Arrows are used to show which CS signals and which column planes are accessed as part of a single access pass.

[0070] In other words, the column decoder (e.g. Figure 1 110) may activate the digit lines and couple them to the LIOs for column planes 416, 418, 426, 428, 436, 438, 446, and 448. This may represent all LIOs available for the column planes activated by C10=0 (e.g., 8 LIOs per column plane). However, in the group of column planes associated with C10=1, the column decoder may activate less than all LIOs because only CS56 in column plane 444 is coupled to the LIOs. The remaining LIOs associated with the column planes activated by C10=1 are not used in this access operation.

[0071] Although Figure 4 , but a similar access may occur as part of a second access operation, where a column address is received that includes C10=1 but the same decoded value of CS. In the example, the column decoder provides CS0 to column planes 412, 414, 422, 424, 432, 434, 442, and 444 and additional column plane 450, while providing a CS56 value to column plane 448. Note that the same 8 bits may be provided from additional column plane 452, but the value of C10 controls which portion of those 8 bits are provided.

[0072] Based on the operating mode of the memory, the controller may have different ranges of addressable values. In this example, the controller may generate column addresses associated with CS values ​​in the range of CS0 to CS55. However, CS55 to CS63 may represent 'unaddressable' space because the controller cannot directly access these columns (they are set aside for parity checking).

[0073] Figure 5 is a flow chart of a method for performing enhanced ECC operations according to some embodiments of the present disclosure. In some embodiments, method 500 may be implemented by one or more of the devices or systems described herein. For example, method 500 may be implemented at least in part by Figure 1 Memory 100, Figure 2 The memory device 200, Figure 3 The memory array 300 and / or Figure 4 The memory storage body 400 is implemented.

[0074] The method 500 may include receiving a column address as part of an access operation at 510. In some examples, the method 500 may also include receiving a row and bank address and an access command as part of an access operation. For example, the access command may be received along a C / A terminal (e.g., Figure 1 C / A terminal) to receive addresses and commands.

[0075] The method 500 may further include, at 520, accessing data bits from a column in a first portion of a plurality of data column planes based on a column address as part of an access operation. In some instances, the method 500 may include selecting a first portion of a plurality of data column planes based on the column address. In some instances, the method 500 may include selecting a first half of the column planes as the first portion, or selecting a second half of the column planes as the first portion. The column address may include a column plane select bit (e.g., C10) that specifies which column planes are in the first portion or are not in the first portion. For example, the method 500 may include selecting the first half when the column plane select bit is in a first state, and selecting the second half when the column plane select bit is in a second state. In some instances, the method 500 may include selecting a first half of the column planes based on the column address. Figure 1 110) generates a column selection signal associated with an access operation.

[0076] The method 500 may further include, at 530, accessing a parity bit from one of a column in a column plane that is not in a first portion of the plurality of data column planes or a column in an additional column plane based on the column address as part of the access operation. For example, the method 500 may include accessing the parity bit from a column in a column plane that is not in the first portion of the plurality of data column planes in response to the column address having a first value, and accessing the parity bit from a column in an additional column plane in response to the column address having a second value. In some examples, the method 500 may further include correcting errors in the data bits based on the parity bit with an error correction code (ECC) circuit. For example, the method 500 may include performing single error correction double error detection (SECDED) with an error correction code (ECC) circuit using the parity bit.

[0077] In some examples, method 500 may include performing a second access operation, such as: receiving a second column address as part of the second access operation; accessing second data bits from a second portion of the plurality of data column planes that does not overlap with the first portion of the plurality of data column planes based on the second column address as part of the second access operation; and accessing parity bits from one of the columns in the first portion of the plurality of data column planes or the columns in the additional column plane based on the second column address as part of the access operation.

[0078] Figure 6 6 is a flow chart of a method for writing an error correction code (ECC) mode to a mode register of a memory device according to some embodiments of the present disclosure. In some embodiments, method 600 may be a method of operating a memory device. For example, method 600 may be performed by a controller (e.g., Figure 1 The controller 150) in its operating memory (eg Figure 1 The semiconductor device 100, Figure 2 The memory device 200, Figure 3 The memory array 300 and / or Figure 4 400).

[0079] The method 600 includes, at 610, writing a value to a mode register of a memory device to set an error correction code (ECC) mode of the memory device to one of a first mode or a second mode. For example, the controller may: perform an MRW operation to write a value to one or more registers that control the ECC mode in which the memory is in. In some instances, both the first mode and the second mode are x4 modes of the memory device. In some instances, the method 600 further includes writing 64-bit data to the memory array in the first mode and the second mode. For example, the controller may provide the 64-bit data in four 16-bit bursts. In some instances, the first mode represents a single error detection ECC mode, and the second mode represents a single error correction double error detection (SECDED) ECC mode.

[0080] The method 600 may further include, at 620, accessing a first percentage of addresses of a memory array of the memory device to store data when the ECC is in the first mode.

[0081] The method 600 may further include, at 630, accessing a second percentage of addresses of a memory array of the memory device to store data when the ECC is in the second mode, wherein the first percentage is greater than the second percentage. In some examples, the method 600 further includes reserving a third percentage of addresses for storing ECC parity data. The third percentage may be based on a difference between the first percentage and the second percentage. In some examples, the method 600 further includes accessing the memory array once in both the first mode and the second mode to write data.

[0082] The method 600 may include generating a column address associated with an addressable region of the memory array based on the first or second mode. Thus, when the memory is in the first mode, the controller may generate a column address associated with a first range of CS values ​​(e.g., CS0 to CS63), and when the memory is in the second mode, the controller may generate a column address associated with a second range of CS values ​​(e.g., CS0 to CS54).

[0083] Of course, it should be understood that any of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and / or processes, or separated and / or performed in separate devices or device portions according to the present systems, devices, and methods.

[0084] Finally, the above discussion is intended to be merely illustrative of the present system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, although the present system has been described in particular detail with reference to exemplary embodiments, it should also be appreciated that numerous modifications and alternative embodiments may be devised by one of ordinary skill in the art without departing from the broader and intended spirit and scope of the present system as set forth in the appended claims. Therefore, the specification and drawings should be viewed in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. A device comprising: A first data column plane including a first bit line; a second data column plane including second bit lines; an additional column plane including a third bit line; a column decoder configured to activate the first bit line and activate one of the second bit line or the third bit line as part of an access operation; and An error correction code (ECC) circuit is configured to access data bits along the first bit line and parity bits along the activated one of the second bit line or the third bit line as part of the access operation.

2. The apparatus of claim 1 , wherein as part of the second access operation: The column decoder is configured to activate a fourth bit line of the second data column plane and activate one of a fifth bit line of the first data column plane or a sixth bit line of the additional column plane; and The ECC circuit is configured to access a second data bit along the fourth bit line and a parity bit along the activated one of the fifth bit line or the sixth bit line.

3. The apparatus of claim 2 , wherein the column decoder is configured to activate the first bit line based on a column select bit of a first column address having a first value specifying that the data bit is stored at the first data column plane during the access operation, and to activate the fourth bit line based on the column select bit of a second column address having a second value specifying that the second data bit is stored at the first data column plane during the second access operation.

4. The apparatus of claim 1, wherein the column decoder is configured to selectively activate said one of the second bit line or the third bit line based on a received column address.

5. The apparatus of claim 1, wherein the first data column plane has the same number of memory cells as the additional column plane.

6. The apparatus of claim 1 , further comprising an input / output circuit configured to receive the data bits from the ECC circuit when the access operation is a read operation and configured to provide the data bits to the ECC circuit when the access operation is a write operation.

7. The apparatus of claim 1, wherein the ECC circuit is configured to locate and correct errors in the data bits based on the parity bits when the access operation is a read operation.

8. The apparatus of claim 1 , wherein in response to a column address received as part of the access operation, the column decoder is configured to provide a column select signal having a first value to the first data column plane and one of providing a second column select signal having a second value to the second data column plane or providing a third column select signal having a first value to the additional column plane.

9. A device comprising: A memory bank comprising: a first plurality of column planes; a second plurality of column planes; and Additional row planes; and a column decoder configured to select the first plurality of column planes or the second plurality of column planes based on a column address received as part of an access operation, wherein data bits are accessed in the selected one of the first plurality of column planes or the second plurality of column planes as part of the access operation, and parity bits are accessed in one of the additional column planes or an unselected one of the first plurality of column planes or the second plurality of column planes based on the column address.

10. The apparatus of claim 9, further comprising an error correction code (ECC) circuit configured to locate and correct errors in the data bits based on the parity bits.

11. The apparatus of claim 9, wherein the ECC circuit is configured to perform single error correction double error detection (SECDED) based on the parity bits and the data bits.

12. The apparatus of claim 9, wherein the column decoder is configured to select the one of the first plurality of column planes or the second plurality of column planes based on a column plane select bit of the column address.

13. The apparatus of claim 11, wherein the column decoder is configured to decode the column address to determine whether the parity bits are stored at the additional column plane or at the unselected one of the first plurality of column planes or the second plurality of column planes.

14. The apparatus of claim 8, wherein the apparatus is a memory device operating in x4 mode.

15. A method comprising: receiving a column address as part of an access operation; accessing data bits from a column in a first portion of a plurality of data column planes based on the column address as part of the access operation; and A parity bit is accessed from one of a column in a column plane that is not in the first portion of the plurality of data column planes or a column of an additional column plane based on the column address as part of the access operation.

16. The method of claim 15, further comprising correcting errors in the data bits based on the parity bits with an error correction code (ECC) circuit.

17. The method of claim 15, further comprising performing single error correction double error detection (SECDED) with an error correction code (ECC) circuit using the parity bits.

18. The method of claim 15, further comprising accessing the parity bits from the columns in the column plane that are not in the first portion of the plurality of data column planes in response to the column address having a first value.

19. The method of claim 18, further comprising accessing the parity bits from the columns in the additional column plane in response to the column address having a second value.

20. The method of claim 19, further comprising: receiving a second column address as part of a second access operation; accessing second data bits from a second portion of the plurality of data column planes that does not overlap with the first portion of the plurality of data column planes based on the second column address as part of the second access operation; and Parity bits are accessed from one of the columns in the first portion of the plurality of data column planes or the columns of the additional column plane based on the second column address as part of the access operation.

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