Single-bare-chip reinforced galvanic isolation device

Abstract

A microelectronic device (100) comprises an isolation device (101). The isolation device (101) comprises a lower isolation element (119), an upper isolation element (148) and an inorganic dielectric level line region (152) located between the lower isolation element (119) and the upper isolation element (148). The inorganic dielectric level line region (152) includes an upper etch stop layer (136) and a lower etch stop layer (129) between the upper isolation element (148) and the lower isolation element (119). The upper etch stop layer (136) provides an endpoint signal during a flat line region etch process (161) that provides feedback about the amount of inorganic dielectric level line regions (152) etched. The lower etch stop layer (129) provides an etch stop function that ensures a complete flat line region etch (161) and protects an underlying metal bond pad (122). The inorganic dielectric level line region (152) contains alternating high stress silicon dioxide layers (141) and low stress silicon dioxide layers (132), which provide a means to strengthen the inorganic dielectric level line region (152).

Description

Technical Field

[0001] The present specification relates to the field of microelectronic devices. More particularly, but not exclusively, the present specification relates to galvanic isolation devices in microelectronic devices. Background Art

[0002] Galvanic isolation is the principle of isolating functional sections of an electrical system to prevent the flow of current, while still enabling the exchange of energy or information between the sections by other means such as capacitance, induction, electromagnetic waves, optics, acoustics, or mechanical means. Galvanic isolation can be used in situations where two or more circuits are communicating, but the ground or reference nodes of the circuits may be at different potentials. It is an effective method of breaking ground loops by preventing unwanted current from flowing between two units sharing a reference conductor. Galvanic isolation is also used for safety purposes as a means of preventing accidental current from reaching ground through the human body.

[0003] Isolators are devices designed to minimize DC current and unwanted transient current between two systems or circuits while allowing data and power transfer between the two systems or circuits. In most applications, isolators act as a barrier to high voltages in addition to allowing the system to operate normally. In the case of capacitive elements used as isolators, dielectric breakdown is a critical issue, especially in high voltage applications.

[0004] As integrated circuit design and semiconductor manufacturing continue to advance, improvements in microelectronic devices, including galvanic isolators, are also advancing in parallel. Summary of the invention

[0005] A simplified summary is presented below to provide a basic understanding of one or more aspects of this patent specification. This summary is not an extensive review of the specification, nor does it identify the key or important elements of the specification, nor does it delineate the scope of the specification. In fact, the main purpose of the summary is to present some concepts of the specification in a simplified form as a prelude to a more detailed description presented later.

[0006] An example of a microelectronic device including a current isolation device (hereinafter referred to as an isolation device) is described. The isolation device includes a lower isolation element (hereinafter referred to as a lower metal coil), an upper isolation element (hereinafter referred to as an upper metal coil) and a reinforced current isolation device inorganic dielectric stack (hereinafter referred to as a flat line area between the lower metal coil and the upper metal coil). The flat line area contains an upper etch stop layer and a lower etch stop layer between the upper metal coil and the lower metal coil located in the flat line area. The upper etch stop layer provides an electrical signal during the flat line area etching process, and the electrical signal provides feedback on the amount of the flat line area that has been etched. The lower etch stop layer provides an etch stop function to provide complete flat line area etching and protection of the underlying metal bonding pad. The combination of the upper bonding pad and the lower bonding pad is advantageous because it provides a means for forming an extremely thick (greater than 10 microns) flat line area between the upper metal coil and the lower metal coil. The flat line area also contains alternating high stress silicon dioxide layers and low stress silicon dioxide layers. The alternating high stress silicon dioxide layers and low stress silicon dioxide layers provide a means of strengthening the plateau region which improves the crack resistance of the plateau region. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Examples of the present specification are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like reference numerals indicate similar elements. In addition, different references to "an" or "one" example in the present specification are not necessarily to the same example, and such references may mean at least one. In addition, when a particular feature, structure, or characteristic is described in conjunction with an example, it should be understood that it is within the purview of a person skilled in the art to implement such feature, structure, or characteristic in conjunction with other examples, whether or not explicitly described.

[0008] The accompanying drawings are incorporated into and form a part of this specification to illustrate one or more examples of the specification. Various advantages and features of the present specification are derived from the following detailed description taken in conjunction with the appended claims and with reference to the accompanying drawings, in which:

[0009] FIG. 1A to FIG. 1T 2 is a cross-section of an example microelectronic device having an isolation device depicted at successive stages of an example formation method.

[0010] Figure 2 A perspective view of a microelectronic device including an isolation device is shown. DETAILED DESCRIPTION

[0011] This specification is described with reference to the accompanying drawings. The drawings are not drawn to scale and are provided only to illustrate this specification. Several aspects of this specification are described below with reference to examples for illustration. Numerous specific details, relationships, and methods are set forth to provide an understanding of this specification. This specification is not limited by the described order of actions or events, as some actions may occur in different orders and / or simultaneously with other actions or events. In addition, not all described actions or events are required to implement the methods in this specification.

[0012] The following co-pending patent applications have related subject matter and are hereby incorporated by reference: U.S. Patent Application No. 17 / 957,847 (Texas Instruments Docket No. T102472US01 to West et al., entitled "GALVANIC ISOLATION DEVICE") and U.S. Patent Application No. 17 / 957,875 (Texas Instruments Docket No. T101074US01 to West et al., entitled "FIELD SUPPRESSION FEATURE FOR GALVANIC ISOLATION DEVICE"), both of which were filed concurrently with the present application. Reference to such patent applications in this section is not an admission that such patent applications are prior art with respect to the present invention.

[0013] The following co-pending patent applications have related subject matter and are hereby incorporated by reference: U.S. Provisional Patent Application No. 63 / 377,877 (Texas Instruments Docket No. T101057US01), U.S. Provisional Patent Application No. 63 / 411,934 (Texas Instruments Docket No. T92887US01), U.S. Provisional Patent Application No. 63 / 411,942 (Texas Instruments Docket No. T92904US01), U.S. Provisional Patent Application No. 63 / 411,952 (Texas Instruments Docket No. T100209US01), and U.S. Provisional Patent Application No. 63 / 411,961 (Texas Instruments Docket No. T102233US01), all of which were filed concurrently with the present application. Reference to such patent applications in this section is not an admission that such patent applications are prior art with respect to the present invention.

[0014] Additionally, although some of the examples described herein are shown in two-dimensional views of various regions having depth and width, such regions are merely illustrations of a portion of a device that is actually a three-dimensional structure. Therefore, when manufactured on an actual device, such regions will have three dimensions, including length, width, and depth. Furthermore, although the present invention is described by way of examples directed to active devices, such descriptions do not limit the scope or applicability of the present invention. The active devices of the present invention are limited to the physical structures described. Such structures are included to demonstrate the utility and application of the present invention to the presently preferred examples.

[0015] The example microelectronic devices described below may include or be formed of semiconductor materials such as silicon (Si), silicon carbide (SiC), silicon germanium (SiGe), gallium arsenide (GaAs), or organic semiconductor materials. The semiconductor material may be embodied as a semiconductor wafer. The microelectronic device includes one or more current isolation devices. The microelectronic device may also include one or more semiconductor components, such as metal oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs) gate drivers, input / output and control circuit systems, and microprocessors, microcontrollers, and / or microelectromechanical components or systems (MEMS). The microelectronic device may be present as a single chip device or may be contained in a multi-chip module (MCM). The semiconductor chip may further include inorganic and / or organic materials that are not semiconductors, for example, insulators such as inorganic dielectric materials or polymers or conductors such as metals.

[0016] For the purposes of this specification, the term "high voltage" refers to an operating potential greater than 450 volts, and "low voltage" refers to an operating potential less than 100 volts. For example, the high voltage portion of the isolation device may operate at 450 volts to 1200 volts, while the low voltage portion of the isolation device may operate at 1.5 volts to 30 volts.

[0017] It should be noted that terms such as top, bottom, front, back, over, above, below, and below may be used in this specification. These terms do not limit the position or orientation of structures or elements, but provide spatial relationships between structures or elements. Similarly, words such as "inwardly" and "outwardly" will refer to directions toward and away from, respectively, the geometric center of a device or area and designated parts thereof.

[0018] For purposes of this specification, the term "lateral" refers to a direction parallel to a plane of an instant top surface of a microelectronic device, and the term "vertical" refers to a direction perpendicular to a plane of an instant top surface of a microelectronic device.

[0019] For the purposes of this specification, the term “conductive” should be interpreted as “electrically conductive.” The term “conductive” refers to materials and structures that are capable of supporting a steady electrical current, such as a direct current (DC).

[0020] For the purposes of this specification, the "dielectric constant" of a material refers to the ratio of the (absolute) dielectric constant of the material to the dielectric constant of a vacuum at frequencies below 1 Hertz (Hz). The dielectric constant of a vacuum has a value of approximately 8.85×10 -12 The value of farad / meter (F / m).

[0021] For the purposes of this specification, unless otherwise indicated, the term high stress silicon dioxide refers to silicon dioxide films having a stress between -150 MPa and -80 MPa, and the term low stress silicon dioxide refers to silicon dioxide films having a stress between -60 MPa and -10 MPa. In addition, negative stress means compressive stress, and positive stress means tensile stress.

[0022] Figure 1A 1 is a cross section of a portion of an example microelectronic device 100 isolation device 101 after forming a first level interconnect 106. The microelectronic device 100 may be implemented as part of a multi-chip array to provide galvanic isolation between high voltage components and low voltage components. The isolation device 101 of this example is a transformer, but may include capacitors, magnetic isolators, optical isolators, thermal isolators, or other elements that require galvanic isolation between high voltage components and low voltage components. The microelectronic device 100 is formed on a substrate 102, which may be part of a semiconductor wafer and may contain additional microelectronic devices. The substrate 102 includes a semiconductor material. By way of example, the semiconductor material may include crystalline silicon, or may include another semiconductor material such as silicon germanium, silicon carbide, gallium nitride, or gallium arsenide.

[0023] A pre-metal dielectric (PMD) layer 104 is formed on the substrate 102. The PMD layer 104 includes one or more dielectric layers of silicon dioxide, phosphosilicate glass (PSG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), organosilicate glass (OSG), low-k dielectric materials, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or other dielectric materials. The PMD layer 104 may be formed by one or more dielectric deposition processes such as a low pressure chemical vapor deposition (LPCVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, a high aspect ratio process (HARP) using ozone and tetraethylorthosilicate (TEOS), a high density plasma deposition (HDP), or an atmospheric pressure chemical vapor deposition (APCVD) process.

[0024] The contact 105 of the first level interconnect 106 is formed through the PMD layer 104 for electrical connection with the substrate 102. The contact 105 is conductive and may include tungsten on a titanium adhesion layer and a titanium nitride liner. The contact 105 may be formed by etching a contact hole through the PMD layer 104 and forming a titanium adhesion layer by a physical vapor deposition (PVD) process. The titanium nitride liner may be formed on the titanium adhesion layer by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. Tungsten may be formed on the titanium nitride liner by a metal organic chemical vapor deposition (MOCVD) process using tungsten hexafluoride reduced by silane and hydrogen. Tungsten, titanium nitride and titanium on the top surface of the PMD layer 104 outside the contact 105 may be removed by a tungsten etch back process, a tungsten chemical mechanical polishing (CMP) process or both.

[0025] For example, the metallization of the isolation device 101 is described for an etched aluminum-based interconnection system. The isolation device 101 can also be formed using a copper-based interconnection system. The first-level interconnect 106 is formed on the PMD layer 104, thereby making an electrical connection with the contact 105. The first-level interconnect 106 is conductive. The first-level interconnect 106 may have an etched aluminum structure, and may include an adhesion layer (not shown) of titanium nitride or titanium tungsten on the PMD layer 104, an aluminum layer (not specifically shown) with several atomic percentages of silicon, titanium or copper on the adhesion layer, and an anti-reflective layer (not specifically shown) of titanium nitride on the aluminum layer. An etching mask (not specifically shown) is formed, followed by a reactive ion etching (RIE) process to etch the anti-reflective layer, aluminum layer and adhesion layer exposed by the etching mask, and then the etching mask is removed to form the first-level interconnect 106.

[0026] refer to Figures 1B to 1D, forming a lower dielectric stack 123, which may include a plurality of dielectric layers and a second level interconnect 113 layer. The formation of the lower dielectric stack 123 begins after forming the first level interconnect 106, wherein a first interlayer dielectric layer (ILD) 107 is formed on the first level interconnect 106. The first ILD layer 107 may include a multi-layer silicon dioxide-based dielectric stack. The multi-layer silicon dioxide-based dielectric stack is formed by depositing a first gap-filling silicon dioxide layer 108 between 400nm and 800nm ​​on the first level interconnect 106 and the exposed PMD layer 104. A first high stress silicon dioxide layer 109 having a thickness between 1000 nm and 1500 nm is formed on the first gap-fill silicon dioxide layer 108, which is planarized by a chemical mechanical planarization (CMP) step (not specifically shown) to leave a stack of between 600 nm and 800 nm of the first gap-fill silicon dioxide layer 108 and the first high stress silicon dioxide layer 109 above the first level interconnect 106. After the CMP step (not specifically shown), a first low stress silicon dioxide layer 110 having a thickness between 2000 and 2500 nm is deposited on the CMP planarized first high stress silicon dioxide layer 109 by a PECVD or CVD process. A second high stress silicon dioxide layer 111 having a thickness between 200 nm and 500 nm is then deposited on the first low stress silicon dioxide layer 110 to complete the first ILD layer 107.

[0027] After forming the first ILD layer 107, a first level via 112 is formed in the first ILD layer 107 to make an electrical connection with the first level interconnect 106. The first level via 112 may be formed by etching a through hole through the first ILD layer 107 and forming a titanium adhesion layer by a physical vapor deposition (PVD) process. A titanium nitride liner may be formed on the titanium adhesion layer by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. Tungsten may be formed on the titanium nitride liner by a metal organic chemical vapor deposition (MOCVD) process using tungsten hexafluoride reduced by silane and hydrogen. Tungsten, titanium nitride, and titanium on the top surface of the first level via 112 outside the through hole may be removed by a tungsten etch back process, a tungsten chemical mechanical polishing (CMP) process, or both.

[0028] refer to Figure 1C, a second-level interconnect 113 is formed on the first ILD layer 107, thereby making electrical contact with the first-level via 112. The second-level interconnect 113 is conductive. The second-level interconnect 113 may have an etched aluminum structure, and may include an adhesion layer (not specifically shown) of titanium nitride or titanium tungsten on the first ILD layer 107, an aluminum layer (not specifically shown) having several atomic percentages of silicon, titanium or copper on the adhesion layer, and an anti-reflective layer (not specifically shown) of titanium nitride on the aluminum layer. A second interconnect etch mask 114 is formed, followed by a reactive ion etching (RIE) process to etch the anti-reflective layer, the aluminum layer, and the adhesion layer exposed by the etch mask, and then the etch mask is removed to form the second-level interconnect 113. In this example, the lower metal coil 119 of the isolation device 101 may be formed in the second-level interconnect 113, but may be formed at other levels. A ground ring 120 (at Figure 1C The grounding second level interconnect filler metal 121 (outside the plane of the cross section of the grounding) is also formed in the second level interconnect 113. Figure 1C A lower bonding pad 122 may also be formed in the second-level interconnect 113.

[0029] exist Figure 1D to Figure 1H In the process, a series of dielectric layers are deposited, the dielectric layers being Figure 1C The lower metal coil 119 shown in Fig. 1I The upper metal coils 148 shown in FIG. 1 form a flat line region 152 of the isolation device 101. Figure 1D , a silicon nitride / silicon oxynitride double layer 124 is formed on the second level interconnect 113. The silicon nitride / silicon oxynitride double layer 124 may include a silicon nitride layer and a silicon nitride layer. The thickness of the silicon nitride layer is between 100nm and 600nm and the stress is -1GPa to -100Mpa. The silicon oxynitride layer is between 300nm and 1000nm and the stress is between -150MPa and 0MPa. A second gap-filling silicon dioxide layer 125 (HDP oxide in this example) is formed on the silicon nitride / silicon oxynitride double layer 124. The second gap-filling silicon dioxide layer 125 is deposited to have a thickness between 1000nm and 1800nm.

[0030] refer to Figure 1E , a second low stress silicon dioxide layer 126 is formed on the second gap-filling silicon dioxide layer 125. The second low stress silicon dioxide layer 126 is deposited to have a thickness between 2000 nm and 3000 nm. After the second low stress silicon dioxide layer 126 is deposited, a CMP process 127 is used to planarize the second low stress silicon dioxide layer 126.

[0031] refer to Figure 1F , depositing an intermediate dielectric stack 128 including a plurality of dielectric films. To form the intermediate dielectric stack 128, a lower etch stop layer (herein referred to as a first silicon oxynitride etch stop layer 129) is deposited on the second low stress silicon dioxide layer 126. The first silicon oxynitride etch stop layer 129 is deposited by a CVD or PECVD process, and has a thickness between 500nm and 1500nm and a stress between -120MPa and 0MPa. A third low stress silicon dioxide layer 130 is deposited on the first silicon oxynitride etch stop layer 129. The third low stress silicon dioxide layer 130 is deposited by a CVD or PECVD process and has a thickness of 2000nm to 4000nm. A third high stress silicon dioxide layer 131 is deposited on the third low stress silicon dioxide layer 130. The third high stress silicon dioxide layer 131 is deposited by a CVD or PECVD process, and has a thickness of 100nm to 400nm. A fourth low stress silicon dioxide layer 132 is deposited on the third high stress silicon dioxide layer 131. The fourth low stress silicon dioxide layer 132 is deposited by CVD or PECVD process and has a thickness of 2000nm to 4000nm. A fourth high stress silicon dioxide layer 133 is deposited on the fourth low stress silicon dioxide layer 132. The fourth high stress silicon dioxide layer 133 is deposited by CVD or PECVD process and has a thickness of 100nm to 400nm. A fifth low stress silicon dioxide layer 134 is deposited on the fourth high stress silicon dioxide layer 133. The fifth low stress silicon dioxide layer 134 is deposited by CVD or PECVD process and has a thickness of 2000nm to 4000nm. A fifth high stress silicon dioxide layer 135 is deposited on the fifth low stress silicon dioxide layer 134. The fifth high stress silicon dioxide layer 135 is deposited by CVD or PECVD process and has a thickness of 100nm to 400nm. An upper etch stop layer (referred to herein as the second silicon oxynitride etch stop layer 136) is deposited on the fifth high stress silicon dioxide layer 135. The second silicon oxynitride etch stop layer 136 is deposited by CVD or PECVD process and has a thickness between 100 nm and 400 nm and a stress between -120 MPa and 0 MPa.

[0032] refer to Figure 1G, patterning and exposing the upper dielectric alignment lithography layer 137 to provide an upper dielectric alignment lithography opening 138 in the etch mask, thereby producing an alignment mark (not specifically shown) to allow the top metal interconnect 145 of the example transformer to be aligned with the second level interconnect 113. Reactive ion etching is used to remove the second silicon oxynitride etch stop layer 136 and the fifth high stress silicon dioxide layer 135 in the opening area. Portions of the fifth low stress silicon dioxide layer 134 in the upper dielectric alignment lithography opening 138 may also be removed by an RIE process. It is advantageous to provide an alignment mark near the top of the flat line area to facilitate acceptable alignment of the upper metal coil 148 with the lower metal coil 119.

[0033] refer to Figure 1H , a series of dielectric depositions form an upper dielectric stack 139. The formation of the upper dielectric stack 139 begins with forming a sixth low stress silicon dioxide layer 140 on the second silicon oxynitride etch stop layer 136 and on the fifth low stress silicon dioxide layer 134 in the upper dielectric alignment lithography opening 138. The sixth low stress silicon dioxide layer 140 is deposited by a CVD or PECVD process and has a thickness of 2000nm to 3000nm. After forming the sixth low stress silicon dioxide layer 140, a sixth high stress silicon dioxide layer 141 is formed on the sixth low stress silicon dioxide layer 140. The sixth high stress silicon dioxide layer 141 is formed by a CVD or PECVD process and has a thickness of 100nm to 400nm. After forming the sixth high stress silicon dioxide layer 141, a seventh low stress silicon dioxide layer 142 is formed on the sixth high stress silicon dioxide layer 141. The seventh low stress silicon dioxide layer 142 is deposited by a CVD or PECVD process and has a thickness of 2000nm to 4000nm. After forming the seventh low stress silicon dioxide layer 142, an upper dielectric stack silicon oxynitride 143 is formed on the seventh low stress silicon dioxide layer 142. The upper dielectric stack silicon oxynitride 143 may be formed by a PECVD process using, for example, a combination of BTBAS and TEOS or a combination of dichlorosilane and nitrous oxide. The upper dielectric stack silicon oxynitride 143 may have a thickness between 100nm and 400nm and a stress between -120MPa and 0MPa. After forming the upper dielectric stack silicon oxynitride 143, an upper dielectric stack silicon nitride 144 is formed on the upper dielectric stack silicon oxynitride 143. The upper dielectric stack silicon nitride 144 is deposited by a CVD or PECVD process and has a thickness of 200nm to 1200nm and a stress between -1GPa and -100MPA. The upper metal stack must contain at least one low stress silicon dioxide layer, at least one high stress silicon dioxide layer, at least one silicon oxynitride layer, and at least one silicon nitride layer.

[0034] refer to Fig. 1I, a top metal interconnect 145 is formed on the upper dielectric stack silicon nitride 144. The top metal interconnect 145 may have an etched aluminum structure and may include an adhesion layer (not specifically shown) of titanium nitride or titanium tungsten, the upper dielectric stack silicon nitride 144, an aluminum layer (not specifically shown) having several atomic percentages of silicon, titanium or copper on the adhesion layer, and an anti-reflective layer (not specifically shown) of titanium nitride on the aluminum layer. A top metal interconnect photolithography mask 146 is formed, followed by a reactive ion etching (RIE) process to etch the anti-reflective layer, aluminum layer and adhesion layer exposed by the etching mask. The RIE process leaves a recess 147 in the underlying upper dielectric stack silicon nitride 144. Figure 1H The cross section of shows the situation before removing the top metal interconnect photolithography mask 146. The RIE used to etch the top metal interconnect can remove up to 200 nm of the underlying upper dielectric stack silicon nitride 144 in the areas exposed to the RIE. Figure 1H Features of the top metal interconnect 145 shown in include an upper metal coil 148 and an upper bonding pad 149 .

[0035] refer to Figure 1J , patterning and exposing the photoresist layer to leave a SOR lithography mask 150 (thickness greater than 5 um) covering the upper bonding pad 149 and the upper metal coil 148 and a SOR lithography mask opening 151 that allows removal of a portion of the upper dielectric stack silicon oxynitride 143, the upper dielectric stack silicon nitride 144 and the seventh low stress silicon dioxide layer 142 above the lower bonding pad 122.

[0036] refer to Figure 1K , showing a cross-section after a first lower bonding pad opening etching step (not specifically shown) which removes the upper dielectric stack silicon nitride 144, the upper dielectric stack silicon oxynitride 143 and the seventh low stress silicon dioxide layer 142 by etching away 153 of the seventh low stress silicon dioxide layer between one and two microns in the SOR lithography mask opening 151 region.

[0037] refer to Figure 1L, a protective coating (PO) inorganic dielectric stack 154 is formed on the top metal interconnect 145, the exposed upper dielectric stack silicon nitride 144, and the exposed seventh low stress silicon dioxide layer 142. The PO inorganic dielectric stack 154 may include a PO silicon dioxide layer 155 (in this example, HDP oxide) formed on the top metal interconnect 145, the upper dielectric stack silicon nitride 144, the upper dielectric stack silicon oxynitride 143, and the seventh low stress silicon dioxide layer 142. The thickness of the PO silicon dioxide layer 155 is between 1000nm and 1500nm, and the stress is between -120MPa and -90MPa. After the PO silicon dioxide layer 155 is formed, a PO high stress silicon dioxide layer 156 is formed on the PO silicon dioxide layer 155. The PO high stress silicon dioxide layer 156 is formed by a CVD or PECVD process, and has a thickness of 100nm to 400nm and a stress between -150MPa and -80MPa. After forming the PO high stress silicon dioxide layer 156, a PO silicon oxynitride layer 157 is formed on the PO high stress silicon dioxide layer 156. The PO silicon oxynitride layer 157 is deposited using PECVD deposition, and has a thickness of 600nm to 2400nm and a stress between -120MPa and 0MPa. The PO silicon dioxide layer 155, the PO high stress silicon dioxide layer 156, and the PO silicon oxynitride layer 157 form a PO inorganic dielectric stack 154.

[0038] refer to Figure 1M , the PO inorganic dielectric stack 154 in the area above the upper bonding pad 149 and the lower bonding pad 122 is removed using the PO photolithography pattern 158 and the PO etching step 171. In the area of ​​the upper bonding pad 149, the PO inorganic dielectric stack 154 is completely removed and the upper bonding pad 149 is exposed. In the area above the lower bonding pad 122, the PO inorganic dielectric stack 154 and the seventh low stress silicon dioxide layer 142 and the sixth high stress silicon dioxide layer 141 are completely removed.

[0039] refer to Figure 1N , forming a flat line region photolithography mask 170. The flat line region photolithography mask exposure area 159 includes both an area above the lower bonding pad 122 and an exposure area 160 extending over a portion of the first silicon oxynitride etch stop layer 129.

[0040] refer to Figure 1O to Figure 1Q , the RIE etching process for exposing the lower bonding pad 122 is continuous but has multiple steps using different fluorine-based etching chemistries. During the etching process, for the sake of clarity of etching profile, the RIE etching process is described in terms of a first flat line area RIE etching sub-process 161, a second flat line area RIE etching sub-process 162, and a third flat line area RIE etching sub-process 164.

[0041] refer to Fig.1O The first flat line region RIE etching sub-process 161 etches a portion of the flat line region 152 in the flat line region photolithography mask exposed area 159 above the lower bonding pad 122. The first flat line region RIE etching sub-process 161 etches through multiple dielectric layers until the first flat line region RIE etching sub-process 161 reaches the second silicon oxynitride etching stop layer 136.

[0042] In the area above the grounded second level interconnect filler metal 121, the first flat line area RIE etch sub-process 161 is terminated by the second silicon oxynitride etch stop layer 136. In the area above the lower bonding pad 122, the first flat line area RIE etch sub-process 161 etches into the fourth low stress silicon dioxide layer 132. It is advantageous to expose the second silicon oxynitride etch stop layer 136 as a means of providing an endpoint signal to the first flat line area RIE etch sub-process 161. The first flat line area RIE etch sub-process 161 consumes approximately 33% of the available resist thickness.

[0043] refer to Figure 1P , the second flatline region RIE etch subprocess 162 etches through the intermediate dielectric stack 128 above the lower bonding pad 122. The second flatline region RIE etch subprocess 162 etches through the first silicon oxynitride etch stop layer 129 and stops in the second low stress silicon dioxide layer 126. The interaction between the PO etch step 171, the second silicon oxynitride etch stop layer 136, the first flatline region RIE etch subprocess 161, and the second flatline region RIE etch subprocess 162 and the flatline region 152 creates an oxide foot space 163 between the edge of the flatline region photolithography mask 170 closest to the lower bonding pad 122 and the lower bonding pad 122.

[0044] refer to Figure 1Q , the third flat line area RIE etching sub-process 164 is used to remove the remaining second low stress silicon dioxide layer 126, the second gap filling silicon dioxide layer 125 and the silicon nitride / silicon oxynitride double layer 124 above the lower bonding pad 122. After the third flat line area RIE etching sub-process 164 is completed, the remaining flat line area photolithography mask 170 is removed. The first flat line area RIE etching sub-process 161, the second flat line area RIE etching sub-process 162 and the third flat line area RIE etching sub-process 164 can be performed sequentially without interruption.

[0045] The first flat line area RIE etching subprocess 161, the second flat line area RIE etching subprocess 162, and the third flat line area RIE etching subprocess 164 all use fluorine-based etching chemistry that also contains carbon and oxygen. During the total processing of the first flat line area RIE etching subprocess 161, the second flat line area RIE etching subprocess 162, and the third flat line area RIE etching subprocess 164, the fluorine-based etching chemistry may include at least one alternation between an etching chemistry having a first carbon-oxygen ratio and an etching chemistry having a second carbon-oxygen ratio greater than the first carbon-oxygen ratio. The first carbon-oxygen ratio can be advantageously used for etching to prevent a retrograde profile. In addition, during the total processing of the first flat line area RIE etching subprocess 161, the second flat line area RIE etching subprocess 162, and the third flat line area RIE etching subprocess 164, the fluorine-based etching chemistry may alternate at least once between an atomic carbon to atomic oxygen ratio of less than 2 and an atomic carbon to atomic oxygen ratio of greater than 2. For example, the carbon source may alternate between C5F8 and C4F8 with a constant O2 flow (e.g., approximately 16 / 18 / 800 standard cubic centimeters per minute (sccm) of C5F8, O2, and Ar alternating with approximately 16 / 18 / 800 sccm of C4F8, O2, and Ar). If a silicon nitride / silicon oxynitride bilayer 124 is present, a carbon-oxygen ratio greater than the second carbon-oxygen ratio may be used in the fluorine-based etch chemistry. If a silicon nitride / silicon oxynitride bilayer 124 is present, an atomic carbon to atomic oxygen ratio greater than 3 may be used in the fluorine-based etch chemistry.

[0046] refer to Figure 1R , a cross-section depicts the microelectronic device 100 after the removal of the flat area photolithography mask 170 and after the ammonia plasma 165 process. The ammonia plasma 165 forms SiO on the exposed silicon dioxide surfaces of the lower dielectric stack 123, the middle dielectric stack 128, and the upper dielectric stack 139. x N y Layer 166. SiO is formed on the exposed areas of the lower dielectric stack 123, the middle dielectric stack 128, and the upper dielectric stack 139. x N y Layer 166 is advantageously configured to minimize moisture absorption which may adversely affect the dielectric integrity and high voltage performance of isolation device 101 .

[0047] refer to Figure 1S A second PO layer 167 of a polymer material such as polyimide, benzocyclobutene (BCB) or polybenzoxazole (PBO) may be formed on the PO inorganic dielectric stack 154. The second PO layer 167 is formed by a spin coating process (not specifically shown) and a subsequent curing process (not specifically shown). The patterning and etching steps are used to remove the second PO layer 167 over the upper bonding pad 149 and the lower bonding pad 122.

[0048] refer to Figure 1T , upper level wire bonds 169 are formed in electrical contact with upper bonding pads 149 , and lower level wire bonds 168 are formed in electrical contact with lower bonding pads 122 .

[0049] refer to Figure 2 , showing a perspective view of a microelectronic device 200 including an isolation device 201. Elements of the isolation device 201 visible in the perspective view include substrate 202, upper coil 248, upper bonding pad 249, upper wire bonds 269, second PO layer 267, lower bonding pad 222, and lower wire bonds 268. The flat area oxide base 280 and oxide base space 263 are also visible in the perspective view.

[0050] Modifications may be made in the described examples, and other examples are possible, within the scope of the claims.

Claims

1. A microelectronic device comprising: substrate; an inorganic dielectric disposed on the substrate; An isolation device comprising: A flat line region, which is located on the inorganic dielectric, and the flat line region includes: a lower dielectric stack, located on the inorganic dielectric, comprising at least one low stress silicon dioxide layer and at least one high stress silicon dioxide layer; an intermediate dielectric stack located on the lower dielectric stack, comprising a lower etch stop layer and at least one low stress silicon dioxide layer and at least one high stress silicon dioxide layer located on the lower etch stop layer; an upper dielectric stack, located on the middle dielectric stack, comprising at least one low stress silicon dioxide layer, at least one high stress silicon dioxide layer, at least one silicon oxynitride layer, and at least one silicon nitride layer; and a lower isolation element located in the lower dielectric stack; an upper isolation element located on the upper dielectric stack; a dielectric protective coating disposed on the upper isolation element; an upper bonding pad in electrical contact with the upper isolation element; and A lower bonding pad is electrically connected to the lower isolation element.

2. The microelectronic device of claim 1, wherein the isolation device includes a ground ring surrounding the lower isolation element. The microelectronic device of claim 1 , wherein the isolation device comprises a filler metal.

4. The microelectronic device of claim 1, wherein the isolation device contains photolithographic alignment marks located in the land area.

5. The microelectronic device of claim 1, wherein the lower dielectric stack contains a bilayer of silicon oxynitride and silicon nitride located on the lower isolation element.

6. The microelectronic device of claim 1, wherein the lower dielectric stack contains a gap-fill silicon dioxide layer and a low-stress silicon dioxide layer.

7. The microelectronic device of claim 1 wherein the lower etch stop layer of the intermediate dielectric stack is silicon nitride.

8. The microelectronic device of claim 1, further comprising an upper etch stop layer in the intermediate dielectric stack over the lower etch stop layer.

9. The microelectronic device of claim 8, wherein the upper etch stop layer of the intermediate dielectric stack is silicon nitride.

10. A method of forming a microelectronic device, comprising: forming an inorganic dielectric on a substrate; An isolation device is formed, comprising: A flat line area is formed, the flat line area comprising: forming a lower dielectric stack on the inorganic dielectric, the lower dielectric stack comprising at least one low stress silicon dioxide layer and at least one high stress silicon dioxide layer; forming a lower isolation element in the lower dielectric stack; forming an intermediate dielectric stack on the lower dielectric stack, the intermediate dielectric stack comprising a lower etch stop layer, an upper etch stop layer, and at least one low stress silicon dioxide layer and at least one high stress silicon dioxide layer between the lower etch stop layer and the upper etch stop layer; forming an upper dielectric stack on the middle dielectric stack, the upper dielectric stack comprising at least one low stress silicon dioxide layer, at least one high stress silicon dioxide layer, at least one silicon oxynitride layer, and at least one silicon nitride layer; and forming an upper isolation element on the upper dielectric stack; forming an upper bonding pad in electrical contact with the upper isolation element; and A lower bonding pad is formed that is electrically connected to the lower isolation element. The method of claim 10 , further comprising forming a filler metal in the flat line region.

12. The method of claim 10, further comprising forming a photolithography alignment mark in the land area.

13. The method of claim 10, further comprising forming a double layer of silicon oxynitride and silicon nitride on the lower isolation element.

14. The method of claim 10, further comprising forming a gap-fill silicon dioxide layer in the lower dielectric stack. The method of claim 10 , wherein the lower etch stop layer comprises silicon oxynitride. The method of claim 10 , wherein the upper etch stop layer comprises silicon oxynitride.

17. The method of claim 10, further comprising performing a dielectric etch process on the plateau region, wherein an endpoint signal is provided when the upper etch stop layer is exposed.

18. A method of forming a microelectronic device, the microelectronic device comprising an isolation device having a lower isolation element, an upper isolation element, and a plateau region between the lower isolation element and the upper isolation element, the plateau region having a plurality of alternating low stress silicon dioxide layers and high stress silicon dioxide layers, the method comprising: The plurality of alternating low stress silicon dioxide layers and high stress silicon dioxide layers are etched by a process including a fluorine-based etch chemistry having at least one alternation between an etch chemistry having a first carbon to oxygen ratio and an etch chemistry having a second carbon to oxygen ratio greater than the first carbon to oxygen ratio. The method according to claim 18 , wherein the etching of the plateau region is continuous without interruption.

20. The method of claim 18, further comprising subsequently etching the silicon nitride / silicon oxynitride bilayer using a fluorine-based etch chemistry having a carbon to oxygen ratio greater than the second carbon to oxygen ratio.

21. A method of forming a microelectronic device, comprising: Etching a flat line region, the flat line region comprising: a lower dielectric stack having at least one low stress silicon dioxide layer and at least one high stress silicon dioxide layer; an intermediate dielectric stack on the lower dielectric stack, the intermediate dielectric stack having a lower silicon oxynitride etch stop layer and an upper silicon oxynitride etch stop layer, and at least one low stress silicon dioxide layer and at least one high stress silicon dioxide layer between the lower etch stop layer and the upper etch stop layer; and an upper dielectric stack, located on the middle dielectric stack, having at least one low stress silicon dioxide layer, at least one high stress silicon dioxide layer, at least one silicon oxynitride layer and at least one silicon nitride layer, by a process including a fluorine-based etch chemistry having at least one alternation between an etch chemistry having a carbon to oxygen ratio of less than 2 and an etch chemistry having a carbon to oxygen ratio of greater than 2, wherein the process removes a portion of the upper dielectric stack, a portion of the middle dielectric stack, and a portion of the lower stack; forming a lower isolation element in the lower dielectric stack; An upper isolation element is formed on the upper dielectric stack.

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