Joint timing recovery and decision feedback equalizer adaptation in wired network receivers

Abstract

A network communication receiver and a method of operating the same in symbol timing recovery and equalization adaptation. A data converter (308) samples a received analog signal (AIN) at an initialization frequency ( / init) that is higher than a symbol frequency of the received signal and converts the samples into a stream of digital samples. A decision feedback equalizer (320) including a digital filter (325) having one or more tap weights is adapted, and an error measurement (MSE) is obtained from an output of the decision feedback equalizer. In response to the error measurement exceeding an error threshold (ALSEnir seq), a timing loop including a timing error detection (350) is started to adjust a phase of a sampling clock (SCLK) applied to the data converter.

Description

Background Art

[0001] This involves the establishment of a network communication channel and, more specifically, timing recovery and adaptive equalizer adaptation in a wired network receiver.

[0002] In the field of network communications, a common reference model for describing the architecture of communication protocols is the Open Systems Interconnection (OSI) layered reference model. This reference model contains a stack of abstraction layers, the "lowest layer" of which is usually called the physical layer or "PHY". The OSI physical layer defines the electrical, timing, and other interfaces through which data bits are transmitted over a communication link, whether wired (e.g., Ethernet) or wireless (e.g., cellular phones, wireless LANs, or WiFi). Communication elements such as electrical signals, signaling speeds, media and connector types, and network topology are contained within the PHY abstraction layer.

[0003] From a hardware perspective, the term "PHY" refers to an electronic circuit, typically implemented as one or more integrated circuits, that implements the physical layer functions of the OSI model in a network interface controller or other network node. For example, "PHY" is often used to refer to the transceiver circuitry in a network node that transmits and receives signals to and from another network node. Within a network node, a PHY connects a link layer device (commonly referred to as a "MAC" as an acronym for medium access control) to a physical medium such as an optical fiber or copper cable. A PHY device may include both a physical coding sublayer (PCS) and a physical medium dependent (PMD) layer functionality.

[0004] In the Ethernet context, a PHY may refer to a physical layer transceiver device used to send and receive Ethernet frames according to the Ethernet physical layer portion of the IEEE Ethernet wired packet transmission standard applicable to a particular network, such as the 1000BASE-T (1000Mbps), 100BASE-TX (100Mbps over copper), and 10BASE-T (10Mbps) standards. In these implementations, the Ethernet PHY provides analog signal physical access to the link, and because the PHY typically does not handle MAC addressing, the Ethernet PHY interfaces with a media independent interface (MII) to a microcontroller or a MAC chip in another system that performs higher layer functions.

[0005] In many network interface card (NIC) implementations, the Ethernet PHY is implemented as an integrated circuit that interfaces between the Ethernet analog and digital domains of the hardware transmit and receive functions of Ethernet frames and link layer packet signaling. The NIC may integrate the PHY, MAC, and other functionality into a single integrated circuit, or alternatively as separate integrated circuits. Examples of modern Ethernet transceivers include the DP838xx, DP83TGxxx, and DP83TMxxx series devices available from Texas Instruments Incorporated.

[0006] One function of Ethernet and some other wired PHYs is called clock and data recovery. Clock recovery involves the PHY receiver obtaining the symbol timing of the received signal stream from the signal stream itself. To achieve this, some PHY receivers include a timing loop function that detects timing errors in the sampling of the received signal and adjusts the phase of the sampling clock to optimize the sampling point. Clock and data recovery also typically includes adaptation of one or more equalizers (typically including an adaptive decision feedback equalizer (DFE)) at the PHY receiver to optimize compensation for the effects of channel distortion in the received signal. This channel distortion in an Ethernet environment manifests itself largely as inter-symbol interference (ISI), which tends to spread higher frequency pulses in time.

[0007] Timing error detection in Ethernet PHY is typically performed according to the method described in Mueller et al., "Timing Recovery in Digital Synchronous Data Receivers," Transactions on Communications, Vol. COM-24, No. 5 (IEEE, 1976), pp. 516-31, which is incorporated herein by this reference. In general, this method adjusts the sampling phase to balance the leading ISI (P -1 ) and its trailing ISI (P1). Adaptation of the DFE in the Ethernet PHY is performed to minimize the magnitude of both the leading and trailing ISI.

[0008] In conjunction with the examples described herein, it has been observed that timing error detection loop ("timing loop") adjustments and DFE adaptation are interconnected, as both involve monitoring and optimizing trailing ISI (P1). Thus, an adjustment of the sampling phase by the timing loop will cause the DFE to adapt its coefficients or tap weights, which in turn may cause the timing loop to adjust the sampling phase again, and so on. In some cases, this dependency of the timing loop and the DFE may result in long link times before convergence, if not for a "deadlock" condition in which the timing loop fails to converge, as the DFE converges to incorrect but stable coefficient values. It has been observed that these problems are particularly prevalent in short channels where the ISI is relatively low and therefore the timing error detection gain is low, and for certain types of modulation that have relatively few symbol transitions (e.g., MLT-3) and therefore exhibit low ISI.

[0009] It is against this background that the examples described in this article arise. Summary of the invention

[0010] According to one aspect, a method for symbol timing recovery and equalization of a signal having a symbol frequency and received by a physical layer transceiver comprises: initially sampling with a sampling clock at a frequency greater than the symbol frequency; converting the sampled signal into a digital sample stream; and equalizing the digital sample stream with a decision feedback equalizer to produce an output digital stream. The method further comprises adapting at least one tap weight of the decision feedback equalizer, and calculating an error measure from the output sample stream. In response to the error measure exceeding an error threshold, a phase of the sampling clock is then adjusted.

[0011] According to another aspect, a network communication receiver has: an input that receives an analog signal having a symbol frequency; and a data converter that is configured to sample the analog signal in response to a sampling clock signal and convert the sampled signal into a digital sample stream. A clock generation circuit system is configured to generate the sampling clock signal at a phase in response to a clock control signal generated by a clock control circuit system in a digital receiver circuit system of the receiver. The digital receiver circuit system has an input coupled to receive the digital sample stream from the data converter, and further includes a decision feedback equalizer, the decision feedback equalizer including a digital filter having one or more tap weights, the digital filter producing an output digital stream from the digital sample stream. The digital receiver circuit system also includes: an error measurement circuit system that measures errors in samples of the output sample stream; a clock control circuit system that is configured to generate the clock control signal to the clock generation circuit system. Sequencer logic controls the operation of the circuit system to: control the clock generation circuit system to generate the sampling clock at an initialization frequency higher than the symbol frequency; adapt at least one tap weight of the decision feedback equalizer; and calculate an error measurement from the output sample stream. In response to the error measurement exceeding an error threshold, the clock control signal then adjusts the phase of the sampling clock.

[0012] Technical advantages achieved by one or more of these aspects include fast and accurate joint convergence of equalization and sample timing in a network receiver, even in implementations where the equalization and timing loops are interdependent.

[0013] Other technical advantages achieved by the described aspects will become apparent to those of ordinary skill in the art after reference to the following description and its drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is an electrical diagram in block form of a network node constructed according to the example.

[0015] Figure 2 is an electrical diagram in block form of a physical layer transceiver (PHY) constructed according to an example.

[0016] Figure 3A It is based on the example Figure 2 An electrical diagram of the circuitry within the receive path of a PHY in block form.

[0017] Figure 3B is based on Figure 3A An electrical diagram of an example decision feedback equalizer in block form.

[0018] Figure 3C is based on Figure 3AAn electrical diagram of an example error calculation circuit system in block form.

[0019] Figure 4 It shows that according to Figure 3A A flow chart of the operation of an example receive path circuit system.

[0020] Figure 5A is based on Figure 4 A graph of decision feedback equalizer coefficient values ​​during adaptation in an operating example of an example.

[0021] Figure 5B is based on Figure 4 A graph of the mean squared error measurement during adaptation of an example in operation.

[0022] Fig. 6A According to another example Figure 2 An electrical diagram of the circuitry within the receive path of a PHY in block form.

[0023] Figure 6B is based on Fig. 6A An electrical diagram in block form of error calculation circuitry in a receive path circuitry of an example.

[0024] Figure 7 It shows that according to Fig. 6A A flow chart of the operation of an example receive path circuit system.

[0025] The same reference numbers or other reference designators are used in the drawings to indicate the same or similar features (functionally and / or structurally). DETAILED DESCRIPTION

[0026] In this specification, one or more examples are described as being implemented into a physical layer transceiver device in a high-speed Ethernet type network, because such implementation is considered particularly advantageous in such applications. However, it is also contemplated that aspects of these examples may be advantageously applied in other applications, such as in conjunction with other wired network technologies. Therefore, the following description is provided by way of example only, and does not limit the true scope of the claimed invention.

[0027] Figure 1An example of a network node 100 in which an example can be implemented is shown. The network node 100 can be implemented as any one of a plurality of network functions, such as a computing device that serves as either or both of a network server or client, a peripheral device such as an input / output function, a sensor or controller, a router, a switch, or another network function. The network node 100 is coupled to a network communication medium 102, through which the network node receives and transmits data and control information. In this particular example in which network communication is performed over an Ethernet network, the network communication medium 102 is implemented as CAT6 copper wiring, etc. In other embodiments, the network communication medium 102 can be implemented as optical fiber, etc.

[0028] exist Figure 1 In the example of , the network node 100 includes an Ethernet physical layer transceiver (PHY) 106 constructed according to the example. For this example where the network communication medium 102 is a copper wire Ethernet connection, the PHY 106 is coupled to the medium 102 through a magnetic coupling interface 104. The magnetic coupling interface 104 is provided to galvanically isolate the medium 102 from the PHY 106 while providing a signal path. For example, the magnetic coupling interface 104 can be implemented as a discrete Ethernet magnetic module that is placed in the signal path between the PHY 106 and the connector socket to physically couple to the network communication medium 102. Alternatively, the magnetic coupling interface 104 can be integrated into the same housing or package as the Ethernet connector socket. In either case, in this implementation, the interface 122 between the PHY 106 and the magnetic coupling interface 104 is called a medium-dependent interface (MDI) in the Ethernet environment because its specifications depend on the specific medium used for the network communication medium 102.

[0029] In this example, the Ethernet PHY 106 includes appropriate circuitry for sending and receiving data and control information between upstream functions and the network communication medium 102. In an Ethernet environment, the PHY 106 receives digital data in the form of Ethernet frames from a media access controller (MAC) 108, and generates analog signals corresponding to these frames for transmission on the medium 102. In its receiving function, the PHY 106 processes the analog signals received through the medium 102, and for those signals representing data for the network node 100, digitizes and formats the digital data into Ethernet frames for consumption and processing by the MAC 108, and further acts upstream. Therefore, the PHY 106 acts as an interface between the Ethernet analog domain at the medium 102 and the digital domain of the link layer packet signaling of the network node 100 performed by the MAC 108. The construction and operation of the PHY 106 according to the example will be described in more detail below.

[0030] According to this example, the PHY 106 is coupled to the MAC 108 via an interface 124, which in this implementation is referred to as a media independent interface (MII) or a reduced gigabit media independent interface (RGMII) in an Ethernet environment because the interface specification is independent of the physical implementation of the network communication medium 102. The media access controller (MAC) 108 in the network node 100 includes appropriate circuitry for processing data received from the network via the PHY 106 and passing it to the PHY 106 for transmission. This processing may include, for example, managing frame buffering of data in the transmit and receive directions, packet formatting and identification, timer functions, and other operations involved in the data link layer or MAC layer portion of the OSI model. The MAC 108 may be integrated into a processor, a field programmable gate array (FPGA), digital circuitry, memory, an application specific integrated circuit (ASIC), software, or a combination thereof. The MAC 108 may be implemented in the same integrated circuit as the PHY 106 and the MII interface 124, or alternatively implemented as one or more integrated circuits separate from the PHY 106.

[0031] exist Figure 1 108. In an example of a network node processor 110, a network node processor 110 is coupled to a MAC 108 via an interface 126. The network node processor 110 provides data processing and control capabilities suitable for performing the functions of the network node 100 in a network. The network node processor 110 may be implemented as a microprocessor, a microcontroller, an FPGA, or another switch fabric and / or other appropriate circuitry for the described functions. The network node processor 110 may be implemented in the same integrated circuit as the MAC 108, or alternatively as one or more separate integrated circuits. In one example of the latter case, the MAC 108, the PHY 106, and the magnetic coupling interface 104 may be implemented in a network interface card (NIC) to which the network node processor 110 is coupled via the interface 126.

[0032] Figure 2 The architecture of the PHY 106 according to an example is shown. As mentioned above, the PHY 106 has the overall function of interfacing communications between the Ethernet analog domain at the network communication medium 102 and the digital domain of link layer packet signaling of the network node 100 performed by the MAC 108. Therefore, in this example, the PHY 106 includes the MII interface circuit system 200, through which the digital signals processed or to be processed by the PHY 106 are transmitted to and received from the MAC 108 through the interface 124 according to the appropriate RGMII or MII protocol (as the case may be).

[0033] In order to process digital data to be transmitted to and received from the MAC 108, the PHY 106 includes one or more communication processing blocks. In this example, the PHY 106 includes a transmission: processing block 202TX for processing data received from an upstream function in the network node 100 for transmission from the PHY 106 to the network; and a reception processing block 202RX for processing data received from the network for forwarding to an upstream function in the network node 100. In this example where the PHY 106 is operable to process communications according to any of the three Ethernet industrial protocols, the processing blocks 202TX, 202RX (collectively or individually referred to as "processing blocks 202") may each include a 100BASE-TX processing block, a 10BASE-Te processing block, and a 1000BASE-T processing block. Alternatively, for the case where the network node 100 is implemented in the context of an automotive network, the processing blocks 202 of the PHY 106 will be constructed to process communications according to the applicable automotive Ethernet protocol. The processing blocks 202TX, 202RX are each coupled to the MII interface circuitry 200 on one side and to the hybrid block 210 on the other side for communicating with the network communication medium 102 via the magnetic coupling interface 104. The processing blocks 202TX, 202RX each include digital logic circuitry (or other circuitry, memory and / or software) configured and operable to process digital data suitable for the specific protocol involved. For example, the digital logic circuitry included in the processing blocks 202TX, 202RX may be implemented at least in part in a digital signal processor, as a stand-alone processor or embedded in a larger scale integrated circuit, and / or in sequential logic in the form of one or more state machines. The PHY control block 208 includes appropriate logic and configuration registers configured to control the processing blocks 202TX, 202RX and other functions of the PHY 106 to operate in a selected operating mode among a plurality of operating modes.

[0034] In the Ethernet environment of this example, the digital logic circuit system in the processing blocks 202TX, 202RX is arranged to implement one or more sublayers of the applicable Ethernet protocol, such as one or more of the physical coding sublayer (PCS), the physical medium attachment (PMA) sublayer, and the physical medium dependent (PMD) sublayer (in order from the MII side to the Ethernet medium side), depending on the operating mode (e.g., 100BASE-TX, 10BASE-Te, and 1000BASE-T).

[0035] In this embodiment, the mixing block 210 is configured and operable to convert signals between the digital domain and the analog domain (e.g., as transmitted over the network communication medium 102) of the processing blocks 202TX, 202RX. Thus, the converter block 210 includes digital-to-analog (DAC) conversion and analog-to-digital (ADC) conversion functionality, as well as driver and receiver circuitry coupled to the magnetic coupling interface 104. Figure 2 2 shows the circuits and functions of the mixing block 210 involved in transmitting digital data to the network communication medium 102 by the transmission subsystem block 214, including, for example, a DAC and appropriate filters and amplifiers for converting digital data from the transmission processing block 202TX to the analog domain. In order to receive signals from the network communication medium 102, the mixing block 210 includes a receiver analog front end (AFE) 216. The AFE 216 includes appropriate circuit systems involved in receiving analog signals from the medium 102 and converting these received signals into digital data and control symbols for transmission to the receive processing block 202RX under the operating protocol. In this regard, and as will be described in further detail below, the AFE 216 may include analog filters, level shifters, one or more programmable gain amplifiers, ADC functionality, and other circuit systems for performing these operations.

[0036] The PHY 106 also includes a clock generator circuit system 220, which is constructed and operable in this example to provide appropriate clock signals to the hybrid block 210 and, for the purposes of the examples described herein, specifically to the receiver AFE 216. The clock generator circuit system 220 may generate these clocks based on a received master clock signal (e.g., a crystal oscillator or bulk acoustic wave device from outside the PHY 106 and coupled at the terminal REFCLK) or based on a master clock signal generated externally or internally to the PHY 106. The clock generator circuit system 220 may also receive control signals from the receive processing block 202RX and / or the PHY control block 208, such as Figure 2 As indicated in .

[0037] According to this example, some additional functionality is also provided in PHY 106. As described above, Figure 2As shown in FIG. 1 , the PHY 106 includes a PHY control block 208, which includes: management and control circuit systems, which are constructed and operable to perform appropriate operations for controlling the PHY 106 as an integrated circuit device, such operations including reset, interrupt generation and processing; circuit systems for receiving status and control information from external circuit systems and transmitting status and control information to external circuit systems, etc. For example, MII registers 222 may be provided to store configuration and status information related to the MII interface 200 and communication with upstream functions. Figure 2 Other functions not shown in the figure include power management, "wake-up LAN" circuit function, automatic negotiation circuit function, etc.

[0038] Figure 3A An example of certain circuitry in a receive path of a PHY 106 according to an example is shown, such circuitry including an AFE 216, a clock generator circuitry 220, and a portion of a receive processing block 202RX. The AFE 216 includes an analog high pass filter 302 having an input coupled to the interface 122 to receive incoming signals from the network communication facility 102 via the magnetic coupling interface 104. The output of the high pass filter 302 is coupled to a programmable gain amplifier 304 and an analog low pass filter 306, the output of which is coupled to the input of an ADC 308. In this example, the high pass filter 302 and the low pass filter 306 provide signal conditioning to the signal received from the interface 122, and the programmable gain amplifier (PGA) 304 applies automatic gain control (AGC) to the conditioned input signal.

[0039] ADC 308 samples the conditioned and amplified analog signal at the phase and frequency of the sampling clock SCLK from the clock generator circuit system 220, and converts each sample of the signal into a digital symbol. In this embodiment in Ethernet PHY106, the sampling rate of ADC 308 is one sample per symbol (1Sps), and therefore the frequency of the sampling clock SCLK is at the symbol rate of the received analog signal. This symbol frequency may be set by an applicable standard (e.g., IEEE Standard 802.3ab for "Gigabit Ethernet"), may be negotiated between the network node 100 and the network when connected, or may be transmitted to PHY 106 in other ways and applied to the clock generation circuit system 220. The phase of the sampling clock SCLK within each symbol period is controlled and adjusted by the clock generation circuit system 220, for example, in response to the observed signal quality, as will be described below. The symbol stream generated by the ADC 308 in the AFE 216 is forwarded to the receive processing block 202RX.

[0040] Figure 3AThe architecture of the symbol timing recovery and equalization circuit system 300 is shown, which forms part of the circuit system of the receive processing block 202RX. Figure 3A The symbol timing recovery and equalization circuitry 300 shown in FIG. 1 operates to perform symbol timing recovery operations from the symbol stream produced by the AFE 216 and adaptation for equalization as part of the clock and data recovery operations performed on the symbol stream from the AFE 216 . Figure 3A The symbol timing recovery and equalization circuitry may be implemented as a digital signal processor (DSP), as an embedded processor integrated into a single integrated circuit with other circuitry of PHY 106, or as a standalone processor, or alternatively may be implemented as custom, semi-custom, dedicated, or other logic circuitry (programmable or hard-wired), etc.

[0041] like Figure 3A As shown in , the symbol stream received from AFE 216 is applied to a digital automatic gain control (AGC) function 310, which dynamically adjusts the gain applied to the received symbol stream in a common manner. In this example, a feed forward equalizer (FFE) 312 receives the output of the AGC function 310 and operates as a preset (e.g., non-adaptive) equalization filter. The coefficients or tap weights of FFE 312 are set by a channel AGC function 314, which obtains a coarse channel estimate from the symbol stream received from AFE 216.

[0042] After amplification by AGC 310 and equalization by FFE 312, the received symbol stream is applied to a decision feedback equalizer (DFE) 320, according to this example. In this implementation, DFE 320 is an adaptive equalizer whose coefficients or tap weights (such terms are used interchangeably in this specification) dynamically adapt to reduce residual post-ISI from the symbol stream.

[0043] like Figure 3A As shown in FIG. 1 , DFE 320 can be viewed as an adder function 322 having one input receiving a symbol stream from the output of FFE 312 and a second input receiving a feedback signal, which adder 322 subtracts from the symbol stream and outputs the remainder as residual samples x(n) to decision limiter 324. Limiter 324 quantizes the residual samples from adder 322 to produce output symbols The digital filter 325 processes the output symbols from the limiter 324 for processing by other circuitry in the receive processing block 302RX before forwarding to upstream functions in the network node 100. A digital filter function is applied to generate feedback to be subtracted from the incoming symbol stream by adder 322. In a general sense of this example implementation, digital filter 325 is adapted such that the feedback signal applied to adder 322 removes one or more residual artifacts to compensate for ISI caused by channel distortion.

[0044] Figure 3B 3 shows a configuration of a DFE 320 in which a digital filter 325 is shown in more detail. In this example, the digital filter 325 includes one or more delay stages 326 connected in series, where the output of each delay stage 326 is multiplied by a tap weight w at a corresponding multiplier in multipliers 327. k , and the resulting products are summed at adder 328 to generate a feedback signal, which is applied as a subtractor to adder 322. Adaptive logic 329 is provided in DFE 320 (or elsewhere in DSP 300) to adapt the tap weights w applied by multiplier 327 according to the adaptive equation k For example, the adaptive logic 329 may adapt according to a recursive least mean square equation Figure 3B The m tap weights w in the example k Each of:

[0045]

[0046] where n and n-1 are the indices of the nth and (n-1)th samples in the digital symbol stream being processed by DFE 320, respectively, μ is a learning constant between 0 and 1, refers to the output of the limiter 324 of the (n-1)th sample, and err represents the difference between the sample x(n) at the input of the limiter 324 of the nth sample and the limiter output The difference between:

[0047]

[0048] The number, m, and therefore the order, of tap weights in the digital filter 325 may vary depending on the particular implementation. Adaptive logic 329 is operable to adapt the tap weights w after each sample. k .

[0049] DFE 320 may alternatively be implemented according to any method used for a decision feedback equalizer.

[0050] according to Figure 3A The symbol timing recovery and equalization circuitry 300 of the example architecture also includes an MSE calculation circuitry 340 having an input received symbol stream from the output of the slicer 324 The input of adder 322 receives residual samples x(n) from the input of limiter 324 and calculates an error measure based on these samples. This error measure is a measure of the noise at limiter 324, including ISI. For example, MSE calculation circuitry 340 may calculate a mean square error measure MSE according to the following equation:

[0051]

[0052] Therein the summation in equation (3) corresponds to a weighted sum of squared differences obtained over a preselected number of samples, for example over a sliding window of samples in the symbol stream.

[0053] like Figure 3A As shown in FIG. 1 , in this example, timing error detection (TED) circuitry 350 is also included in symbol timing recovery and equalization circuitry 300. TED circuitry 300 has input received residual samples x(n) and input received symbol streams x(n) from the input and output of slicer 324, respectively. TED circuit system 350 includes logic and memory circuit system configured to generate a timing error signal ted indicating an estimated error in the phase of the sampling clock SCLK applied to ADC 308 relative to an optimal point in a symbol period. For example, TED circuit system 350 may generate timing error signal ted according to the method described in the article of Mueller et al. incorporated above. According to the method, timing error signal ted is calculated by TED circuit system 350 according to:

[0054]

[0055] The first term on the right side of equation (4) corresponds to the first ISI post-body P1, while the second term corresponds to the first ISI pre-body P -1 .

[0056] The symbol timing recovery and equalization circuitry 300 according to this example implements a timing loop together with the clock generator circuitry 220 that is configured to adjust the phase of the sampling clock SCLK in response to the timing error detected by the TED circuitry 350. In this example, this timing loop operates to adjust the sampling phase so as to minimize the timing error signal ted generated by the TED circuitry 350. Figure 3A As shown in FIG. 1 , the timing error signal ted is applied to a loop filter 352, which is a digital filter that applies a transfer function with appropriate response and stability to adjust the sampling phase, wherein the filtered error signal is applied to one input of an adder 354. The timing error signal ted reflecting the filtering is added to the initialization frequency f initThe output of the summed adder 354 is applied to a numerically controlled oscillator (NCO) 356 , which generates a control signal UP / DN in response to the output of the adder 354 for application to the clock generator circuitry 220 .

[0057] The clock generator circuit system 220 can be constructed in various configurations. For example, Figure 3A As shown in , the clock generator circuit system 220 includes a phase locked loop (PLL) 360. PLL 360 generates a clock signal based on a reference clock REFCLK, which may be a reference clock signal generated externally from the clock generator circuit system 220; alternatively, the clock generator circuit system 220 may include an oscillator that generates the reference clock REFCLK based on an external clock reference such as a crystal resonator. PLL 360 applies its output clock to a phase interpolator (PI) 362, which receives a control signal UP / DN from NC 356 in the symbol timing recovery and equalization circuit system 300 and generates a sampling clock SCLK in response.

[0058] In this example, the PI 362 is configured to advance the phase of the sampling clock SCLK in response to the “up” pulse of the control signal UP / DN, and to delay the phase of the sampling clock SCLK in response to the “down” pulse of the control signal UP / DN. Then, the TED circuit system 350 is configured together with the loop filter 352, the adder 354 and the NCO 356 so that in response to the timing error signal ted indicating the optimal point of the current sampling phase lag (for example, because the trailing P1 is greater than the leading P2), the TED circuit system 350 is configured to delay the phase of the sampling clock SCLK in response to the “down” pulse of the control signal UP / DN. -1 , ted is positive), NCO 356 issues an “up” pulse of the control signal UP / DN. Conversely, in response to the timing error signal ted indicating that the current sampling phase leads the optimal point (for example, because the trailing P1 is less than the leading P -1 , ted is negative), the NCO issues a "down" pulse of the control signal UP / DN. Therefore, the timing loop of the symbol timing recovery and equalization circuit system 300 operates to minimize the amplitude of the timing error signal ted.

[0059] Continuing to adjust the phase of the sampling clock SCLK in the same direction (advance or delay) over multiple sampling cycles may have the effect of adjusting the frequency of the sampling clock SCLK. Therefore, the phase adjustment or tuning described in this specification may also be considered as the frequency adjustment or tuning of the sampling clock SCLK.

[0060] exist Figure 3AThe operation of the symbol timing recovery and equalization circuitry 300 in this example is controlled by sequencer logic 330. Sequencer logic 330 may be constructed as a programmable or hard-wired sequential logic configured to enable the functionality of the symbol timing recovery and equalization circuitry 300 to perform desired operations of various functions, including DFE 320, MSE calculation circuitry 330, and TED circuitry 340. Specifically, according to this example, a mean square error signal MSE from the MSE calculation circuitry 340 is applied to the sequencer logic 330, in response to which the sequencer logic 330 issues a control signal TLOOP_STRT to the TED circuitry 350 to initiate operation of the timing loop of the symbol timing recovery and equalization circuitry 300.

[0061] Figure 3C 3. The configuration of the MSE calculation circuitry 340 and associated functionality, such as may be included in the sequencer logic 330, is shown according to an example. The MSE calculation circuitry 340 includes an adder 370 having one input receiving the residual samples x(n) at the input of the slicer 324 and another input receiving the symbol stream x(n) from the output of the slicer 324. The adder 370 is configured to subtract the slicer output sign from the residue x(n) for each sample. and the resulting difference is provided to a square function 372 which produces a squared error for each sample The squared error from function 372 is forwarded to the input of an infinite impulse response (IIR) filter 374 which produces an error measure MSE from a weighted sum of the squared error calculations over a sliding window of one or more samples.

[0062] The error measure MSE output by the MSE calculation circuitry 340 is forwarded to the minimum / maximum estimator logic 380 , which is constructed and configured to identify the minimum value MSE of the error measures MSE generated by the MSE calculation circuitry 340 min and the maximum MSE max The minimum error value MSE min and the maximum error value MSE max Forward to Figure 3C The MSE monitor logic 382 is configured to receive the error measurement MSE from the MSE calculation circuit system 340 relative to the MSE monitor logic 382 based on the minimum error value MSE. min Or in some embodiments, based on the minimum error value MSE min And the maximum error value MSE maxBased on its monitoring of the error measurement MSE, the MSE monitor logic 382 is further configured to initiate operation of the timing loop by generating a start signal TLOOP_STRT to the TED circuitry 350 .

[0063] exist Figure 3A In the example architecture of FIG. 3 , minimum / maximum estimator logic 380 and MSE monitor logic 382 are shown as being included within sequencer logic 330. Alternatively, these logic functions and circuitry may be incorporated within MSE calculation circuitry 340 itself, or elsewhere within symbol timing recovery and equalization circuitry 300 as desired for a particular implementation.

[0064] Reference now Figure 4 Now we will describe the Figure 3A The operation of the receive path of the PHY 106 of the architecture of FIG. 1 , which includes the AFE 216, the clock generator circuitry 220, and the symbol timing recovery and equalization circuitry 300. According to this method, the activation of the timing loop for adjusting the phase of the sampling clock SCLK is controlled to occur at a time when the DFE 320 has converged to a low error condition to facilitate joint convergence of the sampling timing and equalization of the receive path.

[0065] Operation starts with the receive path in an idle state, such as Figure 4 400. When PHY 106 is started to receive incoming communications from the network, process 402 is first performed to set the gain of programmable gain amplifier 304 in AFE 216, and then digital AGC 310 is set based on the measurement of channel conditions by CAGC 314 in process 404. If not previously selected or otherwise established, the tap weights in FFE 312 in symbol timing recovery and equalization circuitry 300 may also be set in process 404.

[0066] In process 406, the sequencer logic 330 in the symbol timing recovery and equalization circuit system 300 initializes the frequency of the sampling clock SCLK to the initialization frequency f init Initialization frequency f init is selected to be a frequency slightly higher than the symbol frequency of the signal received from the network at AFE 216, for example, as set according to the network standard. For the example of "Gigabit Ethernet" over copper wire operating according to IEEE Standard 802.3ab for the physical layer, the symbol frequency is at a nominal frequency of 125 MHz with a tolerance of ±200 ppm. In the example described, the initialization frequency f initSet to a frequency slightly outside and above the tolerance band, for example, at +400ppm from the nominal frequency of 125MHz, to ensure that the initialization frequency f init is higher than the symbol frequency of the incoming signal. Figure 3A In the architecture of FIG. 1 , the sequencer logic 330 sends an appropriate initialization frequency signal f to the adder 354. init to perform process 406. Adder 354 then controls NCO 356 to issue appropriate "up" pulses of control signal UP / DN to phase interpolator 362 in clock generator circuitry 220. At initialization frequency f init At this point, the phase interpolator 362 advances the phase of the sampling clock SCLK in each sample period to produce a sampling frequency slightly higher than the symbol frequency of the received signal. At this point, the timing loop including the TED circuit system 350 is disabled or otherwise inoperable to allow the clock generator 220 to generate a sampling frequency slightly higher than the symbol frequency of the received signal. init The phase of the sampling clock SCLK is advanced in each symbol period. Therefore, the sampling point will be advanced with each symbol period, and eventually and periodically surround the entire symbol interval.

[0067] In process 406, the initialization frequency f is set init Then, in process 408, the initialization frequency f init The coefficients of DFE 320 are adapted over a plurality of samples obtained from the received signal at . For example, the operation and adaptation process 408 continues sufficiently to make the higher initialization frequency f init The symbol interval is wrapped around at least once, and preferably more than once, for a plurality of sample periods. Figure 5A The behavior of the adaptive process 408 is shown for an example implementation in which the digital filter 325 is second order, thereby adapting two tap weights w1 and w2. Figure 5A As shown in FIG. 4 , after executing process 408 for approximately 4600 samples, due to the initialization frequency f init At least about 200 ppm higher than the symbol frequency of the received signal, the values ​​of the tap weights w1 and w2 change with the sampling clock SCLK at the initialization frequency f init The phase below starts to oscillate around the symbol interval.

[0068] In process 410, MSE calculation circuitry 340 in symbol timing recovery and equalization circuitry 300 calculates and monitors error measurement MSE based on the output of DFE 320. Considering that DFE 320 is generally not well adapted early in process 408, MSE monitoring process 410 may start from the first sample obtained in process 408, or may start later in process 408. Similarly, when the values ​​of tap weights w1 and w2 are as shown in FIG. Figure 5AIn the example shown in the oscillation example, the error measurement MSE is increased with the sampling clock SCLK at the initialization frequency f init The phase below oscillates around the symbol interval. Figure 5B An example of calculation of the error measure MSE in process 410 is shown during operation and adaptation process 410. In this example, the error measure MSE has a local minimum at about 4600 samples, with deeper minima occurring at about 5600 samples, 6400 samples, 7200 samples, and so on.

[0069] Figure 4 The process 410 of the method further comprises determining a threshold error measure MSE thr .exist Figures 3A to 3C In this example, the error measurement threshold MSE in process 410 is thr The determination of the MSE monitor logic 382 of the sequencer logic 330 is based on at least the minimum error measurement MSE observed by the minimum / maximum estimator logic 380 on the samples processed during the adaptation of the DFE 320 in process 408. min For example, the error measurement threshold MSE thr The minimum error measure MSE observed on the sample can be calculated in process 410 as min Add the difference Δ from the minimum (e.g., MSE thr =MSE min The difference Δ may be a fixed value or may be based on the minimum error measure MSE observed during adaptation of the DFE 320 min MSE and maximum error measurement max The difference between , such that:

[0070] MSE thr =MSE min + [σ(MSE max -MSE min )] (5)

[0071] where σ is the chosen fraction.

[0072] In process 410, an error measurement threshold MSE is determined. thr Thereafter, as the symbol timing recovery and equalization circuitry 300 receives additional incoming symbols, the MSE monitor logic 382 continues to monitor the error measurement MSE. In decision 411, during this monitoring period, the MSE monitor logic 382 determines whether the most recent error measurement value MSE(n) is below the error measurement threshold MSE determined in process 410. thr If not ("No" in decision 411), the DFE 320 is adapted again based on the sign and monitoring continues.

[0073] In response to the error measurement value MSE(n) being lower than the error measurement threshold MSE thr (Decision 411 is "yes"), the sequencer logic 330 starts the operation of the timing loop, for example, by sending a signal to the MSE monitor logic 382. Figure 3A The TED circuit system 350 in the example architecture of FIG. 1 issues a control signal TLOOP_START. In response to the control signal TLOOP_START, the TED circuit system 350 operates to generate a timing error signal ted. Figures 3A to 3C In the example implementation of FIG. 3 , for example, according to equation (4) described above, the timing error signal ted is based on the residual samples x(n) and the symbol stream t(n) from the input and output of the slicer 324 of the DFE 320, respectively. The operation of the timing loop of the TED circuit system 350, the loop filter 352, the adder 354, the NCO 356, and the PI 362 may be responsive to the timing error signal ted to first coarsely and then finely adjust the phase of the sampling clock SCLK to achieve convergence more quickly. Figure 4 As shown in FIG, a coarse adjustment of the sampling phase is first performed in process 414, and then a fine adjustment of the sampling phase is performed in process 416. If desired, continued adaptation of the DFE 320 may be performed in conjunction with the adjustment of the timing loop in processes 414, 416, given that the error measure MSE is near its minimum at this point in the process.

[0074] After fine tuning the timing loop in process 416 , steady state operation of the receive path of the PHY 106 , which includes the AFE 216 and the symbol timing recovery and equalization circuitry 300 , is performed in state 420 .

[0075] According to this example, joint convergence of equalization and sample timing in a network receiver can be quickly and accurately achieved even in implementations where the equalization and timing loops are interdependent. By applying a higher initialization frequency f during equalizer adaptation init The equalizer tap weights that provide relatively low error are identified, and the timing loop is started with the equalizer under the low error condition to obtain such convergence. In other words, the sampling phase adjustment is started at the point where the equalizer is close to converging on the correct coefficient value, which reduces the time required for the timing loop to converge and the accuracy of the convergence.

[0076] According to an alternative example, as the phase of the sampling clock wraps around the symbol interval of the incoming analog signal, the periodicity of the oscillation error measurement is used to provide an initial phase adjustment when starting the timing loop adjustment. Figure 5B As shown in FIG. , the ADC 308 is initialized at a frequency f initThe oscillation error measurement MSE obtained when sampling the received signal exhibits a period T MSE Combining these examples, it has been observed that the initialization frequency f init The frequency offset f from the symbol frequency of the incoming signal received from the network delta Available from T MSE This periodicity determination at is used to derive an initial phase correction for the sampling clock.

[0077] Fig. 6A The architecture of certain circuitry in the receive path of PHY 106 according to this alternative example is shown. Fig. 6A The same reference numerals are used to show Figure 3A The same or similar features or functions shown in the arrangement of Fig. 6A In this alternative embodiment, Fig. 6A The symbol timing recovery and equalization circuitry 600 performs symbol timing recovery operations from the symbol stream produced by the AFE 216 and adaptation for equalization as part of the clock and data recovery operations performed on the symbol stream from the AFE 216. Figure 3A In the architecture, the symbol timing recovery and equalization circuit system 600 constitutes part of the circuit system of the receive processing block 202RX of the PHY 106, and can be similarly implemented as an embedded or independent DSP, or as a custom, semi-custom, dedicated or other logic circuit system (programmable or hard-wired), etc.

[0078] The digitized symbol stream produced by AFE 216 and then applied to digital AGC function 310 and FFE 312 is in turn applied to DFE 620. DFE 620 in this alternative embodiment is arranged similarly to DFE 320 described above, but in this example is arranged to allow selective adaptation of its high-order tap weights w2 to w3 relative to its first-order tap weights w1 (tap 625a). m (Tap 625b).

[0079] Each of the TED circuitry 350, loop filter 352, and NCO 356 in the timing loop symbol timing recovery and equalization circuitry 600 according to this alternative embodiment is similarly described above with respect to Figure 3A The sequencer logic 630 is configured similarly to the sequencer logic 330 described above and therefore includes MSE monitor logic for monitoring the error measurement MSE generated by the MSE calculation circuitry 640. However, according to Fig. 6A In this alternative embodiment, MSE calculation circuitry 640 is configured differently from MSE calculation circuitry 340 described above.

[0080] Figure 6B 6 shows the configuration of the MSE calculation circuitry 640 in this example implementation of the symbol timing recovery and equalization circuitry 600. The MSE calculation circuitry 640 includes an adder 670 whose input is coupled to the DFE 620 to receive the residual samples x(n) and the symbol stream at the input and output of the slicer 624 in the DFE 620. The adder 670 is configured to subtract each symbol from its corresponding residue x(n) And the difference is provided to the square function 672. The square function 672 outputs the square of the difference from the adder 670 to be applied to the IIR 674, which produces the error measurement MSE as a weighted sum of the squared difference values ​​over a sliding window of sample periods. Similarly, the error measurement MSE for each sample is forwarded to the MSE monitor logic in the sequencer logic 630 as described above.

[0081] In such Figure 6B , MSE calculation circuitry 640 also includes min / max estimator logic 680, counter 682, and lookup table (LUT) 684. Alternatively, some or all of min / max estimator logic 680, counter 682, and LUT 684 may be implemented in sequencer logic 630, or in separate logic or other circuitry included in symbol timing recovery and equalization circuitry 600.

[0082] In this example, the minimum / maximum estimator logic 680 is constructed as logic circuitry or functionality that is configured to identify certain error metrics from the value of the error measurement MSE. In this example, the minimum / maximum estimator logic 680 is configured to calculate the error measurement threshold MSE based on which the timing loop is started. Thr_seq , and generate the minimum error measure MSE min and the maximum error measure MSE max The arithmetic mean of the corresponding error midpoint value MSE mid In this embodiment, the error measurement threshold MSE is Thr_seq Forwarded to sequencer logic 630 ( Fig. 6A ), and the error midpoint value MSE mid is forwarded to a counter 682 in the MSE calculation circuitry 640. The counter 682 also receives an error measurement MSE at an input.

[0083] In this example, the counter 682 is operable to measure the error midpoint value MSE by the error measurement MSE midThe time between the crossing points of the error measurement is determined by, for example, counting the cycles of the clock signal between the midpoint crossing points and forwarding the count or time measurement to LUT 684. In this embodiment, LUT 684 is a binary data structure that stores count values ​​corresponding to the cycles of the error measurement to the frequency offset f. delta The mapping is based on the following relationship:

[0084] θ=2π(f deta ·T SYM ) (6)

[0085] where θ is the frequency shift f delta The sample period T generated SYM Therefore, for the frequency offset f delta Correction of the phase offset θ at can place the sampling clock SCLK at the correct frequency that matches the symbol period. In this example, the count output by the counter 682 is applied as an address to the LUT 684, and in response to the address, the LUT 684 reads and outputs the mapping stored at the address as the frequency offset f delta .like Fig. 6A As shown in FIG. , the frequency offset f output by LUT 684 is delta The output of loop filter 352 and the initialization frequency f from sequencer logic 630 init Applied together to the input of adder 654.

[0086] According to this alternative embodiment, when the phase of the sampling clock SCLK is changed according to the initialization frequency f init The frequency offset f determined by the MSE calculation circuitry 640 is advanced in each symbol period. delta The frequency offset f determined by the MSE calculation circuitry 640 is thus periodic around the symbol period. delta Used to derive frequency correction of the sampling clock SCLK.

[0087] Figure 7 A method for timing recovery and equalization adaptation based on this observation according to this alternative example is shown. In this method, the timing recovery and equalization adaptation based on this observation are shown. Figure 4 The process 402 to 408 is performed from the idle state 400 in the manner described, including the symbol timing recovery and equalization circuit system 600 initializing the frequency f init The DFE 620 is adapted during operation.

[0088] According to this example implementation, if the network channel is short, such as 10 meters or less, the DFE adaptation process 408 may only adapt the high-order tap weights w2 to w m, without adapting the first-order tap weight w1. This DFE adaptation for short channels is based on the observation that the ISI post-phase P1 is typically very small in short channels and may be negative due to the influence of the HPF 302 in the AFE 216. It has been observed in conjunction with this embodiment that adapting the first-order tap weight w1 during timing loop adjustment may be beneficial in such cases.

[0089] In process 710, the MSE calculation circuitry 640 generates an error measure MSE for each sample, as described above with respect to Figure 4 In this implementation, the minimum / maximum estimator logic 680 is configured to measure the observed minimum MSE value based on the error generated by the MSE calculation circuitry 640. min and the maximum MSE max Either or both of these are used to calculate the error measurement threshold MSE thr_seq For example, the min / max estimator logic 680 may measure the MSE based on the minimum error observed over a number of samples. min Add the difference Δ to determine the error measurement threshold MSE thr_seq This difference Δ may be a fixed value, or may be based on the minimum error measure MSE observed during adaptation of DFE 620 min MSE and maximum error measurement max Once calculated, the error measurement threshold MSE is used thr_seq Forwarded to sequencer logic 680.

[0090] In process 712, the MSE calculation circuit system 640 calculates the MSE value based on the initialization frequency f init The frequency offset f is generated by measuring the periodicity of the error MSE of the samples obtained under delta In this example, the error measurement MSE is measured by counter 682 against the error midpoint value MSE. mid The clock cycles between the crossing points of are counted and the count is applied to LUT 684 to obtain the offset frequency f delta to measure this periodicity.

[0091] In process 714, the offset frequency f determined in process 712 is delta Together with the initialization frequency f from the sequencer logic 630 init The sum output by the adder 654 is applied to the NCO 356, which in turn applies the control signal UP / DN to the PI 362, thereby adjusting the frequency of the sampling clock SCLK to obtain samples of the received signal at the ADC 308.

[0092] The MSE monitor logic in the sequencer logic 630 continues to monitor the error measurement MSE as the symbol timing recovery and equalization circuitry 600 receives additional incoming symbols, thereby comparing the new value of the error measurement MSE to the error measurement threshold MSE. thr_seq In decision 715, sequencer logic 630 determines whether the most recent error measurement value MSE(n) is below the error measurement threshold MSE determined in process 710. thr_seq If not ("No" at decision 715), then the DFE 620 is adapted again based on the symbol in process 716 and monitoring continues.

[0093] In response to the error measurement value MSE being lower than the error measurement threshold MSE thr_seq (Decision 715 is "yes"), sequencer logic 630, for example, by sending Fig. 6A The TED circuit system 350 in the example architecture of FIG. 60 issues a control signal TLOOP_START to start the operation of the timing loop, as described above. In response to the control signal TLOOP_START, the TED circuit system 350 operates to generate a timing error signal ted for application to the adder 654 via the loop filter 352. In this embodiment, the TED circuit system 350 generates a timing error signal ted based on the residual samples x(n) at the input and output of the limiter 624 of the DFE 620 and the symbol stream The difference between Figures 3A to 3C Operate similarly as described.

[0094] The operation of the timing loop of the symbol timing recovery and equalization circuitry 600 may be performed in stages to achieve convergence more quickly starting with the coarse timing adjustment in process 720. Figure 7 As shown in , a fine tuning or adjustment of the sampling phase is then performed in process 722, where such adjustment is based on the timing error detected after the coarse timing adjustment process 720. If the network channel is a short channel, as may be determined from a measurement of the gain required at the PGA 304, for example, then the first-order tap weights w1 (tap 625a) of the DFE 620 may only be adapted during the fine tuning process 722 to the extent that they were not previously adapted in process 408, as mentioned above.

[0095] In either case, after fine tuning the timing loop in process 722 , steady-state operation of the receive path of the PHY 106 , including the AFE 216 and the symbol timing recovery and equalization circuitry 600 , may then be performed in state 730 .

[0096] According to this alternative example, joint convergence of equalization and sample timing in network reception can be achieved quickly and accurately even in implementations where the equalization and timing loops are interdependent. The frequency offset f is determined by measuring the periodicity of the error MSE over multiple cycles. delta And the frequency offset is incorporated into the phase adjustment of the sampling clock SCLK to promote convergence. Then, when the timing loop correction is started at a point where the decision feedback equalizer coefficients have been adapted to values ​​that exhibit relatively low errors and are therefore close to converging at the correct values, the time required for the timing loop to converge can be reduced.

[0097] As used herein, the terms "terminal", "node", "interconnection" and "pin" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to the interconnection between device elements, circuit elements, integrated circuits, devices or other electronic devices or semiconductor components or their terminals.

[0098] Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10% of the stated value. Modifications may be made in the described examples, and other examples may be made within the scope of the claims.

[0099] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0100] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, for example, by an end user and / or a third party. While in some examples, certain elements are included in the integrated circuit and other elements are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features described as being external to the integrated circuit may be included in the integrated circuit, and / or some features described as being internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / on a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0101] The circuits described herein can be reconfigured to include replaced components to provide functionality at least partially similar to functionality available before component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the displayed resistor. For example, a resistor or capacitor shown and described herein as a single component may alternatively be a plurality of resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described herein as a single component may alternatively be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor, respectively.

[0102] Although certain elements are described above as being included in an integrated circuit and other elements being external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features described as being external to the integrated circuit may be included in the integrated circuit, and / or some features described as being internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that: (i) are incorporated in / on a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated in the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0103] The use of the phrase "ground" in the foregoing description includes chassis ground, ground wire ground, floating ground, virtual ground, digital ground, universal ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10% of the value, or if the value is zero, means a reasonable range of values ​​around zero.

[0104] Although one or more examples have been described in this specification, it is of course considered that a person skilled in the art will understand modifications and alternatives to these examples after referring to this specification and its drawings, and such modifications and alternatives can achieve one or more of the technical effects of these examples. It is considered that such modifications and alternatives are within the scope of the claims presented herein.

Claims

1. A method comprising: sampling an input analog signal having a symbol frequency in response to a sampling clock initially at a frequency greater than a symbol frequency; converting a sampled input analog signal into a stream of digital samples; equalizing the digital sample stream using a decision feedback equalizer to produce an output digital stream; adapting at least one tap weight of the decision feedback equalizer; calculating an error measure from the output sample stream; as well as In response to the error measure exceeding an error threshold, a phase of the sampling clock is adjusted.

2. The method of claim 1, wherein the step of calculating the error measure comprises calculating a mean square error for each of the plurality of samples.

3. The method of claim 2, wherein the equalizing step comprises: applying a digital filter to samples in the output digital stream to produce a feedback signal, the digital filter comprising the at least one tap weight; subtracting the feedback signal from samples in the digital sample stream to produce a post-filtered sample stream; as well as limiting the trailing filtered samples to produce the output digital stream; as well as And the step of calculating the mean square error includes: For each of a plurality of samples, the mean square error is generated from a difference between the subsequent filtered sample and the output digital stream.

4. The method of claim 1, wherein the adjusting step comprises: The phase of the sampling clock is adjusted to minimize a timing error function of the output digital stream.

5. The method of claim 4, wherein the step of calculating an error measure comprises: Calculate the mean square error for each of the multiple samples; identifying a minimum value of the mean square error over the plurality of samples; as well as calculating the error threshold relative to the identified minimum value of the mean square error measure; And wherein the adjusting step adjusts the phase of the sampling clock in response to the error measure being below the error threshold.

6. The method of claim 1 , wherein the step of calculating an error measure comprises: Calculate the mean square error for each of the multiple samples; observing a periodicity of the mean square error over the plurality of samples; And wherein the adjusting step comprises: Calculate the frequency shift corresponding to the observed periodicity of the minimum; as well as The phase of the sampling clock is adjusted according to the frequency offset.

7. The method of claim 6, wherein the step of calculating the adjusted sampling frequency comprises: identifying a minimum value and a maximum value of the mean square error; identifying a threshold of the mean square error based on the minimum and maximum values; measuring the time intervals between the crossing points of the thresholds by the mean square error; The measured time interval is mapped to the frequency offset.

8. The method according to claim 7, further comprising: receiving the input analog signal from a communication channel; And wherein the adjusting step further comprises: After adjusting the phase of the sampling clock according to the adjusted sampling frequency, further adjusting the phase of the sampling clock to minimize a timing error function of the output digital stream at a first adjustment step size; as well as The phase of the sampling clock is then further adjusted to minimize a timing error function of the output digital stream at a second adjustment step size that is smaller than the first adjustment step size.

9. The method according to claim 8, comprising: determining whether the communication channel has a length below a length threshold; and wherein the adjusting step comprises, in response to the communication channel having a length below the length threshold: After adjusting the phase of the sampling clock according to the adjusted sampling frequency, further adjusting the phase of the sampling clock to minimize a timing error function of the output digital stream only at the second adjustment step size.

10. A network communication receiver, comprising: a data converter adapted to receive an analog signal at an input and output a stream of digital samples at an output, the analog signal having a symbol frequency, the data converter being configured to sample the analog signal in response to a sampling clock signal and convert the sampled signal into the stream of digital samples; clock generation circuitry configured to generate the sampling clock signal at a phase and frequency in response to a clock control signal, the clock generation circuitry coupled to the data converter; a digital receiver circuitry having an input coupled to the output of the data converter to receive the digital sample stream, and comprising: a decision feedback equalizer (DFE) comprising a digital filter having one or more tap weights and configured to produce an output digital stream from the digital sample stream; error measurement circuitry coupled to the DFE and configured to measure errors in samples of the output digital stream; clock control circuitry coupled to the DFE and configured to generate the clock control signal; a sequencer logic coupled to the DFE, the error measurement circuitry, and the clock control circuitry, the sequencer logic configured to control operation of the decision feedback equalizer, the error measurement circuitry, and the clock control circuitry according to a plurality of operations, the plurality of operations comprising: generating a clock control signal in response to an initialization frequency signal corresponding to a frequency higher than the symbol frequency of the received analog signal; adapting at least one of the tap weights of the adaptive equalizer; computing an error measure from the output sample stream; and In response to the error measurement exceeding an error threshold, the clock control signal is adjusted.

11. The receiver of claim 10, wherein the digital receiver circuitry further comprises: timing error detection circuitry configured to calculate a timing error signal from the output digital stream; And wherein the sequencer logic is configured to control the timing error detection circuitry to generate a clock control adjustment to the clock control signal in response to the error measurement exceeding the error threshold.

12. The receiver of claim 11 , wherein the error measurement circuitry is configured to: calculating the mean square error among the samples of the output sample stream, and identifying a minimum value of the mean square error over a plurality of samples of the output sample stream; And wherein the sequencer logic is further configured to generate a start signal to the timing error detection circuitry in response to the error measure being below an error threshold determined from the minimum value of the mean square error.

13. The receiver of claim 10, wherein the error measurement circuitry is configured to: Calculating a mean square error among samples of the output sample stream; identifying a periodicity in the mean square error over a plurality of samples of the output sample stream; as well as calculating a frequency offset of the identified periodicity corresponding to a mean square error; Wherein the clock control circuitry is configured to adjust the clock control signal in response to the frequency offset.

14. The receiver of claim 13, wherein the error measurement circuitry is configured to calculate the adjusted sampling frequency by: identifying a minimum value and a maximum value of the mean square error; identifying a threshold of the mean square error based on the minimum and maximum values; measuring the time intervals between the crossing points of the thresholds by the mean square error; as well as The measured time interval is mapped to the frequency offset.

15. The receiver of claim 10, wherein the digital receiver circuitry further comprises: A feed-forward equalizer is configured to equalize the digital sample stream prior to the decision feedback equalizer.

16. The receiver of claim 10, wherein the clock generation circuitry comprises: a phase-locked loop configured to generate a clock signal at a frequency based on a reference clock; as well as A phase interpolator has an input receiving the clock control signal, an input receiving the clock signal from the phase locked loop, and is configured to generate the sampling clock signal at a phase in response to the clock signal and the clock control signal.

17. A physical layer transceiver, comprising: Media Independent Interface; Medium dependent interface; a transport processing block coupled to the medium independent interface; a transmitter subsystem coupled between the transport processing block and the medium dependent interface, the transmitter subsystem configured to transmit an analog signal corresponding to data from the transport processing block through the medium dependent interface; a data converter coupled to the medium dependent interface and adapted to receive an analog signal from the medium dependent interface, the analog signal having a symbol frequency, the data converter being configured to sample the analog signal in response to a sampling clock signal and convert the sampled signal into a stream of digital samples; clock generation circuitry coupled to the data converter and configured to generate the sampling clock signal at a phase and frequency in response to a clock control signal; as well as a receive processing block coupled to the medium independent interface and comprising: A symbol timing recovery and equalization circuit system comprising: a decision feedback equalizer comprising a digital filter having one or more tap weights and configured to produce an output digital stream from the digital sample stream; error measurement circuitry coupled to the decision feedback equalizer and configured to measure errors in samples of the output digital stream; clock control circuitry coupled to the error measurement circuitry and configured to generate the clock control signal; and a sequencer logic coupled to the decision feedback equalizer, the error measurement circuitry, and the clock control circuitry, the sequencer logic configured to control operation of the decision feedback equalizer, the error measurement circuitry, and the clock control circuitry according to a plurality of operations, the plurality of operations comprising: generating a clock control signal in response to an initialization frequency signal corresponding to a frequency higher than the symbol frequency of the received analog signal; adapting at least one of the tap weights of the adaptive equalizer; computing an error measure from the output sample stream; and In response to the error measurement exceeding an error threshold, the clock control signal is adjusted.

18. The transceiver of claim 17, wherein the error measurement circuitry is configured to: calculating the mean square error among the samples of the output sample stream, and identifying a minimum value of the mean square error over a plurality of samples of the output sample stream; And wherein the sequencer logic is further configured to generate a start signal to the timing error detection circuitry in response to the error measure being below an error threshold determined from the minimum value of the mean square error.

19. The transceiver of claim 17, wherein the error measurement circuitry is configured to: Calculating a mean square error among samples of the output sample stream; identifying a periodicity in the mean square error over a plurality of samples of the output sample stream; as well as calculating a frequency offset of the identified periodicity corresponding to a mean square error; Wherein the clock control circuitry is configured to adjust the clock control signal in response to the frequency offset.

20. The transceiver of claim 19, wherein the error measurement circuitry is configured to calculate the adjusted sampling frequency by: identifying a minimum value and a maximum value of the mean square error; identifying a threshold of the mean square error based on the minimum and maximum values; measuring the time intervals between the crossing points of the thresholds by the mean square error; as well as The measured time interval is mapped to the frequency offset.

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