Component carrier having embossed design layer structure and embedded with component

Abstract

A component carrier (100), the component carrier comprising: a stack (102) comprising at least one electrically conductive layer structure (104) and at least one electrically insulating layer structure (106) wherein the at least one electrically insulating layer structure (106) comprises at least one design layer structure (108, 110) having an embossed surface profile; and a component (112) embedded in the stack (102) and at least partially covered by the at least one design layer structure (108, 110).

Description

Technical Field

[0001] The invention relates to a component carrier and to a method for producing a component carrier. Background Art

[0002] Against the background of the increasing product functionality of component carriers equipped with one or more electronic components and the increasing miniaturization of such electronic components and the increasing number of electronic components to be mounted on component carriers such as printed circuit boards, increasingly powerful array-like components or packages with a plurality of electronic components are being used, which have a plurality of contacts or connections, wherein the spacing between these contacts is increasingly smaller. The removal of heat generated by such electronic components and by the component carriers themselves during operation is becoming an increasing problem. At the same time, the component carriers should be mechanically robust and electrically reliable in order to be able to operate even under severe conditions.

[0003] It is still difficult to produce electrically conductive connections of component carriers in a simple manner and with high precision, in particular when inserting components. Summary of the invention

[0004] The object of the invention is to create a component carrier with embedded components and electrically conducting structures which can be produced in a simple manner and with high precision.

[0005] In order to achieve the objects defined above, a component carrier and a method for producing the component carrier according to the independent claims are provided.

[0006] According to an exemplary embodiment, a component carrier is provided, which comprises: a stack including at least one electrically conductive layer structure and at least one electrically insulating layer structure, wherein the at least one electrically insulating layer structure comprises at least one design layer structure having an embossed surface contour; and a component, which is embedded in the stack and at least partially covered by the at least one design layer structure (in particular, such that the embedded component shares a common connection surface with at least one of the at least one design layer structures, or such that the embedded component is directly physically connected to at least one of the at least one design layer structures).

[0007] According to another exemplary embodiment, a method for manufacturing a component carrier is provided, wherein the method comprises: forming a stack comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure; embossing a surface contour in at least one design layer structure of the at least one electrically insulating layer structure; and embedding a component in the stack such that the component is at least partially covered by the at least one design layer structure.

[0008] In the context of the present application, the term "component carrier" may particularly denote any support structure on which and / or in which one or more components can be accommodated to provide mechanical support and / or electrical connection. In other words, the component carrier may be configured as a mechanical and / or electronic carrier for the components. In particular, the component carrier may be one of a printed circuit board, an interposer and an IC (integrated circuit) substrate. The component carrier may also be a hybrid board combining different types of component carriers of the above-mentioned types of component carriers.

[0009] In the context of the present application, the term "stack" may particularly denote an arrangement of a plurality of flat layer structures mounted parallel to one another.

[0010] In the context of the present application, the term "layer structure" may particularly denote a continuous layer, a patterned layer, or a plurality of non-continuous islands in a common plane.

[0011] In the context of the present application, the term "design layer" may refer to a layer that can be flexibly processed to design substantially any desired surface contour extending therein and / or extending through it. Thus, any desired wiring design can be converted into a corresponding surface contour of the design layer so that filling the recess created in the design layer with an electrically conductive material can result in a predetermined wiring design. Preferably, the design layer may be an initially at least partially uncured dielectric that may be cured during and / or after forming a predetermined surface contour therein. The surface contour may then be made permanent. Thus, the design layer is deformable before curing and non-deformable after curing. Preferably, the design layer may be made of nanoimprint lithography (NIL) material. The design layer may or may not form a part of a component carrier that is easy to manufacture. Preferably, one or more recesses in the design layer structure may have different horizontal extensions and / or vertical extensions. Alternatively, one or more recesses in the design layer structure may be identical.

[0012] In the context of the present application, the term "embossing a surface contour portion in a design layer" may refer to the process of embossing or embossing a predetermined surface graphic portion in a design layer. For example, this can be accomplished by pressing a working mold (or a working embossing piece) into a (particularly stationary) deformable design layer or by guiding the working mold along a (particularly stationary) deformable design layer. Such a working mold may have a surface contour portion that is opposite to the surface contour portion of the processed design layer. During the development and manufacturing process, a master mold may first be manufactured, for example, by grayscale lithography. Then, the master mold may be replicated into a transparent silicone material or a similar material by embossing several times, and a master working mold may be generated. Finally, a working mold may be made by replicating the master working mold. The working mold may be used during mass production and may be embossed on the panel surface.

[0013] In the context of the present application, the term "embossed surface profile" may refer to a surface profile having a feature structure produced by an embossing process performed by pressing a working mold into a design layer. Due to this manufacturing process, the embossed surface profile has lower roughness, steeper sidewalls and other graphic features than the surface profile obtained by an etching-based or laser-based patterning process. The features of the embossed surface profile are disclosed herein.

[0014] In the context of the present application, the term "component" may particularly denote an inlay, which for example fulfills an electronic task and / or a thermal task. For example, the electronic component may be a semiconductor chip comprising a semiconductor material, in particular as primary or basic material. The semiconductor material may for example be a type IV semiconductor such as silicon or germanium, or may be a type III-V semiconductor material such as gallium arsenide. In particular, the semiconductor component may be a semiconductor chip such as a bare wafer or a molded wafer.

[0015] In the context of the present application, the term "embedded component" may refer to a component that is at least partially placed inside a stack (rather than surface mounted on a major surface of the stack). For example, the embedded component may be inserted into a through hole, a blind hole, or a cavity of the stack. The two major surfaces of the embedded component may be located inside the stack. Alternatively, one or two major surfaces of the embedded component may extend vertically beyond the corresponding major surface of the stack. However, at least a portion of the embedded component should be located inside the stack.

[0016] In the context of the present application, the term "main surface" of a body may particularly denote one of the two opposite largest surfaces of the body. The main surfaces may be connected by a circumferential sidewall. The thickness of a body such as a stack may be defined by the distance between the two opposite main surfaces.

[0017] According to an exemplary embodiment of the present invention, a component carrier (such as a printed circuit board, PCB) having a (preferably laminated) stack of layers is provided, the stack of layers having one or more designed layer structures (preferably, which may be made of nanoimprint lithography (NIL) material) with an imprinted surface contour. At least one component (such as a semiconductor chip) can be embedded in the stack and can be directly physically connected to the designed layer structure. Advantageously, due to the definition of the trace or wiring structure and / or the definition of the vertical through-connection portion by the designed layer structure and its imprinted surface contour, such a component carrier can be manufactured with high spatial precision. Therefore, even tiny electronic components with a large number of input / output pads can be reliably connected inside the component carrier. This may result in a highly compact component carrier embedded with one or more components and having excellent electrical reliability. For example, embedding components in a NIL dielectric can provide high precision of the formed electrical connection structure and a small number of processing stages. In addition, the pads and traces can be manufactured in a common process and have a high surface smoothness, which may be advantageous in particular for high-frequency applications.

[0018] In the following, further exemplary embodiments of the component carrier and the method will be explained.

[0019] In an embodiment, the electrically conductive traces of the at least one electrically conductive layer structure defined by the at least one design layer structure have a roughness Ra of less than 100 nm, in particular a roughness Ra of less than 50 nm. Ra represents the arithmetic mean of all distances of the contour portion from the center line. For example, the measurement or determination of the roughness Ra can be carried out according to DIN EN ISO 4287:2010. The mentioned roughness values ​​may result in low-loss transmission of radio frequency signals through one or more wiring structures, because there is no excessive surface roughness that degrades signal propagation in the case of taking into account the skin effect. According to the skin effect, electrical signals with high frequencies, for example in the gigahertz range, do not propagate over the entire cross-section of the conductor, but essentially only within the skin-like surface portion. This usually results in significant signal losses in the case of rough surfaces. Without wishing to be bound by a particular theory, it is currently believed that such signal losses may be caused by the fact that the traveling radio frequency signal is subjected to additional resistance or impedance due to the rough surface. Advantageously, such signal losses can be prevented or at least strongly suppressed when the low roughness of the electrically conductive wiring structure of the component carrier is ensured due to the formation of recesses in the design layer by embossing.

[0020] In an embodiment, the vertical through-connection of the at least one electrically conductive layer structure defined by the at least one design layer structure has a depth to diameter ratio greater than 1, in particular, the vertical through-connection of the at least one electrically conductive layer structure defined by the at least one design layer structure has a depth to diameter ratio greater than 1.5. By defining the vertical through-connection by embossing instead of laser drilling or mechanical drilling, a very high aspect ratio of the vertical through-connection can be obtained. This can simplify the manufacturing process and can improve power reliability.

[0021] In an embodiment, a component includes at least one pad that is oriented facing upward and / or oriented facing downward. A component oriented facing upward may refer to a component having at least one pad on its upper major surface (optionally, with or without at least one pad on its lower major surface). A component oriented facing downward may refer to a component having at least one pad on its lower major surface (optionally, with or without at least one pad on its upper major surface). In the case where a component has one or more pads oriented facing upward, an electrical connection to the component may be created by subsequently depositing a design layer from the top side of the component and imprinting the design layer. In addition, the pad facing upward may also be used as an alignment mark.

[0022] In an embodiment, at least one surface portion of one or more connection pads of the component is connected to the at least one design layer structure. The remaining portion of the component may not be directly connected to the design layer structure.

[0023] In an embodiment, at least a portion of a vertical side wall of the embedded component is covered by the at least one design layer structure. In particular, at least five side walls of the embedded component may be at least partially covered by the at least one design layer structure. For example, one of the five side walls may include at least one connection pad. An exception may be the lower main surface of the embedded component, which may be mounted on a connection medium, such as solder or sintering paste.

[0024] In an embodiment, a first portion of the dielectric surrounding portion of the embedded component is formed by a non-imprintable dielectric, in particular, a bottom portion of the dielectric surrounding portion of the embedded component is formed by a non-imprintable dielectric, the non-imprintable dielectric is in particular a resin with reinforcing particles or a resin without reinforcing particles, and a second portion of the dielectric surrounding portion is formed by the at least one designed layer structure, in particular, a top portion of the dielectric surrounding portion is formed by the at least one designed layer structure. Accordingly, the method may comprise: forming a first portion of the dielectric surrounding portion of the embedded component by a non-imprintable dielectric, in particular, a bottom portion of the dielectric surrounding portion of the embedded component is formed by a non-imprintable dielectric, the non-imprintable dielectric is in particular a resin with reinforcing particles or a resin without reinforcing particles; and forming a second portion of the dielectric surrounding portion by the at least one designed layer structure, in particular, a top portion of the dielectric surrounding portion is formed by the at least one designed layer structure. For example, a first portion of the embedded component can be directly physically connected to a standard component carrier dielectric comprising a resin (such as epoxy resin), which optionally includes reinforcing particles (such as glass spheres or glass fibers). In addition, a second portion of the embedded component can be directly physically connected to the dielectric material of the design layer having an embossed surface contour portion. Advantageously, this manufacturing architecture can use standard PCB processes to manufacture a portion of the surrounding portion of the embedded component, while another portion of the surrounding portion can be formed from NIL material. This can keep the overall manufacturing effort reasonable while ensuring fine line routing where necessary.

[0025] In another embodiment, the entire dielectric surround of the embedded component can be formed by the at least one engineered layer structure. By completely surrounding the embedded component with a nanoimprint lithography (NIL) dielectric, a uniform dielectric shell completely circumferentially covers the embedded component (especially together with the metal material). However, in the embodiment described, no non-NIL dielectric will directly cover the embedded component. With such a uniform dielectric surround, no significant CTE (coefficient of thermal expansion) mismatch will occur around the component, thereby improving the thermal reliability of the component carrier.

[0026] In an embodiment, the formation of the entire dielectric surround of the embedded component by the at least one design layer structure is performed by forming a first design layer structure at least partially below the component and stamping the first design layer structure at least partially below the component, and forming a second design layer structure at least partially above the component and stamping the second design layer structure at least partially above the component. Thus, the electronic component can be mounted on the first design layer structure after forming the first design layer structure, stamping the first design layer structure and filling the first design layer structure with metal. Thereafter, a second design layer structure can be formed on top of the first design layer structure and the component, stamping the second design layer structure and filling the second design layer structure, thereby embedding the component in the second design layer structure. Even more than two design layers can be formed to provide a dielectric portion of the stack in which the electronic component is embedded.

[0027] In an embodiment, the embedded component is mounted on at least one of the at least one electrically conductive layer structures by a connecting medium, in particular a sintering material, a solder or an adhesive. For example, the embedded component can be assembled to the stack by thermocompression bonding or hybrid bonding.

[0028] In an embodiment, the at least one design layer structure has at least one recess positioned transversely to the embedded component. Such a recess may be defined by embossing and may have a very high depth-to-diameter ratio, for example, such a recess may have a depth-to-diameter ratio greater than 1. For example, a single (e.g., tapered) recess arranged transversely to the embedded component may extend from above the embedded component to below the embedded component. Such a recess may bridge a vertical extent greater than the vertical extension of the component.

[0029] In an embodiment, the method includes: forming at least one of the at least one design layer structures on a metal base; embossing the at least one of the at least one design layer structures on the metal base, thereby exposing a portion of the metal base; and plating at least a portion of the at least one electrically conductive layer structure on or above the exposed portion of the metal base. Advantageously, the exposed portion of the metal base can be used as an electrode during electroplating (e.g., galvanic plating) to fill recesses of the embossed design layer with an electrically conductive material. To this end, the embossing process can form at least one recess that extends completely through the design layer, thereby exposing the metal base. In an embodiment, a component can be placed on the metal base, and the metal base can be used as a heat sink. For example, in Figures 6 to 8In the embodiment, the corresponding embedded component is located on and above the metal that acts as a heat sink. If the component has pads on both opposing major surfaces, the metal connections connected to these pads can act as heat sinks as well as signal and / or power transmission parts.

[0030] In an embodiment, plating includes electroplating. Electroplating can refer to the process of producing a metal coating on a solid substrate by reducing the cations of the metal by direct current. Specifically, electroplating can be implemented by electroplating. However, the plating process can also include a non-electroplating stage, in particular, the non-electroplating stage is used to prepare for subsequent electroplating. By plating and preferably by electroplating, the recess formed by the embossed contour portion of the design layer can be filled with metal to form an electrically conductive structure, such as a wiring pattern portion and / or a vertical through-connection portion.

[0031] In an embodiment, the method comprises: arranging the components such that at least one pad is arranged face-upwards. Advantageously, the at least one pad arranged face-upwards can be used as an alignment mark for subsequent processing. Thus, the at least one pad can perform a dual function, namely electrically connecting the embedded electronic component and contributing to calibration accuracy.

[0032] In an embodiment, the method comprises: forming a metal base on a release layer, which is in turn arranged on a temporary carrier; forming at least one of the at least one design layer structures on the metal base; and subsequently removing the temporary carrier located at the release layer before completing the manufacture of the component carrier. For example, such a temporary carrier can be a support plate, for example, such a temporary carrier is made of glass, steel or FR4. Preferably, the release layer mentioned can have non-adhesiveness or poor adhesion. Examples of materials for the release layer are release ink, polytetrafluoroethylene, polyimide, wax material or suitable varnish. This allows the easy-to-manufacture component carrier or a preform of the component carrier to be detached from the temporary carrier at the end of the manufacturing process.

[0033] In another embodiment, the method comprises: forming a design layer on a carrier, which does not necessarily include a release layer. As previously mentioned, the carrier can be a temporary carrier that can be removed at the end of the manufacturing process. However, alternatively, the carrier can form a part of a component carrier, in which case the carrier is not removed from the design layer. Such a carrier can also be connected to the design layer - in particular directly - (i.e., a release layer may not be provided between the carrier and the design layer). Such a carrier can be an insulating layer (e.g., including a resin) with or without (in particular, patterned) electrically conductive wiring on the insulating layer. Such electrically conductive wiring allows direct electrical connection from the carrier to the metal base structure. According to an exemplary embodiment of the present invention, a permanent carrier that forms a part of the component carrier can preferably be made of glass. It is particularly preferred that such a component carrier with a glass carrier is constructed as an interposer. Therefore, it may be advantageous to use an additive stack with a NIL to manufacture the interposer, in particular when glass is used as an insulating layer or insulating carrier. Since the interposer can advantageously be made of glass as insulating material, the carrier structure (or another stacked structure) can advantageously be used for a NIL process.

[0034] In an embodiment, a cleaning process may be optionally performed after the design layer structure is embossed and before the material is plated in the recessed portion of the embossed design layer structure. Such a cleaning process may remove residues of the design layer structure, for example, residues of the design layer structure on the metal base structure exposed by the recessed portion of the design layer structure, and may thus ensure a high efficiency of the plating process.

[0035] In an embodiment, the method comprises: providing a core of a stack having a through hole; closing the through hole by attaching a temporary carrier to the bottom of the core; mounting a component in the through hole on the temporary carrier; subsequently partially surrounding the component by a dielectric of the at least one electrically insulating layer structure; subsequently removing the temporary carrier; forming the at least one designed layer structure at the core and at the component; stamping a surface contour in the at least one designed layer structure to expose at least one pad of the component; and forming at least one electrically conductive layer structure of the at least one electrically conductive layer structure in the stamped at least one designed layer structure for connection with the exposed at least one pad. Figures 10 to 14 Such a manufacturing process is described by which a simple process can be combined with fine line patterns on the electrical connection surfaces of embedded electronic components.

[0036] In an embodiment, embossing a surface contour portion in the at least one design layer structure includes: forming a tapered recess in the at least one design layer structure. Accordingly, the electroplated structure created in the corresponding recess may have a tapered sidewall. Advantageously, the embossing of the design layer can be accomplished in the following manner: a working mold (e.g., a glass plate having a surface contour portion on one main surface) deforms the design layer to form a surface contour portion in the design layer that is reversed compared to the surface contour portion of the working mold. After the embossing process, the working mold can be removed from the design layer again. In undesirable situations, due to the adhesion between the design layer and the working mold, it may be difficult to remove the main mold from the design layer after embossing without damaging the shaped surface contour portion. However, it is surprisingly found that providing the working mold with a tapered protrusion corresponding to the reverse tapered recess in the design layer significantly reduces the tendency of the working mold to adhere to the contoured design layer when the working mold is removed after embossing. In addition, this tapered geometry can also reduce the risk of defects in the processed design layer.

[0037] In an embodiment, stamping the surface profile in the at least one design layer structure comprises: forming recesses with different depths and / or different lengths in the at least one design layer structure. Accordingly, the electrically conductive layer structure and / or the metal base structure may form substructures with different depths and / or different lengths in the design layer, or may form a part of a substructure with different depths and / or different lengths in the design layer. For example, at least one first recess formed in the design layer may extend through the entire design layer and may thus form a through hole. When filled with plated metal, such a through hole may form an electrically conductive through-connection (e.g., a via) in a component carrier that is easy to manufacture. For example, at least one second recess formed in the design layer may extend through only a portion of the thickness of the design layer and may thus form a blind hole. When filled with plated metal, such a blind hole may form a horizontally extending trace in a component carrier that is easy to manufacture. Advantageously, the horizontal trace may have a length greater than the length of the vertical through-connection. Using the described manufacturing architecture, the design layer can be formed with two or more recesses extending upward to different vertical positions and / or extending along different horizontal extensions. Thus, even complex horizontal and / or vertical wiring structures can be defined in an accurate and simple manner. In particular, this also makes it possible to create three-dimensional curved wiring structures.

[0038] In an embodiment, imprinting a surface contour portion in the at least one design layer structure includes: forming a trace-shaped recess and / or a via-shaped recess and / or a trace-shaped and via-shaped recess in the at least one design layer structure. Therefore, the electroplating structure and the metal base structure (optionally combined with a portion of the seed layer) can form a trace-shaped substructure and / or a via-shaped substructure or a combination thereof, or can form a portion of a trace-shaped substructure and / or a portion of a via-shaped substructure or a combination thereof. It is very advantageous that both the electrically conductive trace and the vertical through-connection portion can be formed simultaneously and thereby quickly in a micro-size in a common design layer.

[0039] In an embodiment, the method comprises: curing the at least one design layer structure, in particular, simultaneously embossing and curing the at least one design layer structure. During the NIL process, embossing and curing can be performed simultaneously (once embossed, the structure can be exposed to prevent the resist from flowing apart). During the embossing process, the design layer is preferably able to deform freely by mechanical impact, which allows the recess to be embossed in the design layer by the working mold according to the required wiring pattern. After embossing, the created surface contour portion should remain permanent at least in some embodiments, that is, the processed design layer should be converted into a non-deformable state. This can be done by curing the design layer. For example, when the design layer includes at least partially uncured resin, curing can be done by applying heat and / or mechanical pressure, which can trigger curing processes such as crosslinking, polymerization, etc. The supply of curing energy can be completed by irradiating the design layer with electromagnetic radiation, preferably ultraviolet (UV) radiation, using an electromagnetic radiation source. It is very advantageous that the curing of the design layer can be completed during embossing, and further advantageously by the working mold itself. For example, a light source (eg a UV lamp) may be integrated into the working mould so that light-triggered (in particular UV-triggered) curing may be performed during the embossing process.

[0040] In an embodiment, the method includes: forming a stack based on a contoured design layer. Preferably, the stack includes at least one laminated printed circuit board type layer stack. The formation of such a stack may involve processes such as laminating additional electrically conductive layer structures (e.g., copper foil) and / or electrically insulating layer structures (e.g., prepreg sheets) to one or two opposite main surfaces of a separated contoured and metallized design layer. However, in some embodiments, electroplating of the copper layer may be preferred. Then, the component carrier that is easy to manufacture may be a mixture of a contoured and metallized design layer and one or more PCB type stacks of a laminated layer structure.

[0041] In an embodiment, the method comprises: removing residues of the design layer in at least one bottom region of a recess of the contoured design layer, in particular, removing residues of the design layer in at least one bottom region of a recess of the contoured design layer by etching. In particular, when it is intended to form a via extending through the entire design layer, it may happen that, after imprinting, a thin layer of design layer material remains at the bottom of the recess where the via is to be formed. During the formation of the seed layer, such artifacts may lead to undesirable electrical isolation through the remaining thin layer of dielectric. In order to avoid this phenomenon, it may be advantageous to process the imprinted design layer (in particular before the seed layer is formed) by an etching process to remove residues in the recess of the design layer after imprinting.

[0042] In an embodiment, the design layer may always be part of a component carrier that is easy to manufacture, i.e., may be a permanent design layer. The material properties of the design layer may then be adjusted so that a component carrier with high electrical, mechanical and / or thermal reliability is obtained. This may allow suppressing undesirable phenomena such as warping, delamination, mechanical stresses and / or thermal stresses. This may be achieved, for example, by configuring the design layer to have the material properties described herein.

[0043] Next, the advantageous material properties of the designed layer structure will be summarized. The designed layer structure may have one property, any combination of at least two properties, or all of the properties described below.

[0044] The glass transition temperature Tg of the material, in particular the resin material, of the design layer structure may be in the range of 120° C. to 260° C. This may avoid undesired phase changes of the design layer during handling and / or use of the component carrier.

[0045] The value of the Young's modulus below the glass transition temperature Tg may be in the range of 1000 MPa to 15000 MPa. The value of the Young's modulus above the glass transition temperature Tg may be in the range of 60 MPa to 800 MPa. These properties may ensure that the material of the designed layer structure has sufficient mechanical strength, so that accurate design of electrically conductive traces, vertical through-connections, etc., can be achieved in the designed layer structure. At the same time, these properties may ensure that the material of the designed layer structure has sufficient elasticity to buffer thermal and / or mechanical stresses.

[0046] The values ​​of the coefficient of thermal expansion (CTE) below the glass transition temperature Tg may be in the range of 10 ppm / K to 40 ppm / K. The values ​​of the coefficient of thermal expansion above the glass transition temperature Tg may be in the range of 50 ppm / K to 100 ppm / K. These values ​​may suppress thermal stresses within the component carrier.

[0047] The value of the strain at break below the glass transition temperature Tg can be at least 2%. This can lead to advantageous mechanical properties for the design of the layer structure and the correspondingly produced component carrier.

[0048] The value of the chemical shrinkage may be no greater than 3%. Thus, shrinkage-based curing stresses within the component carrier may be avoided.

[0049] The Dk value of the material of the designed layer structure (especially the resin of the designed layer structure) may be no greater than 3. The Df value of the material of the designed layer structure (especially the resin of the designed layer structure) may be no greater than 0.003. Therefore, the obtained component carrier can have excellent performance in terms of high-frequency behavior.

[0050] The number of press cycles that the material of the designed layer structure can withstand can be in the range of 1 to 10. The number of reflow tests that the material of the designed layer structure can withstand can be at least 6. This can allow the component carrier to be manufactured using a designed layer structure with a stack thickness that can be selected in a sufficiently wide range.

[0051] The material of the designed layer structure can be characterized by a peel test on copper of at least 600 N / m. The moisture absorption rate of the material of the designed layer structure can be no more than 0.1%. The decontamination rate of the material of the designed layer structure can be at least 0.006 grams per minute (g / min). The material of the designed layer structure can be characterized by a UL listing from V1 to V0 (according to industrial standards IEC / DIN EN 60695-11-10 and IEC / DIN EN 60695-11-20, in the latest version valid on the priority date of the present application) (this can ensure safety against flammability). The mentioned material properties can simplify the processing of the designed layer structure.

[0052] Advantageously, the engineered layer structure may comprise a resin and a (preferably inorganic) filler (such as filler particles). Optionally, one or more additives may be included in the material of the engineered layer structure to functionalize the engineered layer structure.

[0053] Preferably, the inorganic filler may be in a crystalline state. Additionally and / or alternatively, the inorganic filler may be in an amorphous state. Furthermore, the inorganic filler may be encapsulated. The average size of the inorganic filler may be less than 0.1 μm (calculated as an arithmetic mean). For example, the inorganic filler may be made of molten silicon oxide. The inorganic filler particles may be plasma etchable. The weight percentage of the filler particles relative to the total weight of the material of the design layer may be up to 95 weight percent.

[0054] Another component of the designed layer structure can be a resin. Epoxy resins, poly(p-phenylene ether) (PPE), bisbenzocyclobutene (BCB), polybenzoxazolyl (PBO) and / or polyimides can be used. Phenolic resins, acrylic resins and their halides or modified versions can also be used as components of the designed layer structure. In the context of the present application, the term "halide" can describe a substance and / or material comprising at least one halogen atom, such as fluorine, chlorine, bromine or iodine. However, in one embodiment, the chlorine content of the resin can preferably be less than 30ppm. Advantageously, salts should not be formed during the processing of the resin. In addition, a high crosslinking ability of the resin may be advantageous. Low porosity may be preferred to avoid undesirable phenomena such as cracks, migration, etc.

[0055] In an embodiment, the component carrier includes at least one additional component, which can be a surface mounted component or an additional embedded component. For example, such an additional component can be electrically connected to an electrically conductive layer structure in the design layer structure. Such an additional component, for example an electronic component such as a semiconductor chip, can be surface mounted on the design layer structure with an integrated wiring structure, or can also be embedded in the design layer structure with an integrated wiring structure. In particular, the at least one additional component can be located in the same layer as the above-mentioned component (in particular at the same vertical height of the layer stack). In addition, the additional component can be directly or indirectly physically and / or electrically connected to the component.

[0056] In an embodiment, the component carrier further comprises at least one further design layer structure in which a further surface contour is embossed. Thus, a plurality of design layer structures, each of which integrates one or more wiring structures, can be stacked vertically to form a more complex three-dimensional arrangement of wiring structures. Thus, this can make it possible to create even sophisticated or complex wiring architectures in the component carrier in a straightforward manner. The working moulds of different stacked design layer structures can be identical or can also be different.

[0057] Specifically, the design layer material can be constructed for a prepolymer composite, characterized in that the design layer material can be used for continuous structuring and in-situ electromagnetic radiation-based curing during the NIL imprint process. The corresponding NIL material may remain in the final stack. Preferably, this can be done in a roll-to-board process (which has the advantage of being very fast) and / or a board-to-board process (which can provide better alignment accuracy). In particular, curing based on electromagnetic radiation can be carried out by electromagnetic radiation in the wavelength range of 10nm to 700nm, in particular 100nm to 450nm. Preferably, the electromagnetic radiation used for curing can be in the ultraviolet (UV) range. In addition to or instead of curing based on electromagnetic radiation, thermal curing is also feasible.

[0058] In particular, the design layer material may be configured to serve as an etching mask during an etching process for structuring the surface.

[0059] According to another exemplary embodiment, the layer structure is designed to have an adhesion greater than 600 N / m. Adhesion refers to the tendency of different particles or surfaces to adhere to each other. The force causing adhesion can be an intermolecular force, which is responsible for the function of various adhesives and adhesive sheets, falling into the categories of chemical adhesion, dispersed adhesion and diffuse adhesion.

[0060] According to a further exemplary embodiment, the engineered layer structure comprises a temperature resistance between 200° C. and 300° C., in particular between 230° C. and 260° C. The engineered layer structure may in particular be a cured, cross-linked resist material having a temperature resistance between 230° C. and 260° C. The higher the cross-linking, the higher the modulus, depending on the base oligomers and / or polymers used.

[0061] According to another exemplary embodiment, the design layer structure includes a flame retardant grade 4 material (FR4). FR4 can be a composite material composed of woven fiberglass cloth and a flame retardant (self-extinguishing) epoxy resin adhesive. FR4 glass epoxy is a high pressure thermosetting plastic laminate grade and has a good strength to weight ratio. With almost zero water absorption, FR4 is used as an electrical insulator with considerable mechanical strength.

[0062] According to a further exemplary embodiment, the design layer structure comprises a material having a glass transition temperature between 120°C and 200°C, in particular between 135°C and 170°C.

[0063] According to a further exemplary embodiment, the (Young's) modulus of the designed layer structure below the glass transition temperature (in the fully cured stage) is 1000 MPa to 14000 MPa, in particular 5000 MPa to 13000 MPa.

[0064] According to another exemplary embodiment, the (Young's) modulus of the designed layer structure above the glass transition temperature (i.e., in the reflow state) is 60MPa to 800MPa, in particular 100MPa to 600MPa. The glass-liquid transition is a gradual and reversible transition from a hard and relatively brittle glass state to a viscous or rubbery state in an amorphous material (or an amorphous region in a semi-crystalline material) as the temperature rises. An amorphous solid that exhibits a glass transition is called glass. The reverse transition achieved by supercooling a viscous liquid into a glass state is called vitrification. The glass transition temperature Tg of a material characterizes the temperature range over which the glass transition occurs. The glass transition temperature can be lower than the melting temperature of a (e.g., crystalline) filler.

[0065] These properties ensure that the material of the designed layer structure has sufficient mechanical strength to accurately design electrical conductive traces, vertical through-connections, etc. At the same time, these properties ensure that the material of the designed layer structure has sufficient elasticity to buffer thermal and / or mechanical stresses.

[0066] According to a further exemplary embodiment, the thermal expansion coefficient of the layer structure below the glass transition temperature is designed to be 10 ppm / K to 40 ppm / K, in particular 20 ppm / K to 40 ppm / K. These values ​​can suppress thermal stresses within the component carrier.

[0067] According to a further exemplary embodiment, the coefficient of thermal expansion of the designed layer structure above the glass transition temperature is 50 ppm / K to 100 ppm / K, in particular 60 ppm / K to 85 ppm / K. These values ​​can suppress thermal stresses inside the component carrier. The higher the value of the coefficient of thermal expansion (CTE) above Tg, the more serious the reliability problem. The designed layer structure may include non-woven glass fibers so that thermal expansion occurs in all directions. The coefficient of thermal expansion is also affected by the amount of filler. If the amount of filler increases, the coefficient of thermal expansion decreases. The designed layer structure may have a filler content greater than 50%, for example, the designed layer structure may have 80% filler.

[0068] According to a further exemplary embodiment, the layer structure is designed to have a fracture strain below the glass transition temperature of 2%. This can lead to advantageous mechanical properties of the designed layer structure and the correspondingly produced component carrier.

[0069] According to a further exemplary embodiment, the layer structure is designed to be formed with a chemical shrinkage of less than 3%. Thus, shrinkage-based curing stresses within the component carrier can be avoided.

[0070] According to further exemplary embodiments, the engineered layer structure is formed with a moisture absorption rate of less than 0.1%.

[0071] According to further exemplary embodiments, the soil removal rate is less than 0.006 g / min.

[0072] The Dk value of the material of the designed layer structure (especially the resin of the designed layer structure) can be no more than 3, especially for high-frequency applications. The Df value of the material of the designed layer structure (especially the resin of the designed layer structure) can be no more than 0.003, especially for high-frequency applications. As a result, the component carrier obtained can have excellent properties in terms of high-frequency behavior. If the filler content increases, the values ​​of Dk and Df also increase.

[0073] The number of press cycles that the material of the designed layer structure can withstand can be in the range of 1 to 10. The number of reflow tests that the material of the designed layer structure can withstand can be at least 6 times. This can allow the use of a designed layer structure with a stack thickness that can be selected in a sufficiently wide range to manufacture component carriers. The material of the designed layer structure can be characterized by a peel test of at least 600N / m to copper. The press cycle of the designed layer structure can withstand 6 to 10 times.

[0074] The decontamination rate of the material of the designed layer structure can be at least 0.006 g / min. The material of the designed layer structure can be characterized by a UL listing from V1 to V0 (according to industrial standards IEC / DIN EN 60695-11-10 and IEC / DIN EN 60695-11-20, in the latest version valid at the priority date of the present application) (this can ensure safety against flammability). The mentioned material properties can simplify the processing of the designed layer.

[0075] According to further exemplary embodiments, the design layer structure comprises a fully cured polymer based on at least one of the following: epoxy resin, acrylate, polyphenylene ether, polyimide, polyamide and polyetheretherketone, poly(p-phenylene ether) (PPE), bisbenzocyclobutene (BCB) and / or polybenzomethylbenzazole (PBO).

[0076] In particular, combinations of the oligomers listed above can be used for (particularly permanent) design layers (i.e. UV-NIL resists). For example, a combination of loaded BCB, PPE and SU8 can be used with encapsulated inorganic round SiO2 nanofillers and halogen-free materials in amounts up to more than 50%. Different kinds of encapsulated nanofillers can be used. Further examples of suitable filling materials are boron nitride (BN) or aluminum nitride (AlN).

[0077] For example, BCB (divinylsiloxane-bisbenzocyclobutene (DVS-bis-BCB, or BCB), such as CYCLOTENE TMDuPont's line of advanced electronic resins) are photopolymers. These polymers are derived from B-grade bisbenzocyclobutene (BCB) chemistry.

[0078] For example, PPE (eg, Sabic NORYL SA9000 resin) is a modified low molecular weight, bifunctional oligomer based on polyphenylene ether (PPE) with vinyl end groups (used in Megtron 6 and 7 materials).

[0079] For example, SU-8 (eg, Kayaku Advanced Materials SU-8) is a high contrast epoxy-based photoresist designed for micromachining and other microelectronics applications.

[0080] The chloride content of the resin can be less than 30 ppm. Specifically, the designed layer structure can be almost free of halogens (e.g., less than 1 ppm), which are ions and not bound to the polymer. The halogens can be washed out by multiple water washing steps.

[0081] Advantageously, no salts should be formed during the processing of the resin. Furthermore, a high crosslinking ability of the resin may be advantageous. Low porosity may be preferred to avoid undesirable phenomena such as cracks, migration, etc.

[0082] According to a further exemplary embodiment, the engineered layer structure comprises polymer- or oligomer-based stacking blocks, wherein at least one of the stacking blocks is based on one of the above-mentioned polymers.

[0083] According to a further exemplary embodiment, at least one of the stacking blocks of the designed layer structure has at least one functional group covalently bonded to another of the at least one stacking block. The covalently bonded functional group is responsible for the cross-linking connection.

[0084] According to another exemplary embodiment, the at least one functional group is selected from one of the following: a mercapto group selected from 3-mercaptopropionate, 3-mercaptoacetate, mercaptoacetate and alkylthiol; and / or a double bond selected from acrylate, methacrylate, vinyl ether, allyl ether, propene ether, allyl ether, allyl ether, allyl ester, diene, unsaturated ester and allyl triazine, allyl isocyanate and N-vinylamide.

[0085] According to a further exemplary embodiment, the engineered layer structure comprises a prepolymer having at least one photoinitiator in an amount of 0.1 wt % to 10 wt %, in particular 0.5 wt % to 5 wt %.

[0086] According to a further exemplary embodiment, the design layer structure is in particular a fully cured resin, wherein the design layer further comprises filler particles, the amount of the filler particles being, for example, 1 wt % to 10 wt %, in particular 1 wt % to 3 wt %.

[0087] According to another exemplary embodiment, the filler particles include an inorganic filler, wherein the inorganic filler is in a crystalline and / or amorphous state and is particularly encapsulated. The inorganic filler can be a nanofiller, which can be coated to avoid agglomeration and reduce thixotropy. The porous filler can have a lower Dk due to air, but the porous filler can absorb chemicals. Therefore, the porous filler has a hydrophobic silane coating, just like the case in Rogers 3000 material, and the mixing of the filler in the resin matrix is ​​easier. Halogenated organic matter, hydrophobic polymers and halogens with covalent bonds can be used for fillers, so that high flame retardancy can be achieved. The design layer structure can include a high inorganic filler with aromatic content. The inorganic filler can have a round smooth shape or a needle-like shape. In addition, shapes including edges are also possible, such as cubes, pyramids, etc.

[0088] According to further exemplary embodiments, the filler particles include a size (eg, an average size calculated according to an arithmetic mean) of less than 0.1 μm.

[0089] According to another exemplary embodiment, the filler particles include talc (ie, layered silicate), zeolite, BN, AlN and / or fused SiO 2. SiO 2 or zeolite nanofillers are usually agglomerated, but this agglomeration can be reduced by coating, and thixotropy can also be reduced.

[0090] According to a further exemplary embodiment, the filler particles comprise a plasma-etchable material.

[0091] According to a further exemplary embodiment, the design layer structure comprises less than 95% (by weight) filler particles, in particular 80% to 95% filler particles, relative to the total weight of the material of the design layer. More filler particles lead to a smaller degree of shrinkage of the ink during, for example, electromagnetic radiation-based (for example UV-based) and / or thermal curing, and at the same time result in a better CTE. In addition, better flame retardancy is achieved at the same time.

[0092] In an embodiment, the component carrier comprises a stack of at least one electrically insulating layer structure and at least one electrically conductive layer structure. For example, the component carrier may be a laminate of the mentioned one or more electrically insulating layer structures and one or more electrically conductive layer structures, in particular a laminate of the mentioned one or more electrically insulating layer structures and one or more electrically conductive layer structures formed by applying mechanical pressure and / or thermal energy. The mentioned stack may provide a plate-like component carrier that is able to provide a large mounting surface for other components and yet is very thin and compact.

[0093] In an embodiment, the component carrier is formed as a plate. This contributes to a compact design, wherein the component carrier nevertheless provides a large base for mounting components on the component carrier. In particular, a bare chip (die) as an example of an electronic component can be surface mounted on a thin board such as a printed circuit board.

[0094] In an embodiment, the component carrier is configured as one of a printed circuit board, a substrate (in particular an IC substrate) and an interposer.

[0095] In the context of the present application, the term "printed circuit board (PCB)" may particularly denote a plate-like component carrier formed by laminating a plurality of electrically conductive layer structures with a plurality of electrically insulating layer structures, for example by applying pressure and / or by supplying thermal energy. As a preferred material for PCB technology, the electrically conductive layer structures are made of copper, while the electrically insulating layer structures may include resin and / or glass fibers, so-called prepregs, or FR4 materials. The individual electrically conductive layer structures may be connected to each other in a desired manner by forming holes through the laminate, for example by laser drilling or mechanical drilling, and by partially or completely filling these holes with an electrically conductive material, in particular copper, thereby forming vias or any other through-hole connections. The filled holes connect the entire stack (i.e., through-hole connections extending through a plurality of layers or the entire stack), or the filled holes connect at least two electrically conductive layers, i.e., so-called vias. Similarly, optical interconnects may be formed through the various layers of the stack to receive an electro-optical circuit board (EOCB). A printed circuit board is generally configured to accommodate one or more components on one surface or two opposite surfaces of a plate-shaped printed circuit board. The one or more components may be connected to the corresponding main surface by soldering. The dielectric portion of the PCB may include a resin with reinforcing fibers (e.g., glass fibers).

[0096] In the context of the present application, the term "substrate" may particularly refer to a small component carrier. Relative to a PCB, a substrate may be a relatively small component carrier on which one or more components may be mounted, and the relatively small component carrier may be used as a connection medium between one or more chips and another PCB. For example, a substrate may have substantially the same size as a component (particularly an electronic component) to be mounted on the substrate (for example, in the case of a chip-scale package (CSP)). More specifically, a substrate may be understood as a carrier for electrical connectors or power grids, and a component carrier for a connection portion that is comparable to a printed circuit board (PCB) but has a relatively high density of lateral and / or vertical arrangements. The lateral connection portion is, for example, a conductive path, and the vertical connection portion may, for example, be a drill hole. These lateral connections and / or vertical connections are arranged in the substrate and may be used to provide electrical, thermal and / or mechanical connections between a contained component or an uncontained component (e.g., a bare wafer), particularly an IC chip and a printed circuit board or an intermediate printed circuit board. Therefore, the term "substrate" also includes an "IC substrate". The dielectric portion of the substrate may include a resin with reinforcement particles, such as reinforcement spheres, particularly glass spheres.

[0097] The substrate or interposer may include or be composed of a layer of at least one of the following: glass; silicon (Si) and / or photoimageable or dry-etchable organic materials, such as epoxy-based stack materials (e.g., epoxy-based stack films); or polymer compounds (the polymer compounds may or may not include photosensitive and / or heat-sensitive molecules), such as polyimide or polybenzoxazole.

[0098] In an embodiment, the at least one electrically insulating layer structure comprises at least one of the following: a resin or polymer, such as an epoxy resin, a cyanate resin, a benzocyclobutene resin, a melamine derivative, polyparaphenylene benzobisoxazole (PBO), a bismaleimide-triazine resin, a polyphenylene derivative (e.g., based on polyphenylene ether, PPE), a polyimide (PI), a polyamide (PA), a liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE), dibenzocyclobutene (Bisbenzocyclobutene, BCB) and / or a combination thereof. Reinforcement structures such as meshes, fibers, spheres or other types of filler particles, such as those made of glass (multilayer glass), may also be used to form a composite. Semi-cured resins combined with reinforcing agents, such as fibers impregnated with the above resins, are referred to as prepregs. These prepregs are typically named after their properties, such as FR4 or FR5, which describe their flame retardant properties. Although prepregs, especially FR4, are generally preferred for rigid PCBs, other materials, especially epoxy-based stacking materials (e.g., stacking films) or photosensitive dielectric materials may also be used. For high-frequency applications, high-frequency materials such as polytetrafluoroethylene, liquid crystal polymers, and / or cyanate ester resins may be preferred. In addition to these polymers, low-temperature co-fired ceramics (LTCC) or other low, very low, or ultra-low DK materials may be used in component carriers as electrical insulating structures.

[0099] In an embodiment, the at least one electrically conductive layer structure comprises at least one of the following: copper, aluminum, nickel, silver, gold, palladium, tungsten and magnesium. Although copper is generally preferred, other materials or coated variants thereof are also possible, in particular variants coated with superconducting materials or conductive polymers, such as graphene or poly (3,4-ethylenedioxythiophene) (PEDOT), respectively.

[0100] The at least one component may be selected from at least one of the following: a non-electrically conductive inlay, an electrically conductive inlay (such as a metal inlay, preferably comprising copper or aluminum), a heat transfer unit (e.g. a heat pipe), a light-conducting element (e.g. an optical waveguide or optical conductor connection), an electronic component, or a combination thereof. The inlay may be, for example, a metal block with or without a coating of insulating material (IMS-inlay), which may be surface mounted for the purpose of promoting heat dissipation. Suitable materials are defined according to the thermal conductivity of the material, which should be at least 2 W / mK. Such materials are typically based on, but not limited to, metals, metal oxides and / or ceramics, such as copper, aluminum oxide (Al2O3) or aluminum nitride (AlN). Other geometries with increased surface areas are also often used in order to increase the heat exchange capacity. Furthermore, the component may be an active electronic component (implemented with at least one pn junction), a passive electronic component such as a resistor, an inductor or a capacitor, an electronic chip, a memory device (e.g., a DRAM or other data storage), a filter, an integrated circuit (e.g., a field programmable gate array (FPGA), a programmable array logic (PAL), a general purpose array logic (GAL), and a complex programmable logic device (CPLD)), a signal processing component, a power management component (e.g., a field effect transistor (FET), a metal oxide semiconductor field effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS), a junction field effect transistor (JFET), or an insulated gate field effect transistor (IGFET). In some embodiments, the present invention relates to a device for producing a semiconductor material, such as a semiconductor material, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide (Ga2O3), indium gallium arsenide (InGaAs), and / or any other suitable inorganic compound), an optoelectronic interface element, a light emitting diode, an optical coupler, a voltage converter (e.g., a DC / DC converter or an AC / DC converter), a cryptographic component, a transmitter and / or a receiver, an electromechanical transducer, a sensor, an actuator, a microelectromechanical system (MEMS), a microprocessor, a capacitor, a resistor, an inductor, a battery, a switch, a camera, an antenna, a logic chip, and an energy collection unit. However, other components may also be surface mounted on the component carrier. For example, a magnetic element may be used as a component. Such a magnetic element may be a permanent magnetic element (e.g., a ferromagnetic element, an antiferromagnetic element, a multiferroic element, or a ferrimagnetic element, such as a ferrite core) or may be a paramagnetic element. However, the component may also be an IC substrate, an interposer, or another component carrier, such as a plate-in-plate configuration. The component may be surface mounted on the component carrier. Furthermore, other components may be used as components, in particular components which generate and emit electromagnetic radiation and / or are sensitive to electromagnetic radiation propagating from the environment.

[0101] In an embodiment, the component carrier is a laminated component carrier. In such an embodiment, the component carrier is a composite of multiple layers that are stacked and connected together by applying pressure and / or heat.

[0102] After the internal layer structure of the component carrier has been processed, one or both main surfaces of the processed layer structure can be covered symmetrically or asymmetrically with one or more further electrically insulating layer structures and / or electrically conductive layer structures (in particular, by lamination). In other words, the stacking can be continued until the desired number of layers is obtained.

[0103] After the formation of the stack having the electrically insulating layer structure and the electrically conductive layer structure has been completed, the resulting layer structure or component carrier can be subjected to a surface treatment.

[0104] In particular, in terms of surface treatment, an electrically insulating solder resist may be applied to one or both of the main surfaces of a stack or component carrier. For example, such a solder resist may be formed over the entire main surface and the layer of the solder resist may be subsequently patterned to expose one or more electrically conductive surface portions that will be used to electrically couple the component carrier to an electronic peripheral. The surface portions of the component carrier that remain covered with the solder resist, in particular the surface portions containing copper, may be effectively protected from oxidation or corrosion.

[0105] In terms of surface treatment, a surface finish can also be selectively applied to the exposed electrically conductive surface portion of the component carrier. Such a surface finish can be an electrically conductive covering material on an exposed electrically conductive layer structure (e.g., pads, conductive traces, etc., particularly including or consisting of copper) on the surface of the component carrier. If such an exposed electrically conductive layer structure is not protected, the exposed electrically conductive component carrier material (especially copper) will be oxidized, thereby making the reliability of the component carrier low. In addition, the surface finish can be formed as, for example, a joint between a surface mounted component and a component carrier. The surface finish has the function of protecting the exposed electrically conductive layer structure (especially the copper circuit), and the surface finish can be joined to one or more components, for example, by welding. Examples of suitable materials for the surface finish are organic solderability preservatives (OSP), electroless nickel immersion gold (ENIG), electroless nickel immersion palladium immersion gold (ENIPIG), gold (especially hard gold), chemical tin, nickel gold, nickel palladium, etc.

[0106] The aspects defined above and further aspects of the invention are apparent from the examples of embodiment described hereinafter and are explained with reference to these examples of embodiment. BRIEF DESCRIPTION OF THE DRAWINGS

[0107] Figures 1 to 8 Shows that in the implementation of Figure 8 A cross-sectional view of a structure obtained during a method for manufacturing a component carrier according to an exemplary embodiment of the present invention is shown.

[0108] Fig. 9 An apparatus for imprinting a surface contour in a design layer using a working mold according to an exemplary embodiment is shown.

[0109] Figures 10 to 14 Shows that in the implementation of Fig.14 A cross-sectional view of a structure obtained during a method for manufacturing a component carrier according to an exemplary embodiment of the present invention is shown.

[0110] Figures 15 to 21 Shows that in the implementation of Fig.21 A cross-sectional view of a structure obtained during a method for manufacturing a component carrier according to an exemplary embodiment of the present invention is shown. DETAILED DESCRIPTION

[0111] The illustrations in the drawings are schematically. In different drawings, similar or identical elements are provided with the same reference signs.

[0112] Before exemplary embodiments will be described in more detail with reference to the accompanying drawings, some basic considerations based on which exemplary embodiments of the present invention were developed will be summarized.

[0113] According to an exemplary embodiment of the present invention, a stamped design layer structure with corresponding surface contours can be used as a basis for embedding components in a component carrier such as a printed circuit board (PCB) or an integrated circuit (IC) substrate. Using, for example, a NIL-type design layer structure to embed electronic components (such as semiconductor chips) can allow the embedded components to be electrically connected to the electrically conductive structure formed in the stamped design layer with excellent spatial accuracy. In addition, a highly compact component carrier with a high integration density can be provided, which is embedded with electronic components and has an electrically conductive layer structure.

[0114] More specifically, exemplary embodiments may provide an embedded multi-wafer interconnect semi-additive processing (SAP) nanoimprint lithography (NIL) process for manufacturing IC substrates or other types of component carriers. Particularly preferred may be the realization of a wafer-type electronic component with a facing pad and thermal bonding for wafer assembly. Advantageously, the SAP NIL process may be performed to simultaneously form vias and traces for lines greater than 10 μm (but preferably for the finest lines less than 10 μm, and preferably for the finest lines less than 5 μm), and for the connection of small pitch components. Furthermore, advantageously, all geometries may be defined by a single common production stage. Furthermore, all of the geometries may be formed within a single common layer. For example, a thicker copper trace formed in a processed NIL layer may be used for thermal management and / or power supply, while the finest copper trace may be used for signal transmission purposes. Advantageously, the described manufacturing architecture may allow fine line processing to be performed for electrically conductive structures having a line spacing ratio L / S of 10 μm / 10 μm and below. In particular, exemplary embodiments may allow for selective protection via inking of the highest copper pattern areas for supporting a selective copper electroplating process.

[0115] Exemplary applications of exemplary embodiments of the present invention are fine line applications, mobile applications, IC substrates, and the like.

[0116] In particular, exemplary embodiments may combine thermal compression bonding of the chip with face-up placement, followed by NIL (nanoimprint lithography) and SAP (semi-additive processing) processes for connecting the chip pads and for plating the finest interconnect structures. With regard to the mentioned thermal compression bonding, this can be achieved, for example, by forming a metal-metal connection using the surface of the component made of metal. When the component is made of silicon, a wafer attach paste can be applied for assembly. In particular, the manufacturing effort for via formation may be reasonable, and SAP-type mass production of the finest lines may become possible. In particular, exemplary embodiments may provide the finest lines for organic substrates. This can avoid the provision of a silicon interposer.

[0117] Exemplary embodiments of the present invention provide a component carrier of PCB type or IC substrate type, which includes one or more embedded components (such as wafers) and fine interconnection structures. Such a component carrier can be manufactured with low manufacturing effort. In particular, such a manufacturing process can include hot compression bonding of different components in an upward facing direction on a (e.g. copper) metal structure. This can be followed by a nanoimprint lithography process for forming a fine line pattern portion for interconnecting the components embedded in the component carrier. For the manufacture of fine interconnected copper structures between components, a SAP (semi-additive processing) copper plating process can be applied. Such a manufacturing process can make an effective component carrier (especially substrate) manufacturing process possible. Such a process can be performed without laser drilling to connect different components (especially wafers) to copper structures that can be applied in different layers of the component carrier.

[0118] According to an exemplary embodiment of the present invention, an IC substrate or PCB production process is provided, which is highly suitable for low-effort mass production of component carriers with at least one embedded semiconductor chip-type component or preferably multiple embedded semiconductor chip-type components. In this manufacturing process, the interconnection of at least one embedded electronic component can be completed by a semi-additive processing nanoimprint lithography process (SAP NIL). In particular, the process can include a face-up assembly of electronic components and a thermal compression bonding process for connecting the component on a metal (preferably copper) surface. This can be followed by a NIL stamping process and a semi-additive treatment for defining an electrically conductive connection structure. After one or more electronic components are thermally bonded to a substrate with a face-up orientation, the one or more electronic components can be embedded by a permanent NIL resist and then subjected to a NIL stamping process. Preferably, the same alignment mark on the copper foil can be used for a UV nanoimprint lithography resist structuring process for manufacturing a fine interconnection structure and connecting chip pads. However, the copper pads of the components assembled for subsequent embedding can also be used as alignment marks. The interconnection structure between wafers can be formed by a copper electroplating SAP process.

[0119] According to an exemplary embodiment, after the heat diffusion bonding process and the NIL imprinting process of different components on the metal foil, the metal seed layer can be deposited on the exposed surface (and in particular, on the exposed surface of the recess in the design layer structure), and then the metal traces and vias are filled. The advantage of the heat diffusion bonding process is that any movement or offset of one or more components can be avoided (however, such offset may occur when a strong sintered metal bond is formed). At the same time, effective heat transfer to the metal substrate can be provided. By using alignment marks from the metal foil for aligning the components and additionally using alignment marks of the components for the NIL imprinting process, high precision (e.g., better than 3μm) for the NIL imprinting process can be achieved. High-density copper interconnect structures and low-density structures can be formed by a simple plating process, in particular, high-density copper interconnect structures and low-density structures can be formed using a modified semi-additive process (mSAP) or using a semi-additive process (SAP) method. For the thermal sintering process, any thermal sintering processing equipment can be used. Examples are diffusion soldering, or sintering with copper, tin, silver and / or composite sintering pastes that are suitable for connecting component pad surfaces (e.g., copper, aluminum and / or gold) on copper foil surfaces to form a stable, mechanically robust connection with good electrical conductivity. If a sintering paste is used, copper micro-sintering pastes and / or nano-sintering pastes or copper-tin-silver (Cu-Sn-Ag) sintering pastes are preferred. In order to embed one or more components, any resin or NIL resist with appropriate mechanical and thermal specifications can be used with a structured copper layer suitable for substrate and PCB manufacturing and embossing processes. An advantage of the substrate or PCB manufacturing process of an embodiment of the present invention is that when the NIL resist is in a liquid state, the thermally bonded components on the copper surface will not move during the NIL embossing process. The NIL resist can fill the space between components and can be used to structure fine lines and vias to connect chip pads at the same time. Preferably, no cavities are created within the NIL resist and / or between the NIL resist and a surface of a different material, such as a metal trace, component or component connection pad, or dielectric material.

[0120] In this way, cutting out of prepreg can be avoided. Additional processes, such as laser drilling, can also be avoided. Due to the reduction of process steps, the complexity of manufacturing can be reduced, and the quality can be improved and an economical mass production path can be possible.

[0121] In one embodiment, a component at least partially embedded in a stamped design layer structure comprises at least one metal pad only at the upper main surface. This can simplify the assembly of the chip on a metal base or the like. Alternatively, the at least one metal pad can be located exclusively at the lower main surface of the component. In this case, it should be noted that the at least one pad is correctly aligned with respect to the metal connection structure of the pad located below the component. In a further embodiment, a component having at least one pad on each of its two opposite main surfaces can be at least partially embedded in a stamped design layer structure so that the metal connection structure for connecting the pad can be formed above the component and below the component.

[0122] As photoresist or NIL resist material, it may be preferred to use a permanent dielectric resist material that remains in the substrate or PCB. However, temporary resist materials may also be used to manufacture fine interconnect copper structures having a line spacing ratio L / S of less than 40 μm / 40 μm, in particular less than 20 μm / 20 μm. Particularly preferred for structures less than 20 μm may be a nanoimprint lithography process using an ultraviolet (UV) curable NIL resist.

[0123] Figures 1 to 8 Shows that in the implementation of Figure 8 The structure obtained during the method of manufacturing the component carrier 100 according to the exemplary embodiment of the present invention is shown in cross section. Figures 1 to 8 In FIG. 1 , a production route for manufacturing a component carrier 100 of an integrated circuit substrate type or a printed circuit board type is shown, which includes embedding multiple wafers and forming a fine interconnect structure. The embedded components 112 can be assembled in a chip-first process and in a chip-last process.

[0124] Figure 1 It is shown in Figures 1 to 8The starting point of the manufacturing method. A metal base 122 (such as a sputtered metal seed layer or an attached metal foil, wherein the metal may be copper) may be formed on an optional release layer 124 arranged on a carrier 126. The release layer 124 may have poor adhesion properties and may be formed, for example, of polytetrafluoroethylene. The release layer 124 (the release layer 124 may also be represented as a separation film) may also be a UV release layer that may be released by ultraviolet radiation. However, the release layer may also be configured to be released by electromagnetic radiation other than the UV range and / or by the supply of thermal energy. For example, a temporary carrier 126 may be configured to support a glass plate or a steel plate, and the temporary carrier 126 may be removed before the manufacture of the component carrier 100 is completed. In particular, in an embodiment in which the carrier 126 has always been a part of the component carrier 100 that is easy to manufacture (i.e., not temporary), the release layer 124 may be omitted.

[0125] Reference Figure 2 , the electrically insulating layer structure 106 implemented as the design layer structure 108 can be directly distributed on the metal base 122. Preferably, the design layer structure 108 covers the entire surface of the metal base 122 after being distributed. After distributing a continuous layer made of the design layer structure material on the metal base 122, the continuous layer can be structured to obtain the graphical design layer structure 108 shown. The metal base 122 and the design layer structure 108 can form the basis of the layer stack 102. For example, the thickness d of the design layer structure 108 can be in the range of 0.1 μm to 25 μm. Therefore, this makes it possible to form a very thin stack. Advantageously, the design layer structure 108 can be configured as a nanoimprint lithography (NIL) layer. In other words, the metal base 122 can be coated with a NIL imprintable resist. After being formed on the metal base 122, the design layer structure 108 can still be at least partially uncured, that is, it can still be cross-linked or polymerized in particular. For example, the design layer structure 108 may be implemented as a permanent NIL UV (ultraviolet) resist coating.Other kinds of curing, in particular thermal curing and / or curing in another wavelength range, are also possible.

[0126] To obtain Figure 3 According to the structure shown in FIG. 1 , the design layer structure 108 may be embossed on the metal base 122 by a contoured working mold (not shown) such that a predetermined surface portion of the metal base 122 is exposed relative to the embossed design layer structure 108 .

[0127] Thus, the surface contour shown can be embossed in the design layer structure 108. To this end, the working mold ( Figure 3 Not shown, please refer to Fig. 9) is pressed into the still deformable design layer structure 108 so as to convert the surface contour of the working mold into an inverse surface contour impressed in the design layer structure 108. Descriptively speaking, the surface contour created in the design layer structure 108 corresponds to the electrically conductive pattern to be formed. In the embodiment shown, the formation of the surface contour in the design layer structure 108 can create a plurality of recesses 136.

[0128] As from Figure 3 As can also be seen in FIG. 1 , the recesses 136 formed in the design layer structure 108 taper inwardly. All recesses 136 have the same depth (with Figure 7 different, Figure 7 Different recess depths are formed). This is a result of the corresponding tapered shape of the protrusion of the working mold that produces the recess 136 in the design layer structure 108. Forming the recess 136 tapered (rather than vertical) can advantageously suppress problems with unwanted adhesion between the working mold and the design layer structure 108. In the case of vertically extending side walls, high friction between the working mold and the design layer structure 108 may occur, which may lead to defects and low embossing speeds. In the case of tapered side walls of the working mold and recesses 136 in the design layer structure 108, high processing speeds and low defect rates can be achieved.

[0129] Advantageously, the design layer structure 108 can be cured simultaneously during the embossing process. For this purpose, the working mold (preferably optically transparent, for example made of glass, transparent flexible cross-linked silicone rubber and / or a combination of the two) can be provided with a curing UV lamp, which is configured to emit UV radiation. More specifically, the UV lamp can emit UV radiation during the embossing of the recess 136 in the design layer structure 108. This speeds up the manufacturing process and makes a subsequent curing process unnecessary. As an alternative to the UV lamp, another optical emitter or heat source can also be used for curing. Such an optical emitter or heat source can be formed integrally with the working mold, or can be provided as a separate component. Fig. 9 An apparatus for embossing the design layer structure 108 using a working mold is shown in . Simultaneously with or after forming the contour, the design layer structure 108 may be cured by subjecting the deformed design layer structure 108 to heating or suitable electromagnetic radiation, such as UV radiation.

[0130] In an undesirable situation, it may happen that after the recesses 136 have been embossed by the working mold, remnants of the design layer structure 108 remain in the recesses 136, which should be processed to create corresponding through-holes. Since this undesirable phenomenon may be critical for the subsequent continuation of the manufacturing process, it may be advantageous to remove the remnants of the design layer structure 108 from at least one bottom region of the recesses 136 of the contoured design layer structure 108, preferably by plasma etching. Advantageously, the embossing of the design layer structure 108 on the metal base 122 may expose parts of the metal base 122. This may be suitably prepared. Figure 3 The structure shown in FIG. 1 is used for subsequent electroplating (control Figure 4 ).

[0131] Forming the recess 136 by embossing using a working mold can also ensure that the exposed surface portion of the design layer structure 108 that defines the recess 136 has a very low roughness Ra, which is preferably less than 50nm. This makes the manufacture of microstructures possible and can result in the component carrier 100 having excellent high-frequency characteristics.

[0132] In particular, a roll-to-plate process may result in a permanent UV-NIL imprint such that the resulting surface contours may define subsequently formed vias and die bonding areas.

[0133] Reference Figure 4 , an electrically conductive layer structure 104 is formed in a recess 136 of the electrically insulating layer structure 106. More specifically, the electrically conductive layer structure 104 is formed in the recess 136 located on the exposed portion of the metal base 122 by plating. In particular, the plating process may include a non-electroplating stage for lining the recess 136 with a seed layer of metal. The non-electrometallic material located outside the recess 136 may be removed, for example by a photolithography and etching process to remove the non-electrometallic material located outside the recess 136. Advantageously, an electroplating process (e.g., electroplating) may be performed to fill the recess 136 with a metal such as copper. The electroplating process may be facilitated by the presence of an exposed surface portion of the metal base 122 and / or by an (optional) seed layer.

[0134] By means of the described plating process, the recesses 136 can be selectively filled with metal, thereby forming vertical through-connections 160 (particularly copper vias), component accommodation areas 164 (component accommodation areas 164 can also be indicated as chip filling areas) and alignment marks 162. Thus, the copper traces and areas for the subsequent placement of the components 112, as well as the alignment marks 162 are plated by means of a bottom-up copper electroplating process (more specifically by means of a semi-additive process, SAP). Thus, in addition to the fine line structures, the alignment marks 162, the vias and the pad areas for placing the components 112 face-up on the copper are also structured.

[0135] Reference Figure 5 , the connection medium 120 is applied to the exposed metal surface of the component receiving area 164. More specifically, a wafer attach sintering paste can be applied to the component receiving area 164 as the connection medium 120, for example, the wafer attach sintering paste can be applied to the component receiving area 164 as the connection medium 120 by screen printing. More generally, the sintering paste can be printed on the copper area using the alignment mark 162, for example, the sintering paste can be printed on the copper area using the alignment mark 162 by dispensing, screen printing or inkjet printing. If the component 112 is to be assembled by diffusion soldering, solder (as another example of the connection medium 120) can be placed on the pad of the component 112 and / or on the component receiving area 164. More specifically, Cu, Ag or Sn sintering paste, or a mixture thereof can be applied as the connection medium 120 by screen printing. Electroplating of a Cu-Sn-Ag sintering paste may also be performed on the component receiving area 164 for thermal bonding of the component 112. For example, such a Cu-Sn-Ag sintering paste may be formed by plating different layers of different metals one after another (i.e., layer by layer) before performing a sintering process to create the alloy. In addition, the process may also be performed layer by layer for each metal (such as Cu / Sn / Cu ... Sn), wherein the obtained result may already contain some content of Ag. Instead of dispensing the sintering paste, solid-liquid interdiffusion (SLID) bonding, for example, may also be performed by electroplating.

[0136] Reference Figure 6 , electronic components 112 are assembled on the connection medium 120, and the electronic components 112 each have a pad 118 arranged facing upward. Since the pads 118 of the components 112 are arranged facing upward, the pads 118 of the components 112 can be advantageously used as alignment marks for subsequent processing. Preferably, the electronic components 112 are semiconductor chips. Such a wafer oriented facing upward can be connected to the connection medium 120, in particular, such a wafer oriented facing upward can be connected to the connection medium 120 with a high accuracy of, for example, better than 3 μm by thermal sintering.

[0137] After the connection medium 120 (particularly the sintering paste) is dried, the electronic component 112 is assembled at the target position with high precision by using the alignment mark 162 with the help of a thermal bonding process. Any bonding process and bonding material that form a reliable electrical connection between the corresponding component 112 and the designated component receiving area 164 can be used. The thermal bonding process can also be applied as a touch wafer stage, followed by curing the sintering paste in a curing oven through an appropriate curing process for final sintering. In addition, after the bonding process, the pad 118 of the component will withstand all subsequent PCB processes (such as filling with NIL resist and pressing at a temperature of more than 200°C) without delaminating the component 112 from the designated component receiving area 164.

[0138] Reference Figure 7 The second design layer structure 110, which may also be implemented as a nanoimprint lithography (NIL) dielectric, may be applied on top of the assembled electronic component 112, on top of the exposed first design layer structure 108, on top of the designated component receiving area 164, and on top of the exposed surface of the electrically conductive layer structure 104. Thus, the electronic component 112 is embedded in the stack 102 such that the electronic component 112 is covered by the dielectric material of the design layer structure 110. More specifically, the entire dielectric surrounding of the embedded component 112 is formed by the design layer structure 110.

[0139] Thereafter, the surface contour of the further design layer structure 110 is embossed to form a tapered recess 136 in the further design layer structure 110. The recess 136 is formed in the further design layer structure 110 to have different depths and different lengths, such as Figure 7 As shown in . Thus, trace-shaped and via-shaped recesses 136 are created in the further design layer structure 110. As described above for the design layer structure 108, the further design layer structure 110 can also be processed such that imprinting and curing occur simultaneously.

[0140] The recesses 136 located in the further design layer structure 110 include through holes 136' extending through the entire further design layer structure 110 and / or blind holes 136" extending through only part of the further design layer structure 110. Therefore, the embossing forms recesses 136 with different depths and / or different lengths in the further design layer structure 110. More specifically, the through holes 136' have a greater depth and / or a smaller length than the blind holes 136". In the component carrier 100, which is easy to manufacture, the through hole 136' can form a vertical electrically filled via, while the blind hole 136" can form a horizontal electrically conductive trace (the electrically conductive trace can be indicated as an embedded trace). As a result of the stamping, a recess 136 can be obtained, which includes a through hole 136' (the through hole 136' can subsequently form a metal-filled via) and a blind hole 136" (the blind hole 136" can subsequently form an electrically conductive trace), and the recess 136 has different depths and different lengths in the further design layer structure 110. Optionally, an etching process (preferably plasma etching) can be performed to ensure that there are no residues of the further design layer structure 110 at the bottom of the through hole 136'.

[0141] Still refer to Figure 7 , the NIL resist can coat and fill the area on and above the electronic components 112 with a permanent dielectric. For this purpose, a high-precision NIL imprint (especially with respect to vias and traces with a precision better than 3 μm) can be repeated once or several times. Thus, after the components 112 are thermally bonded, the spaces between the components 112 can be filled with a suitable resin. Any process for filling the spaces between the components 112 can be used, such as a printing process.

[0142] In particular, plasma etching can be performed on the residue of the further design layer structure 110 (implemented as a NIL resist) located on the bottom of the recess 136 to expose the copper. Thereafter, a seed layer deposition can be performed, followed by copper plating, to fill the via-type recess 136 and the trace-type recess 136. Thereafter, the copper traces can be separated by etching the seed layer.

[0143] Thus, permanent NIL resist may be dispensed for overmolding components 112 and for filling spaces between components 112 with NIL resist. Structuring of the NIL resist for forming vias may be done to connect with pads 118 of components 112 and as a basis for forming fine lines and interconnect structures.

[0144] In short, according to Figure 7 A very advantageous feature of the process is the use of NIL technology to form the basis for the electrical connections to the pads 118 of the component.

[0145] Figure 8 A component carrier 100 obtained by the described manufacturing process is shown. The component carrier 100 shown can be embodied as a printed circuit board or as an integrated circuit substrate.

[0146] For the purpose of Figure 7 The structure shown is obtained according to Figure 8 In the component carrier 100 of the embodiment of the present invention, the additional electrically conductive layer structure 104 can be formed in the recess 136 of the further design layer structure 110 by plating. In particular, the plating process can include a non-electroplating stage for lining the recess 136 with a metal seed layer. The non-electroplated metal located outside the recess 136 can be removed, for example, the non-electroplated metal located outside the recess 136 can be removed by a photolithography and etching process. In addition, an electroplating process (e.g. electroplating) can be performed to fill the recess 136 of the further design layer structure 110 with a metal such as copper. The electroplating process can be promoted by the presence of an exposed surface portion of the electrically conductive layer structure 104 of the design layer structure 108 and by the (optional) seed layer.

[0147] As a basis for forming an additional electrically conductive layer structure 104 in another design layer structure 110, a copper seed layer can be deposited (e.g., by copper sputtering or non-electroplating deposition of copper). Optionally, an adhesion promoter can be deposited before the seed layer is deposited to improve adhesion. Additionally or alternatively, surface activation can be performed before the seed layer is deposited. Further optionally, the working mold for imprinting the other design layer structure 110 can be provided with a locally higher roughness in the corresponding specific area to ease the subsequent seed layer formation and adhere to the NIL resist surface with appropriate adhesion. A selective protective layer can also be formed to selectively ink the highest area of ​​the graphic portion. In addition, a selective electroplating copper plating process can also be performed. The temporary protective layer can also be plasma etched. In addition, etching of the copper seed layer can be performed to form the desired graphics.

[0148] according to Figure 8 The component carrier 100 includes a stack 102 having an electrically conductive layer structure 104 (the electrically conductive layer structure 104 can be formed by plated copper) and an electrically insulating layer structure 106 (the electrically insulating layer structure 106 can be formed by a NIL dielectric). The electrically insulating layer structure 106 includes design layer structures 108, 110, each having a stamped surface contour. A plurality of chip-type components 112 are embedded in the stack 102 and are covered by portions of the design layer structure 110, portions of the electrically conductive layer structure 104, and a connecting medium 120.

[0149] The electrically conductive layer structure 104 comprises an electrically conductive trace 114 and is defined by the further design layer structure 110. Thus, the electrically conductive trace 114 has an advantageously low roughness Ra, for example a roughness Ra of less than 50 nm. This is a result of forming the electrically conductive trace 114 in the stamped surface contour of the further design layer structure 110. Furthermore, the electrically conductive layer structure 104 comprises a vertical through-connection 116 defined by the design layer structures 108, 110. Advantageously, the vertical through-connection 116 may have a high depth-to-diameter ratio of greater than 1. This may ensure a low-ohmic electrical connection in the vertical direction, which may be manufactured with reasonable effort.

[0150] Since the component 112 has the pads 118 oriented facing upward, the pads 118 may not only facilitate electrical connection of the component 112 but may also be used as alignment marks during the manufacturing process.

[0151] The four vertical side walls of the cuboid-shaped embedded components 112 are completely covered by the dielectric material of the design layer structure 110. The upper horizontal side wall of each embedded component 112 is partially covered by the dielectric material of the other design layer structure 110 and partially covered by the metal material of the electrically conductive layer structure 104. The lower horizontal side wall of each embedded component 112 is connected to a designated connecting medium 120.

[0152] Although not in Figure 8 1 , but before completing the manufacture of the component carrier 100, the carrier 126 located at the release layer 124 can be removed. In this scenario, the carrier 126 is a temporary carrier. Alternatively, the carrier 126 can be a permanent carrier that is always part of the component carrier 100 that is easy to manufacture. The metal base 122 can always be part of the component carrier 100 that is easy to manufacture, or it can also be removed.

[0153] Although not shown, in the Figure 8After the stacking of component carriers 100 and the plurality of components 112 have been embedded in the plurality of layers of the stack 102, the carrier 126 can be removed, for example by detaching the release layer 124 to remove the carrier 126. For example, the detachment process can be triggered by electromagnetic radiation (such as UV radiation) and / or thermal energy. After etching the metal base 122 (which can be a copper metal layer), the alignment mark 162 can be used from the other side to place and solder one or more additional electronic components 112 on the external side. This chip-after method can achieve an alignment accuracy of less than 10 μm, preferably less than 5 μm. After placing such at least one additional surface mount component 112 on top of the component carrier 100, the one or more surface mount components 112 can be underfilled and / or overmolded. Then, the complete stack of component carriers 100 can be soldered on a mounting base, such as a motherboard or other type of printed circuit board (PCB).

[0154] As Figures 1 to 8 Alternatively to the embodiment shown, the entire dielectric surrounding of the embedded component 112 may also not consist of NIL material, but only a portion of the embedded component 112 may consist of NIL material. Alternatively, it is also possible, for example, to form the bottom portion of the dielectric surrounding of the embedded component 112 by a non-embossable dielectric (e.g. FR4) and to form the top portion of the dielectric surrounding by one or more designed layer structures 108, 110. Further alternatively, it is also possible, for example, to form the top portion of the dielectric surrounding of the embedded component 112 by a non-embossable dielectric (e.g. FR4) and to form the bottom portion of the dielectric surrounding by one or more designed layer structures 108, 110. This may in particular allow, if desired, to form the dielectric surrounding only using NIL material with excellent properties in terms of fine lining, while the remaining dielectric surrounding can be formed with very low effort by standard PCB dielectrics (e.g. prepreg or FR4).

[0155] Fig. 9 An apparatus 150 for embossing a surface contour in a design layer 108 , 110 using a working die 172 is shown in accordance with an exemplary embodiment.

[0156] As shown, a planar uncured design layer structure 108, 110 can be formed on a carrier 126, which can be transported along a support 168. The material of the design layer structure 108, 110 can be applied to the carrier 126 from a reservoir 170. The working mold 172 can have a designable and preferably tapered surface contour 174, and can emboss an inverse and preferably tapered surface contour 176 in the design layer structure 108, 110. For this purpose, the working mold 172 can be rotated, for example using a rotating wheel (not shown), thereby producing a continuous sheet of the design layer structure 108, 110 with an embossed contour. The design layer structure 108, 110 can be cured during embossing by a light source 180 (such as a UV lamp).

[0157] Figures 10 to 14 Shows that in the implementation of Fig.14 1. A cross-sectional view of a structure obtained during a method for manufacturing a component carrier 100 according to an exemplary embodiment of the present invention is shown.

[0158] Reference Fig.10 , a core 132 having a through hole 130 is provided as part of the stack 102. For example, the core 132 can be a plate of a fully cured resin, such as an epoxy resin, which includes reinforcing particles such as glass fibers. As shown, a patterned metal layer is provided at the lower main surface of the core 132. An additional patterned metal layer is formed at the upper main surface of the core 132. The two patterned metal layers can be structured copper foils, and an electrically conductive layer structure 104 can be formed on and / or in the core-type electrically insulating layer structure 106. The patterned metal layers can be interconnected by extending vertically through the additional electrically conductive layer structure 104 of the core 132. The bottom of the through hole 130 is closed by attaching a temporary carrier 126 to the bottom of the core 132. An electronic component 112 such as a semiconductor chip is mounted in the through hole 130 on the temporary carrier 126. The pad 118 of the electronic component 112 is oriented facing downward.

[0159] Reference Fig.11 , a sheet dielectric 134 may be provided for subsequent attachment to the top side of the core 132 and the top side of the component 112. For example, the dielectric 134 is a pure resin layer, which may be free of glass fibers and free of filler particles. This may ensure appropriate flow properties during subsequent lamination. In another embodiment, the sheet dielectric 134 may be implemented as an additional imprintable design layer structure, in particular a NIL resist. This additional imprintable design layer structure may be structured.

[0160] Reference Fig.12, dielectric 134 is attached to the top side of core 132 and the top side of component 112 by lamination, i.e., by applying heat and / or pressure. Thus, core 132, component 112, and dielectric 134 may be connected or fixed to each other by lamination. Thus, component 112 is partially surrounded by dielectric 134.

[0161] Reference Fig.13 , the temporary carrier 126 can then be removed.

[0162] Reference Fig.14 , the designed layer structure 108 can be applied to Fig.13 The bottom side of the structure shown, i.e., the engineered layer structure 108 may be applied to the core 132, to the component 112 (including portions of the pad 118 of the component 112), and to portions of the dielectric 134 that fill the gap between the component 112 and the core 132 during lamination.

[0163] Thereafter, the surface contour may be embossed on the bottom surface of the design layer structure 108, for example, using a working mold such as Fig. 9 The working mold shown is used to emboss the surface contour on the bottom surface of the designed layer structure 108. As a result of the embossing process, the pads 118 of the component 112 can be selectively exposed outside the designed layer structure 108. In addition, the embossing process can be adjusted so that the electrically conductive layer structure 104 located on the bottom side of the core 132 is also exposed.

[0164] Thereafter, further electrically conductive layer structures 104 may be formed by plating in recesses of the imprinted design layer structure 108 to connect with the exposed pads 118 and the exposed electrically conductive layer structures 104 located on the bottom side of the core 132. This may involve the formation of one or more electrically conductive traces 114 and / or one or more vertical through connections 116. Thus, the component 112 is suitably embedded in the stack 102 and is electrically connected within the component carrier 100. Furthermore, the dielectric surround of the component 112 is provided in part by the dielectric 134 and in part by the design layer structure 108.

[0165] Figures 15 to 21 Shows that in the implementation of Fig.21 1. A cross-sectional view of a structure obtained during a method for manufacturing a component carrier 100 according to an exemplary embodiment of the present invention is shown.

[0166] Fig.15 The manufacturing process starts at Figure 8 The component carrier 100 shown. On this basis, a connecting medium 120 (for example, solder or sintering paste) can be applied to the Figure 8The exposed electrically conductive layer structure 104 on the top side of the component carrier 100 shown. Thereafter, a further component 112 can be assembled on the connecting medium 120. Thereafter, a further (ie third) design layer structure 110 is applied on top of the further component 112 and Figure 8 On top of the component carrier 100 shown, and on top of the further component 112 and Figure 8 On top of the component carrier 100 shown, a further (ie third) design layer structure 110 is embossed. Fig.15 A further recess 136 is formed in the top major surface of the structure shown. This process corresponds to the above reference Figure 7 Describe the process.

[0167] Reference Fig.16 , can be made of metal materials according to Fig.15 The recess 136 formed is filled to form a further electrically conductive layer structure 104. This process corresponds to the above reference Figure 8 The metal material may be, for example, plated metal, sintered paste and / or magnetic paste.

[0168] Reference Fig.17 , an additional connecting medium 120 (e.g., solder or sintering paste) may be applied to Fig.16 On the exposed electrically conductive layer structure 104 on the top side of the structure shown. Thereafter, further components 112 may be assembled on said further connecting medium 120.

[0169] Reference Fig.18 , a further (i.e. fourth) design layer structure 110 is applied on top of the further component 112 and on top of the third design layer structure 110 and the further (i.e. fourth) design layer structure 110 is embossed on top of the further component 112 and on top of the third design layer structure 110. The obtained recess may then be filled with a further metallic material to form a further electrically conductive layer structure 104.

[0170] Reference Fig.19 , the temporary carrier 126 at the release layer 124 can be removed and the resulting structure can be turned upside down. Thus, a rotation of the panel can be performed and the (eg glass) carrier 126 can be detached.

[0171] Fig. 20 After the metal base 122 is removed, Fig.19The finest structures on the outer layer can be formed by etching the copper layer that can form the metal base 122 (and optionally, plasma back etching of the uppermost NIL resist). Due to the flatness of the carrier 126, a flat surface of the outer layer can be obtained.

[0172] Reference Fig.21 ,according to Fig. 20 The component carrier 100 can be mounted on a mounting base 186, such as a motherboard or a printed circuit board. On top of the component carrier 100, additional components 112 can be assembled by surface mounting. Connection structures 188 such as solder balls can be used to connect the surface mounted components 112 to the component carrier 100 and / or to connect the mounting base 186 to the component carrier 100.

[0173] Although not shown, an underfill may be inserted between the component carrier 100 and the surface mounted components 112. The surface mounted components 112 on the component carrier 100 may also be overmolded (not shown). Also not shown is that a surface finish may be applied to one or more of the exterior major surfaces (e.g., gold on metal structures and / or solder resist on dielectric structures).

[0174] The chip-last placement of one or more surface mounted components 112 can be accomplished by a connection structure 188, such as solder balls or any sintering paste. In particular, a substrate-type component carrier 100 with embedded components 112 and one or more chip-back components 112 can be soldered on top of a motherboard or other type of mounting base 186.

[0175] It should be pointed out that the term "comprising" does not exclude other elements or steps, and "a" or "an" does not exclude a plurality. Furthermore, elements described in connection with different embodiments may be combined.

[0176] It should also be noted that reference signs in the claims should not be construed as limiting the scope of the claims.

[0177] The implementation of the invention is not limited to the preferred embodiments shown in the figures and described above. Rather, even in the case of fundamentally different embodiments, multiple variations using the solutions shown and according to the principle of the invention are possible.

Claims

1. A component carrier (100), the component carrier (100) comprising: A stack (102) comprising at least one electrically conductive layer structure (104) and at least one electrically insulating layer structure (106), wherein the at least one electrically insulating layer structure (106) comprises at least one designed layer structure (108, 110) having an embossed surface contour; and A component (112) is embedded in the stack (102) and at least partially covered by the at least one engineered layer structure (108, 110).

2. The component carrier (100) according to claim 1, wherein: The electrically conductive traces (114) of the at least one electrically conductive layer structure (104) defined by the at least one designed layer structure (108, 110) have a roughness Ra of less than 100 nm, in particular, the electrically conductive traces (114) of the at least one electrically conductive layer structure (104) defined by the at least one designed layer structure (108, 110) have a roughness Ra of less than 50 nm.

3. The component carrier (100) according to claim 1 or 2, wherein: A vertical through-connection (116) of the at least one electrically conductive layer structure (104) defined by the at least one design layer structure (108, 110) has a depth-to-diameter ratio greater than 1, in particular, a vertical through-connection (116) of the at least one electrically conductive layer structure (104) defined by the at least one design layer structure (108, 110) has a depth-to-diameter ratio greater than 1.

5.

4. The component carrier (100) according to any one of claims 1 to 3, comprising at least one of the following features: in, The component (112) includes at least one pad (118) oriented to face upward and / or downward; wherein the connection region of the embedded component (112) is connected only to the at least one design layer structure (108, 110); wherein at least a portion of a vertical side wall of the embedded component (112) is covered by the at least one design layer structure (108, 110), in particular, at least five side walls of the embedded component (112) are at least partially covered by the at least one design layer structure (108, 110); wherein a first portion of the dielectric surrounding portion of the embedded component (112) is formed by a non-embossable dielectric, in particular, a bottom portion of the dielectric surrounding portion of the embedded component (112) is formed by a non-embossable dielectric, in particular, the non-embossable dielectric comprises a resin, and a second portion of the dielectric surrounding portion is formed by the at least one design layer structure (108, 110), in particular, a top portion of the dielectric surrounding portion is formed by the at least one design layer structure (108, 110); wherein the embedded component (112) is mounted on at least one of the at least one electrically conductive layer structures (104) via a connecting medium (120), in particular, the connecting medium (120) is a sintering material, a solder or an adhesive; wherein the at least one design layer structure (108, 110) has at least one recess (136), the at least one recess (136) being positioned transversely to the embedded component (112); Wherein the at least one engineered layer structure (108, 110) having the imprinted surface contour comprises a nanoimprint lithography dielectric.

5. A method for manufacturing a component carrier (100), wherein: The method comprises: forming a stack (102) comprising at least one electrically conductive layer structure (104) and at least one electrically insulating layer structure (106); embossing a surface contour in at least one design layer structure (108, 110) of the at least one electrically insulating layer structure (106); and A component (112) is embedded in the stack (102) such that the component (112) is at least partially covered by the at least one engineered layer structure (108, 110).

6. The method according to claim 5, wherein: The method includes forming an entire dielectric surround of the embedded component (112) by means of the at least one engineered layer structure (108, 110).

7. The method according to claim 6, wherein: Forming the entire dielectric surrounding of the embedded component (112) by means of the at least one designed layer structure (108, 110) is performed by: forming a first design layer structure (108) at least partially below the component (112) and embossing the first design layer structure (108) at least partially below the component (112); as well as A second design layer structure (110) is formed at least partially above the component (112) and the second design layer structure (110) at least partially above the component (112) is embossed.

8. The method according to claim 5, wherein: The method comprises: forming a first portion of the dielectric surrounding of the embedded component (112) by a non-embossable dielectric, in particular forming a bottom portion of the dielectric surrounding of the embedded component (112) by a non-embossable dielectric, in particular the non-embossable dielectric is a resin with reinforcing particles or a resin without reinforcing particles; and A second portion of the dielectric enclosure is formed by the at least one designed layer structure (108, 110), in particular a top portion of the dielectric enclosure is formed by the at least one designed layer structure (108, 110).

9. The method according to any one of claims 5 to 8, wherein: The method comprises: forming at least one of the at least one design layer structure (108, 110) on a metal base (122); embossing the at least one of the at least one design layer structures (108, 110) on the metal base (122) so that a portion of the metal base (122) is exposed; and At least a portion of the at least one electrically conductive layer structure (104) is plated on or over the exposed portion of the metal base (122).

10. The method according to claim 9, wherein: The plating includes electroplating.

11. The method according to any one of claims 5 to 10, wherein: The method includes arranging the component (112) such that at least one pad (118) is arranged facing upward.

12. The method according to claim 11, wherein: The method includes using the at least one pad (118) disposed face-upward as an alignment mark for subsequent processing.

13. The method according to any one of claims 5 to 12, wherein: The method comprises: forming a metal base (122) on a release layer (124) on a temporary carrier (126); forming at least one of the at least one design layer structure (108, 110) on the metal base (122); and Before the component carrier (100) is completed, the temporary carrier (126) located at the release layer (124) is removed.

14. The method according to claim 5, wherein: The method comprises: Providing a core (132) of the stack (102) having a through hole (130); closing the through hole (130) by attaching a temporary carrier (126) to the bottom of the core (132); Mounting the component (112) on the temporary carrier (126) in the through hole (130); subsequently partially surrounding the component (112) by a dielectric (134) of the at least one electrically insulating layer structure (106); The temporary carrier (126) is then removed; forming the at least one engineered layer structure (108, 110) at the core (132) and at the component (112); embossing a surface contour in the at least one engineered layer structure (108, 110) to expose at least one pad (118) of the component (112); and At least one electrically conductive layer structure of the at least one electrically conductive layer structure (104) is formed in the at least one imprinted design layer structure (108, 110) for connection with the exposed at least one pad (118).

15. The method according to any one of claims 5 to 14, comprising at least one of the following features: in, Imprinting a surface contour in the at least one designed layer structure (108, 110) includes: forming a tapered recess (136) in the at least one designed layer structure (108, 110); Wherein, embossing the surface contour portion in the at least one design layer structure (108, 110) comprises: forming recesses (136) having different depths and / or different lengths in the at least one design layer structure (108, 110); wherein embossing the surface contour in the at least one design layer structure (108, 110) comprises: forming a trace-shaped recess (136) and / or a via-shaped recess (136) and / or a combined trace-shaped and via-shaped recess (136) in the at least one design layer structure (108, 110); Wherein, the method comprises constructing the at least one designed layer structure (108, 110) as a dielectric for nanoimprint lithography; The method comprises: curing the at least one design layer structure (108, 110), in particular, simultaneously embossing and curing the at least one design layer structure (108, 110).

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