Method for improving efficiency of Topcon electroplating battery
By using discontinuous dot laser groove and seed layer growth technology on the Topcon cell, a controllable strip grid groove is formed and electroplating is performed, which solves the problems of cell opening voltage loss and low conversion efficiency after electroplating, and improves the plating effect and current.
Patent Information
- Application Number
- CN202510021436.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-03
- Publication Date
- 2025-04-22
AI Technical Summary
The existing Topcon electroplating technology is directly plating after slotting, which can easily lead to problems such as cell opening voltage loss, low conversion efficiency and reduced current.
Using discontinuous dot-shaped laser groove technology, several dot-shaped grooved points distributed between the front and back of the silicon substrate are formed, and then a seed layer is grown at the grooved point, and a strip-shaped grid line groove with controllable width is formed by mask exposure and development, and finally the metal grid line is electroplated on the exposed seed layer.
The impact of grooves on the passivation layer is minimized, the pressure opening loss is reduced, the electroplating effect and conversion efficiency are improved, and the adhesion between the electroplating metal gate lines and the silicon substrate is enhanced.
Smart Images
Figure CN119859829A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the technical field of solar cell manufacturing, and in particular, relates to a method for improving the efficiency of Topcon electroplating cells. Background Art
[0002] Topcon (Tunnel Oxide Passivated Contact) cells use an N-type structure. Compared with traditional PERC cells, a tunneling layer is added. This layer is composed of 1-2nm ultra-thin SiO2 and 100nm doped polysilicon layer, forming a heterojunction structure on the back. The conversion efficiency of Topcon cells is higher than that of PERC (Passivated Emitter and Rear Cell), reaching 24.7%; and it is compatible with existing PERC production lines and has excellent cell parameter performance. It is one of the photovoltaic cell technologies with the most room for development.
[0003] Because Topcon cells use silver paste on both the front and back sides, if the traditional printing silver paste method is used, as the battery production capacity expands, the silver consumption of photovoltaic cells will increase greatly, and the cost of the battery will increase a lot, which will seriously hinder the development of photovoltaic cells. At present, the traditional Topcon electroplating technology requires continuous laser grooving on the front and back sides of the cell to form a strip grid line groove. At the same time, in order to smoothly carry out electroplating and form a good ohmic contact, the silicon nitride at the strip groove needs to be cleaned up. However, since there is a velvet surface on the front side of the cell, if the silicon nitride on the pyramid is to be cleaned up, it is bound to damage the silicon substrate at the bottom of the pyramid, resulting in a loss of the cell opening voltage. In addition, the silicon nitride and aluminum oxide at the laser strip groove have a passivation effect. If they are all removed, it will not only affect the passivation of the cell, but also affect the opening voltage and efficiency; and if electroplating is directly carried out at the laser groove, the grid line will be widened after electroplating, resulting in a larger shading area occupied by the grid line, resulting in a decrease in current. Summary of the invention
[0004] The present application provides a method for improving the efficiency of Topcon electroplating cells, which solves the technical problem that the existing grid line is directly electroplated after grooving, which easily leads to cell voltage loss, low conversion efficiency and reduced current.
[0005] In order to solve at least one of the above technical problems, the technical solution adopted in this application is:
[0006] A method for improving the efficiency of a Topcon electroplating cell, comprising:
[0007] Laser grooves are made on both sides of the silicon substrate, and the grooves on the front side are located at the top of the velvet surface;
[0008] Growing a seed layer on both sides of the grooved silicon substrate;
[0009] printing a mask on the seed layer;
[0010] Expose and develop the silicon substrate to obtain a strip-shaped gate line groove and expose the seed layer at that location;
[0011] Electroplating metal grid lines on the exposed seed layer;
[0012] The mask and seed layer at the non-strip grid line grooves are removed to obtain a Topcon cell.
[0013] Furthermore, a picosecond laser is used to perform discontinuous laser grooving on the front and back sides of the silicon substrate, respectively, to obtain a number of dot-shaped grooving points spaced apart along the length of the grid line.
[0014] Furthermore, the pulse energy used for front grooving is less than 1uj, and the groove depth is the depth of the top passivation layer of the suede surface; the pulse energy used for back grooving is 1-2uj, and the groove depth is the depth of the back passivation layer;
[0015] Preferably, after the groove forming, the method further includes removing the silicon dioxide oxide layer generated during the groove forming.
[0016] Furthermore, a PVD process is used to sputter metal on the front and back sides of the silicon substrate in sequence to obtain a metal seed layer covering the grooved areas and the non-grooved areas; the material of the seed layer includes one or more combinations of nickel, titanium, aluminum, and silver; wherein the metal sputtered on the front side is an alloy of aluminum and nickel; and the metal sputtered on the back side is nickel.
[0017] Furthermore, the method further includes performing oxygen-free sintering on the sputtered seed layer so that the seed layer metal at the slotted point forms ohmic contact with the silicon substrate, wherein the temperature of the oxygen-free sintering is 200-600° C. and the sintering time is 30-180 seconds.
[0018] Furthermore, the printing of the mask on the seed layer is specifically as follows: based on the area of the seed layer, photosensitive ink is printed on the front and back sides of the silicon substrate respectively to a thickness of 5-20 um to form a mask layer.
[0019] Furthermore, the front and back sides of the silicon substrate are exposed respectively, and then both sides are developed simultaneously to expose the mask layer at the non-strip gate line grooves, so that the mask layer at the strip gate line grooves that are not exposed is washed away by the developer, thereby exposing the metal seed layer at the strip gate line grooves.
[0020] Furthermore, before electroplating the metal gate lines, a circle of ink is coated on the edges of both sides of the silicon substrate to complete the edge wrapping of the silicon substrate and prevent metal from growing on the edges of the silicon substrate when electroplating the metal gate lines.
[0021] Furthermore, electroplating is simultaneously performed on the seed layer leaking out from both sides of the silicon substrate after the hemming is completed, and copper and tin are electroplated in sequence to obtain metal grid lines, wherein the copper layer has a thickness of 10-30 um and the tin layer has a thickness of 1-2 um.
[0022] Furthermore, a strong alkaline solution is used to remove the remaining mask layer on both sides of the silicon substrate simultaneously; and a strong acid is used to remove the seed layer at the non-strip grid line groove to obtain a Topcon cell.
[0023] A method for improving the efficiency of Topcon electroplating cells designed in the present application is adopted to perform non-continuous point-shaped grooves on the top of the velvet surface on the front side and the back side of the silicon substrate, respectively, so as to facilitate the deposition of a seed layer on both sides thereof, so that ohmic contact is first formed at the point-shaped groove points; then, a mask is exposed and developed on the seed layer to obtain a strip-shaped gate line groove with controllable width; finally, metal gate lines are electroplated based on the strip-shaped gate line grooves, so as to minimize the influence of the grooves on the passivation layer, reduce the opening voltage loss, improve the electroplating effect, increase the adhesion of the electroplated metal gate lines to the silicon substrate, and improve the conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 is a flow chart of a method for improving the efficiency of a Topcon electroplating cell in the present application;
[0025] Figure 2 is a schematic diagram of a partial cross section of a silicon substrate in the present application;
[0026] Figure 3 It is a schematic diagram showing the distribution of some dot-shaped slot points in the front side of the present application;
[0027] Figure 4 is a schematic diagram of a partial cross section of a silicon substrate after grooves are formed in the present application;
[0028] Figure 5 is a schematic diagram of a partial cross section of a silicon substrate with a seed layer in the present application;
[0029] Figure 6 is a schematic diagram of a partial cross section of a silicon substrate printed with a mask layer in the present application;
[0030] Figure 7 is a schematic diagram of a partial cross section of a silicon substrate after exposure and development in the present application;
[0031] Figure 8 is a schematic diagram showing the distribution of some strip-shaped gate line grooves in the front side after exposure and development in this application;
[0032] Fig. 9 is a schematic diagram of a partial cross section of a silicon substrate plated with metal grid lines in the present application;
[0033] Fig.10 is a schematic diagram of a partial cross section of a silicon substrate after removing the mask layer in the present application;
[0034] Fig.11 It is a partial cross-sectional schematic diagram of a Topcon cell in this application.
[0035] 10. Silicon substrate 20. Passivation layer 30. Grooving point
[0036] 40, seed layer 50, mask layer 60, metal gate line DETAILED DESCRIPTION
[0037] The present application is described in detail below with reference to the accompanying drawings and specific embodiments.
[0038] This embodiment proposes a method for improving the efficiency of Topcon electroplating cells, such as Figure 1 As shown, the steps include:
[0039] S1. Laser grooves are made on both sides of the silicon substrate, and the groove position on the front side is located at the top of the velvet surface.
[0040] like Figure 2 As shown, the silicon substrate 10 is a semi-finished blue film with a passivation layer 20 on both sides. The upper end face of the silicon substrate 10 is the front side, and the surface is a pyramid-shaped velvet surface; the lower end face is the back side, and the surface is a polished surface with an arc-shaped curved surface. Passivation layers 20 adapted to the surface structure are provided on the front and back sides of the silicon substrate 10, wherein the front velvet surface has a passivation layer 20 formed of aluminum oxide and silicon nitride; the back polished surface has a passivation layer 20 formed of a poly layer and silicon nitride. These passivation layers not only help to increase the battery opening voltage, but also help to protect the surface of the silicon substrate.
[0041] In this embodiment, all steps are performed sequentially or synchronously on both sides of the silicon substrate. Although the layout and structure of the gate line structure on the front side and the gate line structure on the back side are different, the overall operation method is the same. Therefore, in all corresponding drawings, some structures on the front side and back side of the silicon substrate are used as examples for illustration. All subsequent drawings are the same as above and will not be repeated.
[0042] Laser grooving is performed on the front and back sides of the silicon substrate 10 respectively, wherein the grooving sequence is not limited, and the grooving can be performed on the front side first and then on the back side, or on the back side first and then on the front side.
[0043] like Figure 3As shown, no matter what the slotting sequence is, a picosecond laser is used to perform a discontinuous laser slotting operation on each side, that is, intermittent single-pulse laser slotting is performed on the front and back of the silicon substrate, respectively, to obtain a number of point-shaped slotting points spaced apart along the length direction of the grid line. For adjacent slotting points along the length direction of the same grid line, the gap L between them is 1-10um. By controlling the power of the laser, the front slotting position can be placed at the top position of its velvet surface, and a point-shaped slotting point 30 can be obtained. The laser can remove the passivation layer at the top and retain the silicon substrate at the top, so that the slotting point 30 only occupies the area of the point-shaped hole type, thereby retaining most of the passivation layer in the length direction of the grid line, and thus will not weaken the effect of the passivation layer in the length direction of the grid line, nor will it reduce the battery opening voltage and conversion efficiency.
[0044] As shown in Figure 4, the pulse energy of the laser used for front grooving is less than 1uJ, and the grooving depth is the depth of the passivation layer in the top of the suede. Using a low-power single-pulse laser for discontinuous grooving, several spaced dot-shaped grooving points 30 can be formed in the length direction of the grid lines on the front.
[0045] This low-power laser pulse can perform discontinuous laser grooving at a relatively low power on the top of the front suede surface to form a plurality of spaced grooving points 30, which only damages the passivation layer at the top of the pyramid in the suede surface and does not affect the passivation layer at the base of the suede surface. It can protect the overall passivation layer and reduce the damage to the passivation layer caused by grooving. The silicon substrate is only exposed at the location of the grooving points 30 to facilitate subsequent electroplating operations and form an effective ohmic contact.
[0046] On the back side of the silicon substrate, a discontinuous laser grooving operation is also performed to obtain a number of dot-shaped grooving points 30 spaced apart along the length direction of the gate line. The distribution positions are as follows: Figure 3 The laser pulse energy used for back grooving is 1-2uj, which is larger than that used for front grooving. Accordingly, the point diameter of the grooving point 30 obtained is larger, and the grooving point 30 with a width of 5-20um can be obtained at the grooving position.
[0047] During grooving, the grooving point 30 on the surface of the silicon substrate is affected by the laser temperature, and the silicon substrate at the location of the grooving point 30 is easily oxidized to form a layer of silicon dioxide oxide layer (omitted in the figure). Since this silicon dioxide oxide layer will hinder the growth of the seed layer, it is necessary to use a hydrogen fluoride solution with a concentration ratio of 1-15% to remove the silicon dioxide oxide layer on both sides of the silicon substrate, and the removal amount on one side of the silicon substrate should be 3-5um, so that the silicon dioxide oxide layer can be completely removed.
[0048] Since the groove lines at the grooves are not continuous, there is no way to directly electroplate metal. Therefore, it is necessary to first continuously grow and deposit a layer of gate line metal seed layer 40 at the groove points 30 and non-grooved points 30 in the length direction of the gate line, and then perform metal electroplating to make the metal gate line 60 have better adhesion to the silicon substrate.
[0049] S2. Growing seed layers on both sides of the grooved silicon substrate.
[0050] like Figure 5 As shown, a PVD process is used to sputter a metal layer on the front and back sides of the silicon substrate 10 in sequence to obtain a metal seed layer 40 covering the grooved areas and non-grooved areas. That is, a seed layer 40 is first deposited and grown on an entire surface of the front and back sides of the silicon substrate 10, so that the seed layer 40 first forms an ohmic contact with the silicon substrate at the groove point 30, and then a layer of metal gate line 60 is plated on the metal seed layer 40 at the gate line position.
[0051] This step also includes oxygen-free sintering of the sputtered seed layer 40 to make the seed layer metal at the groove point 30 form an ohmic contact with the silicon substrate, wherein the oxygen-free sintering temperature is 200-600° C. and the sintering time is 30-180 seconds.
[0052] Since the metal grid line 60 has unstable adhesion when it is directly combined with the silicon substrate 10 and is easy to fall off, a seed layer 40 is first deposited and grown on the silicon substrate 10 at the groove, and an ohmic contact is first formed between the seed layer at the groove point 30 and the silicon substrate. After that, metal copper and tin are electroplated on the seed layer 40. The metal copper and tin are more easily combined with the seed layer 40, which is also a metal, and the bonding force is stronger, thereby indirectly increasing the adhesion between the metal copper and tin and the silicon substrate. Then, the metal grid line 60 required for the Topcon cell is formed on the silicon substrate, which not only ensures that the final width of the metal grid line 60 is within the standard range and will not be widened, reduces the shading area, and prevents the current from decreasing; but also improves the adhesion between the metal grid line 60 and the silicon substrate 10, solves the technical problem of poor adhesion between the metal grid line 60 and the cell, and improves the conductivity of the metal grid line.
[0053] In this process, the metal seed layer 40 completely covers the grooved and non-grooved areas on both sides of the silicon substrate 10, that is, covers the entire surface of both sides of the silicon wafer. The material of the seed layer 40 includes one or more combinations of nickel, titanium, aluminum, and silver, that is, the material of the seed layer 40 can be a material made of a single metal, or an alloy material formed by a mixture of multiple metals. In this embodiment, the metal sputtered on the front side is an alloy of aluminum and nickel, forming an aluminum-nickel alloy seed layer 40; the metal sputtered on the back side is nickel, forming a nickel seed layer 40.
[0054] S3. Printing a mask on the seed layer.
[0055] like Figure 6 As shown, based on the area of the double-sided seed layer, photosensitive ink is printed on the front and back sides of the silicon substrate 10 respectively to cover the entire seed layer, and its thickness is 5-20um, forming a mask layer 50 to facilitate subsequent exposure and development operations.
[0056] S4, exposing and developing the silicon substrate to obtain a strip-shaped gate line groove and exposing the seed layer there.
[0057] like Figure 7 As shown, an exposure machine is used to expose the front side first and then the back side, and by grabbing the laser mark point, the exposed gate line and the gate line where the laser slot point 20 is located are aligned to expose the mask layer on all non-strip gate line grooves, and the exposure line width is 5-15um. Then, both sides are developed simultaneously, so that the mask layer 50 at the strip gate line groove that is not exposed is washed away by the developer, thereby exposing the metal seed layer 40 on the strip gate line groove.
[0058] like Figure 8 As shown, it is an example diagram of the distribution of the strip-shaped gate line grooves on the front side; wherein the strip-shaped gate line groove structure of the back side gate line has the same shape as that in the front side.
[0059] S5. Electroplating metal grid lines on the exposed seed layer.
[0060] Before electroplating the metal gate line 60 , a circle of ink is coated on the edges of both sides of the silicon substrate to complete the edge wrapping of the silicon substrate to prevent metal from growing on the edge of the silicon substrate 10 when electroplating the metal gate line 60 .
[0061] like Fig. 9 As shown, electroplating is simultaneously performed on the seed layer 40 leaking out of the strip-shaped gate line grooves on both sides of the silicon substrate 10 after the edge wrapping is completed, and copper and tin are electroplated in sequence to obtain metal gate lines 60, wherein the copper layer thickness is 10-30um and the tin layer thickness is 1-2um.
[0062] S6. Remove the mask and seed layer at the non-strip-shaped gate line grooves to obtain a Topcon cell.
[0063] like Fig.10 As shown, in the etching groove section, the double sides of the silicon substrate 10 are simultaneously cleaned by spraying, and the remaining mask layer 50 is first removed by a strong alkaline solution, that is, the mask layer 50 at the non-gate line groove is removed; then the seed layer 40 at the non-strip gate line groove is removed by a strong acid, and finally the following is obtained: Fig.11 The Topcon cell shown.
[0064] The cell efficiency characterization parameters of the cell prepared by the method of the present application and the cell prepared by the prior art are shown in Table 1. It can be clearly seen from the table that the short-circuit current, open-circuit voltage and conversion efficiency of the cell prepared by the method of the present application are significantly better than those of the cell prepared by the prior art, and the filling factor of the cell prepared by the method of the present application is lower than that of the cell prepared by the prior art. Therefore, it can be better explained that the use of point-shaped grooving to obtain a seed layer that can form an ohmic contact with the silicon substrate in advance can be used to obtain a precisely controllable strip grid line width through mask matching in the subsequent process to increase the short-circuit current. Not only can the adhesion between the grid line and the silicon substrate be improved, but also the grooving power can be reduced, the damage to the passivation layer can be reduced, and the opening voltage can be increased; and the metal seed layer is prepared by PVD, even if the grooving area is not continuous, metal copper and nickel can be electroplated to improve the adhesion between the metal grid line and the silicon substrate. Moreover, oxygen-free sintering in the local area can improve the ohmic contact between the metal and silicon, effectively reduce metal recombination, and improve conversion efficiency.
[0065] Table 1 Characterization parameters of cell efficiency of cells prepared by different methods
[0066] Short circuit current Isc / A Open circuit voltage Uoc / V Filling factor FF / % Conversion efficiency Eta / % Comparative example of existing methods 18.267 0.730 86.47 26.147 Embodiments of the present application method 18.304 0.739 86.34 26.487
[0067] A method for improving the efficiency of Topcon electroplating cells designed in the present application is adopted to perform non-continuous point-shaped grooves on the top of the velvet surface on the front side and the back side of the silicon substrate, respectively, so as to facilitate the deposition of a seed layer on both sides thereof, so that ohmic contact is first formed at the point-shaped groove points; then, a mask is exposed and developed on the seed layer to obtain a strip-shaped gate line groove with controllable width; finally, metal gate lines are electroplated based on the strip-shaped gate line grooves, so as to minimize the influence of the grooves on the passivation layer, reduce the opening voltage loss, improve the electroplating effect, increase the adhesion of the electroplated metal gate lines to the silicon substrate, and improve the conversion efficiency.
[0068] The above detailed description of the embodiments of the present application is only a preferred embodiment of the present application and cannot be considered to limit the scope of implementation of the present application. All equivalent changes and improvements made within the scope of the present application should still fall within the scope of the patent coverage of the present application.
Claims
1. A method for improving the efficiency of Topcon electroplating cells, characterized in that the steps include: Laser grooves are made on both sides of the silicon substrate, and the grooves on the front side are located at the top of the velvet surface; Growing a seed layer on both sides of the grooved silicon substrate; printing a mask on the seed layer; Expose and develop the silicon substrate to obtain a strip-shaped gate line groove and expose the seed layer at that location; Electroplating metal grid lines on the exposed seed layer; The mask and seed layer at the non-strip grid line grooves are removed to obtain a Topcon cell.
2. A method for improving the efficiency of a Topcon electroplating cell according to claim 1, characterized in that: A picosecond laser is used to perform discontinuous laser grooving on the front and back of a silicon substrate, respectively, to obtain a number of dot-shaped grooving points spaced along the length of the grid line.
3. A method for improving the efficiency of a Topcon electroplating cell according to claim 2, characterized in that: The pulse energy used for front grooving is less than 1uj, and the grooving depth is the depth of the passivation layer on the top of the suede surface; The pulse energy used for back side groove is 1-2uj, and the groove depth is the depth of the back side passivation layer; Preferably, after the groove forming, the method further includes removing the silicon dioxide oxide layer generated during the groove forming.
4. A method for improving the efficiency of a Topcon electroplating cell according to any one of claims 1 to 3, characterized in that: The PVD process is used to sputter metal on the front and back of the silicon substrate in sequence to obtain a metal seed layer covering the grooved and non-grooved areas; the material of the seed layer includes one or more combinations of nickel, titanium, aluminum, and silver; wherein the metal sputtered on the front is an alloy of aluminum and nickel; and the metal sputtered on the back is nickel.
5. A method for improving the efficiency of a Topcon electroplating cell according to claim 4, characterized in that: The method also includes oxygen-free sintering of the sputtered seed layer so that the seed layer metal at the slotted point forms ohmic contact with the silicon substrate, wherein the temperature of the oxygen-free sintering is 200-600° C. and the sintering time is 30-180 seconds.
6. A method for improving the efficiency of a Topcon electroplating cell according to any one of claims 1-3 and 5, characterized in that: The printing of the mask on the seed layer specifically includes: printing photosensitive ink on the front and back sides of the silicon substrate respectively based on the area of the seed layer to a thickness of 5-20 um to form a mask layer.
7. A method for improving the efficiency of a Topcon electroplating cell according to claim 6, characterized in that: The front and back sides of the silicon substrate are exposed respectively, and then both sides are developed simultaneously to expose the mask layer at the non-strip gate line grooves, so that the mask layer at the strip gate line grooves that are not exposed is washed away by the developer, thereby exposing the metal seed layer at the strip gate line grooves.
8. A method for improving the efficiency of a Topcon electroplating cell according to any one of claims 1-3, 5, and 7, characterized in that: Before electroplating the metal grid lines, a circle of ink is applied to the edges of both sides of the silicon substrate to complete the edge wrapping of the silicon substrate and prevent metal from growing on the edges of the silicon substrate when electroplating the metal grid lines.
9. A method for improving the efficiency of a Topcon electroplating cell according to claim 8, characterized in that: Electroplating is simultaneously performed on the seed layer leaking out from both sides of the silicon substrate after the hemming is completed, and copper and tin are electroplated in sequence to obtain metal grid lines, wherein the copper layer is 10-30um thick and the tin layer is 1-2um thick.
10. A method for improving the efficiency of a Topcon electroplating cell according to any one of claims 1-3, 5, 7, and 9, characterized in that: At the same time, a strong alkaline solution is used to remove the remaining mask layer on both sides of the silicon substrate; and a strong acid is then used to remove the seed layer at the non-strip grid line groove to obtain a Topcon cell.