Method for depositing thick-layer silicon epitaxial wafer on ultra-thin substrate for semiconductor power device

Abstract

The present invention discloses a method for depositing a thick layer of silicon epitaxial wafer on an ultra-thin substrate for semiconductor power devices. By comprehensively designing key process parameters different from traditional growth temperature, heating power, heating-up time, cooling-down time, etc., the induced defects of epitaxy such as stacking faults, dislocations, slip lines, orange peel, and back and edge crystal point adsorption easily generated by traditional processes are overcome. The traditional process is simplified, the process is simple, the industrial continuous production cost is reduced, and the batch deposition of thick layer silicon epitaxial wafers on 6-inch and 8-inch ultra-thin silicon substrates is realized. The product parameters have good uniformity, and the five-point thickness non-uniformity is <0.8%, meeting the market demand in the industry for thick layer silicon epitaxial wafers on 6-inch and 8-inch ultra-thin substrates.

Description

Technical Field

[0001] The present invention belongs to the field of deposition of semiconductor silicon epitaxial wafers on semiconductor substrates, and particularly relates to a method for depositing a thick silicon epitaxial wafer on an ultra-thin substrate for semiconductor power devices. Background Art

[0002] A silicon epitaxial wafer is a silicon wafer obtained by depositing a semiconductor silicon epitaxial layer on a silicon substrate wafer. Through a gas-phase chemical reaction at high temperature, a semiconductor silicon single-crystal thin film layer is epitaxially grown on a polished silicon single-crystal substrate. By controlling the growth conditions, silicon epitaxial layers with different resistivities, different thicknesses, and different types can be obtained for manufacturing various silicon-based semiconductor power devices. The semiconductor power device structures of high-voltage large semiconductor power devices such as 1200V FRED, PIN, and IGBT require a relatively thick silicon epitaxial layer of more than 120μm as a voltage-resistant functional layer. Based on the slot size requirements of conventional process carriers, conventional thickness silicon epitaxial wafers of (5 - 100)μm can also use silicon substrate wafers with conventional thicknesses specified by the corresponding national standards. However, for relatively thick silicon epitaxial layers far above 100μm, thinner silicon substrate wafers must be used to ensure that the total thickness of the final silicon wafer can be placed in the wafer slot of the process carrier without damage.

[0003] For example, the national standard stipulates the thickness of silicon substrate wafers. For 6-inch silicon substrate wafers, the thickness is (625 ± 15)μm, and for 8-inch silicon substrate wafers, the thickness is (725 ± 15)μm. However, silicon epitaxial wafers for high-voltage semiconductor power devices such as 1200V FRED, PIN, and IGBT require a relatively thick silicon epitaxial layer of more than 120μm. Therefore, according to the requirement of the total thickness, ultra-thin 6-inch silicon substrate wafers with a thickness of (525 ± 15)μm or ultra-thin 8-inch silicon substrate wafers with a thickness of (625 ± 15)μm are selected for epitaxial growth to ensure that the thick silicon epitaxial wafer formed after the thick silicon epitaxial layer is formed on the silicon substrate wafer can be placed in the wafer slot of the process carrier without damage. Moreover, the ultra-thin silicon substrate wafers can save the process time of back thinning in the subsequent device processing, and further reduce the device manufacturing cost.

[0004] However, the ultra-thin silicon substrate wafer increases the difficulty of controlling the film-forming quality of the thick silicon epitaxial layer. The probability of induced defects in epitaxy such as stacking faults, dislocations, slip lines, orange peel, and back and edge crystal point adsorption is higher. This is because after the silicon wafer size reaches a relatively large size of 6 inches or 8 inches, problems such as severe position deviation of the silicon substrate wafer during the wafer loading process and the heating process are more likely to occur. The uncontrollable adhesion problem between the silicon substrate wafer and the edge of the base wafer pit causes the silicon epitaxial wafer to be easily broken, significantly increasing the breakage rate. Especially when growing a thick silicon epitaxial layer, it is easier to generate induced defects in epitaxy such as stacking faults, dislocations, slip lines, orange peel, and back and edge crystal point adsorption compared to a conventional thin silicon epitaxial layer. Therefore, growing a thick silicon epitaxial layer on an ultra-thin silicon substrate wafer requires higher process parameters such as process temperature and growth rate, and the difficulty is obviously greater.

[0005] Currently, the process methods for growing silicon epitaxial wafers on ultra-thin silicon substrate wafers far below the conventional thickness are as follows: The Chinese patent with the publication number CN 104947183 A discloses a method for preparing a silicon epitaxial layer on a heavily doped thin phosphorus substrate for a Schottky device: using a thin phosphorus-silicon substrate wafer instead of a silicon substrate wafer with a conventional thickness, first growing an intrinsic epitaxial layer with a growth rate of the intrinsic layer controlled at 1 μm / min, and then growing a doped epitaxial layer with a growth rate controlled at 1.2 μm / min. The disadvantage is that it introduces the growth of two silicon epitaxial layers with a changing growth rate, and the process is more complex, increasing the control difficulty of batch industrial production. The Chinese patent with the publication number CN 106128938 A discloses a method for preparing a thick epitaxial layer on a thin Sb substrate for a VDMOS device. Selecting a thin Sb substrate instead of a silicon substrate wafer with a conventional thickness requires first growing a very thin intrinsic epitaxial layer on the silicon wafer with the growth rate of the intrinsic epitaxial layer controlled at 2.0 - 2.5 μm / min, and then growing a doped epitaxial layer with a growth rate controlled at 2.5 - 2.8 μm / min, achieving good control over the epitaxial growth of the thin Sb substrate and successfully preparing an epitaxial layer with good thickness uniformity and good edge crystallization quality. However, the disadvantage is also that it introduces the growth of two silicon epitaxial layers with a changing growth rate, and the process is more complex, increasing the control difficulty of batch industrial production.

[0006] Currently, there is no publicly reported deposition method for growing a thick silicon epitaxial layer of more than 100 μm to form a silicon epitaxial wafer on 6-inch and 8-inch ultra-thin silicon substrate wafers far below the conventional thickness. Therefore, a deposition method for 6-inch and 8-inch ultra-thin substrate thick-layer silicon epitaxial wafers for semiconductor power devices with good parameter uniformity (five-point thickness non-uniformity < 0.8%), simple process, and meeting the requirements of industrial continuous production is needed. Summary of the Invention

[0007] In view of the existing technical situation and problems, the present invention provides a method for depositing a thick silicon epitaxial wafer on an ultra-thin substrate for a semiconductor power device. By using this method, the problem that the silicon epitaxial wafers grown on 6-inch and 8-inch ultra-thin silicon substrates by traditional silicon epitaxial furnaces need to adopt more complex process methods such as growing two layers of silicon epitaxial layers with gradually changing growth rates due to overcoming thermal stress, mechanical stress, internal stress of silicon wafer deformation, etc., which affects industrial continuous production, is solved. The ultra-thin silicon substrate deposited by this method realizes that the thickness non-uniformity at five points of the silicon epitaxial layer is <0.8%, and overcomes the induced defects of epitaxy such as no layer faults, dislocations, slip lines, orange peel on the surface, and no crystal point adsorption on the back and edges.

[0008] The technical solution adopted by the present invention is: a method for depositing a thick silicon epitaxial wafer on an ultra-thin substrate for a semiconductor power device includes the following steps in sequence:

[0009] S1. Heat the reaction chamber of the silicon epitaxial furnace to 1120 - 1140 °C, and introduce hydrogen chloride and hydrogen to etch and clean the reaction chamber and the graphite base. The flow rate of the hydrogen chloride gas is 30 - 35 L / min, the flow rate of the hydrogen gas is 25 - 30 L / min, and the etching and cleaning time is 15 - 16 min.

[0010] S2. The reaction chamber of the silicon epitaxial furnace starts to cool down. After cooling to 300 - 350 °C, wait for another 300 - 360 s and then place the ultra-thin silicon substrate in the wafer pit of the graphite base in the reaction chamber of the silicon epitaxial furnace in the center to avoid serious deviation of the wafer placement position of the ultra-thin silicon substrate.

[0011] S3. Heat the reaction chamber of the silicon epitaxial furnace and the graphite base starting from the initial 300 - 350 °C. First, perform power heating. The initial set heating power is 20 kW, which is increased to 78 - 80 kW, and the time is set to 480 - 540 s, corresponding to the reaction chamber of the silicon epitaxial furnace heating up to 900 - 930 °C. Then, continue to heat at a constant power to finally heat the reaction chamber of the silicon epitaxial furnace to 1040 - 1060 °C. Subsequently, bake the surface of the ultra-thin silicon substrate, and the baking time is set to 3 - 5 min.

[0012] S4. Use hydrogen to carry trichlorosilane as the growth silicon source to grow a silicon epitaxial layer on the polished surface of the ultra-thin silicon substrate. The rotation speed of the graphite base is set to 3 - 4 r / min, and the acceleration of the rotation speed of the graphite base is set to 0.4 - 0.6 r / min 2, used to reduce the severe displacement of the position of the ultra-thin silicon substrate wafer during the rotation of the graphite base. The hydrogen flow rate is 180 - 200 L / min, the flow rate of trichlorosilane is 7 - 8 g / min, the growth temperature of the silicon epitaxial layer is 1020 - 1040 °C, and the growth rate is set to 1.2 - 1.5 μm / min, which is used to reduce the occurrence of cracking caused by the continuous accumulation of stress during the growth of the thick silicon epitaxial layer; the target thickness of the silicon epitaxial layer is 125 - 135 μm, and the target five-point thickness non-uniformity is <0.8%. After reaching the target thickness of the silicon epitaxial layer, a thick silicon epitaxial wafer is formed.

[0013] S5. Purge the reaction chamber of the silicon epitaxial furnace with nitrogen. The nitrogen purge flow rate is 100 - 150 L / min, the nitrogen purge time is 10 - 15 min, the temperature of the reaction chamber of the silicon epitaxial furnace is cooled to 300 - 350 °C, and the cooling time is 700 - 840 sec. Then, take out the thick silicon epitaxial wafer from the wafer pit of the graphite base of the reaction chamber of the silicon epitaxial furnace.

[0014] The silicon epitaxial furnace described in the present invention is the North China Technology 630 model silicon epitaxial furnace.

[0015] In step S2 of the present invention, the ultra-thin silicon substrate wafers are 6-inch and 8-inch ultra-thin silicon substrate wafers. Among them, the thickness specification of the 6-inch ultra-thin silicon substrate wafer is designed as 525 ± 15 μm, and the thickness specification of the 8-inch ultra-thin silicon substrate wafer is designed as 625 ± 15 μm.

[0016] In step S3 of the present invention, a slow heating design is adopted, and the total time for heating the reaction chamber of the silicon epitaxial furnace from the initial temperature to 1040 - 1060 °C is set to 800 - 1000 sec, which is used to reduce the situation of severe deformation and cracking of the ultra-thin silicon substrate wafer during the heating process.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] 1. The North China Technology 630 model flat multi-wafer silicon epitaxial furnace is adopted, and the comprehensive design is different from the key process parameters such as the traditional growth temperature, heating power, heating time, and cooling time; it overcomes the induced defects of epitaxy such as stacking faults, dislocations, slip lines, orange peel, and back and edge crystal point adsorption easily generated by the traditional process.

[0019] 2. The traditional process is simplified, the process is simple, the industrialized continuous production cost is reduced, and the batch deposition of thick silicon epitaxial wafers on 6-inch and 8-inch ultra-thin silicon substrates is realized.

[0020] 3. The product parameters have good uniformity, the five-point thickness non-uniformity of the silicon epitaxial layer is <0.8%, which meets the market demand in the industry for thick silicon epitaxial wafers on 6-inch and 8-inch ultra-thin silicon substrates. Description of the Drawings

[0021] Figure 1 Schematic diagram of the five - point thickness distribution of the silicon epitaxial layer produced in Example 1 of the present invention;

[0022] Figure 2 Schematic diagram of the five - point thickness distribution of the silicon epitaxial layer produced in Example 2 of the present invention;

[0023] Figure 3 Schematic diagram of the five - point thickness distribution of the silicon epitaxial layer produced in Example 3 of the present invention;

[0024] Figure 4 Schematic diagram of the five - point thickness distribution of the silicon epitaxial layer produced in Example 4 of the present invention;

[0025] Figure 5 Schematic diagram of the five - point thickness distribution of the silicon epitaxial layer produced in Example 5 of the present invention;

[0026] Figure 6 Schematic diagram of the five - point thickness distribution of the silicon epitaxial layer produced in Comparative Example 2 of the present invention. Detailed implementation manners

[0027] The technical solutions of the present invention will be clearly and completely described below in conjunction with the embodiments.

[0028] A method for depositing a thick - layer silicon epitaxial wafer on an ultra - thin substrate for a semiconductor power device includes the following steps in sequence:

[0029] S1. Using a silicon epitaxial furnace of the 630 model from North China Electronic Equipment Corporation, heating the reaction chamber of the silicon epitaxial furnace to 1120 - 1140 °C, introducing hydrogen chloride and hydrogen to etch and clean the reaction chamber and the graphite base. The flow rate of the hydrogen chloride gas is 30 - 35 L / min, the flow rate of the hydrogen gas is 25 - 30 L / min, and the etching and cleaning time is 15 - 16 min.

[0030] S2. The reaction chamber of the silicon epitaxial furnace starts to cool down. After cooling to 300 - 350 °C, wait for another 300 - 360 sec and then place the ultra - thin silicon substrate wafer in the wafer pit of the graphite base in the reaction chamber of the silicon epitaxial furnace in the center to avoid serious deviation in the wafer - placing position of the ultra - thin silicon substrate wafer; the ultra - thin silicon substrate wafer is a 6 - inch or 8 - inch ultra - thin silicon substrate wafer. Among them, the thickness specification of the 6 - inch ultra - thin silicon substrate wafer is designed to be 525 ± 15 μm, and the thickness specification of the 8 - inch ultra - thin silicon substrate wafer is designed to be 625 ± 15 μm.

[0031] The crystal orientation of the 6 - inch and 8 - inch ultra - thin silicon substrate wafers is <100>, the resistivity is 1 - 4 Ω·cm, the oxygen content is 8 - 14 ppma. The front surface of the 6 - inch and 8 - inch ultra - thin silicon substrate wafers is a polished surface, and the back surface is coated with a 450 - 550 nm silicon dioxide back - sealing layer, and the edge removal amount is 0.8 - 1.0 mm.

[0032] S3. Heat the reaction chamber of the silicon epitaxial furnace and the graphite pedestal starting from an initial temperature of 300 - 350 °C. First, perform power heating. The initial set heating power is 20 kW, which is increased to 78 - 80 kW. The time required for the power increase is set to 480 - 540 sec. Correspondingly, the reaction chamber of the silicon epitaxial furnace is heated to 900 - 930 °C. Then, continue heating while maintaining a constant power to raise the temperature of the reaction chamber of the silicon epitaxial furnace to 1040 - 1060 °C. Subsequently, bake the surface of the ultra-thin silicon substrate wafer, and the baking time is set to 3 - 5 min.

[0033] Adopt a slow heating design, and set the total time for heating the reaction chamber of the silicon epitaxial furnace from the initial temperature to 1040 - 1060 °C to 800 - 1000 sec to reduce the situation where the ultra-thin silicon substrate wafer undergoes severe deformation and breaks during the heating process.

[0034] S4. Use hydrogen to carry trichlorosilane as the growth silicon source to grow a silicon epitaxial layer on the polished surface of the ultra-thin silicon substrate wafer. The rotation speed of the graphite pedestal is set to 3 - 4 r / min, and the acceleration of the rotation speed of the graphite pedestal is set to 0.4 - 0.6 r / min 2 , to reduce the severe deviation of the position of the ultra-thin silicon substrate wafer during the rotation of the graphite pedestal. The hydrogen flow rate is 180 - 200 L / min, the flow rate of trichlorosilane is 7 - 8 g / min, the growth temperature of the silicon epitaxial layer is 1020 - 1040 °C, and the growth rate is set to 1.2 - 1.5 μm / min to reduce the occurrence of cracking caused by the continuous accumulation of stress during the growth of the thick silicon epitaxial layer; the target thickness of the silicon epitaxial layer is 125 - 135 μm, and the target five-point thickness non-uniformity < 0.8%. After reaching the target thickness of the silicon epitaxial layer, a thick silicon epitaxial wafer is formed.

[0035] S5. Introduce nitrogen to purge the reaction chamber of the silicon epitaxial furnace. The nitrogen purge flow rate is 100 - 150 L / min, the nitrogen purge time is 10 - 15 min, the temperature of the reaction chamber of the silicon epitaxial furnace is cooled to 300 - 350 °C, and the cooling time is 700 - 840 sec. Then, take out the thick silicon epitaxial wafer from the wafer pit of the graphite pedestal in the reaction chamber of the silicon epitaxial furnace.

[0036] Through a sufficient cooling process for the silicon epitaxial wafer, the thermal stress continuously accumulated during the growth of the silicon epitaxial wafer is released well, significantly reducing the risk of cracking of the silicon epitaxial wafer.

[0037] Example 1: The method for depositing a thick silicon epitaxial wafer on an ultra-thin substrate for a semiconductor power device in this example is as follows:

[0038] S1. The reaction chamber of the silicon epitaxial furnace is heated to 1120 °C, and hydrogen chloride and hydrogen are introduced to etch and clean the reaction chamber and the graphite base. The flow rate of hydrogen chloride gas is 35 L / min, the flow rate of hydrogen gas is 25 L / min, and the etching and cleaning time is 15 min.

[0039] S2. The reaction chamber of the silicon epitaxial furnace starts to cool down. After cooling to 300 °C, wait for another 360 sec and then place the 6-inch ultra-thin silicon substrate in the wafer pit of the graphite base in the reaction chamber of the silicon epitaxial furnace centered to avoid serious deviation in the wafer placement position of the ultra-thin silicon substrate; the thickness specification of the 6-inch ultra-thin silicon substrate is designed to be 525 ± 15 μm.

[0040] S3. Heat the reaction chamber of the silicon epitaxial furnace and the graphite base starting from the initial 300 °C. First, perform power heating. The initial set heating power is 20 kW, which is increased to 78 kW, and the time is set to 480 sec, corresponding to the reaction chamber of the silicon epitaxial furnace heating up to 900 °C. Then, continue to heat at a constant power to finally heat the reaction chamber of the silicon epitaxial furnace to 1040 °C. The total time required for heating is 850 sec. Subsequently, bake the surface of the 6-inch ultra-thin silicon substrate, and the baking time is set to 3 min.

[0041] S4. Use hydrogen to carry trichlorosilane as the growth silicon source to grow a silicon epitaxial layer on the polished surface of the 6-inch ultra-thin silicon substrate. The rotation speed of the graphite base is set to 4 r / min, and the acceleration of the rotation speed of the graphite base is set to 0.4 r / min 2 , which is used to reduce the serious deviation in the position of the 6-inch ultra-thin silicon substrate during the rotation of the graphite base. The hydrogen flow rate is 180 L / min, the flow rate of trichlorosilane is 7 g / min, the growth temperature of the silicon epitaxial layer is 1040 °C, and the growth rate is set to 1.2 μm / min, which is used to reduce the occurrence of cracking caused by continuous stress accumulation during the growth of the thick silicon epitaxial layer; the target thickness of the silicon epitaxial layer is 125 - 135 μm, and the target five-point thickness non-uniformity is <0.8%. After reaching the target thickness of the silicon epitaxial layer, a thick silicon epitaxial wafer is formed.

[0042] S5. Introduce nitrogen to purge the reaction chamber of the silicon epitaxial furnace. The nitrogen purge flow rate is 100 L / min, the nitrogen purge time is 10 min, the reaction chamber of the silicon epitaxial furnace cools down to 300 °C, and the cooling time is 840 sec. Then, take out the thick silicon epitaxial wafer from the wafer pit of the graphite base in the reaction chamber of the silicon epitaxial furnace.

[0043] For Example 1, the 5-point test positions for the thickness of the silicon epitaxial wafer are the center point with the main parameter facing up and the four points 6 mm away from the edge directly above, below, left, and right of the center point. Calculate the average thickness of the silicon epitaxial wafer according to the 5-point test positions, as Figure 1As shown, the thicknesses of the silicon epitaxial layers are 125.442 μm, 126.225 μm, 124.194 μm, 125.113 μm, and 125.176 μm respectively, with an average value of 125.23 μm, and the five-point thickness non-uniformity is 0.58%, which meets the standard of the target five-point thickness non-uniformity < 0.8%, and there are no epitaxial-induced defects such as stacking faults, dislocations, slip lines, orange peel on the surface, and no crystal point adsorption on the back and edges.

[0044] Example 2: The method steps of the ultra-thin substrate deposited thick-layer silicon epitaxial wafer for semiconductor power devices in this example are as follows:

[0045] S1. Heat the reaction chamber of the silicon epitaxial furnace to 1120 °C, and introduce hydrogen chloride and hydrogen to etch and clean the reaction chamber and the graphite base. The flow rate of hydrogen chloride gas is 35 L / min, the flow rate of hydrogen gas is 25 L / min, and the etching and cleaning time is 15 min.

[0046] S2. The reaction chamber of the silicon epitaxial furnace starts to cool down. After cooling to 300 °C, wait for another 300 sec and then place the 6-inch ultra-thin silicon substrate in the wafer pit of the graphite base in the reaction chamber of the silicon epitaxial furnace in the center to avoid serious deviation of the placement position of the ultra-thin silicon substrate; the thickness specification of the 6-inch ultra-thin silicon substrate is designed to be 525 ± 15 μm.

[0047] S3. Heat the reaction chamber of the silicon epitaxial furnace and the graphite base starting from the initial 300 °C. First, perform power heating. The initial set heating power is 20 kW, which is increased to 80 kW, and the time is set to 480 sec, corresponding to the reaction chamber of the silicon epitaxial furnace heating up to 900 °C. Then, continue to heat at a constant power to make the reaction chamber of the silicon epitaxial furnace finally heat up to 1040 °C. The total time required for heating is 800 sec. Subsequently, bake the surface of the 6-inch ultra-thin silicon substrate, and the baking time is set to 3 min.

[0048] S4. Use hydrogen to carry trichlorosilane as the growth silicon source to grow the silicon epitaxial layer on the polished surface of the 6-inch ultra-thin silicon substrate. The rotation speed of the graphite base is set to 4 r / min, and the acceleration of the rotation speed of the graphite base is set to 0.4 r / min 2 , which is used to reduce the serious deviation of the position of the 6-inch ultra-thin silicon substrate during the rotation of the graphite base. The hydrogen flow rate is 185 L / min, the flow rate of trichlorosilane is 7 g / min, the growth temperature of the silicon epitaxial layer is 1040 °C, and the growth rate is set to 1.25 μm / min, which is used to reduce the occurrence of cracking caused by continuous stress accumulation during the growth of the thick-layer silicon epitaxial layer; the target thickness of the silicon epitaxial layer is 125 - 135 μm, and the target five-point thickness non-uniformity < 0.8%. After reaching the target thickness of the silicon epitaxial layer, a thick-layer silicon epitaxial wafer is formed.

[0049] S5. Purge the reaction chamber of the silicon epitaxial furnace with nitrogen. The nitrogen purge flow rate is 100 L / min, and the nitrogen purge time is 10 min. Cool the reaction chamber of the silicon epitaxial furnace to 300 °C, and the cooling time is 840 sec. Then, take out the thick-layer silicon epitaxial wafer from the wafer pit of the graphite base of the reaction chamber of the silicon epitaxial furnace.

[0050] For Example 2, the 5-point test positions for the thickness of the silicon epitaxial wafer are the center point with the main parameter facing up and the four points 6 mm away from the edge directly above, below, left, and right of the center point. Calculate the average thickness of the silicon epitaxial wafer according to the 5-point test positions. As Figure 2 shown, the thicknesses of the silicon epitaxial layers are 125.558 μm, 126.512 μm, 124.176 μm, 125.265 μm, and 125.372 μm respectively. The average value is 125.38 μm, and the non-uniformity of the five-point thickness is 0.66%, that is, it meets the standard of the target five-point thickness non-uniformity < 0.8%, and there are no epitaxial-induced defects such as stacking faults, dislocations, slip lines, orange peel on the surface, and no crystal point adsorption on the back and edges.

[0051] Example 3: The method steps for depositing a thick-layer silicon epitaxial wafer on an ultra-thin substrate for a semiconductor power device in this example are as follows:

[0052] S1. Heat the reaction chamber of the silicon epitaxial furnace to 1120 °C, and introduce hydrogen chloride and hydrogen to etch and clean the reaction chamber and the graphite base. The flow rate of hydrogen chloride gas is 35 L / min, the flow rate of hydrogen gas is 25 L / min, and the etching and cleaning time is 15 min.

[0053] S2. Start to cool the reaction chamber of the silicon epitaxial furnace. After cooling to 300 °C, wait for another 360 sec and then place the 6-inch ultra-thin silicon substrate wafer in the center of the wafer pit of the graphite base of the reaction chamber of the silicon epitaxial furnace to avoid serious deviation of the wafer placement position of the ultra-thin silicon substrate wafer; the thickness specification of the 6-inch ultra-thin silicon substrate wafer is designed to be 525 ± 15 μm.

[0054] S3. Heat the reaction chamber of the silicon epitaxial furnace and the graphite base starting from the initial 300 °C. First, perform power heating. The initial set heating power is 20 kW, which is increased to 80 kW, and the time is set to 540 sec, corresponding to the reaction chamber of the silicon epitaxial furnace heating up to 900 °C. Then, continue to heat at a constant power to finally heat the reaction chamber of the silicon epitaxial furnace to 1040 °C. The total heating time required is 850 sec. Subsequently, bake the surface of the 6-inch ultra-thin silicon substrate wafer, and the baking time is set to 3 min.

[0055] S4. Use hydrogen to carry trichlorosilane as the growth silicon source, and grow a silicon epitaxial layer on the polished surface of a 6-inch ultra-thin silicon substrate wafer. Set the rotation speed of the graphite pedestal to 4 r / min, and the acceleration of the rotation speed of the graphite pedestal to 0.6 r / min 2 , which is used to reduce the serious deviation of the position of the 6-inch ultra-thin silicon substrate wafer during the rotation of the graphite pedestal. The hydrogen flow rate is 190 L / min, the flow rate of trichlorosilane is 8 g / min, the growth temperature of the silicon epitaxial layer is 1040 °C, and the growth rate is set to 1.4 μm / min, which is used to reduce the occurrence of cracking caused by the continuous accumulation of stress during the growth of the thick silicon epitaxial layer; the target thickness of the silicon epitaxial layer is 125 - 135 μm, the target five-point thickness non-uniformity < 0.8%, and after reaching the target thickness of the silicon epitaxial layer, a thick silicon epitaxial wafer is formed.

[0056] S5. Introduce nitrogen to purge the reaction chamber of the silicon epitaxial furnace. The nitrogen purge flow rate is 100 L / min, the nitrogen purge time is 10 min, the reaction chamber of the silicon epitaxial furnace is cooled to 300 °C, and the cooling time is 840 sec. Then, take out the thick silicon epitaxial wafer from the wafer pit of the graphite pedestal in the reaction chamber of the silicon epitaxial furnace.

[0057] For the 5-point test positions of the thickness of the silicon epitaxial wafer in Example 3, the center point with the main parameter facing up and the four points 6 mm away from the edge directly above, below, left, and right of the center point are used. Calculate the average thickness of the silicon epitaxial wafer according to the 5-point test positions. As Figure 3 shown, the thicknesses of the silicon epitaxial layers are 125.682 μm, 126.711 μm, 124.198 μm, 125.361 μm, and 125.422 μm respectively, the average value is 125.47 μm, and the five-point thickness non-uniformity is 0.71%, that is, it meets the standard of the target five-point thickness non-uniformity < 0.8%, and there are no epitaxial-induced defects such as stacking faults, dislocations, slip lines, orange peel on the surface, and no crystal point adsorption on the back and edges.

[0058] Example 4: The method steps for depositing a thick silicon epitaxial wafer on an ultra-thin substrate for a semiconductor power device in this example are as follows:

[0059] S1. Heat the reaction chamber of the silicon epitaxial furnace to 1120 °C, and introduce hydrogen chloride and hydrogen to etch and clean the reaction chamber and the graphite pedestal. The flow rate of hydrogen chloride gas is 35 L / min, the flow rate of hydrogen gas is 25 L / min, and the etching and cleaning time is 15 min.

[0060] S2. The reaction chamber of the silicon epitaxial furnace starts to cool down. After cooling to 300 °C, wait for another 360 sec and then place the 6-inch ultra-thin silicon substrate wafer in the center of the wafer pit of the graphite pedestal in the reaction chamber of the silicon epitaxial furnace to avoid serious deviation of the wafer placement position of the ultra-thin silicon substrate wafer; the thickness specification of the 6-inch ultra-thin silicon substrate wafer is designed to be 525 ± 15 μm.

[0061] S3. Heat the reaction chamber of the silicon epitaxial furnace and the graphite pedestal starting from the initial 300 °C. First, perform power heating. The initial set heating power is 20 kW, which is increased to 78 kW, and the time is set to 480 sec. Correspondingly, the reaction chamber of the silicon epitaxial furnace is heated to 900 °C. Then, continue heating at a constant power to finally heat the reaction chamber of the silicon epitaxial furnace to 1040 °C. The total time required for heating is 850 sec. Subsequently, bake the surface of the 6-inch ultra-thin silicon substrate, and the baking time is set to 3 min.

[0062] S4. Use hydrogen to carry trichlorosilane as the growth silicon source to grow a silicon epitaxial layer on the polished surface of the 6-inch ultra-thin silicon substrate. The rotation speed of the graphite pedestal is set to 4 r / min, and the acceleration of the rotation speed of the graphite pedestal is set to 0.4 r / min 2 , which is used to reduce the serious position deviation of the 6-inch ultra-thin silicon substrate during the rotation of the graphite pedestal. The hydrogen flow rate is 195 L / min, the flow rate of trichlorosilane is 8 g / min, the growth temperature of the silicon epitaxial layer is 1040 °C, and the growth rate is set to 1.45 μm / min, which is used to reduce the occurrence of cracking caused by the continuous accumulation of stress during the growth of the thick silicon epitaxial layer; the target thickness of the silicon epitaxial layer is 125 - 135 μm, and the target five-point thickness non-uniformity is <0.8%. After reaching the target thickness of the silicon epitaxial layer, a thick silicon epitaxial wafer is formed.

[0063] S5. Introduce nitrogen to purge the reaction chamber of the silicon epitaxial furnace. The nitrogen purge flow rate is 100 L / min, and the nitrogen purge time is 10 min. The reaction chamber of the silicon epitaxial furnace is cooled to 300 °C, and the cooling time is 840 sec. Then, take out the thick silicon epitaxial wafer from the wafer pit of the graphite pedestal in the reaction chamber of the silicon epitaxial furnace.

[0064] For Example 4, the 5-point test positions for the thickness of the silicon epitaxial wafer are the center point with the main parameter facing up and the four points 6 mm away from the edge directly above, below, left, and right of the center point. Calculate the average thickness of the silicon epitaxial wafer according to the 5-point test positions. As Figure 4 shown, the thicknesses of the silicon epitaxial layers are 125.695 μm, 126.825 μm, 124.223 μm, 125.473 μm, and 125.655 μm respectively. The average value is 125.57 μm, and the five-point thickness non-uniformity is 0.73%, which meets the standard of the target five-point thickness non-uniformity <0.8%, and there are no epitaxial-induced defects such as stacking faults, dislocations, slip lines, orange peel on the surface, and no crystal point adsorption on the back and edges.

[0065] Example 5: The method steps for depositing a thick silicon epitaxial wafer on an ultra-thin substrate for a semiconductor power device in this example are as follows:

[0066] S1. The reaction chamber of the silicon epitaxial furnace is heated to 1120 °C, and hydrogen chloride and hydrogen are introduced to etch and clean the reaction chamber and the graphite base. The flow rate of hydrogen chloride gas is 35 L / min, the flow rate of hydrogen gas is 25 L / min, and the etching and cleaning time is 15 min.

[0067] S2. The reaction chamber of the silicon epitaxial furnace starts to cool down. After cooling to 300 °C, wait for another 360 sec and then place the 6-inch ultra-thin silicon substrate in the wafer pit of the graphite base in the reaction chamber of the silicon epitaxial furnace centered to avoid serious deviation of the placement position of the ultra-thin silicon substrate; the thickness specification of the 6-inch ultra-thin silicon substrate is designed to be 525 ± 15 μm.

[0068] S3. Heat the reaction chamber of the silicon epitaxial furnace and the graphite base starting from the initial 300 °C. First, perform power heating. The initial set heating power is 20 kW, which is increased to 80 kW, and the time is set to 540 sec, corresponding to the reaction chamber of the silicon epitaxial furnace heating up to 900 °C. Then, continue to heat at a constant power to finally heat the reaction chamber of the silicon epitaxial furnace to 1040 °C. The total time required for heating is 850 sec. Subsequently, bake the surface of the 6-inch ultra-thin silicon substrate, and the baking time is set to 3 min.

[0069] S4. Use hydrogen to carry trichlorosilane as the growth silicon source to grow a silicon epitaxial layer on the polished surface of the 6-inch ultra-thin silicon substrate. The rotation speed of the graphite base is set to 4 r / min, and the acceleration of the rotation speed of the graphite base is set to 0.4 r / min 2 , which is used to reduce the serious deviation of the position of the 6-inch ultra-thin silicon substrate during the rotation of the graphite base. The hydrogen flow rate is 200 L / min, the flow rate of trichlorosilane is 7 g / min, the growth temperature of the silicon epitaxial layer is 1040 °C, and the growth rate is set to 1.3 μm / min, which is used to reduce the occurrence of cracking caused by continuous stress accumulation during the growth of the thick silicon epitaxial layer; the target thickness of the silicon epitaxial layer is 125 - 135 μm, and the target five-point thickness non-uniformity < 0.8%. After reaching the target thickness of the silicon epitaxial layer, a thick silicon epitaxial wafer is formed.

[0070] S5. Introduce nitrogen to purge the reaction chamber of the silicon epitaxial furnace. The nitrogen purge flow rate is 100 L / min, the nitrogen purge time is 10 min, the reaction chamber of the silicon epitaxial furnace cools down to 300 °C, and the cooling time is 840 sec. Then, take out the thick silicon epitaxial wafer from the wafer pit of the graphite base in the reaction chamber of the silicon epitaxial furnace.

[0071] For the 5-point thickness test position of the silicon epitaxial wafer in Example 5, the center point with the main parameter facing up and the four points 6 mm away from the edge directly above, below, left, and right of the center point are used. Calculate the average thickness of the silicon epitaxial wafer according to the 5-point test position, as Figure 5As shown, the thicknesses of the silicon epitaxial layers are 125.727μm, 126.952μm, 124.324μm, 125.589μm, and 125.793μm respectively. The average value is 125.67μm, and the five-point thickness non-uniformity is 0.74%, which meets the standard of the target five-point thickness non-uniformity <0.8%, and there are no epitaxial-induced defects such as stacking faults, dislocations, slip lines, orange peel on the surface, and no crystal point adsorption on the back and edges.

[0072] Comparative Example 1: The difference between this comparative example and Example 5 is that the heating power in step S3 of this comparative example is increased from 20kW to a different power, and the heating power in step S3 of this comparative example is set to 81kW when increased from 20kW.

[0073] Slip lines appear at the edge of the surface of the silicon epitaxial wafer prepared in Comparative Example 1, which does not meet the requirements of the present invention.

[0074] Comparative Example 2: The difference between this comparative example and Example 5 is that the hydrogen flow rate in step S4 of this comparative example is different; the hydrogen flow rate in this comparative example is set to 205 L / min.

[0075] For the silicon epitaxial wafer prepared in Comparative Example 2, the five-point test positions of the thickness are the center point with the main parameter facing up and the four points 6mm away from the edge directly above, below, left, and right of the center point. The average value of the thickness of the silicon epitaxial wafer is calculated according to the five-point test positions, as Figure 6 shown, the thicknesses of the silicon epitaxial layers are 125.802μm, 127.190μm, 124.332μm, 125.603μm, and 125.802μm respectively. The average value is 125.74μm, and the five-point thickness non-uniformity is 0.81%, that is, it does not meet the standard of the target five-point thickness non-uniformity <0.8%, and does not meet the requirements of the present invention.

[0076] Comparative Example 3: The difference between this comparative example and Example 5 is that the time for temperature reduction in step S5 of this comparative example is different, and the time for temperature reduction in this comparative example is set to 690sec.

[0077] Slip lines appear at the edge of the surface of the silicon epitaxial wafer prepared in Comparative Example 3, which does not meet the requirements of the present invention.

[0078] Comparative Example 4: The difference between this comparative example and Example 5 is that the growth temperature in step S4 of this comparative example is different, and the growth temperature of the silicon epitaxial layer in this comparative example is set to 1050°C.

[0079] Dislocation defects appear on the surface of the silicon epitaxial wafer prepared in Comparative Example 4, which does not meet the requirements of the present invention.

[0080] Comparative Example 5: The difference between this comparative example and Example 5 is that the acceleration of the pedestal rotation speed in step S4 of this comparative example is different, and the acceleration of the pedestal rotation speed in this comparative example is set to 0.7 r / min. 2 .

[0081] Stacking fault defects appeared at the edge of the silicon epitaxial wafer obtained in Comparative Example 5, which did not meet the requirements of the present invention.

[0082] Comparative Example 6: The difference between this comparative example and Example 5 is that the waiting time after cooling in step S2 of this comparative example is different, and the waiting time after cooling in this comparative example is set to 290 sec.

[0083] Stacking fault defects appeared at the edge of the silicon epitaxial wafer obtained in Comparative Example 6, which did not meet the requirements of the present invention.

[0084] Comparative Example 7: The difference between this comparative example and Example 5 is that the total time required for heating up in step S3 of this comparative example is different, and the total time required for heating up in this comparative example reaches 790 sec.

[0085] Slip line defects appeared at the edge of the silicon epitaxial wafer obtained in Comparative Example 7, which did not meet the requirements of the present invention.

[0086] Through the above five examples and seven comparative examples, it can be verified that on the one hand, the present invention avoids the problem of serious position deviation of the ultra-thin silicon substrate during the wafer loading process and the heating process by designing key process parameters such as the waiting time after cooling of the reaction chamber and the acceleration of the pedestal rotation speed, thereby improving the film formation quality of depositing a thick silicon epitaxial layer on the ultra-thin silicon substrate, effectively alleviating the adhesion problem between the silicon substrate and the edge of the pedestal pit, and greatly reducing the breakage rate. On the other hand, by designing key process parameters such as the heating power, the total heating time, and the cooling time of the reaction chamber, the thermal stress accumulated by the silicon substrate during the heating stage and the epitaxial deposition process can be released in a timely manner.

[0087] By comprehensively designing key process parameters different from traditional growth temperature, heating power, heating time, cooling time, etc., the present invention overcomes the induced defects of epitaxy such as stacking faults, dislocations, slip lines, orange peel, and back and edge crystal point adsorption that are prone to occur in thick silicon epitaxial wafers under traditional epitaxial deposition processes, and achieves remarkable results in batch depositing thick silicon epitaxial wafers on 6-inch and 8-inch ultra-thin silicon substrates. The product parameters have good uniformity, and the thickness non-uniformity at five points is <0.8%, which is conducive to large-scale popularization and application.

[0088] The above five embodiments and seven comparative examples are all part of the implementation cases in the research and development process of the present invention. However, the protection scope of the present invention is not limited thereto. Those skilled in the art should understand that any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed by the present invention fall within the protection scope and the disclosure scope of the present invention.

Claims

1. A method for depositing thick silicon epitaxial wafers on ultra-thin substrates for semiconductor power devices, characterized in that: The method comprises the following steps: S1. The temperature of the silicon epitaxial furnace reaction chamber is raised to 1120-1140°C, and hydrogen chloride and hydrogen are introduced to etch and clean the reaction chamber and the graphite base. The hydrogen chloride gas flow rate is 30-35 L / min, the hydrogen gas flow rate is 25-30 L / min, and the etching and cleaning time is 15-16 min. S2, the silicon epitaxial furnace reaction chamber starts to cool down, and after cooling down to 300-350° C., wait for 300-360 seconds and then place the ultra-thin silicon substrate in the center of the sheet pit of the graphite base of the silicon epitaxial furnace reaction chamber to avoid serious deviation of the placement position of the ultra-thin silicon substrate; S3, heating the silicon epitaxial furnace reaction chamber and the graphite base from the initial 300-350°C, firstly power heating, the initial heating power is set to 20kW, increased to 78-80kW, the time is set to 480-540 seconds, the corresponding silicon epitaxial furnace reaction chamber is heated to 900-930°C, and then the temperature is continued to be raised at a constant power, so that the silicon epitaxial furnace reaction chamber is finally heated to 1040-1060°C, and then the surface of the ultra-thin silicon substrate is baked, and the baking time is set to 3-5min; adopting a slow heating design, the total time for heating the silicon epitaxial furnace reaction chamber from the initial temperature to 1040-1060°C is set to 800-1000sec, so as to reduce the situation that the ultra-thin silicon substrate is severely deformed and cracked during the heating process; S4, using hydrogen to carry trichlorosilane as a silicon growth source, growing a silicon epitaxial layer on the polished surface of the ultra-thin silicon substrate, the graphite pedestal speed is set to 3-4 r / min, and the acceleration of the graphite pedestal speed is set to 0.4-0.6 r / min 2 , used to reduce the serious position deviation of the ultra-thin silicon substrate during the rotation of the graphite base, the hydrogen flow rate is 180~200 L / min, the trichlorosilane flow rate is 7~8 g / min, the silicon epitaxial layer growth temperature is 1020~1040℃, and the growth rate is set to 1.2~1.5μm / min, which is used to reduce the occurrence of cracks caused by the continuous accumulation of stress in the thick silicon epitaxial layer during the growth process; the target thickness of the silicon epitaxial layer is 125~135μm, and the target five-point thickness non-uniformity is <0.8%. When the target thickness of the silicon epitaxial layer is reached, a thick silicon epitaxial wafer is formed; S5. Nitrogen is introduced into the silicon epitaxial furnace reaction chamber for purging. The nitrogen purge flow rate is 100-150 L / min. The nitrogen purge time is 10-15 min. The silicon epitaxial furnace reaction chamber is cooled to 300-350°C. The cooling time is 700-840 sec. Then, the thick silicon epitaxial wafer is taken out from the wafer pit of the graphite base of the silicon epitaxial furnace reaction chamber.

2. The method for depositing a thick silicon epitaxial wafer on an ultra-thin substrate for a semiconductor power device according to claim 1, characterized in that: The silicon epitaxial furnace is a North Huachuang 630 model silicon epitaxial furnace.

3. The method for depositing a thick silicon epitaxial wafer on an ultra-thin substrate for a semiconductor power device according to claim 1, characterized in that: In step S2, the ultra-thin silicon substrate sheet is a 6-inch or 8-inch ultra-thin silicon substrate sheet, wherein the thickness specification of the 6-inch ultra-thin silicon substrate sheet is designed to be 525±15 μm, and the thickness specification of the 8-inch ultra-thin silicon substrate sheet is designed to be 625±15 μm.

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