Chip packaging performance testing method

Abstract

The invention discloses a chip packaging performance test method. The method comprises the following steps: acquiring a first loss value of a chip of a to-be-tested chip packaging structure; under the state that the waveguide transmission assembly is not correspondingly connected with the chip packaging structure to be tested, the vector network analysis device is kept to be connected with the waveguide transmission assembly through a cable, and a second loss value of the waveguide transmission assembly is obtained; keeping the to-be-tested chip packaging structure to be correspondingly connected with the waveguide transmission assembly, keeping the vector network analysis device to be connected with the waveguide transmission assembly through a cable, and obtaining third loss values of the to-be-tested chip packaging structure and the waveguide transmission assembly; and based on the first loss value, the second loss value and the third loss value, determining the packaging loss of the to-be-tested chip packaging structure. The packaging loss of the chip packaging structure to be tested can be obtained by subtracting the first loss value and the second loss value from the third loss value, then the packaging performance of the chip packaging structure to be tested is determined according to the packaging loss, and the purpose of independently testing the packaging performance of the chip packaging structure is achieved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a chip packaging performance testing method. Background Art

[0002] In recent years, the automotive radar technology landscape has undergone major changes, especially in the field of millimeter-wave radar semiconductor packaging and 3D waveguide antennas. From the initial microstrip patch antenna to the 3D waveguide antenna, it has been driving the development of millimeter-wave radar technology.

[0003] The more advanced packaging technology is the key research object of major manufacturers. Among them, the loading on package (LoP) technology is to convert the chip signal into a waveguide form through the packaging substrate, and then connect it to the 3D antenna through an external metal waveguide to achieve low-loss and high-efficiency transmission of electromagnetic waves. With the 3D waveguide antenna, the radar can have better distance detection and target recognition capabilities.

[0004] In traditional packaging, the signal in the MMIC (monolithic microwave integrated circuit) is transmitted to the PCB (printed circuit board) through the BGA (solder ball), and then transitions to the antenna through the microstrip line. During this signal transmission process, the signal has four conversion losses, such as the "bare die-package substrate-BGA-PCB-antenna" conversion loss. In the loading on package (LoP) technology, the signal can have only two "bare die-package substrate-3D waveguide antenna" conversion losses, which reduces signal loss and improves the overall signal-to-noise ratio.

[0005] However, the inventors found in their research that the current performance testing of millimeter-wave radar chips mainly involves parameters such as the detection distance of the overall product-level test radar, the radiation power of the antenna, and the echo intermediate frequency signal. There is a lack of performance testing methods for the packaging structure, making it impossible to quantify the conversion loss in the load-on-package (LoP) technology. It is difficult to effectively determine the ability of the millimeter-wave radar chip to reduce signal loss and improve the overall signal-to-noise ratio using the load-on-package (LoP) technology. Summary of the invention

[0006] In view of this, the present invention provides a chip packaging performance testing method to solve the problem that the packaging performance of the chip packaging structure cannot be independently tested.

[0007] The present application provides a chip packaging performance testing method, comprising:

[0008] Obtaining a first loss value of a chip of the chip packaging structure to be tested;

[0009] When the waveguide transmission component is not connected to the chip package structure to be tested, the vector network analysis device is kept connected to the waveguide transmission component through a cable to obtain a second loss value of the waveguide transmission component;

[0010] Maintaining the corresponding connection between the chip packaging structure to be tested and the waveguide transmission component, maintaining the connection between the vector network analysis device and the waveguide transmission component via a cable, and obtaining the third loss value of the chip packaging structure to be tested and the waveguide transmission component;

[0011] Based on the first loss value, the second loss value and the third loss value, the packaging loss of the chip packaging structure to be tested is determined.

[0012] In some embodiments, the vector network analysis device includes a vector network analyzer and a calibration element; the step of obtaining a first loss value of a chip of a chip package structure to be tested includes:

[0013] calibrating the vector network analyzer by using the calibration element;

[0014] Calibrate the probe card on the probe station, keep the vector network analyzer connected to the probe card via the cable, and obtain the loss value L1 of the probe card via the vector network analyzer;

[0015] Placing the chip of the chip package structure to be tested on the probe station, keeping the probe card electrically connected to the chip, and obtaining the total loss value L2 of the chip and the probe card through the vector network analyzer;

[0016] Based on the loss value L1 of the probe card and the total loss value L2 of the chip and the probe card, a first loss value of the chip is determined.

[0017] In some embodiments, the vector network analysis device includes a vector network analyzer and a calibration element, the waveguide transmission component includes a circuit board, a positioning member and a waveguide coaxial converter, and when the waveguide transmission component is not connected to the chip packaging structure to be tested, the vector network analysis device is kept connected to the waveguide transmission component through a cable to obtain a second loss value of the waveguide transmission component, including:

[0018] When the positioning member is not connected to the circuit board, the waveguide-coaxial converter is kept connected to the positioning member, the vector network analyzer is kept connected to the waveguide-coaxial converter via the cable, and the loss value L3 of the positioning member is obtained via the vector network analyzer;

[0019] When the circuit board is not connected to the positioning piece, the waveguide-coaxial converter is kept connected to the circuit board, the vector network analyzer is kept connected to the waveguide-coaxial converter via the cable, and the loss value L4 of the circuit board is obtained via the vector network analyzer.

[0020] In some embodiments, the step of maintaining the corresponding connection between the chip package structure to be tested and the waveguide transmission component, maintaining the connection between the vector network analysis device and the waveguide transmission component via a cable, and obtaining the third loss value of the chip package structure to be tested and the waveguide transmission component includes:

[0021] Keep the circuit board, the positioning piece and the waveguide-coaxial converter connected, keep the chip packaging structure to be tested connected to the circuit board, keep the vector network analyzer connected to the waveguide-coaxial converter via the cable, and obtain the total loss value L5 of the chip packaging structure to be tested, the circuit board and the positioning piece through the vector network analyzer.

[0022] In some embodiments, determining the package loss of the chip package structure to be tested based on the first loss measurement value, the second loss measurement value, and the third loss measurement value includes:

[0023] The package loss L6 is obtained by L5-L4-L3-the first loss value of the chip.

[0024] In some embodiments, when the chip packaging structure to be tested has n symmetrically arranged signal transmission paths, the loss value of a single signal transmission path is obtained by L6 / n.

[0025] In some embodiments, the step of maintaining the connection between the waveguide-to-coaxial converter and the positioning member and maintaining the connection between the vector network analyzer and the waveguide-to-coaxial converter via the cable comprises:

[0026] Keeping the two waveguide coaxial converters connected to the vector network analyzer through the cables respectively;

[0027] The positioning member is clamped by two waveguide-coaxial converters, and the converter waveguides of the two waveguide-coaxial converters are respectively connected to the positioning member waveguides of the positioning member accordingly.

[0028] In some embodiments, the number of the positioning members is multiple, and the positioning member is clamped by two waveguide-coaxial converters, and the converter waveguides of the two waveguide-coaxial converters are respectively connected to the two ends of the positioning member waveguide of the positioning member, including:

[0029] A plurality of the positioning members are stacked, and the positioning member waveguides of the plurality of the positioning members are correspondingly connected in sequence along the stacking direction;

[0030] The plurality of stacked positioning members are clamped by two waveguide-coaxial converters, and the converter waveguides of the two waveguide-coaxial converters are respectively connected to the positioning member waveguides of the two positioning members located on the outside in the stacking direction.

[0031] In some embodiments, the step of maintaining the connection between the waveguide-to-coaxial converter and the circuit board and maintaining the connection between the vector network analyzer and the waveguide-to-coaxial converter via the cable comprises:

[0032] Keeping the two waveguide coaxial converters connected to the vector network analyzer through the cables respectively;

[0033] The circuit board is clamped by two waveguide-coaxial converters, and the converter waveguides of the two waveguide-coaxial converters are respectively connected to the two ends of the circuit board waveguide of the circuit board.

[0034] In some embodiments, it also includes:

[0035] Providing a plurality of the chip packaging structures to be tested of the same type, and obtaining the first loss value, the second loss value and the third loss value for each of the chip packaging structures to be tested;

[0036] Determine the packaging loss of each of the chip packaging structures to be tested based on the corresponding first loss value, the second loss value and the third loss value;

[0037] Based on the packaging losses of the plurality of chip packaging structures to be tested, it is determined whether the test result is accurate.

[0038] Compared with the prior art, the chip packaging performance testing method provided by the present invention has at least the following beneficial effects:

[0039] By respectively obtaining the first loss value of the chip, the second loss value of the waveguide transmission component, and the third loss value of the chip packaging structure to be tested and the waveguide transmission component, and subtracting the first loss value and the second loss value from the third loss value, the packaging loss of the chip packaging structure to be tested can be obtained, and then the packaging performance of the chip packaging structure to be tested can be determined according to the packaging loss, thereby achieving the purpose of individually testing the packaging performance of the chip packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A schematic diagram of a chip packaging structure to be tested provided by an embodiment of the present invention;

[0041] Figure 2 A flowchart of a chip packaging performance testing method provided by an embodiment of the invention;

[0042] Figure 3 A schematic diagram of a vector network analyzer provided in one embodiment of the present invention when testing the loss value of a chip and a probe card;

[0043] Figure 4 A schematic diagram of a vector network analyzer provided in one embodiment of the present invention when testing the loss value of a positioning component;

[0044] Figure 5 A schematic diagram of a vector network analyzer provided in one embodiment of the present invention when testing the loss value of a circuit board;

[0045] Figure 6 A schematic diagram of a vector network analyzer provided in one embodiment of the present invention testing a chip packaging structure to be tested and a total loss value of a waveguide transmission component.

[0046] In the figure: 10, chip packaging structure; 11, chip; 13, package body; 15, waveguide transmission channel; 21, probe station; 23, probe card; 30, cable; 40, vector network analyzer; 51, positioning piece; 52, positioning piece waveguide; 53, waveguide coaxial converter; 54, connecting piece; 55, circuit board; 56, circuit board waveguide. DETAILED DESCRIPTION

[0047] The present invention is further described below in conjunction with the accompanying drawings and specific implementation methods. It should be noted that, under the premise of no conflict, the various embodiments or technical features described below can be arbitrarily combined to form a new embodiment.

[0048] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, inside, outside, top, bottom...) are only used to explain the relative position relationship between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0049] It should also be noted that when an element is referred to as being "fixed on" or "disposed on" another element, the element may be directly on the other element or there may be an intermediate element at the same time. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element at the same time.

[0050] An embodiment of the present invention provides a chip packaging performance testing system, in which the test objects of the testing system include a chip packaging structure to be tested and a chip. The testing system obtains the loss of the chip packaging structure to be tested and the loss of the chip by testing respectively, and subtracts the loss of the chip from the loss of the chip packaging structure to be tested to obtain the packaging loss of the chip packaging structure to be tested, and determines the packaging performance of the chip packaging structure to be tested based on the packaging loss.

[0051] like Figure 1 As shown, the chip packaging structure 10 to be tested includes a chip 11 and a packaging body 13 that carries the chip 11. The loss of the chip 11 refers to the loss of the signal generated by the chip during the process of being transmitted from the chip 11 to the packaging body 13. The packaging loss refers to the loss of the signal during the process of being transmitted from the packaging body 13 to the external components connected to the packaging body 13. The loss obtained when the chip packaging structure 10 to be tested is used as a test object is the total loss of the chip 11 and the packaging body 13. Therefore, after the test system tests and obtains the total loss of the chip packaging structure 10 to be tested and the loss of the chip 11 respectively, the packaging loss is obtained by subtracting the loss of the chip 11 from the total loss of the chip packaging structure 10 to be tested.

[0052] It should be noted that the chip used as the test object may be the chip of the chip packaging structure to be tested itself. For example, before the chip is packaged, the chip loss may be tested first, and then the chip is packaged to form the chip packaging structure to be tested. The loss of the chip packaging structure to be tested may be further tested to obtain the packaging loss. Alternatively, the chip used as the test object may not be the chip of the chip packaging structure to be tested itself, but may be another chip that can accurately simulate the port characteristics of the chip of the chip packaging structure to be tested within the corresponding working frequency band. Therefore, the loss of the chip of the chip packaging structure to be tested may be indirectly obtained by testing the loss of the chip.

[0053] In another embodiment, the test object of the test system is the chip packaging structure to be tested. The test object does not include the chip, and the loss of the chip is used as a known condition. After the test system tests and obtains the loss of the chip packaging structure to be tested, the loss of the chip packaging structure to be tested is subtracted from the known chip loss, and the packaging loss of the chip packaging structure to be tested can also be obtained.

[0054] See also Figure 2 The present invention also provides a chip packaging performance testing method, which is applied to the above chip packaging performance testing system, and the method comprises:

[0055] Step 101: Obtain a first loss value of a chip of a chip packaging structure to be tested.

[0056] The loss value of a chip refers to the loss of a signal generated by the chip during transmission from the chip to an external component connected to the chip. The first loss value of the chip can be obtained by performing a corresponding test on the test system during the performance test, or the loss of the corresponding chip can be measured before the performance test. The first loss value of the chip is directly used as a known parameter during the performance test. In an optional example, the test system includes a vector network analyzer, a waveguide transmission component, and a probe component. The vector network analyzer and the probe component cooperate to test and obtain the first loss value of the chip.

[0057] It can be understood that the chip can be a radar chip used for vehicle-mounted millimeter-wave radar, or it can be an analog chip that can accurately simulate the port characteristics of the radar chip within the corresponding working frequency band.

[0058] Step 102: When the waveguide transmission component is not connected to the chip package structure to be tested, the vector network analysis device is connected to the waveguide transmission component via a cable to obtain a second loss value of the waveguide transmission component.

[0059] After the vector network analysis device is connected to the waveguide transmission component through a cable, the signal can be transmitted from the waveguide transmission component to the vector network analysis device through the cable, and the vector network analysis device can obtain the loss of the signal during the transmission process in the waveguide transmission component, that is, the second loss value of the waveguide transmission component.

[0060] Step 103: Keep the chip packaging structure to be tested connected to the waveguide transmission component accordingly, keep the vector network analysis device connected to the waveguide transmission component via a cable, and obtain the third loss value of the chip packaging structure to be tested and the waveguide transmission component.

[0061] When the chip packaging structure to be tested is connected to the waveguide transmission component in correspondence, the waveguide transmission channel of the package body corresponds to the waveguide structure of the waveguide transmission component. The signal generated by the chip is first transmitted to the waveguide transmission channel, and then from the waveguide transmission channel to the waveguide structure of the waveguide transmission component, and then from the waveguide structure to the vector network analysis device. The vector network analysis device can obtain the signal loss in the transmission process, that is, the signal loss in the process of being transmitted from the chip to the waveguide transmission channel of the package body, from the waveguide transmission channel of the package body to the waveguide structure of the waveguide transmission component, and from the waveguide structure of the waveguide transmission component to the vector network analysis device, that is, the total loss of the chip packaging structure to be tested and the waveguide transmission component.

[0062] Step 104: Determine the packaging loss of the chip packaging structure to be tested based on the first loss value, the second loss value, and the third loss value.

[0063] The total loss of the chip packaging structure to be tested and the waveguide transmission component, that is, the third loss value, is subtracted from the second loss value of the waveguide transmission component to obtain the overall loss of the chip packaging structure to be tested. Then, the overall loss of the chip packaging structure to be tested is subtracted from the loss of the chip to obtain the packaging loss of the chip packaging structure to be tested. The packaging performance of the chip packaging structure to be tested is determined based on the packaging loss. It should be noted that the first, second, and third here are only introduced to distinguish the description, and they do not have any meaning restrictions on the order or quantity. That is to say, in the above embodiments, the steps corresponding to the first loss value, the second loss value, and the third loss value can be interchanged arbitrarily.

[0064] In one embodiment, the probe assembly includes a probe station and a probe card, and the vector network analysis device includes a vector network analyzer and a calibration element; the vector network analysis device is connected to the probe assembly through a cable to obtain a corresponding first loss measurement value, including:

[0065] The vector network analyzer is calibrated using calibration components.

[0066] Connect the two cables to the vector network analyzer, select the calibration frequency band, and use the calibration components to calibrate the vector network analyzer. After the calibration is completed, check the loss error of the instrument through the S parameters of the vector network analyzer, control the error within ±0.05dB, save the calibration file, and reduce the impact of the error of the test instrument itself on the test results.

[0067] The probe card is calibrated on the probe station, the vector network analyzer is kept connected to the probe card via a cable, and the loss value L1 of the probe card is obtained through the vector network analyzer.

[0068] The chip of the chip package structure to be tested is placed on the probe station, the probe card is kept electrically connected to the chip, and the total loss value L2 of the chip and the probe card is obtained by a vector network analyzer.

[0069] Based on the loss value L1 of the probe card and the total loss value L2 of the chip and the probe card, a first loss value of the chip is determined.

[0070] After the vector network analyzer is connected to the probe card through a cable, you can choose not to place the chip on the probe station first, and calibrate the probe card on the probe station. The signal is transmitted from the probe card to the vector network analyzer, so as to obtain the loss value L1 of the probe card. After obtaining the loss value of the probe, Figure 3 As shown, the chip 11 can be placed on the probe station 21 of the probe assembly. The probe station 21 carries the chip 11 and provides an environment for on-wafer testing of the chip 11, so that the probe card 23 of the probe assembly is electrically connected to the chip 11. The signal generated by the chip 11 is first transmitted from the chip 11 to the probe card 23, and then transmitted from the probe card 23 to the vector network analyzer 40 through the cable 30. The vector network analyzer 40 can obtain the total loss value L2 of the chip 11 and the probe card 23. The loss value L1 of the probe card 23 is subtracted from the total loss value L2 to obtain the loss of the chip 11. It should be noted that L1 and L2 here, as well as L3, L4, and L5 below, are only introduced to distinguish the description, and they do not have any meaning restrictions on the order or quantity.

[0071] In one embodiment, the waveguide transmission component includes a circuit board, a positioning member, and a waveguide coaxial converter. When the waveguide transmission component is not connected to the chip packaging structure to be tested, the vector network analysis device is connected to the waveguide transmission component through a cable to obtain a second loss value of the waveguide transmission component, including:

[0072] When the positioning piece is not connected to the circuit board, the waveguide coaxial converter is kept connected to the positioning piece, the vector network analyzer is kept connected to the waveguide coaxial converter via the cable, and the loss value L3 of the positioning piece is obtained via the vector network analyzer.

[0073] The positioning piece is provided with a positioning piece waveguide, and the waveguide coaxial converter has a converter waveguide. In the process of obtaining the positioning piece loss value, the waveguide coaxial converter can be detachably mounted to the positioning piece through a connector, and the converter waveguide of the waveguide coaxial converter corresponds to the positioning piece waveguide of the positioning piece. The waveguide coaxial converter is connected to the vector network analyzer through a cable. The waveguide coaxial converter can convert the signal from the waveguide transmission form to the coaxial line transmission form. The positioning piece can transmit the signal to the waveguide coaxial converter through the positioning piece waveguide, and then convert the signal transmission form through the waveguide converter, so that the signal is transmitted to the cable and finally received by the vector network analyzer. The vector network analyzer can obtain the signal loss during the transmission process in the positioning piece, that is, in the positioning piece waveguide.

[0074] In an optional example, the positioning member is a metal member, and the positioning member waveguide is a through hole provided on the positioning member, and the through hole penetrates the positioning member along the thickness direction of the positioning member.

[0075] When the circuit board is not connected to the positioning piece, keep the waveguide coaxial converter connected to the circuit board, keep the vector network analyzer connected to the waveguide coaxial converter via the cable, and obtain the loss value L4 of the circuit board through the vector network analyzer.

[0076] A circuit board waveguide is provided on the circuit board. In the process of obtaining the loss value of the circuit board, the waveguide coaxial converter can be detachably mounted on the circuit board through the connector, and the converter waveguide of the waveguide coaxial converter corresponds to the positioning component waveguide of the positioning component. The vector network analyzer is connected to the circuit board through the cable waveguide coaxial converter, thereby indirectly connecting to the circuit board. The circuit board can transmit the signal to the waveguide coaxial converter through the circuit board waveguide, and then convert the signal transmission form through the waveguide converter, so that the signal is transmitted to the cable, and finally received by the vector network analyzer. The vector network analyzer can obtain the loss of the signal during the conduction in the circuit board, that is, in the circuit board waveguide.

[0077] In an optional example, a mounting hole is provided through the circuit board, the inner diameter of the mounting hole is not less than the inner diameter of the positioning member waveguide, i.e., the through hole, a conductive member is provided in the mounting hole, the height of the conductive member is consistent with the thickness of the circuit board, the conductive member extends from one side of the circuit board to the other opposite side along the axial direction of the mounting hole, the conductive member is annular, and the channel inside the conductive member constitutes the circuit board waveguide. Usually, the substrate of the circuit board is made of insulating material, and the conductive layers on the upper and lower surfaces thereof can be electrically connected through the conductive member in the mounting hole, and the conductive member can be arranged in an annular shape, so that the conductive member can be used as a circuit conduction element to electrically connect the conductive layers on the upper and lower surfaces, and can also form a circuit board waveguide using the channel inside it.

[0078] It can be understood that the conductive member is provided in the mounting hole by directly fixing an annular conductive element on the inner wall of the mounting hole, or by directly forming a metal layer on the inner wall of the mounting hole through a deposition or electroplating process.

[0079] By obtaining the loss values ​​of the positioning member and the circuit board respectively in different steps, the loss value of the positioning member and the loss of the circuit board are added together to obtain the loss value of the waveguide transmission component. In other embodiments, the circuit board and the positioning member can be assembled together to form an assembly, and the assembly is connected to the vector network analyzer through a waveguide coaxial converter and a cable. The loss value of the assembly is obtained by testing the vector network analyzer, that is, the sum of the loss values ​​of the circuit board and the positioning member.

[0080] It should be noted that when there are multiple positioning member waveguides and multiple circuit board waveguides, the signal is conducted in multiple positioning member waveguides and multiple circuit board waveguides respectively. When the signal is conducted in each positioning member waveguide and each circuit board waveguide, loss will be generated. The loss value of the positioning member refers to the total loss of the signal when it is conducted in multiple positioning member waveguides, and the loss value of the circuit board refers to the total loss of the signal when it is conducted in multiple circuit board waveguides. When obtaining the loss value of the positioning member, it can be obtained by first obtaining the loss of a single positioning member waveguide, and then multiplying the loss of a single positioning member waveguide by the number of positioning member waveguides to obtain the loss value of the positioning member, or it can be obtained by directly obtaining the sum of the loss values ​​of multiple positioning member waveguides by making multiple positioning member waveguides stacked in sequence, that is, directly obtaining the loss value of the positioning member. Similarly, when obtaining the loss value of the circuit board, it can also be obtained by first obtaining the loss of a single circuit board waveguide, and then multiplying the loss of a single circuit board waveguide by the number of circuit board waveguides, or it can also be obtained by stacking the sum of the loss values ​​of multiple circuit board waveguides, that is, the loss value of the circuit board. When the number of the positioning member waveguide and the circuit board waveguide is one, the loss value of the circuit board is the loss value of the single circuit board waveguide, and the loss value of the positioning member is the loss value of the single positioning member waveguide.

[0081] In one embodiment, the number of the waveguide coaxial converters is two, and the waveguide coaxial converter is kept connected to the positioning member, and the vector network analyzer is kept connected to the waveguide coaxial converter via a cable, including:

[0082] Keep the two waveguide coaxial converters connected to the vector network analyzer through cables respectively.

[0083] The positioning piece is clamped by two waveguide coaxial converters, and the converter waveguides of the two waveguide coaxial converters are respectively connected to the positioning piece waveguides of the positioning piece correspondingly.

[0084] The vector network analyzer is connected to the two waveguide-coaxial converters through a cable, and then the two waveguide-coaxial converters are used to clamp the positioning piece so that the positioning piece waveguide is located between the converter waveguides of the two waveguide-coaxial converters, and the waveguide-coaxial converter and the positioning piece are closely matched to minimize the signal loss when transmitting between the positioning piece and the waveguide-coaxial converter, thereby improving the accuracy of the positioning piece loss value obtained by the test.

[0085] The number of positioning members may be one or more, and may be set according to the number and distribution positions of the circuit board waveguides. When the number of circuit board waveguides is more than one, multiple positioning member waveguides may be set on one positioning member, or multiple positioning members may be set, and a positioning member waveguide may be set on each positioning member, as long as the circuit board waveguide and the positioning member waveguide can correspond one to one.

[0086] In one embodiment, the number of the positioning members is multiple, and the positioning members are clamped by two waveguide coaxial converters, and the converter waveguides of the two waveguide coaxial converters are respectively connected to the two ends of the positioning member waveguide of the positioning member, including:

[0087] A plurality of positioning members are stacked and arranged, and the positioning member waveguides of the plurality of positioning members are correspondingly connected in sequence along the stacking direction.

[0088] A plurality of stacked positioning members are clamped by two waveguide coaxial converters, and the converter waveguides of the two waveguide coaxial converters are respectively connected to the positioning member waveguides of the two positioning members located on the outside in the stacking direction.

[0089] In the process of testing the loss of positioning parts, when there are multiple positioning parts and each positioning part is provided with a positioning part waveguide, the signal is conducted in the positioning part waveguides of the multiple positioning parts respectively. The multiple positioning parts can be stacked together to form a stacked body, and the multiple positioning part waveguides are arranged opposite to each other to form a continuous waveguide channel. Then, two waveguide coaxial converters are used to clamp the stacked body to measure the sum of the signal losses in the multiple positioning parts, so as to directly obtain the loss value of the positioning parts.

[0090] exist Figure 4In the illustrated embodiment, there are two positioning members 51, each positioning member 51 is provided with a positioning member waveguide 52, and signals are respectively conducted in the positioning member waveguides 52 of the two positioning members 51. When testing the total loss of the signal conducted in the positioning member 51, the two positioning members 51 are first stacked together, and the two positioning member waveguides 52 are arranged opposite to each other. The two waveguide coaxial converters 53 are respectively located on the opposite sides of the two positioning members 51, and the two waveguide coaxial converters 53 and the two positioning members 51 are fixed together by a connecting member 54. The vector network analyzer 40 is respectively connected to the two waveguide coaxial converters 53 through a cable 30. The vector network analyzer 40 can directly obtain the total loss of the signal when it is conducted in multiple positioning member waveguides 52, and directly obtain the loss value of the positioning member 51.

[0091] In other embodiments, when there are multiple positioning pieces, two waveguide-coaxial converters can be used to clamp one positioning piece, and the two waveguide-coaxial converters can be located on opposite sides of the waveguide of the same positioning piece. After the vector network analyzer is connected to the two waveguide-coaxial converters through a cable, the vector network analyzer can obtain the loss of a single positioning piece waveguide, and then multiply the loss of a single positioning piece waveguide by the number of positioning piece waveguides to obtain the total loss of the signal when it is transmitted in the positioning piece.

[0092] In one embodiment, maintaining the waveguide-coaxial converter connected to the circuit board, and maintaining the vector network analyzer connected to the waveguide-coaxial converter via a cable, comprises:

[0093] Keep two waveguide coaxial converters connected to the vector network analyzer through cables respectively;

[0094] The circuit board is clamped by two waveguide coaxial converters, and the converter waveguides of the two waveguide coaxial converters are respectively connected to the two ends of the circuit board waveguide of the circuit board correspondingly.

[0095] The vector network analyzer is connected to two waveguide coaxial converters through a cable, and then the circuit board is clamped by the two waveguide coaxial converters so that one circuit board waveguide is located between the converter waveguides of the two waveguide coaxial converters, and the waveguide coaxial converter and the circuit board are closely matched to minimize the signal loss when it is transmitted between the circuit board and the waveguide coaxial converter, thereby improving the accuracy of the circuit board loss value obtained by the test.

[0096] like Figure 5As shown, the number of circuit boards 55 is one, two waveguide coaxial converters 53 are respectively located on opposite sides of the circuit board 55 in the thickness direction, and the two waveguide coaxial converters 53 and the circuit board 55 are fixed together by a connector 54, forming an effect of clamping the circuit board 55. At this time, the waveguide coaxial converters 53 are respectively located on opposite sides of the same circuit board waveguide 56, and the vector network analyzer 40 is respectively connected to the two waveguide coaxial converters 53 through a cable 30, so as to obtain the loss of the signal when it is conducted in a single circuit board waveguide 56. When the number of circuit board waveguides 56 on the circuit board 55 is multiple, the loss value of the circuit board 55 can be obtained by multiplying the loss value of a single circuit board waveguide 56 by the number of circuit board waveguides 56. When the number of circuit board waveguides 56 on the circuit board 55 is one, the loss value of a single circuit board waveguide 56 is the loss value of the circuit board 55.

[0097] In one embodiment, the chip packaging structure to be tested is kept in corresponding connection with the waveguide transmission component, the vector network analysis device is kept in connection with the waveguide transmission component through a cable, and the third loss value of the chip packaging structure to be tested and the waveguide transmission component is obtained, including:

[0098] Keep the circuit board, positioning piece and waveguide coaxial converter connected, keep the chip package structure to be tested connected to the circuit board, keep the vector network analyzer connected to the waveguide coaxial converter via a cable, and obtain the total loss value L5 of the chip package structure to be tested, the circuit board and the positioning piece through the vector network analyzer.

[0099] When testing the total loss of the chip packaging structure to be tested and the waveguide transmission component, the circuit board, the positioning piece and the waveguide-coaxial converter can be assembled together, so that the circuit board waveguide, the positioning piece waveguide and the coaxial converter waveguide are connected in sequence to form a waveguide transmission component. The chip packaging structure to be tested is then fixed to the circuit board of the waveguide transmission component by soldering with solder balls, and the waveguide transmission channel and the waveguide structure are connected correspondingly. The chip packaging structure to be tested and the waveguide transmission component are assembled together, and the vector network analyzer can obtain the total loss value of the chip packaging structure to be tested and the waveguide transmission component.

[0100] like Figure 6As shown, the waveguide transmission component includes a positioning member 51, a circuit board 55 and a waveguide coaxial converter 53. The waveguide structure includes a positioning member waveguide 52 provided on the positioning member 51 and a circuit board waveguide 56 provided on the circuit board 55. The circuit board 55 and the positioning member 51 are fixed together. The waveguide coaxial converter 53 is installed to the side of the positioning member 51 away from the circuit board 55 through a connector 54. The circuit board waveguide 56, the positioning member waveguide 52 and the converter waveguide are arranged in sequence. The package body 13 of the chip package structure 10 to be tested is welded and fixed to the side of the circuit board 55 away from the positioning member 51, and the waveguide transmission channel 15 on the package body 13 corresponds to the circuit board waveguide 56 to assemble the chip package structure 10 to be tested and the waveguide transmission component together. The vector network analyzer 40 is connected to the waveguide-coaxial converter 53 through the cable 30. The signal generated by the chip 11 is first transmitted from the chip 11 to the package body 13, then from the package body 13 to the circuit board waveguide 56, and then from the circuit board waveguide 56 to the positioning member waveguide 52, and finally from the positioning member waveguide 52 to the vector network analyzer 40 through the waveguide-coaxial converter 53 and the cable 30, so as to measure the total loss value of the chip packaging structure 10 to be tested, the circuit board 55 and the positioning member 51. The total loss value is subtracted from the loss value of the chip 11, the loss value of the circuit board 55 and the loss value of the positioning member 51 to obtain the packaging loss of the chip packaging structure 10 to be tested.

[0101] In one embodiment, determining the package loss of the chip package structure to be tested based on the first loss value, the second loss value, and the third loss value includes:

[0102] The package loss L6 is obtained by L5-L4-L3-first loss value.

[0103] The first loss value of the chip is L2-L1, and the second loss value of the waveguide transmission component is L3+L4. The packaging loss L6 can be obtained by subtracting the first loss value and the second loss value from the third loss value L5 of the chip packaging structure to be tested and the waveguide transmission component, that is, L6=L5-L4-L3-L2+L1.

[0104] In one embodiment, when the chip packaging structure to be tested has n symmetrically arranged signal transmission paths, the loss value of a single signal transmission path is obtained by L6 / n.

[0105] The signal generated by the chip of the chip packaging structure to be tested is transmitted to the waveguide transmission component through the waveguide transmission channel of the package body. The signal transmission path is the waveguide transmission channel of the package body. When the number of signal transmission paths is multiple, the signal generated by the chip is transmitted to the waveguide transmission component along n signal transmission paths respectively. Signal loss will be generated when it is transmitted in each signal transmission path. Since the n signal transmission paths are symmetrically arranged, the package loss is divided by the number of signal transmission paths to obtain the signal loss when it is transmitted in a single signal transmission path.

[0106] exist Figure 1 In the illustrated embodiment, the number of waveguide transmission channels 15 , i.e., signal transmission paths, is two, and the two waveguide transmission channels 15 are symmetrically arranged. By subtracting the packaging loss L6 / 2, the signal loss in a single waveguide transmission channel 15 can be obtained.

[0107] In some embodiments, the method further comprises:

[0108] Providing a plurality of chip packaging structures to be tested of the same type, and obtaining a first loss value, a second loss value, and a third loss value for each chip packaging structure to be tested;

[0109] Determine the packaging loss of each chip packaging structure to be tested based on the corresponding first loss value, second loss value and third loss value;

[0110] Based on the package losses of multiple chip package structures to be tested, determine whether the test results are accurate.

[0111] By testing multiple chip packaging structures of the same type one by one, the packaging loss of each chip packaging structure to be tested is obtained respectively. By comparing the packaging losses obtained from multiple tests, it is determined whether the test results are accurate, thereby improving the reliability of the test results.

[0112] In an optional example, after obtaining the packaging losses of multiple chip packaging structures to be tested, the packaging losses of different chip packaging structures to be tested are compared. When multiple loss values ​​are the same or close, the test result is determined to be accurate. When there is a loss value that is significantly different from other loss values, it is determined that the test result is abnormal. The chip packaging structure to be tested can be re-provided for testing, or the packaging loss of the chip packaging structure to be tested can be determined by the number of the same or close loss values.

[0113] Optionally, the number of chip package structures to be tested of the same type is three, and three package losses can be tested to meet the comparison requirements while preventing the test efficiency from being affected by an excessive number.

[0114] The above-mentioned embodiments are only preferred embodiments of the present invention and cannot be used to limit the scope of protection of the present invention. Any non-substantial changes and substitutions made by technicians in this field on the basis of the present invention shall fall within the scope of protection required by the present invention.

Claims

1. A chip packaging performance testing method, characterized in that: include: Obtaining a first loss value of a chip of the chip packaging structure to be tested; When the waveguide transmission component is not connected to the chip package structure to be tested, the vector network analysis device is connected to the waveguide transmission component through a cable to obtain a second loss value of the waveguide transmission component; Maintaining the corresponding connection between the chip packaging structure to be tested and the waveguide transmission component, maintaining the connection between the vector network analysis device and the waveguide transmission component via a cable, and obtaining the third loss value of the chip packaging structure to be tested and the waveguide transmission component; Based on the first loss value, the second loss value and the third loss value, the packaging loss of the chip packaging structure to be tested is determined.

2. The chip packaging performance testing method according to claim 1, characterized in that: The vector network analysis device includes a vector network analyzer and a calibration element; the step of obtaining a first loss value of a chip of a chip package structure to be tested includes: calibrating the vector network analyzer by using the calibration element; Calibrate the probe card on the probe station, keep the vector network analyzer connected to the probe card via the cable, and obtain the loss value L1 of the probe card via the vector network analyzer; Placing the chip of the chip package structure to be tested on the probe station, keeping the probe card electrically connected to the chip, and obtaining the total loss value L2 of the chip and the probe card through the vector network analyzer; Based on the loss value L1 of the probe card and the total loss value L2 of the chip and the probe card, a first loss value of the chip is determined.

3. The chip packaging performance testing method according to claim 1, characterized in that: The vector network analysis device includes a vector network analyzer and a calibration element, the waveguide transmission component includes a circuit board, a positioning member and a waveguide coaxial converter, and when the waveguide transmission component is not connected to the chip packaging structure to be tested, the vector network analysis device is kept connected to the waveguide transmission component through a cable to obtain a second loss value of the waveguide transmission component, including: When the positioning member is not connected to the circuit board, the waveguide-coaxial converter is kept connected to the positioning member, the vector network analyzer is kept connected to the waveguide-coaxial converter via the cable, and the loss value L3 of the positioning member is obtained via the vector network analyzer; When the circuit board is not connected to the positioning piece, the waveguide-coaxial converter is kept connected to the circuit board, the vector network analyzer is kept connected to the waveguide-coaxial converter via the cable, and the loss value L4 of the circuit board is obtained via the vector network analyzer.

4. The chip packaging performance testing method according to claim 3, characterized in that: The step of maintaining the corresponding connection between the chip packaging structure to be tested and the waveguide transmission component, maintaining the connection between the vector network analysis device and the waveguide transmission component via a cable, and obtaining the third loss value of the chip packaging structure to be tested and the waveguide transmission component includes: Keep the circuit board, the positioning piece and the waveguide-coaxial converter connected, keep the chip packaging structure to be tested connected to the circuit board, keep the vector network analyzer connected to the waveguide-coaxial converter via the cable, and obtain the total loss value L5 of the chip packaging structure to be tested, the circuit board and the positioning piece through the vector network analyzer.

5. The chip packaging performance testing method according to claim 4, characterized in that: The step of determining the package loss of the chip package structure to be tested based on the first loss measurement value, the second loss measurement value, and the third loss measurement value includes: The package loss L6 is obtained by L5-L4-L3-the first loss value of the chip.

6. The chip packaging performance testing method according to claim 5, characterized in that: When the chip packaging structure to be tested has n symmetrically arranged signal transmission paths, the loss value of a single signal transmission path is obtained by L6 / n.

7. The chip packaging performance testing method according to claim 3, characterized in that: The method of maintaining the connection between the waveguide-to-coaxial converter and the positioning member and maintaining the connection between the vector network analyzer and the waveguide-to-coaxial converter via the cable comprises: Keeping the two waveguide coaxial converters connected to the vector network analyzer through the cables respectively; The positioning member is clamped by two waveguide-coaxial converters, and the converter waveguides of the two waveguide-coaxial converters are respectively connected to the positioning member waveguides of the positioning member accordingly.

8. The chip packaging performance testing method according to claim 7, characterized in that: The number of the positioning members is multiple, the positioning members are clamped by two waveguide-coaxial converters, and the converter waveguides of the two waveguide-coaxial converters are respectively connected to the two ends of the positioning member waveguide of the positioning member, including: A plurality of the positioning members are stacked, and the positioning member waveguides of the plurality of the positioning members are correspondingly connected in sequence along the stacking direction; The plurality of stacked positioning members are clamped by two waveguide-coaxial converters, and the converter waveguides of the two waveguide-coaxial converters are respectively connected to the positioning member waveguides of the two positioning members located on the outside in the stacking direction.

9. The chip packaging performance testing method according to claim 3, characterized in that: The method of maintaining the connection between the waveguide-to-coaxial converter and the circuit board and maintaining the connection between the vector network analyzer and the waveguide-to-coaxial converter via the cable comprises: Keeping the two waveguide coaxial converters connected to the vector network analyzer through the cables respectively; The circuit board is clamped by two waveguide-coaxial converters, and the converter waveguides of the two waveguide-coaxial converters are respectively connected to the two ends of the circuit board waveguide of the circuit board.

10. The chip packaging performance testing method according to claim 1, characterized in that: Also includes: Providing a plurality of the chip packaging structures to be tested of the same type, and obtaining the first loss value, the second loss value and the third loss value for each of the chip packaging structures to be tested; Determine the packaging loss of each of the chip packaging structures to be tested based on the corresponding first loss value, the second loss value and the third loss value; Based on the packaging losses of the plurality of chip packaging structures to be tested, it is determined whether the test result is accurate.

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