Array substrate, display panel and display device

Abstract

The application discloses an array substrate, a display panel and a display device to improve the problem that the on-state current of high-brush products or products with high charging rate requirements is difficult to improve. The array substrate comprises a first substrate, a transistor located on one side of the first substrate, and a first electrode. The transistor comprises a first gate, a source and a drain located on the side of the first gate away from the first substrate. The first electrode is located on the side of the source away from the first substrate, and the first electrode covers at least part of the source in the orthographic projection of the first substrate and covers at least part of the drain in the orthographic projection of the first substrate, and the first electrode is insulated from the first gate.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to an array substrate, a display panel, and a display device. Background Technology

[0002] To improve viewing angle, brightness, contrast, and response speed, current LCD monitors employ High Aperture Advanced Super Dimensional Switching (HADS) technology. With technological advancements, consumer demands for screen image display have increased, evolving from the initial 60Hz to 120Hz, 144Hz, 165Hz, 288Hz, 330Hz, and even 450Hz. However, as refresh rates increase, pixel charging time decreases, leading to poor black levels in the products, such as… Figure 1 As shown. To improve the product's charging rate, the thickness of the passivation layer is increased to reduce the storage capacitance. However, this design leads to a decrease in the on-state current of the transistor devices, resulting in a corresponding decrease in the product's charging rate. Therefore, existing LCD technologies cannot simultaneously achieve high on-state current and small pixel storage capacitance, making it difficult to improve the on-state current. Summary of the Invention

[0003] The present invention provides an array substrate, a display panel, and a display device to improve the problem that it is difficult to increase the on-state current of high refresh rate products or products with high charge rate requirements.

[0004] This invention provides an array substrate, comprising: a first substrate, a transistor located on one side of the first substrate, and a first electrode; wherein the transistor comprises: a first gate, a source electrode located on the side of the first gate electrode opposite to the first substrate, and a drain electrode;

[0005] The first electrode is located on the side of the source electrode opposite to the first substrate, and the orthographic projection of the first electrode onto the first substrate covers at least a portion of the orthographic projection of the source electrode onto the first substrate, and covers at least a portion of the orthographic projection of the drain electrode onto the first substrate, and the first electrode is insulated from the first gate electrode.

[0006] In one possible implementation, the array substrate further includes: a pixel electrode; the first electrode is in the same layer and made of the same material as the pixel electrode, and the first electrode and the pixel electrode are integrally connected.

[0007] In one possible implementation, the array substrate includes: a plurality of gate lines extending along a first direction; the first electrode includes: a first electrode portion and a second electrode portion arranged along a second direction; the second direction is perpendicular to the first direction;

[0008] The array substrate comprises: a passivation layer between a layer where the pixel electrode is located and a layer where the drain is located; the passivation layer has a first via hole exposing a part of the drain;

[0009] The first electrode part covers the first via hole and overlaps the drain; the second electrode part overlaps the gate line in the orthographic projection of the first substrate.

[0010] In a possible implementation, the array substrate further comprises: a first active pattern on a side of the drain facing the first substrate and in contact with the drain; the first active pattern has a first active part overlapping the drain, and a second active part extending from the first active part;

[0011] The first via hole exposes a part of the drain away from a surface of the first substrate, a side surface of the drain, a part of the second active part away from a surface of the first substrate, and a part of the second active part away from a side surface of the first substrate, and exposes a part of the passivation layer adjacent to the second active part.

[0012] In a possible implementation, the source comprises: a source main part, and a first source branch part and a second source branch part extending from the source main part in a second direction;

[0013] The second electrode part covers the first source branch part, the second source branch part, and a region between the first source branch part and the second source branch part in the orthographic projection of the first substrate.

[0014] In a possible implementation, a maximum depth of the first via hole is less than a maximum thickness of the passivation layer.

[0015] In a possible implementation, the array substrate further comprises: a pixel electrode; the first electrode and the pixel electrode are in the same layer and made of the same material, and the first electrode and the pixel electrode are insulated from each other.

[0016] In a possible implementation, the array substrate comprises: a plurality of gate lines extending in a first direction; the first electrode comprises: a third electrode part, a fourth electrode part, and a fifth electrode part extending in a third direction and connecting the third electrode part and the fourth electrode part; the third direction intersects the first direction and the second direction;

[0017] The third electrode part and the pixel electrode are located on the same side of the gate line; the fourth electrode part overlaps the gate line in the orthographic projection of the first substrate.

[0018] In a possible implementation, the array substrate further comprises: a passivation layer between the layer where the pixel electrode is located and the layer where the drain electrode is located, a transfer electrode in the layer where the drain electrode is located, a second active pattern on the side of the transfer electrode facing the first substrate and in contact with the transfer electrode, a gate insulating layer on the side of the second active pattern facing the first substrate, a common electrode layer on the side of the gate insulating layer facing the first substrate, and a second via hole penetrating through the passivation layer and the gate insulating layer; the second active pattern has a third active part overlapping the transfer electrode, and a fourth active part extending from the third active part; the common electrode layer comprises: a plurality of common electrode strips extending along the first direction;

[0019] The second via hole exposes a part of the transfer electrode away from the surface of the side of the first substrate, a side surface of the transfer electrode, a part of the fourth active part away from the surface of the side of the first substrate and a part of the side surface of the fourth active part, and exposes a part of the common electrode strip away from the surface of the side of the first substrate; the third electrode part covers the second via hole and at least overlaps the transfer electrode and the common electrode strip.

[0020] In a possible implementation, the source electrode comprises: a source electrode main part, and a first source electrode branch part and a second source electrode branch part extending from the source electrode main part along a second direction.

[0021] The fourth electrode part covers the first source electrode branch part, the second source electrode branch part, and a region between the first source electrode branch part and the second source electrode branch part in the projection of the first substrate.

[0022] In a possible implementation, the passivation layer further has a first recess on the surface away from the first substrate and recessed toward the first substrate; the first recess, in the projection of the first substrate, covers at least part of the source electrode in the projection of the first substrate, and covers at least part of the drain electrode in the projection of the first substrate.

[0023] In a possible implementation, the second electrode part is located in the first recess; or the fourth electrode part is located in the first recess.

[0024] Embodiments of the present application further provide a display panel comprising the array substrate provided by the embodiments of the present application, and further comprising a counter substrate arranged opposite to the array substrate.

[0025] In a possible implementation, the array substrate has a first recess; the counter substrate comprises a second substrate and a spacer on a side of the second substrate facing the array substrate, a projection of the spacer on the first substrate overlaps with a projection of the first recess on the first substrate; a surface of the spacer on a side facing the array substrate is covered with a conductive part; the conductive part is in contact with the first electrode.

[0026] In a possible implementation, the conductive part is an integral transparent planar electrode.

[0027] In a possible implementation, the counter substrate further comprises a black matrix layer on a side of the spacer facing the second substrate; the black matrix layer comprises a plurality of first sub-black matrix parts extending in a first direction and a plurality of second sub-black matrix parts extending in a second direction.

[0028] The conductive part comprises a plurality of first sub-conductive parts extending in a first direction and a plurality of second sub-conductive parts extending in a second direction; a projection of the first sub-black matrix parts on the second substrate covers a projection of the first sub-conductive parts on the second substrate; a projection of the second sub-black matrix parts on the second substrate covers a projection of the second sub-conductive parts on the second substrate.

[0029] In a possible implementation, a material of the conductive part comprises a transparent metal oxide or metal.

[0030] In a possible implementation, the array substrate further comprises a common electrode layer; a voltage loaded by the conductive part is different from a voltage loaded by the common electrode layer, or the voltage loaded by the conductive part is the same as the voltage loaded by the common electrode layer.

[0031] Embodiments of the present application further provide a display device comprising the display panel provided by the embodiments of the present application.

[0032] The beneficial effects of the embodiments of the present invention are as follows: In the embodiments of the present invention, the array substrate further includes a first electrode, which is located on the side of the source electrode away from the first substrate. The orthographic projection of the first electrode onto the first substrate covers at least a portion of the orthographic projection of the source electrode onto the first substrate and at least a portion of the orthographic projection of the drain electrode onto the first substrate. This allows the first electrode to be formed as the top gate of the transistor, making the transistor a dual-gate structure, which is beneficial for increasing the on-state current. That is, since the orthographic projection of the first electrode partially or completely overlaps with the orthographic projection of the source electrode and / or the drain electrode, the edge electric field can be enhanced, thereby increasing the lateral electric field strength and increasing the carrier concentration in the active layer, thereby increasing the on-state current. In addition, since the orthographic projection of the first electrode partially or completely overlaps with the orthographic projection of the source electrode and / or the drain electrode, the presence of the first electrode above the channel can protect the channel from the influence of the external environment and isolate the risk of external moisture penetrating from the passivation layer into the channel and corroding the active layer channel. Moreover, the first electrode is insulated from the first gate, that is, the voltage of the first electrode, which serves as the top gate, can be flexibly adjusted to obtain the required on-state current, realize digital on-state current, and meet the charging rate of broadband products. Attached Figure Description

[0033] Figure 1 This is a diagram illustrating poor blackening on the display panel.

[0034] Figure 2 This is a schematic diagram showing the relationship between the on-state current coefficient of a transistor and the passivation layer thickness.

[0035] Figure 3 This is a schematic diagram illustrating the relationship between the on-state current coefficient of a transistor and the passivation layer thickness.

[0036] Figure 4A This is one of the top views of the array substrate provided in the embodiments of this disclosure;

[0037] Figure 4B for Figure 4A Schematic diagram of the film layer of the common electrode layer;

[0038] Figure 4C for Figure 4A Schematic diagram of the middle gate line layer;

[0039] Figure 4D for Figure 4A Schematic diagram of the film layer in the middle data line layer;

[0040] Figure 4E for Figure 4A A schematic diagram of a single film layer of the middle pixel electrode layer;

[0041] Figure 5 for Figure 4A A schematic diagram of the cross section at point e1 along the dashed line in the middle;

[0042] Figure 6For Figure 4A A cross-sectional view along the dotted line e2;

[0043] Figure 7A A second top view schematic diagram of an array substrate provided by the embodiment of the present disclosure;

[0044] Figure 7B For Figure 7A A film layer schematic diagram of the common electrode layer;

[0045] Figure 7C For Figure 7A A film layer schematic diagram of the gate line layer;

[0046] Figure 7D For Figure 7A A film layer schematic diagram of the data line layer;

[0047] Figure 7E For Figure 4A A single film layer schematic diagram of the pixel electrode layer;

[0048] Figure 8 For Figure 7A A cross-sectional view along the dotted line e1;

[0049] Figure 9 For Figure 7A A cross-sectional view along the dotted line e2;

[0050] Figure 10 A first cross-sectional schematic diagram of a display panel provided by the embodiment of the present disclosure;

[0051] Figure 11 A schematic diagram of the black matrix and the conductive part;

[0052] Figure 12 A second cross-sectional schematic diagram of a display panel provided by the embodiment of the present disclosure. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without any creative effort fall within the protection scope of the present disclosure.

[0054] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the meanings as understood by a person of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms are used herein to distinguish one element from another, but do not necessarily indicate an order of importance, a number or one of several. The terms "comprises", "comprising", "includes", "including" and the like can mean the presence of a stated element or items along with others. The terms "connected", "coupled", and the like can not necessarily mean physically or mechanically connected or coupled, but can include electrical connection or coupling, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are used to describe relative positions only and can change accordingly when the absolute position of the described object changes.

[0055] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for a particular value, as determined by one of ordinary skill in the art to be considered acceptable in light of the measurement and error associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ± 30%, 20%, 10%, 5% of the stated value.

[0056] In the drawings, the thicknesses of layers, films, panels, regions, etc., can be exaggerated for clarity. The exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as being limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an area illustrated or described as flat can typically have rough and / or nonlinear features. Moreover, sharp angles that are illustrated can be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present claims.

[0057] In order to keep the following description of the embodiments of the present disclosure clear and concise, the detailed description of known functions and known components will be omitted.

[0058] As Figure 2 shown, where the abscissa represents the thickness of the passivation layer in the display product (unit: angstrom), the ordinate represents the on-state current coefficient of the transistor, the solid line represents the connecting line of the on-state current coefficient corresponding to different thicknesses of the passivation layer, and the dashed line represents the fitting line of the thickness of the passivation layer and the on-state current coefficient, which is determined by Figure 2It can be seen that the on-state current coefficient of the transistor in the display product decreases with the increase of the thickness of the passivation layer, and the relationship is approximately linear. When the thickness of the passivation layer of the display product is greater than 3000 angstroms, the on-state current coefficient of the transistor decreases significantly, which cannot meet the design requirements of the display product (design requirement: on-state current coefficient ≥ 0.8). In order to reduce the pixel storage capacitance, the thickness of the passivation layer of the high refresh product can be ≥ 7000 angstroms or more. According to the experimental results, the on-state current coefficient is much smaller than the design requirement. The small on-state current coefficient indicates that the on-state current of the transistor device is too low, that is, the transistor device cannot fully charge the pixel storage capacitance in a fixed time, which will cause the product to have black cloud mura (Mura) defects.

[0059] As shown in (a) of Figure 3 , the transistor device is composed of a gate, a gate insulator (GI), an active layer (a-Si), a source and drain electrode (SD electrode for short), a passivation layer (PVX), a pixel electrode (PXL ITO), and a common electrode (Com ITO). The mechanism of the influence of the thickness of the passivation layer on the on-state current of the product can include: when a positive voltage is applied to the gate, generally 15V, and a voltage is applied to the source and drain electrode, generally 15V, the transistor device is in an open state, the current in the transistor is the on-state current, and the pixel electrode obtains an electrical signal to start charging the pixel storage capacitance. Due to the potential difference between the source and drain electrodes, the surface of the passivation layer is induced to have electric charges, that is, a top-gate transistor device is formed, and the induced electric charges act as a gate, and the passivation layer acts as a gate insulator. When the bottom-gate / top-gate transistor device is simultaneously turned on, two electric fields are simultaneously applied to the active layer, the energy band of the active layer is effectively reduced, the electrons at the interface between the gate insulator / active layer and the active layer / passivation layer are more quickly filled to be conductive, as shown in (b) of Figure 3 . In addition, it can be known from the on-state current and capacitance formulas that: , with the increase of the thickness of the passivation layer film (d), the capacitance per unit area (C) decreases, the electron concentration at the interface between the active layer and the passivation layer decreases, and the on-state current of the top-gate transistor device decreases. That is, by increasing the thickness of the passivation layer film, the pixel capacitance of the high refresh product or the product with high charging rate requirement can be reduced, but the high on-state current cannot be considered.

[0060] Therefore, referring to Figures 4A-4E , Figure 5 , Figure 6 , wherein Figure 4B is a film layer schematic diagram of the common electrode layer in Figure 4A , Figure 4C is a film layer schematic diagram of the gate line layer in Figure 4A , Figure 4D is a film layer schematic diagram of the passivation layer in Figure 4AA schematic view of a film layer of a middle data line layer, Figure 4E As Figure 4A A schematic view of a single film layer of a middle pixel electrode layer, Figure 5 As Figure 4A A schematic view of a cross section along a dashed line e1, Figure 6 As Figure 4A A schematic view of a cross section along a dashed line e2, the embodiment of the present application provides an array substrate, comprising: a first substrate 11, a transistor T located at one side of the first substrate 11, and a first electrode 12; wherein the transistor T comprises: a first gate TA, a source TB located at a side of the first gate TA away from the first substrate 11, and a drain TC;

[0061] The first electrode 12 is located at a side of the source TB away from the first substrate 11, and a projection of the first electrode 12 on the first substrate 11 covers at least part of a projection of the source TB on the first substrate 11, and covers at least part of a projection of the drain TC on the first substrate 11, and the first electrode 12 is insulated from the first gate TA.

[0062] In the embodiment of the present application, the array substrate further comprises the first electrode 12, the first electrode 12 is located at a side of the source TB away from the first substrate 11, and a projection of the first electrode 12 on the first substrate 11 covers at least part of a projection of the source TB on the first substrate 11, and covers at least part of a projection of the drain TC on the first substrate 11, which can make the first electrode 12 form a top gate of the transistor T, so that the transistor T is a double-gate structure. Since the projection of the first electrode 12 partially or completely overlaps the projection of the source TB and / or the drain TC, the edge electric field can be enhanced, so that the lateral electric field intensity is enhanced, which is beneficial to increasing the carrier concentration of the active layer, thereby increasing the on-state current. In addition, since there is the first electrode 12 above the channel, the channel can be protected from the external environment, and the risk of external moisture penetrating from the passivation layer to the channel to corrode the active layer channel is isolated. Moreover, the first electrode 12 is insulated from the first gate TA, that is, the voltage of the first electrode 12 as the top gate can be flexibly adjusted to obtain the required on-state current, realize digital on-state current, and meet the charging rate of wide frequency products.

[0063] In a possible implementation, referring to Figures 4A-4E 、 Figure 5 、 Figure 6As shown, the array substrate further comprises: a common electrode layer on the side of the first substrate 11, a plurality of gate lines 14 extending along the first direction X on the side of the common electrode layer away from the first substrate 11, a gate insulating layer 141 on the side of the gate lines 14 away from the common electrode layer, an active layer and a data line layer (the data line layer can comprise a plurality of data lines 15 extending along the second direction Y) on the side of the gate insulating layer 141 away from the gate lines 14, a passivation layer 142 on the side of the data lines 15 away from the active layer, and a pixel electrode 13 on the side of the passivation layer 142 away from the data lines 15; wherein,

[0064] The common electrode layer can comprise a plurality of common electrode strips 16 extending along the first direction X, and a first auxiliary trace 162; wherein the common electrode strips 16 can comprise a plurality of common electrode blocks 160 arranged on the side of the first direction X, and a second auxiliary trace 161 connecting the common electrode blocks 160 at one end of the common electrode blocks 160;

[0065] The layer on which the gate lines 14 are located can further comprise a plurality of first common traces 143 extending along the first direction X; wherein the orthographic projection of the gate lines 14 on the first substrate 11 can coincide with the first auxiliary trace 162; the orthographic projection of the first common traces 143 on the first substrate 11 can coincide with the second auxiliary trace 161; the layer on which the gate lines 14 are located can be in direct contact with the common electrode layer, and no insulating layer can be arranged therebetween, and the layer on which the gate lines 14 are located and the common electrode layer can be formed through one mask process, thereby saving the manufacturing cost of the array substrate; the first common traces 143 can form at least part of the pixel storage capacitance with the pixel electrode 13;

[0066] The active layer can be in direct contact with the layer on which the data lines are located, and no insulating layer can be arranged therebetween, and the active layer and the layer on which the data lines are located can be formed through one mask process, thereby saving the manufacturing cost of the array substrate; the film layer patterns of at least part of the regions of the active layer and the layer on which the data lines are located are the same; the active layer can comprise a transistor active pattern TD0, a first active pattern TD1, and a second active pattern TD2; the layer on which the data lines 15 are located can comprise a source TB, a drain TC, and a switching electrode 151; the switching electrode 151 can be used to conduct adjacent two rows of common electrode strips 16.

[0067] The layer on which the pixel electrode 13 is located can further have a lap joint electrode 131, and the orthographic projection of the lap joint electrode 131 on the first substrate 11 can overlap with the part of the orthographic projection of the switching electrode 151 on the first substrate 11, and the lap joint electrode 131 and the switching electrode 151 jointly conduct adjacent two rows of common electrode strips 16.

[0068] In a possible implementation, referring to Figures 4A-4E 、 Figure 5 、 Figure 6As shown, the first electrode 12 is in the same layer and of the same material as the pixel electrode 13, and the first electrode 12 is integrally connected with the pixel electrode 13. In the embodiment of the present application, the first electrode 12 is integrally connected with the pixel electrode 13, so that the voltage of the first electrode 12 as the top gate can change with the pixel voltage, or the required on-state current can be obtained by adjusting the pixel voltage to change the top gate voltage; and the first electrode 12 can be formed at the same time as the pixel electrode 13, without increasing the process cost.

[0069] In a possible implementation, referring to Figure 4E As shown, the first electrode 12 includes: a first electrode part 121 arranged along the second direction Y, and a second electrode part 122; the second direction Y is perpendicular to the first direction X; referring to Figure 6 As shown, the passivation layer 142 has a first via K1 exposing the part of the drain TC; the first electrode part 121 covers the first via K1 and overlaps the drain TC; in combination with Figure 4A As shown, the second electrode part 122 overlaps the gate line 14 in the orthographic projection of the first substrate 11.

[0070] In the embodiment of the present application, the first electrode 12 includes: a first electrode part 121 arranged along the second direction Y, and a second electrode part 122, the first electrode part 121 covers the first via K1 and overlaps the drain TC; the second electrode part 122 overlaps the gate line 14 in the orthographic projection of the first substrate 11, by extending the part of the pixel electrode 13 overlapping the drain TC and covering part of the gate line 14, the first electrode 12 covers the channel region of the transistor T, forming the top gate of the transistor T; and the integrally connected mode of the first electrode 12 and the pixel electrode 13 can optimize the number of vias of the array substrate, without the need to additionally increase deep vias (such as deep vias formed by etching from the passivation layer to the gate insulating layer, and then etching to the gate scanning line), thereby avoiding via-related defects.

[0071] In a possible implementation, the shape of the first electrode 12 can be block-shaped, strip-shaped, or contain a hollow structure.

[0072] In a possible implementation, referring to Figure 6 As shown, the array substrate further includes: a first active pattern TD1 located on the side of the drain TC facing the first substrate 11 and in contact with the drain TC; the first active pattern TD1 has a first active part TD11 overlapping the drain TC, and a second active part TD12 extending from the first active part TD11;

[0073] The first via K1 exposes a portion of the drain TC facing away from the first substrate 11, the side surface of the drain TC, a portion of the second active portion TD12 facing away from the first substrate 11, a portion of the side surface of the second active portion TD12, and exposes a portion of the passivation layer 142 adjacent to the second active portion TD12, so that a gap J is formed between the exposed side surface of the second active portion TD12 and the side surface of the passivation layer 142 facing the second active portion TD12.

[0074] In this embodiment of the invention, the first via K1 exposes a portion of the drain TC on the side facing away from the first substrate 11, the side of the drain TC, a portion of the second active part TD12 on the side facing away from the first substrate 11, and a portion of the side of the second active part TD12. That is, the first via K1 is a shallow via, which can avoid the difficulty of etching deep vias and the risk of poor contact that may exist in deep vias.

[0075] In one possible implementation, see Figure 6 As shown, the maximum depth d1 of the first via K1 is less than the maximum thickness d2 of the passivation layer 142. In this embodiment of the invention, the first via K1 is only partially etched with the passivation layer 142, which can reduce water stains or stripping fluid residue in the channel and improve via corrosion defects.

[0076] In one possible implementation, combining Figure 4A and Figure 4D As shown, the source electrode TB includes: a source main portion TB0, and a first source branch TB1 and a second source branch TB2 extending from the source main portion TB0 along the second direction Y; the second electrode portion 122 is projected onto the first substrate 11 and covers the first source branch TB1, the second source branch TB2, and the region between the first source branch TB1 and the second source branch TB2.

[0077] In one possible implementation, combining Figures 7A-7E , Figure 8 and Figure 9 As shown, where, Figure 7B for Figure 7A A schematic diagram of a single film layer containing the middle pixel electrode. Figure 8 for Figure 7A A schematic diagram of the cross-section at the dashed line e1. Figure 9 for Figure 7A In the cross-sectional schematic diagram at the dashed line e2, the array substrate further includes: a pixel electrode 13; a first electrode 12 and the pixel electrode 13 are on the same layer and made of the same material, and the first electrode 12 and the pixel electrode 13 are spaced apart and insulated from each other. In this embodiment of the invention, the first electrode 12 and the pixel electrode 13 are on the same layer and made of the same material, so that the first electrode 12 can be formed at the same time as the pixel electrode 13, without increasing the process cost.

[0078] In one possible implementation, combiningFigures 7A-7E , Figure 8 and Figure 9 As shown, the first electrode 12 includes a third electrode portion 123, a fourth electrode portion 124, and a fifth electrode portion 125 extending along a third direction Z and connecting the third electrode portion 123 and the fourth electrode portion 124; the third direction Z intersects both the first direction X and the second direction Y; the third electrode portion 123 and the pixel electrode 13 are located on the same side of the gate line 14; the orthographic projection of the fourth electrode portion 124 on the first substrate 11 overlaps with the orthographic projection of the gate line 14 on the first substrate 11.

[0079] It should be noted that the third electrode portion 123 and the pixel electrode 13 are located on the same side of the gate line 14, which can be within the same pixel area.

[0080] In one possible implementation, combining Figures 7A-7E , Figure 8 and Figure 9 As shown, the array substrate further includes: a transition electrode 151 located on the drain TC layer; a second active pattern TD2 located on the side of the transition electrode 151 facing the first substrate 11 and in contact with the transition electrode 151; a gate insulating layer 141 located on the side of the second active pattern TD2 facing the first substrate 11; a common electrode layer located on the side of the gate insulating layer 141 facing the first substrate 11; and a second via K2 penetrating the passivation layer 142 and the gate insulating layer 141; the second active pattern TD2 has a third active portion TD21 overlapping with the transition electrode 151, and a fourth active portion TD22 extending from the third active portion TD21; the common electrode layer includes: a plurality of common electrode strips 16 extending along the first direction X;

[0081] The second via K2 exposes the portion of the surface of the adapter electrode 151 facing away from the first substrate 11, the side surface of the adapter electrode 151, the portion of the fourth active part TD22 facing away from the first substrate 11, the side surface of the fourth active part TD22, and the portion of the common electrode strip 16 facing away from the first substrate 11; the third electrode part 123 covers the second via K2 and overlaps at least with the adapter electrode 151 and the common electrode strip 16.

[0082] In the embodiment of the present application, the first electrode 12 is overlapped with the common electrode strip 16 through the third electrode part 123, so that the voltage of the first electrode 12 as the top gate can be changed with the common voltage, or the required on-state current can be obtained by adjusting the common voltage to change the top gate voltage; and when the first electrode 12 is electrically connected with the common electrode strip 16, the second via hole K2 is reused when the two adjacent rows of common electrode strips 16 are electrically connected, so that the number of via holes of the array substrate can be optimized, and additional deep via holes (such as deep via holes formed by etching from the passivation layer to the gate insulating layer and then to the gate scanning line) are not needed, thereby avoiding via hole defects.

[0083] In a possible implementation, as shown in Figures 7A-7E 、 Figure 8 and Figure 9 , the source electrode TB includes a source main part TB0, and a first source branch part TB2 and a second source branch part TB2 extending from the source main part TB0 in the second direction Y; the fourth electrode part 124 covers the first source branch part TB1, the second source branch part TB2, and a region between the first source branch part TB1 and the second source branch part TB2 in the orthographic projection of the first substrate 11.

[0084] In a possible implementation, as shown in Figure 7A , the transfer electrode 151 and the first electrode 12 can be arranged only at part of the sub-pixels, for example, the transfer electrode 151 and the first electrode 12 can be arranged at one of the three sub-pixels in each pixel (one pixel can include three sub-pixels), and the transfer electrode 151 and the first electrode 12 are not arranged at the remaining two sub-pixels; in another possible implementation, the transfer electrode 151 and the first electrode 12 can be arranged at each sub-pixel.

[0085] In a possible implementation, as shown in Figure 5 and Figure 8 , the passivation layer 142 further has a first recess Q recessed toward the first substrate 11 side from the surface away from the first substrate 11 side; the first recess Q in the orthographic projection of the first substrate 11 covers at least part of the source electrode TB in the orthographic projection of the first substrate 11, and covers at least part of the drain electrode TC in the orthographic projection of the first substrate 11.

[0086] In the embodiment of the present application, the first recess Q in the orthographic projection of the first substrate 11 covers at least part of the source electrode TB in the orthographic projection of the first substrate 11, and covers at least part of the drain electrode TC in the orthographic projection of the first substrate 11, that is, part of the passivation layer 142 at the position of the transistor T is excavated, the thickness of the passivation layer 142 at the top of the transistor T is reduced, while the film thickness of the passivation layer 142 in the pixel area is retained, and the technical problems of improving the on-state current of the transistor T and reducing the pixel storage capacitance (the capacitance formed by the pixel electrode and the common wiring) are considered.

[0087] In one possible implementation, the size of the first groove Q can be determined based on the gate size and transistor T size of the actual display product. For example, the orthographic projection of the first groove Q on the first substrate 11 can coincide with the orthographic projection of the overlapping area formed by the gate line 14 and the transistor T. Optionally, the length of the first groove Q in the first direction X can be 14 micrometers to 17 micrometers, and the length of the first groove Q in the second direction Y can be 35 micrometers to 50 micrometers.

[0088] In one possible implementation, the depth d2 of the first groove Q in the direction perpendicular to the first substrate 11 can range from 0.5 micrometers to 2 micrometers; in another possible implementation, the top passivation layer 142 at the transistor T location is partially etched and partially retained, and the thickness d3 of the retained passivation layer 142 can range from 500 angstroms to 1000 angstroms to ensure that there is still an insulating layer between the source TB (and / or drain TC) and the first electrode 12.

[0089] In one possible implementation, combining Figure 5 As shown, the second electrode portion 122 is located within the first groove Q; in one possible embodiment, combined with Figure 8 As shown, the second electrode portion 122 (or the fourth electrode portion 124) is located within the first groove Q. In this embodiment of the invention, the second electrode portion 122 (or the fourth electrode portion 124) is located within the first groove Q, and the first groove Q, in its orthographic projection onto the first substrate 11, covers at least a portion of the orthographic projection of the source electrode TB onto the first substrate 11, and covers at least a portion of the orthographic projection of the drain electrode TC onto the first substrate 11. That is, the lateral electric field strength between the second electrode portion 122 (or the fourth electrode portion 124) and the source electrode TB (and / or the drain electrode TC) can be enhanced, which is beneficial to increasing the carrier concentration in the active layer of the transistor, thereby increasing the on-state current. Moreover, due to the presence of the second electrode portion 122 (or the fourth electrode portion 124) above the channel, the channel is protected from the influence of the external environment, and the risk of external moisture penetrating from the passivation layer into the channel and corroding is isolated.

[0090] Based on the same inventive concept, see [link to inventive concept] Figure 10 As shown, this embodiment of the invention also provides a display panel, including an array substrate 1 as provided in this embodiment of the invention, and a counter substrate 2 disposed opposite to the array substrate 1.

[0091] In one possible implementation, see Figure 10As shown, the array substrate has a first groove Q; the counter substrate 2 comprises a second substrate 21 and a spacer PS on the side of the second substrate 21 facing the array substrate 1, the spacer PS is overlapped with the first groove Q in the orthographic projection of the first substrate 11; the surface of the spacer PS on the side facing the array substrate 1 is covered with a conductive part 22; the conductive part 22 is in contact with the first electrode 12.

[0092] In the embodiment of the present application, the counter substrate 2 comprises the conductive part 22 covering the surface of the spacer PS; the conductive part 22 is in contact with the first electrode 12, that is, by sputtering a layer of conductive film (as the conductive part 22) on the surface of the spacer PS of the counter substrate 2, when the array substrate 1 and the counter substrate 2 are assembled, the conductive part 22 on the surface of the spacer PS is in contact with the first electrode 12 above the transistor T of the array substrate 1 to form a conduction, that is, the voltage of the top gate (the first electrode 12) of the transistor T is flexibly adjusted through the conductive part 22 of the counter substrate 2 to obtain the required on-state current.

[0093] In the embodiment of the present application, the top gate first electrode 12 of the transistor T can have various beneficial effects, including: ① the number of vias can be optimized, and there is no need to additionally increase deep holes or shallow holes to conduct with the bottom gate, thereby avoiding via-related defects; ② smart top gate, since the top gate is not connected with the bottom gate, the top gate is connected with the conductive part 22 of the counter substrate 2, and the voltage can be flexibly adjusted to obtain the required on-state current, realize digital on-state current, and meet the charging rate of wideband products; ③ edge field enhancement, since the top gate is fully overlapped or partially overlapped with the source / drain electrode, the lateral electric field intensity is enhanced, which is beneficial to increasing the carrier concentration of the active layer, thereby increasing the on-state current; ④ protecting the channel from the external environment, since there is the first electrode 12 above the channel, the risk of external water vapor penetrating from the passivation layer to the channel to cause corrosion is isolated; ⑤ improvement of the scratch of the alignment film, in the original design, the spacer PS is on the surface of the passivation layer 142, and when the surface of the display panel is pressed, the spacer PS will be displaced and scratch the alignment film layer, causing broken bright point defects, while in the design of the present application, the displacement range of the spacer PS is in the first groove Q, that is, the first groove Q can clamp the spacer PS inside the first groove Q, avoiding the scratch of the alignment film, and at the same time, the first groove Q provides a reference when the array substrate 1 and the counter substrate 2 are aligned, improving the alignment accuracy, thereby avoiding the light leakage caused by the alignment accuracy.

[0094] In a possible implementation, the array substrate 1 and the counter substrate 2 are combined Figure 10 As shown, on the side of the array substrate 1, the first electrode 12 can be in an isolated state, and the first electrode 12 can be flexibly adjusted through the conductive part 22 of the counter substrate 2.

[0095] For example, in a possible implementation, referring to Figure 12As shown, the conductive portion 22 is an integral layer transparent surface electrode, which can be charged by an external driving circuit to provide a dynamic voltage to the conductive portion 22, serving as a top gate signal to achieve control of the top gate voltage of the transistor T on the array substrate 1 side.

[0096] For example, in a possible implementation, referring to Figure 10 and Figure 11 As shown, the facing substrate 2 further includes: a black matrix layer BM located on the side of the spacers PS facing the second substrate 21; the black matrix layer BM includes: a plurality of first sub-black matrix portions BM1 extending along the first direction X, and a plurality of second sub-black matrix portions BM2 extending along the second direction Y; the conductive portion 22 includes: a plurality of first sub-conductive portions 221 extending along the first direction X, and a plurality of second sub-conductive portions 222 extending along the second direction Y; the first sub-black matrix portion BM1 on the second substrate 21 covers the first sub-conductive portion 221 on the second substrate 21 in the orthographic projection; the second sub-black matrix portion BM2 on the second substrate 21 covers the second sub-conductive portion 222 on the second substrate 21 in the orthographic projection. The first sub-conductive portion 221 and the second sub-conductive portion 222 intersect to form a mesh structure, which can be charged by an external driving circuit to provide a dynamic voltage to the meshed first sub-conductive portion 221 and the second sub-conductive portion 222, serving as a top gate signal to achieve control of the top gate voltage of the transistor T on the array substrate 1 side.

[0097] In a possible implementation, for the array substrate corresponding to Figure 10 , Figure 11 The material of the conductive portion 22 includes: a transparent metal oxide or a metal. The transparent metal oxide may, for example, be indium tin oxide.

[0098] In a possible implementation, the voltage loaded on the conductive portion 22 of the facing substrate 2 can be different from the common voltage loaded on the common electrode strip 16 in the array substrate 1. In another possible implementation, the voltage loaded on the conductive portion 22 of the facing substrate 2 can be the same as the common voltage loaded on the common electrode strip 16 in the array substrate 1.

[0099] In a possible implementation, in combination with Figure 10 As shown, the facing substrate 2 can further include: a color resistance layer located between the spacers PS and the black matrix BM, which can include: a red color resistance R, a green color resistance, and a blue color resistance.

[0100] Based on the same inventive concept, the embodiments of the present application further provide a display device including the display panel provided by the embodiments of the present application. The implementation of the display device can refer to the above-mentioned embodiments of the display panel, and the repeated parts will not be described herein.

[0101] In specific implementation, in the embodiments of the present disclosure, the display device can be any product or component with display function such as mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator and the like. Other essential components of the display device should be understood by those skilled in the art, which are not described herein and should not be regarded as a limitation on the present disclosure.

[0102] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make further changes and modifications to the embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including all the preferred embodiments and all the changes and modifications falling within the scope of the present disclosure.

[0103] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these modifications and variations.

Claims

1. An array substrate, characterized by, The array substrate comprises: a first substrate, a transistor located on one side of the first substrate, and a first electrode; wherein the transistor comprises: a first gate, a source located on a side of the first gate away from the first substrate, and a drain; the first electrode is located on a side of the source away from the first substrate, and a projection of the first electrode on the first substrate covers at least part of a projection of the source on the first substrate and at least part of a projection of the drain on the first substrate, and the first electrode is insulated from the first gate; the array substrate further comprises: an active layer between a layer where the first gate is located and a layer where the drain is located, and a passivation layer between a layer where the first electrode is located and the layer where the drain is located; the active layer comprises an active pattern, and the passivation layer has a via hole exposing part of a surface of the active pattern away from the first substrate and part of a side surface of the active pattern; the first electrode comprises a plurality of electrode portions, one of the plurality of electrode portions covers the via hole and at least overlaps the active pattern exposed by the via hole.

2. The array substrate of claim 1, wherein, The array substrate further comprises: a pixel electrode; the first electrode and the pixel electrode are of the same layer and the same material, and the first electrode and the pixel electrode are integrally connected.

3. The array substrate of claim 2, wherein, The array substrate comprises: a plurality of gate lines extending in a first direction; the plurality of electrode portions comprise: a first electrode portion arranged in a second direction, and a second electrode portion; the second direction is perpendicular to the first direction; the via hole comprises a first via hole exposing part of the drain; the first electrode portion covers the first via hole and overlaps the drain; the second electrode portion overlaps the gate line in a projection of the first substrate.

4. The array substrate of claim 3, wherein, The active pattern comprises: a first active pattern located on a side of the drain facing the first substrate and in contact with the drain; the first active pattern has a first active portion overlapping the drain, and a second active portion extending from the first active portion; the first via hole exposes part of a surface of the drain away from the first substrate, a side surface of the drain, part of a surface of the second active portion away from the first substrate, and part of a side surface of the second active portion, and exposes part of the passivation layer adjacent to the second active portion.

5. The array substrate of claim 3, wherein, The source comprises: a source main portion, and a first source branch portion and a second source branch portion extending from the source main portion in a second direction; the second electrode portion covers the first source branch portion, the second source branch portion, and a region between the first source branch portion and the second source branch portion in a projection of the first substrate.

6. The array substrate of claim 3, wherein, A maximum depth of the first via hole is less than a maximum thickness of the passivation layer.

7. The array substrate of claim 1, wherein, The array substrate further comprises: a pixel electrode; the first electrode and the pixel electrode are of the same layer and the same material, and the first electrode and the pixel electrode are insulated from each other.

8. The array substrate of claim 7, wherein, The array substrate comprises: a plurality of gate lines extending along a first direction; the plurality of electrode portions comprise: a third electrode portion, a fourth electrode portion, and a fifth electrode portion extending along a third direction and connecting the third electrode portion and the fourth electrode portion; the third direction intersects the first direction and a second direction; The third electrode portion and the pixel electrode are located on the same side of the gate line; the fourth electrode portion, in the orthographic projection of the first substrate, overlaps the gate line in the orthographic projection of the first substrate.

9. The array substrate of claim 8, wherein, The active pattern comprises a second active pattern; the array substrate further comprises: a transfer electrode located at the layer where the drain electrode is located, a gate insulating layer located at the side of the second active pattern facing the first substrate, and a common electrode layer located at the side of the gate insulating layer facing the first substrate; the via hole comprises a second via hole penetrating through the passivation layer and the gate insulating layer; the second active pattern is located at the side of the transfer electrode facing the first substrate and is in contact with the transfer electrode; the second active pattern has a third active portion overlapping the transfer electrode and a fourth active portion extending from the third active portion; the common electrode layer comprises a plurality of common electrode strips extending along the first direction; The second via hole exposes the part of the transfer electrode facing away from the surface of the side of the first substrate, the side of the transfer electrode, the part of the fourth active portion facing away from the surface of the side of the first substrate, and the part of the side of the fourth active portion, and exposes the part of the common electrode strip facing away from the surface of the side of the first substrate; the third electrode portion covers the second via hole and at least overlaps the transfer electrode and the common electrode strip.

10. The array substrate of claim 8, wherein, The source electrode comprises: a source main portion, and a first source branch portion and a second source branch portion extending from the source main portion along a second direction; The fourth electrode portion, in the orthographic projection of the first substrate, covers the first source branch portion, the second source branch portion, and the region between the first source branch portion and the second source branch portion.

11. The array substrate of claim 3 or 9, wherein, The passivation layer further has a first recess with a surface facing away from the first substrate and recessed toward the first substrate; the first recess, in the orthographic projection of the first substrate, covers at least part of the source electrode in the orthographic projection of the first substrate and at least part of the drain electrode in the orthographic projection of the first substrate.

12. The array substrate of claim 11, wherein, The second electrode portion is located in the first recess; or, the fourth electrode portion is located in the first recess.

13. A display panel, characterized by The array substrate comprises: a plurality of gate lines extending along a first direction; the plurality of electrode portions comprise: a third electrode portion, a fourth electrode portion, and a fifth electrode portion extending along a third direction and connecting the third electrode portion and the fourth electrode portion; the third direction intersects the first direction and a second direction; 14. The display panel of claim 13, wherein, The array substrate has a first recess; the counter substrate comprises: a second substrate, and a spacer located at the side of the second substrate facing the array substrate; the spacer, in the orthographic projection of the first substrate, overlaps the first recess in the orthographic projection of the first substrate; the surface of the spacer facing the array substrate is covered with a conductive portion; the conductive portion is in contact with the first electrode.

15. The display panel of claim 14, wherein, The conductive portion is an integral transparent surface electrode.

16. The display panel of claim 14, wherein, The counter substrate further comprises a black matrix layer on the side of the spacers facing the second substrate; the black matrix layer comprises a plurality of first sub-black matrix portions extending in a first direction, and a plurality of second sub-black matrix portions extending in a second direction; The conductive portions comprise a plurality of first sub-conductive portions extending in a first direction, and a plurality of second sub-conductive portions extending in a second direction; the first sub-black matrix portions cover the first sub-conductive portions in the orthographic projection of the second substrate; the second sub-black matrix portions cover the second sub-conductive portions in the orthographic projection of the second substrate.

17. The display panel of claim 16, wherein, The material of the conductive portions comprises a transparent metal oxide or metal.

18. The display panel of claim 14, wherein, The array substrate further comprises a common electrode layer; the conductive portions are loaded with a voltage different from the voltage loaded on the common electrode layer; or, the conductive portions are loaded with a voltage same as the voltage loaded on the common electrode layer.

19. A display device comprising: A display panel comprising any one of claims 13-18.

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