Single-chip microcomputer embedded system based on electronic engineering information

Abstract

The invention provides a single-chip microcomputer embedded system based on electronic engineering information, and belongs to the technical field of single-chip microcomputers. The single-chip microcomputer embedded system based on the electronic engineering information comprises a main processor, an interface controller, an A / D converter, a D / A converter, a sensing module, an execution module and a memory storage module, wherein the main processor adopts a single-chip microcomputer which is arranged on a silicon plate by adopting a common integrated circuit. The interface controller is arranged, the memory storage module is combined, the memory storage module is used for receiving and sending signals between the memory storage module and the microprocessor to construct an independent exclusive storage area for a user, and based on a strict access control and encryption mechanism, multi-level management and control are implemented from the physical storage level and the logic access permission dimension, so that the security of the user is improved. External illegal access is effectively isolated, the security and confidentiality of private data storage of the user are practically guaranteed, the risk of data leakage is completely eradicated, and a firm and firm protection barrier is built for sensitive information of the user.

Description

Technical Field

[0001] The invention relates to the technical field of single-chip microcomputers, and in particular to a single-chip microcomputer embedded system based on electronic engineering information. Background Art

[0002] In today's era of rapid technological development, electronic information technology has become one of the key components of modern life. In recent years, the emerging electronic application system - embedded system, is increasingly gaining favor and popularity with its unique advantages. The embedded system uses a small and dedicated embedded microprocessor as the "core brain", cleverly integrating advanced software and hardware architecture design, achieving high integration and intelligence in a very small physical space, and can smoothly access the electronic information engineering ecosystem.

[0003] As a key device with independent operation capability, embedded system has two core components, namely processor and software. The processor relies on its powerful computing power to efficiently process various complex data information, laying a solid foundation for the stable operation of the entire system, while the software weaves the system architecture to realize multiple functions. The existing single-chip embedded system structure has not yet built components and operating logic that are closely coordinated enough, and cannot meet the requirements of high efficiency of electronic engineering information. Summary of the invention

[0004] In order to make up for the above deficiencies, the present invention provides a single-chip microcomputer embedded system based on electronic engineering information that overcomes the above technical problems or at least partially solves the above problems.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] A single-chip embedded system based on electronic engineering information includes a main processor, the main processor is a single-chip microcomputer on a silicon board using a common integrated circuit;

[0007] An interface controller, the interface controller comprising a CMOS chip, a local DMA and a remote DMA, the CMOS chip comprising an SRAM and a memory arbitration circuit, a general register, a media access control core, a Manchester codec, an interface circuit and a physical transceiver;

[0008] A / D converter, the A / D converter is an analog-to-digital converter, and the A / D converter converts an analog signal into a digital signal;

[0009] D / A converter, which is a digital-to-analog converter that converts digital signals into analog signals

[0010] A sensor module, which converts various detected physical quantities into digital signals and transmits them to the main processor and the memory storage module via the D / A sensor module;

[0011] An execution module, which adjusts various physical quantities after the main processor converts the signal into an analog signal via a D / A converter;

[0012] A memory storage module is used to store the digital signal of the A / D converter and the digital signal of the sensor module. The memory storage module is also used to receive and send signals with the microprocessor.

[0013] By setting up an interface controller and combining it with a memory storage module, the memory storage module is used to receive and send signals with the microprocessor to build an independent exclusive storage area for the user. Based on strict access control and encryption mechanisms, multi-level management and control are implemented from the physical storage level and logical access permission dimension to effectively isolate external illegal access, effectively ensure the security and confidentiality of the user's private data storage, eliminate the risk of data leakage, and build a solid protection barrier for user sensitive information.

[0014] In one embodiment of the present invention, the local DMA is a connection channel between CMOS and a network cable, the remote DMA is an ISA bus interface, and the remote DMA is a bus for reading and writing RAM inside a main processor.

[0015] In one embodiment of the present invention, the total register adopts a bit internal register, and the total register includes a command register, a receiving page start register, a receiving page end register, a boundary pointer register, a sending page start register, an interrupt status register, a remote byte counter, a receiving configuration register, a sending configuration register, a data configuration register and an interrupt mask register.

[0016] In one embodiment of the present invention, the command register is used to issue various operation commands and control instructions to the system or related modules, the receiving page start register specifies the starting address or starting page number of the receiving data storage area, the receiving page end register defines the end position of the receiving data storage area, the boundary pointer register is used to indicate the boundary position of the data storage area, the sending page start register is used to specify the starting address or starting page number of the sending data storage area, the interrupt status register is used to record the current status of each interrupt source in the system, the remote byte counter is used to count the number of data bytes transmitted remotely, the receiving configuration register is used to configure various parameters and working modes of the receiving module, the sending configuration register is used to configure various parameters and working modes of the sending module, the data configuration register ensures the correct representation and processing of data within the system and between external devices, and the interrupt mask register is used to control whether each interrupt source is allowed to generate an interrupt request.

[0017] In one embodiment of the present invention, the working modes of the interface controller include a jumper mode, a plug-and-play mode, and a jumper-free mode. The jumpers involved in the jumper mode include pins fixed on a circuit board and jumper caps for plugging and unplugging the pins. When the jumper caps are inserted into a specific pin or socket combination, a path is formed between the corresponding circuit nodes, thereby changing the direction of current flow or realizing the connection or disconnection of certain signals, thereby achieving the purpose of changing the function or parameters of the device.

[0018] In one embodiment of the present invention, the functional logic of the CMOS chip includes first-in-first-out logic, receiving logic, CRC check logic, sending logic, address recognition logic, direct memory access and buffer control logic. The first-in-first-out logic is FIFO logic. The first-in-first-out logic involves a FIFO memory for caching continuous data streams and preventing data loss during machine entry and storage operations while reducing the burden on the CPU and increasing data transmission speed. The receiving logic realizes serial to parallel data conversion during the receiving process. After receiving pulse information in each line, the receiving logic sends one byte of data to the FIFO memory and then sends it to the address recognition logic for comparison.

[0019] In one embodiment of the present invention, the CRC check logic is a cyclic redundancy check logic. After performing CRC check on the input data, the CRC check logic compares the result with the last data frame. If the results compared by the CRC check logic are the same, the results are sent and stored in the receiving buffer. If the results compared by the CRC check logic are different, the result data is received. The sending logic is used to convert the data read from the FIFO into a serial bit stream for transmission during the sending process. The address recognition logic compares the destination address in the received data frame and the station address in the address register array and determines whether the address is a data frame sent to the local. The direct memory access is local DMA and remote DMA. When receiving data, the local DMA stores the received data in the receiving buffer. When sending data, the local DMA transfers the data sent to the receiving buffer to the FIFO.

[0020] In one embodiment of the present invention, the main processor is electrically connected to the A / D converter, the D / A converter, and the memory storage module respectively, the sensor module is electrically connected to the D / A converter, and the execution module is electrically connected to the A / D converter.

[0021] In one embodiment of the present invention, the sensing module includes a sensitive element, a conversion element, a conversion circuit and an auxiliary power supply. The output signal of the sensitive element is a physical quantity of displacement, voltage and strain. The conversion element converts the signal sensed by the sensitive element into an electrical signal. The electrical signal is easier to process, amplify, filter and transmit in a single-chip embedded system. The presence of the conversion element enables the sensing module to better interface and work with electronic devices such as a single-chip microcomputer. The conversion circuit adjusts and amplifies the electrical signal output by the conversion element, and converts the signal output by the sensing module into a standard signal form suitable for the single-chip microcomputer to collect and process, such as converting an analog signal into a digital signal, so that the single-chip microcomputer can accurately read and analyze the information measured by the sensing module. The auxiliary power supply provides necessary energy support for the sensing module. In some low-power single-chip embedded systems, a reasonable design of the auxiliary power supply circuit is of great significance for reducing the power consumption of the entire system, extending the working time of the system and improving the reliability of the system.

[0022] In one embodiment of the present invention, the execution module is composed of an actuator, a drive circuit and a control circuit. The actuator converts other forms of energy into mechanical energy or other energy forms that can directly drive the controlled object. The actuator is the core component of the actuator, which directly acts on the controlled object to realize various actions or functions required by the system. The drive circuit is mainly used to amplify the power of the control signal to provide sufficient energy to drive the actuator, and is responsible for converting the control signal output by the single-chip microcomputer into the signal form and level required by the actuator. The control circuit is responsible for receiving the control instructions issued by the single-chip microcomputer and parsing and processing them. It has certain logical operation capabilities, and performs logical judgment and control on the actions of the actuator according to the system requirements and the information fed back by the sensor to realize complex control tasks.

[0023] In one embodiment of the present invention, the memory storage module is composed of a storage cell array, an address decoder, a read-write control circuit and a storage controller. The storage cell array is composed of storage cells arranged in a matrix form. The address decoder decodes the address signal sent by the single-chip microcomputer to determine the specific position of the storage cell to be accessed in the storage cell array. When the single-chip microcomputer needs to read or write data in a certain storage cell, it will send an address signal. The address decoder will analyze and interpret this signal to find the corresponding storage cell. The read-write control circuit performs read and write operations on the data in the storage cell array according to the read and write commands of the single-chip microcomputer. When the single-chip microcomputer sends a read command, the read-write control circuit will take out data from the specified storage cell and transmit it to the single-chip microcomputer; when the single-chip microcomputer sends a write command, the read-write control circuit will write the data sent by the single-chip microcomputer into the specified storage cell. The storage controller is responsible for coordinating and managing the work between the storage cell array, the address decoder and the read-write control circuit. The storage controller can also set and adjust the working mode, read and write speed, storage capacity and other parameters of the memory to meet the memory requirements of the single-chip microcomputer embedded system in different application scenarios.

[0024] The present invention provides a single-chip embedded system based on electronic engineering information, and its beneficial effects include:

[0025] 1. By setting up an interface controller and combining it with a memory storage module, the memory storage module is used to receive and send signals between the microprocessor to build an independent exclusive storage area for the user. Based on strict access control and encryption mechanisms, multi-level management and control are implemented from the physical storage level and the logical access permission dimension to effectively isolate external illegal access, effectively ensure the security and confidentiality of the user's private data storage, eliminate the risk of data leakage, and build a solid protection barrier for the user's sensitive information.

[0026] 2. By setting up a CMOS chip, in terms of operating performance, this system has excellent parallel processing capabilities. Relying on advanced multi-threaded and multi-process scheduling architecture, it can simultaneously carry out multiple complex transaction processing processes. According to the priority and resource demand characteristics of each transaction, it can efficiently and accurately allocate computing resources to achieve orderly execution and coordinated operation of various tasks, avoid system freezes or delays caused by resource preemption, and comprehensively improve task processing efficiency and system response speed.

[0027] 3. By setting local DMA and remote DMA, in terms of the internal architecture of the system, each processing program module follows standardized communication protocols and interface specifications, and uses efficient message queues, shared memory and other data interaction methods to achieve real-time and accurate interaction of device information, break the data islands between modules, achieve information interconnection, reduce the manual coordination costs caused by information isolation, automatically promote task flow, significantly reduce the user's operating burden, and optimize the overall user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1 is a system configuration diagram provided by an embodiment of the present invention;

[0030] Figure 2 A structural diagram of a CMOS chip provided for an embodiment of the present invention;

[0031] Figure 3 A schematic diagram of signal transmission and reception of an interface controller provided in an embodiment of the present invention;

[0032] Figure 4 A schematic diagram of the overall register composition provided for an embodiment of the present invention;

[0033] Figure 5 A schematic diagram of the working mode of the interface controller provided in an embodiment of the present invention;

[0034] Figure 6 A functional logic diagram of a CMOS chip provided by an embodiment of the present invention;

[0035] Figure 7 A diagram showing the structure of a sensor module provided in an embodiment of the present invention;

[0036] Figure 8 Execution module structure diagram provided for the implementation mode of the present invention

[0037] In the figure: 1. main processor; 2. interface controller; 2001. CMOS chip; 201. SRAM and memory arbitration circuit; 202. total register; 2021. command register; 2022. receive page start register; 2023. receive page end register; 2024. boundary pointer register; 2025. send page start register; 2026. interrupt status register; 2027. remote byte counter; 2028. receive configuration register; 2029. send configuration register; 2030. data configuration register; 2031. interrupt mask register; 203. media access control core; 204. Manchester encoder; 205. interface circuit; 206. physical transceiver; 3. local DMA; 4. remote DMA; 5. A / D converter; 6. D / A converter; 7. sensor module; 8. execution module; 9. memory storage module. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] In the description of the present invention, it should be noted that the terms "upper", "lower", "left", "right", "inner", "outer", "top / bottom" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0040] Example

[0041] See also Figure 1-8The present invention provides a technical solution: a single-chip embedded system based on electronic engineering information, including a main processor 1, an interface controller 2, an A / D converter 5, a D / A converter 6, a sensor module 7, a sensor module 7, an execution module 8 and a memory storage module 9, the main processor 1 adopts a single-chip microcomputer with common integrated circuits arranged on a silicon board, the interface controller 2 includes a CMOS chip 2001, a local DMA 3 and a remote DMA 4, the CMOS chip 2001 includes an SRAM and a memory arbitration circuit 201, a total register 202, a media access control core 203, a Manchester encoder 204, an interface circuit 205 and a physical transceiver 206, A / The D converter 5 is an analog-to-digital converter. The A / D converter 5 converts analog signals into digital signals. The D / A converter 6 is a digital-to-analog converter. The D / A converter 6 converts digital signals into analog signals. The various physical quantities detected are converted into digital signals and transmitted to the main processor 1 and the memory storage module 9 via the D / A sensor module 7. The execution module 8 adjusts various physical quantities after the main processor 1 converts the signal into an analog signal via the D / A converter 6. The memory storage module 9 is used to store the digital signals of the A / D converter 5 and the digital signals of the sensor module 7. The memory storage module 9 is also used to receive and send signals between the microprocessor and can receive signals. The port controller 2 is combined with the memory storage module 9. The memory storage module 9 is used to receive and send signals between the microprocessor and to build an independent exclusive storage area for the user. Based on strict access control and encryption mechanisms, multi-level management and control are implemented from the physical storage level and the logical access permission dimension to effectively isolate external illegal access, effectively protect the security and confidentiality of the user's private data storage, eliminate the risk of data leakage, and build a solid protection barrier for the user's sensitive information. It can CMOS chip 2001. In terms of operating efficiency, this system has excellent parallel processing capabilities. Relying on advanced multi-threaded and multi-process scheduling architecture, it can simultaneously carry out multiple complex transaction processing processes. According to each transaction Priority and resource demand characteristics, efficient and accurate allocation of computing resources, orderly execution of tasks, coordinated operation, avoiding system freezes or delays caused by resource preemption, and comprehensively improving task processing efficiency and system response speed. It can perform local DMA3 and remote DMA4. In terms of the internal architecture of the system, each processing program module follows standardized communication protocols and interface specifications, and uses efficient message queues, shared memory and other data interaction methods to achieve real-time and accurate interaction of device information, break the data islands between modules, achieve information interconnection, reduce the manual coordination costs caused by information isolation, automatically promote task flow, significantly reduce the user's operating burden, and optimize the overall user experience.

[0042] See also Figure 1-8Local DMA3 is the connection channel between CMOS and the network cable, and remote DMA4 is the ISA bus interface. Remote DMA4 is the bus for reading and writing the internal RAM of the main processor 1.

[0043] See also Figure 1-8 The total register 202 uses an 8-bit internal register. The total register 202 includes a command register 2021, a receive page start register 2022, a receive page end register 2023, a boundary pointer register 2024, a send page start register 2025, an interrupt status register 2026, a remote byte counter 2027, a receive configuration register 2028, a send configuration register 2029, a data configuration register 2030 and an interrupt mask register 2031. The command register 2021 is used to issue various operation commands and control instructions to the system or related modules. The receive page start register 2022 specifies the starting address or starting page number of the receive data storage area. The receive page end register 2023 defines the end of the receive data storage area. The boundary pointer register 2024 is used to indicate the boundary position of the data storage area. The sending page start register 2025 is used to specify the starting address or starting page number of the sending data storage area. The interrupt status register 2026 is used to record the current status of each interrupt source in the system. The remote byte counter 2027 is used to count the number of data bytes transmitted remotely. The receiving configuration register 2028 is used to configure various parameters and working modes of the receiving module. The sending configuration register 2029 is used to configure various parameters and working modes of the sending module. The data configuration register 2030 ensures the correct representation and processing of data within the system and between external devices. The interrupt mask register 2031 is used to control whether each interrupt source is allowed to generate an interrupt request.

[0044] See also Figure 1-8 The working modes of the interface controller 2 include a jumper mode, a plug-and-play mode, and a jumper-free mode. The jumpers involved in the jumper mode include pins fixed on the circuit board and jumper caps for plugging and unplugging the pins. When the jumper caps are inserted into a specific pin or socket combination, a path is formed between the corresponding circuit nodes, thereby changing the direction of current flow or realizing the connection or disconnection of certain signals, thereby achieving the purpose of changing the function or parameters of the device.

[0045] See also Figure 1-8The functional logic of CMOS chip 2001 includes first-in-first-out logic, receiving logic, CRC check logic, sending logic, address recognition logic, direct memory access and buffer control logic. The first-in-first-out logic is FIFO logic. The first-in-first-out logic involves FIFO memory, which is used to cache continuous data streams and prevent data loss during machine entry and storage operations, while reducing the burden on the CPU and increasing data transmission speed. The receiving logic realizes serial to parallel data conversion in the receiving process. The receiving logic sends one byte of data to the FIFO memory after receiving pulse information in each line, and then sends it to the address recognition logic for comparison.

[0046] See also Figure 1-8 , CRC check logic is cyclic redundancy check logic. After CRC check is performed on the input data, the CRC check logic compares the result with the last data frame. If the comparison result of the CRC check logic is the same, it is sent and stored in the receiving buffer. If the comparison result of the CRC check logic is different, the result data is received. The sending logic is used to convert the data read from the FIFO into a serial bit stream during the sending process. The address recognition logic compares the destination address in the received data frame with the station address in the address register array and determines whether the address is a data frame sent to the local. Direct memory access is local DMA3 and remote DMA4. When receiving data, the local DMA3 stores the received data in the receiving buffer. When sending data, the local DMA3 transfers the data sent to the receiving buffer to the FIFO.

[0047] See also Figure 1-8 The main processor 1 is electrically connected to the A / D converter 5, the D / A converter 6, and the memory storage module 9 respectively, the sensor module 7 is electrically connected to the D / A converter 6, and the execution module 8 is electrically connected to the A / D converter 5.

[0048] See also Figure 1-8The sensor module 7 includes a sensitive element, a conversion element, a conversion circuit and an auxiliary power supply. The output signal of the sensitive element is the physical quantity of displacement, voltage and strain. The conversion element converts the signal sensed by the sensitive element into an electrical signal. The electrical signal is easier to process, amplify, filter and transmit in the single-chip embedded system. The existence of the conversion element enables the sensor module 7 to better interface and work with electronic devices such as single-chip microcomputers. The conversion circuit adjusts and amplifies the electrical signal output by the conversion element, and converts the signal output by the sensor module 7 into a standard signal form suitable for the single-chip microcomputer to collect and process, such as converting analog signals into digital signals, so that the single-chip microcomputer can accurately read and analyze the information measured by the sensor module 7. The auxiliary power supply provides necessary energy support for the sensor module 7. In some low-power single-chip embedded systems, a reasonable design of the auxiliary power supply circuit is of great significance for reducing the power consumption of the entire system, extending the working time of the system and improving the reliability of the system.

[0049] See also Figure 1-8 The execution module 8 is composed of an actuator, a drive circuit and a control circuit. The actuator converts other forms of energy into mechanical energy or other energy forms that can directly drive the controlled object. The actuator is the core component of the actuator. It directly acts on the controlled object to realize various actions or functions required by the system. The drive circuit is mainly used to amplify the power of the control signal to provide sufficient energy to drive the actuator. It is responsible for converting the control signal output by the single-chip microcomputer into the signal form and level required by the actuator. The control circuit is responsible for receiving the control instructions issued by the single-chip microcomputer and parsing and processing them. It has certain logical operation capabilities. According to the requirements of the system and the information fed back by the sensor, the action of the actuator is logically judged and controlled to realize complex control tasks.

[0050] See also Figure 1-8The memory storage module 9 is composed of a storage cell array, an address decoder, a read-write control circuit and a storage controller. The storage cell array is arranged in a matrix form by storage cells. The address decoder decodes the address signal sent by the single-chip microcomputer to determine the specific position of the storage cell to be accessed in the storage cell array. When the single-chip microcomputer needs to read or write data in a certain storage cell, it will send an address signal. The address decoder will analyze and interpret this signal to find the corresponding storage cell. The read-write control circuit reads and writes the data in the storage cell array according to the read-write command of the single-chip microcomputer. When the single-chip microcomputer sends a read command, the read-write control circuit will take out the data from the specified storage cell and transmit it to the single-chip microcomputer; when the single-chip microcomputer sends a write command, the read-write control circuit will write the data sent by the single-chip microcomputer into the specified storage cell. The storage controller is responsible for coordinating and managing the work between the storage cell array, the address decoder and the read-write control circuit. The storage controller can also set and adjust the working mode, read-write speed, storage capacity and other parameters of the memory to meet the memory requirements of the single-chip microcomputer embedded system in different application scenarios.

[0051] Specifically, the working process or working principle of the single-chip microcomputer embedded system based on electronic engineering information is as follows: when in use, the functional logic of the CMOS chip is a first-in-first-out logic, namely, a FIFO logic, involving a FIFO memory. The FIFO memory is the buffering link of the system, which caches continuous data streams to prevent data loss during machine entry and storage operations, while reducing the burden on the CPU and increasing the data transmission speed; the receiving logic realizes the serial to parallel data conversion in the receiving process, and after receiving pulse information in each line, a byte of data is sent to the FIFO memory, and then sent to the address recognition logic for comparison, the correct information is sent to the I / O buffer, and then the main processor is notified to read the data away; during the sending process of the CRC check logic, the data frame is subjected to a cyclic redundancy check algorithm, and the CRC code after the data frame is generated is sent out; during the construction process, the received frame is subjected to a CRC check. Specifically, after the CRC check is performed on the input data, the result is compared with the last data frame. If they are different, the result data is received, and if they are the same, they are sent and stored in the receiving buffer; during the sending process, the sending logic converts the data read from the FIFO into a serial bit stream for transmission; the address recognition logic compares the destination address in the received data frame with the station address in the address register array to determine whether the address is a data frame sent to the local; when the direct memory access and buffer control logic receives data, the local DMA stores the received data into the receiving buffer I / O buffer, and when sending data, the local DMA transfers the data sent to the receiving buffer to the FIFO. The working modes of the interface controller 2 include jumper mode, plug-and-play mode and jumper-free mode. The jumpers involved in the jumper mode include pins fixed on the circuit board and jumper caps for plugging and unplugging pins. When the jumper cap is inserted into a specific pin or socket combination, a path is formed between the corresponding circuit nodes, thereby changing the direction of current flow or implementation. The connection or disconnection of certain signals is realized, thereby achieving the purpose of changing the function or parameter of the device. The first-in-first-out logic involves the FIFO memory, which is used to cache continuous data streams and prevent data loss during machine entry and storage operations, while reducing the burden on the CPU and increasing the data transmission speed. The receiving logic realizes the serial to parallel data conversion in the receiving process. The receiving logic sends one byte of data into the FIFO memory after receiving the pulse information in each line, and then sends it to the address recognition logic for comparison. The CRC check logic compares the result with the last data frame after performing a CRC check on the input data. If the results compared by the CRC check logic are the same, they are sent and stored in the receiving buffer. If the results compared by the CRC check logic are different, the result data is received. The sending logic is used to convert the data read from the FIFO into a serial bit stream during the sending process. The address recognition logic compares the destination address in the received data frame with the station address in the address register array and determines whether the address is a data frame sent to the local.Direct memory access is local DMA3 and remote DMA4. When receiving data, local DMA3 stores the received data into the receiving buffer. When sending data, local DMA3 transmits the data sent to the receiving buffer to FIFO. The output signal of the sensitive element is the physical quantity of displacement, voltage and strain. The conversion element converts the signal sensed by the sensitive element into an electrical signal. The electrical signal is easier to process, amplify, filter and transmit in the single-chip embedded system. The existence of the conversion element enables the sensor module 7 to better interface and work with electronic devices such as single-chip microcomputers. The conversion circuit adjusts and amplifies the electrical signal output by the conversion element, and converts the signal output by the sensor module 7 into a standard signal form suitable for the single-chip microcomputer to collect and process, such as converting analog signals into digital signals, so that the single-chip microcomputer can accurately read and analyze the information measured by the sensor module 7. The auxiliary power supply provides necessary energy support for the sensor module 7. The actuator converts other forms of energy into mechanical energy or other energy forms that can directly drive the controlled object. The actuator is the core component of the actuator. It directly acts on the controlled object to realize various actions or functions required by the system. The drive circuit is mainly used to amplify the power of the control signal to provide sufficient energy to drive the actuator. The mechanism is responsible for converting the control signal output by the single-chip microcomputer into the signal form and level required by the actuator. The control circuit is responsible for receiving the control instructions issued by the single-chip microcomputer and parsing and processing them. According to the requirements of the system and the information fed back by the sensor, the action of the actuator is logically judged and controlled to achieve complex control tasks. The storage cell array is arranged in a matrix form by the storage cells. The address decoder decodes the address signal issued by the single-chip microcomputer to determine the specific location of the storage cell to be accessed in the storage cell array. When the single-chip microcomputer needs to read or write data in a storage cell, it will send an address signal, and the address decoder will Analyze and interpret this signal to find the corresponding storage unit. The read-write control circuit reads and writes the data in the storage unit array according to the read-write command of the microcontroller. When the microcontroller issues a read command, the read-write control circuit will take out the data from the specified storage unit and transmit it to the microcontroller; when the microcontroller issues a write command, the read-write control circuit will write the data sent by the microcontroller into the specified storage unit. The storage controller is responsible for coordinating and managing the work between the storage unit array, the address decoder and the read-write control circuit. The storage controller can also set and adjust the working mode, read-write speed, storage capacity and other parameters of the memory.

[0052] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A single-chip embedded system based on electronic engineering information, characterized in that: The system comprises: A main processor (1), the main processor (1) is a single chip microcomputer using a common integrated circuit arranged on a silicon board; An interface controller (2), the interface controller (2) comprising a CMOS chip (2001), a local DMA (3) and a remote DMA (4), the CMOS chip (2001) comprising an SRAM and memory arbitration circuit (201), a general register (202), a media access control core (203), a Manchester codec (204), an interface circuit (205) and a physical transceiver (206); An A / D converter (5), wherein the A / D converter (5) is an analog-to-digital converter, and the A / D converter (5) converts an analog signal into a digital signal; D / A converter (6), the D / A converter (6) is a digital-to-analog converter, the D / A converter (6) converts a digital signal into an analog signal A sensor module (7), wherein the sensor module (7) converts various detected physical quantities into digital signals and transmits the digital signals to the main processor (1) and the memory storage module (9) via the D / A sensor module (7); An execution module (8), wherein the execution module (8) adjusts various physical quantities after the main processor (1) converts the signal into an analog signal via the D / A converter (6); A memory storage module (9), the memory storage module (9) is used to store the digital signal of the A / D converter (5) and the digital signal of the sensor module (7), and the memory storage module (9) is also used to receive and send signals between the microprocessor.

2. The single-chip embedded system based on electronic engineering information according to claim 1, characterized in that: The local DMA (3) is a connection channel between the CMOS and the network cable, and the remote DMA (4) is an ISA bus interface. The remote DMA (4) is a bus for reading and writing the internal RAM of the main processor (1).

3. A single chip microcomputer embedded system based on electronic engineering information according to claim 2, characterized in that: The total register (202) adopts an 8-bit internal register, and the total register (202) includes a command register (2021), a receiving page start register (2022), a receiving page end register (2023), a boundary pointer register (2024), a sending page start register (2025), an interrupt status register (2026), a remote byte counter (2027), a receiving configuration register (2028), a sending configuration register (2029), a data configuration register (2030) and an interrupt mask register (2031). The command register (2021) is used to issue various operation commands and control instructions to the system or related modules, the receiving page start register (2022) specifies the starting address or starting page number of the receiving data storage area, and the receiving page end register (2023) defines the receiving data storage area. The end position of the domain, the boundary pointer register (2024) is used to indicate the boundary position of the data storage area, the sending page start register (2025) is used to specify the starting address or starting page number of the sending data storage area, the interrupt status register (2026) is used to record the current status of each interrupt source in the system, the remote byte counter (2027) is used to count the number of data bytes transmitted remotely, the receiving configuration register (2028) is used to configure various parameters and working modes of the receiving module, the sending configuration register (2029) is used to configure various parameters and working modes of the sending module, the data configuration register (2030) ensures the correct representation and processing of data within the system and between external devices, and the interrupt mask register (2031) is used to control whether each interrupt source is allowed to generate an interrupt request.

4. A single chip embedded system based on electronic engineering information according to claim 3, characterized in that: The working modes of the interface controller (2) include a jumper mode, a plug-and-play mode and a jumper-free mode. The jumpers involved in the jumper mode include pins fixed on a circuit board and jumper caps for plugging and unplugging the pins.

5. A single chip microcomputer embedded system based on electronic engineering information according to claim 4, characterized in that: The functional logic of the CMOS chip (2001) includes first-in-first-out logic, receiving logic, CRC check logic, sending logic, address recognition logic, direct memory access and buffer control logic. The first-in-first-out logic is FIFO logic. The first-in-first-out logic involves a FIFO memory for caching continuous data streams and preventing data loss during machine entry and storage operations, while reducing the burden on the CPU and increasing data transmission speed. The receiving logic realizes serial to parallel data conversion during the receiving process. After receiving pulse information in each line, the receiving logic sends one byte of data to the FIFO memory and then sends it to the address recognition logic for comparison.

6. A single chip microcomputer embedded system based on electronic engineering information according to claim 5, characterized in that: The CRC check logic is a cyclic redundancy check logic. After performing CRC check on the input data, the CRC check logic compares the result with the last data frame. If the comparison results of the CRC check logic are the same, the result data is sent and stored in the receiving buffer. If the comparison results of the CRC check logic are different, the result data is received. The sending logic is used to convert the data read from the FIFO into a serial bit stream for transmission during the sending process. The address recognition logic compares the destination address in the received data frame and the station address in the address register array and determines whether the address is a data frame sent to the local. The direct memory access is a local DMA (3) and a remote DMA (4). When receiving data, the local DMA (3) stores the received data in the receiving buffer. When sending data, the local DMA (3) transfers the data sent to the receiving buffer to the FIFO.

7. A single chip microcomputer embedded system based on electronic engineering information according to claim 6, characterized in that: The main processor (1) is electrically connected to the A / D converter (5), the D / A converter (6), and the memory storage module (9), respectively; the sensor module (7) is electrically connected to the D / A converter (6); and the execution module (8) is electrically connected to the A / D converter (5).

8. A single chip microcomputer embedded system based on electronic engineering information according to claim 7, characterized in that: The sensor module (7) comprises a sensitive element, a conversion element, a conversion circuit and an auxiliary power supply. The output signal of the sensitive element is a physical quantity of displacement, voltage and strain. The conversion element converts the signal sensed by the sensitive element into an electrical signal. The conversion circuit adjusts and amplifies the electrical signal output by the conversion element (converting the signal output by the sensor module (7) into a standard signal form suitable for collection and processing by a single-chip microcomputer, such as converting an analog signal into a digital signal so that the single-chip microcomputer can accurately read and analyze the information measured by the sensor module (7)). The auxiliary power supply provides necessary energy support for the sensor module (7).

9. A single chip embedded system based on electronic engineering information according to claim 8, characterized in that: The execution module (8) is composed of an actuator, a drive circuit and a control circuit. The actuator converts other forms of energy into mechanical energy or other energy forms that can directly drive the controlled object. The drive circuit is mainly used to amplify the power of the control signal to provide sufficient energy to drive the actuator. The control circuit is responsible for receiving the control instructions issued by the single-chip microcomputer and analyzing and processing them.

10. A single chip microcomputer embedded system based on electronic engineering information according to claim 9, characterized in that: The memory storage module (9) is composed of a storage cell array, an address decoder, a read-write control circuit and a storage controller. The storage cell array is composed of storage cells arranged in a matrix form. The address decoder decodes the address signal sent by the single-chip computer to determine the specific position of the storage cell to be accessed in the storage cell array. The read-write control circuit performs read and write operations on the data in the storage cell array according to the read and write commands of the single-chip computer. The storage controller is responsible for coordinating and managing the work between the storage cell array, the address decoder and the read-write control circuit.

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