Segmented temperature control circuit and radio frequency module

Abstract

The invention relates to a segmented temperature control circuit and a radio frequency module. According to the segmented temperature control circuit, a first temperature coefficient signal generation circuit provides a first temperature coefficient signal; the second temperature coefficient signal generation circuit provides a second temperature coefficient signal; the size relation of the first temperature coefficient signal and the second temperature coefficient signal changes at the set temperature; the comparison circuit is configured to generate and output a first start-stop control signal of a first level and a second start-stop control signal of a second level which are opposite to each other according to a first comparison result of the first temperature coefficient signal and the second temperature coefficient signal under the condition that the current temperature is lower than the set temperature; therefore, the first temperature coefficient biasing circuit and the second temperature coefficient biasing circuit are controlled to start and stop. Different temperature coefficient signals can be provided in different temperature sections, and the requirements of the radio frequency PA on different temperature coefficients of the bias current in different temperature sections can be met.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a segmented temperature control circuit and a radio frequency module. Background Art

[0002] RF power amplifier (or operational amplifier, PA for short) is an important component in wireless communication systems. It is mainly used to amplify low-power RF signals to a sufficient power level so that they can be radiated through the antenna. RF PA usually requires a suitable current source or voltage source to provide bias current to provide a suitable operating point to achieve high efficiency and high linearity.

[0003] For example, the bias current provided to the RF PA has different requirements at different temperature ranges. If the bias current remains unchanged when the temperature changes, it may not be suitable in the bias circuit design of the RF PA.

[0004] Therefore, in order to meet the above requirements of RF PA in different temperature ranges, it is crucial to provide a bias current supply circuit with segmented temperature control. Summary of the invention

[0005] In view of this, the embodiments of the present application provide a segmented temperature control circuit and a radio frequency module to solve at least one problem existing in the background technology.

[0006] In a first aspect, an embodiment of the present application provides a segmented temperature control circuit, the segmented temperature control circuit comprising:

[0007] A first temperature coefficient signal generating circuit configured to provide a first temperature coefficient signal;

[0008] A second temperature coefficient signal generating circuit is configured to provide a second temperature coefficient signal; a first curve of the value of the first temperature coefficient signal changing with temperature and a second curve of the value of the second temperature coefficient signal changing with temperature have at least one intersection point at a set temperature, so that the magnitude relationship between the value of the first temperature coefficient signal and the value of the second temperature coefficient signal changes at the set temperature;

[0009] a comparison circuit configured to generate and output a first start / stop control signal of a first level and a second start / stop control signal of a second level that are inverse to each other according to a first comparison result of the first temperature coefficient signal and the second temperature coefficient signal when the current temperature is lower than the set temperature, so that the first temperature coefficient bias circuit is turned on under the control of the first start / stop control signal of the first level, and the second temperature coefficient bias circuit is turned off under the control of the second start / stop control signal of the second level;

[0010] In the case where the current temperature is higher than the set temperature, according to the second comparison result of the first temperature coefficient signal and the second temperature coefficient signal, a first start-stop control signal of a second level and a second start-stop control signal of a first level which are inverse to each other are generated and output, so that the first temperature coefficient bias circuit is turned off under the control of the first start-stop control signal of the second level, and the second temperature coefficient bias circuit is turned on under the control of the second start-stop control signal of the first level;

[0011] A first temperature coefficient bias circuit, configured to be turned on or off under the control of the first start / stop control signal, so as to turn on or off the generation and output of the first temperature coefficient bias signal;

[0012] The second temperature coefficient bias circuit is configured to be turned on or off under the control of the second start / stop control signal to turn on or off the generation and output of the second temperature coefficient bias signal.

[0013] In combination with the first aspect, in an optional implementation,

[0014] The first temperature coefficient signal generating circuit includes any one of the following: a negative temperature coefficient current source; a positive temperature coefficient current source; a zero temperature coefficient current source; a negative temperature coefficient voltage source; a positive temperature coefficient voltage source; a zero temperature coefficient voltage source;

[0015] The second temperature coefficient signal generating circuit includes any one of the following: a negative temperature coefficient current source; a positive temperature coefficient current source; a zero temperature coefficient current source; a negative temperature coefficient voltage source; a positive temperature coefficient voltage source; a zero temperature coefficient voltage source.

[0016] In combination with the first aspect, in an optional implementation,

[0017] The first temperature coefficient signal generating circuit includes a negative temperature coefficient current source configured to provide a negative temperature coefficient current;

[0018] The second temperature coefficient signal generating circuit includes a positive temperature coefficient current source configured to provide a positive temperature coefficient current;

[0019] The comparison circuit is configured to compare the negative temperature coefficient current and the positive temperature coefficient current so as to generate and output a first start-stop control signal of a first level and a second start-stop control signal of a second level that are inverted to each other when the current temperature is lower than the set temperature; and to generate and output a first start-stop control signal of a second level and a second start-stop control signal of a first level that are inverted to each other when the current temperature is higher than the set temperature.

[0020] In combination with the first aspect, in an optional implementation,

[0021] The comparison circuit comprises:

[0022] A first conversion circuit is configured to determine a first input voltage according to the negative temperature coefficient current;

[0023] A second conversion circuit is configured to determine a second input voltage according to the positive temperature coefficient current;

[0024] a two-stage operational amplifier comparator configured to compare the first input voltage and the second input voltage to obtain an output voltage of a first level when the current temperature is lower than the set temperature, and to obtain an output voltage of a second level when the current temperature is higher than the set temperature;

[0025] a first inverter configured to invert the output voltage to obtain a second start / stop control signal;

[0026] The second inverter is configured to invert the second start-stop control signal to obtain a first start-stop control signal.

[0027] In combination with the first aspect, in an optional implementation,

[0028] The comparison circuit includes a thirty-first resistor, a thirty-second resistor, a thirty-third resistor, a thirty-fourth resistor, a thirty-first NMOS tube, a thirty-second NMOS tube, a thirty-third PMOS tube, a thirty-fourth PMOS tube, a thirty-fifth NMOS tube, a thirty-sixth PMOS tube, a thirty-seventh NMOS tube, a first inverter and a second inverter;

[0029] The first end of the thirty-first resistor is configured to obtain a negative temperature coefficient current, and the first end of the thirty-third resistor is configured to obtain a positive temperature coefficient current; the second end of the thirty-first resistor is respectively connected to the first end of the thirty-second resistor and the gate of the thirty-first NMOS tube, and the second end of the thirty-third resistor is respectively connected to the first end of the thirty-fourth resistor and the gate of the thirty-second NMOS tube; the second end of the thirty-second resistor and the second end of the thirty-fourth resistor are respectively connected to the ground terminal;

[0030] The drain of the thirty-first NMOS tube is connected to the drain of the thirty-third PMOS tube, the gate of the thirty-third PMOS tube, and the gate of the thirty-fourth PMOS tube respectively; the drain of the thirty-second NMOS tube is connected to the drain of the thirty-fourth PMOS tube and the gate of the thirty-sixth PMOS tube respectively; the source of the thirty-third PMOS tube, the source of the thirty-fourth PMOS tube, and the source of the thirty-sixth PMOS tube are connected to the power supply terminal respectively;

[0031] The source of the thirty-first NMOS tube and the source of the thirty-second NMOS tube are respectively connected to the drain of the thirty-fifth NMOS tube; the gate of the thirty-fifth NMOS tube and the gate of the thirty-seventh NMOS tube are respectively configured to obtain the first low-bit bias signal; the source of the thirty-fifth NMOS tube and the source of the thirty-seventh NMOS tube are respectively connected to the ground terminal;

[0032] The drain of the thirty-seventh NMOS tube is respectively connected to the drain of the thirty-sixth PMOS tube and the input end of the first inverter, and is configured to provide an output voltage; the output end of the first inverter is connected to the input end of the second inverter, and is configured to provide a second start-stop control signal; the output end of the second inverter is configured to provide the first start-stop control signal.

[0033] In combination with the first aspect, in an optional implementation,

[0034] The negative temperature coefficient current source comprises a high current mirror module, a self-starting module, a low current mirror module, a negative temperature current generating module, and an output module respectively coupled to the high current mirror module and the self-starting module.

[0035] The output module is used to replicate and output a negative temperature coefficient current;

[0036] The control end of the self-starting module is coupled to the output end of the low-level current mirror module, so that during the power-on process of the negative temperature coefficient current source, the self-starting module is turned on under the control of the low voltage at the output end of the low-level current mirror module, so as to prompt the low-level current mirror module and the high-level current mirror module to be turned on, so that the negative temperature coefficient current source completes the startup and the negative temperature current generating module generates a first negative temperature current corresponding to the negative temperature coefficient current, so that the output module can copy and output the negative temperature coefficient current.

[0037] In combination with the first aspect, in an optional implementation,

[0038] The negative temperature coefficient current source includes an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, an eleventh resistor and an eleventh triode;

[0039] The source of the eleventh PMOS tube, the source of the twelfth PMOS tube, and the source of the fifteenth PMOS tube are respectively connected to the power supply terminal, the gate of the eleventh PMOS tube is respectively connected to the gate of the twelfth PMOS tube, the gate of the fifteenth PMOS tube, the drain of the sixteenth PMOS tube, and the drain of the thirteenth NMOS tube, the drain of the eleventh PMOS tube is connected to the source of the sixteenth PMOS tube, and the drain of the twelfth PMOS tube is connected to the source of the seventeenth PMOS tube;

[0040] The gate of the sixteenth PMOS tube is respectively connected to the source of the fourteenth NMOS tube and the emitter of the eleventh transistor; the gate of the seventeenth PMOS tube is respectively connected to the gate of the eighteenth PMOS tube, the source of the thirteenth NMOS tube and the first end of the eleventh resistor; the second end of the eleventh resistor, the collector of the eleventh transistor and the base of the eleventh transistor are respectively connected to the ground terminal;

[0041] The source of the eighteenth PMOS tube is connected to the drain of the fifteenth PMOS tube, and the drain of the eighteenth PMOS tube is configured to provide a negative temperature coefficient current.

[0042] In combination with the first aspect, in an optional implementation,

[0043] The positive temperature coefficient current source includes a twenty-first PMOS tube, a twenty-second PMOS tube, a twenty-third PMOS tube, a twenty-fourth PMOS tube, a twenty-fifth PMOS tube, a twenty-sixth PMOS tube, a twenty-seventh PMOS tube, a twenty-eighth PMOS tube, a first operational amplifier, a twenty-first resistor, a twenty-second resistor, a twenty-first triode, a twenty-second triode and a twenty-third triode;

[0044] The source of the twenty-first PMOS tube, the source of the twenty-second PMOS tube, the source of the twenty-third PMOS tube, and the source of the twenty-fourth PMOS tube are respectively connected to the power supply terminal; the gate of the twenty-first PMOS tube is respectively connected to the gate of the twenty-second PMOS tube, the gate of the twenty-third PMOS tube, the gate of the twenty-fourth PMOS tube and the output terminal of the first operational amplifier; the drain of the twenty-first PMOS tube is connected to the source of the twenty-fifth PMOS tube, the drain of the twenty-second PMOS tube is connected to the source of the twenty-sixth PMOS tube, the drain of the twenty-third PMOS tube is connected to the source of the twenty-seventh PMOS tube, and the drain of the twenty-fourth PMOS tube is connected to the source of the twenty-eighth PMOS tube; the gate of the twenty-fifth PMOS tube, the gate of the twenty-sixth PMOS tube, the gate of the twenty-seventh PMOS tube, and the gate of the twenty-eighth PMOS tube are respectively configured to obtain the first high-bit bias signal;

[0045] The drain of the twenty-fifth PMOS tube is respectively connected to the second input terminal of the first operational amplifier and the first terminal of the twenty-first resistor, and the second terminal of the twenty-first resistor is connected to the emitter of the twenty-first triode; the drain of the twenty-sixth PMOS tube is respectively connected to the first input terminal of the first operational amplifier and the emitter of the twenty-second triode; the drain of the twenty-seventh PMOS tube is connected to the first terminal of the twenty-second resistor, and the second terminal of the twenty-second resistor is connected to the emitter of the twenty-third triode; the base and collector of the twenty-first triode, the base and collector of the twenty-second triode, and the base and collector of the twenty-third triode are respectively connected to the ground terminal;

[0046] The drain of the twenty-eighth PMOS tube is configured to provide a positive temperature coefficient current.

[0047] In combination with the first aspect, in an optional implementation,

[0048] The first temperature coefficient bias circuit includes any one of the following:

[0049] a positive temperature coefficient bias circuit configured to provide a positive temperature coefficient bias current;

[0050] a zero temperature coefficient bias circuit configured to provide a zero temperature coefficient bias current;

[0051] a negative temperature coefficient bias circuit configured to provide a negative temperature coefficient bias current;

[0052] The second temperature coefficient bias circuit includes any one of the following:

[0053] a positive temperature coefficient bias circuit configured to provide a positive temperature coefficient bias current;

[0054] a zero temperature coefficient bias circuit configured to provide a zero temperature coefficient bias current;

[0055] A negative temperature coefficient bias circuit is configured to provide a negative temperature coefficient bias current.

[0056] In combination with the first aspect, in an optional implementation,

[0057] The first temperature coefficient bias circuit includes a positive temperature coefficient bias circuit;

[0058] The positive temperature coefficient bias circuit comprises:

[0059] a positive temperature current generating circuit configured to generate a positive temperature coefficient bias current based on a positive temperature bias voltage by utilizing a virtual short characteristic of an operational amplifier;

[0060] The first switch circuit is configured to be turned on or off under the control of the first start-stop control signal to turn on or off the generation and output of the positive temperature coefficient bias current.

[0061] In combination with the first aspect, in an optional implementation,

[0062] The positive temperature current generating circuit includes a third operational amplifier, a forty-first capacitor, a forty-first resistor, a forty-first PMOS tube, a forty-second PMOS tube, a forty-third PMOS tube, a forty-fourth PMOS tube, a forty-fifth NMOS tube, a forty-sixth NMOS tube, a forty-seventh PMOS tube and a forty-eighth PMOS tube;

[0063] The second input end of the third operational amplifier is configured to obtain a positive temperature bias voltage, the output end of the third operational amplifier is respectively connected to the first end of the 41st capacitor, the gate of the 401st PMOS tube, the gate of the 402nd PMOS tube and the gate of the 407th PMOS tube, and the first input end of the third operational amplifier is respectively connected to the second end of the 41st capacitor, the drain of the 403rd PMOS tube and the first end of the 41st resistor;

[0064] The source of the 401st PMOS tube, the source of the 402nd PMOS tube, the source of the 404th PMOS tube and the source of the 407th PMOS tube are respectively connected to the power supply terminal; the drain of the 401st PMOS tube is connected to the source of the 403rd PMOS tube; the gate of the 403rd PMOS tube is respectively connected to the gate of the 404th PMOS tube, the drain of the 404th PMOS tube, the drain of the 406th NMOS tube and the gate of the 408th PMOS tube; the drain of the 402nd PMOS tube is respectively connected to the drain of the 405th NMOS tube, the gate of the 405th NMOS tube and the gate of the 406th NMOS tube; the second end of the 41st resistor, the source of the 405th NMOS tube and the source of the 406th NMOS tube are respectively connected to the ground terminal;

[0065] The source of the 408th PMOS tube is connected to the drain of the 407th PMOS tube, and the drain of the 408th PMOS tube is configured to provide a positive temperature coefficient bias current;

[0066] The first switch circuit includes at least one of the following: a 409th NMOS transistor; a 410th PMOS transistor; a 411th PMOS transistor;

[0067] The gate of the 409th NMOS tube is configured to obtain the first low-level switch signal, the drain of the 409th NMOS tube is respectively connected to the gate of the 405th NMOS tube and the gate of the 406th NMOS tube, and the source of the 409th NMOS tube is connected to the ground terminal;

[0068] The gate of the 410th PMOS tube is configured to obtain the first high-level switch signal, the drain of the 410th PMOS tube is connected to the output end of the third operational amplifier, and the source of the 410th PMOS tube is connected to the power supply end;

[0069] The gate of the 411th PMOS tube is configured to obtain the first high-level switch signal, the drain of the 411th PMOS tube is respectively connected to the gate of the 403rd PMOS tube and the gate of the 404th PMOS tube, and the source of the 411th PMOS tube is connected to the power supply terminal.

[0070] In combination with the first aspect, in an optional implementation,

[0071] The first switch circuit further includes a forty-first inverter; or a forty-first inverter and a forty-second inverter;

[0072] The input end of the 41st inverter is configured to obtain the first start-stop control signal; the output end of the 41st inverter is connected to the input end of the 42nd inverter and is configured to provide a first high-level switch signal; the output end of the 42nd inverter is configured to provide a first low-level switch signal.

[0073] In combination with the first aspect, in an optional implementation,

[0074] The second temperature coefficient bias circuit includes a zero temperature coefficient bias circuit;

[0075] The zero temperature coefficient bias circuit comprises:

[0076] a zero-temperature current generating circuit configured to generate a zero-temperature coefficient bias current based on a zero-temperature bias voltage by utilizing a virtual short characteristic of an operational amplifier;

[0077] The second switch circuit is configured to be turned on or off under the control of the second start-stop control signal to turn on or off the generation and output of the zero temperature coefficient bias current.

[0078] In combination with the first aspect, in an optional implementation,

[0079] The zero-temperature current generating circuit includes a fourth operational amplifier, a fifty-first capacitor, a fifty-first resistor, a fifty-first PMOS transistor, a fifty-second PMOS transistor, a fifty-third PMOS transistor, a fifty-fourth PMOS transistor, a fifty-fifth NMOS transistor, a fifty-sixth NMOS transistor, a fifty-seventh PMOS transistor and a fifty-eighth PMOS transistor;

[0080] The second input end of the fourth operational amplifier is configured to obtain a zero-temperature bias voltage, the output end of the fourth operational amplifier is respectively connected to the first end of the fifty-first capacitor, the gate of the fifty-first PMOS tube, the gate of the fifty-second PMOS tube, and the gate of the fifty-seventh PMOS tube, and the first input end of the fourth operational amplifier is respectively connected to the second end of the fifty-first capacitor, the drain of the fifty-third PMOS tube, and the first end of the fifty-first resistor;

[0081] The source of the 501st PMOS tube, the source of the 502nd PMOS tube, the source of the 504th PMOS tube and the source of the 507th PMOS tube are respectively connected to the power supply terminal; the drain of the 501st PMOS tube is connected to the source of the 503rd PMOS tube; the gate of the 503rd PMOS tube is respectively connected to the gate of the 504th PMOS tube, the drain of the 504th PMOS tube, the drain of the 506th NMOS tube and the gate of the 508th PMOS tube; the drain of the 502nd PMOS tube is respectively connected to the drain of the 505th NMOS tube, the gate of the 505th NMOS tube and the gate of the 506th NMOS tube; the second end of the 51st resistor, the source of the 505th NMOS tube and the source of the 506th NMOS tube are respectively connected to the ground terminal;

[0082] The source of the 508th PMOS tube is connected to the drain of the 507th PMOS tube, and the drain of the 508th PMOS tube is configured to provide a zero temperature coefficient bias current;

[0083] The first switch circuit includes at least one of the following: a fifth 09th NMOS transistor; a fifth 10th PMOS transistor; a fifth 11th PMOS transistor;

[0084] The gate of the 509th NMOS tube is configured to obtain the second low-level switch signal, the drain of the 509th NMOS tube is respectively connected to the gate of the 505th NMOS tube and the gate of the 506th NMOS tube, and the source of the 509th NMOS tube is connected to the ground terminal;

[0085] The gate of the 510th PMOS tube is configured to obtain the second high-level switch signal, the drain of the 510th PMOS tube is connected to the output end of the fourth operational amplifier, and the source of the 510th PMOS tube is connected to the power supply end;

[0086] The gate of the 511th PMOS tube is configured to obtain the second high-level switch signal, the drain of the 511th PMOS tube is respectively connected to the gate of the 503rd PMOS tube and the gate of the 504th PMOS tube, and the source of the 511th PMOS tube is connected to the power supply terminal.

[0087] In combination with the first aspect, in an optional implementation,

[0088] The first switch circuit further includes a fifty-first inverter; or a fifty-first inverter and a fifty-second inverter;

[0089] The input end of the fifty-first inverter is configured to obtain the second start-stop control signal; the output end of the fifty-first inverter is connected to the input end of the fifty-second inverter and is configured to provide a second high-level switch signal; the output end of the fifty-second inverter is configured to provide a second low-level switch signal.

[0090] In combination with the first aspect, in an optional implementation,

[0091] The segmented temperature control circuit also includes a voltage mode bandgap reference circuit;

[0092] The voltage-mode bandgap reference circuit comprises a sixty-first PMOS tube, a sixty-second PMOS tube, a sixty-third PMOS tube, a sixty-fourth PMOS tube, a sixty-fifth PMOS tube, a sixty-sixth PMOS tube, a sixty-seventh PMOS tube, a sixty-eighth PMOS tube, a second operational amplifier, a sixty-first resistor, a sixty-second resistor, a sixty-third resistor, a sixty-first triode, a sixty-second triode, a sixty-third triode and a sixty-fourth triode;

[0093] The source of the sixty-first PMOS tube, the source of the sixty-second PMOS tube, the source of the sixty-third PMOS tube, and the source of the sixty-fourth PMOS tube are respectively connected to the power supply terminal; the gate of the sixty-first PMOS tube is respectively connected to the gate of the sixty-second PMOS tube, the gate of the sixty-third PMOS tube, the gate of the sixty-fourth PMOS tube, and the output terminal of the second operational amplifier; the drain of the sixty-first PMOS tube is connected to the source of the sixty-fifth PMOS tube, the drain of the sixty-second PMOS tube is connected to the source of the sixty-sixth PMOS tube, the drain of the sixty-third PMOS tube is connected to the source of the sixty-seventh PMOS tube, and the drain of the sixty-fourth PMOS tube is connected to the source of the sixty-eighth PMOS tube; the gate of the sixty-fifth PMOS tube, the gate of the sixty-sixth PMOS tube, the gate of the sixty-seventh PMOS tube, and the gate of the sixty-eighth PMOS tube are respectively configured to obtain the second high-bit bias signal;

[0094] The drain of the sixty-fifth PMOS tube is respectively connected to the second input terminal of the second operational amplifier and the first terminal of the sixty-first resistor, and the second terminal of the sixty-first resistor is connected to the emitter of the sixty-first transistor; the drain of the sixty-sixth PMOS tube is respectively connected to the first input terminal of the second operational amplifier and the emitter of the sixty-second transistor; the drain of the sixty-seventh PMOS tube is connected to the first terminal of the sixty-second resistor and is configured to provide a positive temperature bias voltage; the second terminal of the sixty-second resistor is connected to the emitter of the sixty-third transistor; the drain of the sixty-eighth PMOS tube is connected to the first terminal of the sixty-third resistor and is configured to provide a zero temperature bias voltage; the second terminal of the sixty-third resistor is connected to the emitter of the sixty-fourth transistor; the base and collector of the sixty-first transistor, the base and collector of the sixty-second transistor, the base and collector of the sixty-third transistor, and the base and collector of the sixty-fourth transistor are respectively connected to the ground terminal.

[0095] In a second aspect, an embodiment of the present application provides a radio frequency module, wherein the radio frequency module includes the segmented temperature control circuit and the radio frequency power amplifier as described in the first aspect;

[0096] The segmented temperature control circuit is configured to output a plurality of temperature coefficient bias signals corresponding to a plurality of temperature segments one by one, so as to control the input of the radio frequency power amplifier in segments.

[0097] Furthermore, the multiple temperature coefficient bias signals are bias currents.

[0098] The beneficial effects brought by the technical solution provided by the embodiment of the present application include: through the first temperature coefficient signal generating circuit and the second temperature coefficient signal generating circuit, the first temperature coefficient signal and the second temperature coefficient signal whose magnitude relationship changes at the set temperature are provided, so that the magnitude relationship of the first temperature coefficient signal and the second temperature coefficient signal can be compared to generate the first start-stop control signal and the second start-stop control signal which are mutually inverted, so as to control one of the first temperature coefficient bias circuit and the second temperature coefficient bias circuit to be turned on and the other to be turned off, that is, one of the first temperature coefficient bias circuit and the second temperature coefficient bias circuit can be selected to work. Furthermore, the segmented temperature control circuit can provide different temperature coefficient signals in different temperature segments, such as the first temperature coefficient bias signal and the second temperature coefficient bias signal, so that the segmented temperature control bias current output can be realized, and the requirements of the RF PA for different temperature coefficients of the bias current in different temperature segments can be met.

[0099] Additional aspects and advantages of the embodiments of the present application will be given in part in the description below and in part will become apparent from the description below or will be learned through the practice of the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0100] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0101] Figure 1 A schematic diagram of a principle block diagram of a specific example of a segmented temperature control circuit in an embodiment of the present application;

[0102] Figure 2 A schematic diagram of a specific example of the first curve and the second curve in the embodiment of the present application;

[0103] Figure 3 It is a schematic diagram of a principle block diagram of another specific example of a segmented temperature control circuit in an embodiment of the present application;

[0104] Figure 4 A circuit diagram of a specific example of a comparison circuit in an embodiment of the present application;

[0105] Figure 5 A circuit diagram of a specific example of a negative temperature coefficient current source in an embodiment of the present application;

[0106] Figure 6 A circuit diagram of a specific example of a positive temperature coefficient current source in an embodiment of the present application;

[0107] Figure 7 A circuit diagram of a specific example of a first temperature coefficient bias circuit in an embodiment of the present application;

[0108] Figure 8 A circuit diagram of a specific example of a second temperature coefficient bias circuit in an embodiment of the present application;

[0109] Fig. 9 A circuit diagram of a specific example of a voltage-mode bandgap reference circuit in an embodiment of the present application. DETAILED DESCRIPTION

[0110] In order to make the technical solutions and beneficial effects of the present application more obvious and easy to understand, the following is a detailed description by listing specific embodiments. The drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which the present application belongs.

[0111] The embodiments of the present application are not exhaustive, but are only illustrative of some embodiments, and are not intended to be a specific limitation on the scope of protection of the present application. In the absence of contradiction, each step in a certain embodiment can be implemented as an independent embodiment, and the steps can be arbitrarily combined. For example, in a certain embodiment, the solution after removing some steps can also be implemented as an independent embodiment, and the order of the steps in a certain embodiment can be arbitrarily exchanged. In addition, the optional implementations in a certain embodiment can be arbitrarily combined; in addition, the embodiments can be arbitrarily combined, for example, some or all of the steps of different embodiments can be arbitrarily combined, and a certain embodiment can be arbitrarily combined with the optional implementations of other embodiments.

[0112] In each embodiment of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between the embodiments are consistent and can be referenced to each other. The technical features in different embodiments can be combined to form a new embodiment based on their internal logical relationships.

[0113] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0114] In the embodiments of the present application, unless otherwise specified, elements expressed in the singular form, such as "a", "an", "the", "above", "said", "aforementioned", "this", etc., may mean "one and only one", or "one or more", "at least one", etc. For example, when using articles such as "a", "an", "the" in English in translation, the noun after the article may be understood as a singular expression or a plural expression.

[0115] In the embodiments of the present application, "plurality" refers to two or more.

[0116] In some embodiments, the terms "at least one", "one or more", "a plurality of", "multiple", etc. can be used interchangeably.

[0117] The prefixes such as "first" and "second" in the embodiments of the present application are only used to distinguish different description objects, and do not constitute restrictions on the position, order, priority, value or content of the description objects. The statement of the description object refers to the description in the context of the claims or embodiments, and should not constitute unnecessary restrictions due to the use of prefixes. For example, the numerical value of the description object is not limited by the ordinal number, and can be one or more. Take "first device" as an example, where the numerical value of "device" can be one or more. In addition, the objects modified by different prefixes can be the same or different. For example, if the description object is "device", the "first device" and the "second device" can be the same device or different devices, and their types can be the same or different.

[0118] In some embodiments, the term "connection" may indicate that an electrical signal or data is transmitted between a connected end and a connected end, and may be understood as "electrical connection", "communication connection", etc. "Connection" may be a direct connection between two components, an indirect connection established through other components, internal communication between two components, or any other possible connection form.

[0119] In some embodiments, terms such as "greater than", "greater than or equal to", "not less than", "more than", "more than or equal to", "not less than", "higher than", "higher than or equal to", "not less than", "above", and "exceed" can be replaced with each other, and terms such as "less than", "less than or equal to", "not greater than", "less than", "less than or equal to", "no more than", "lower than", "lower than or equal to", "not higher than", and "below" can be replaced with each other.

[0120] In some embodiments, high voltage and low voltage, or high voltage and low voltage, or high level and low level may be relative values ​​and are not limited to absolute values.

[0121] In some embodiments, the transistor may be a single transistor; or a plurality of transistors connected in series and / or in parallel, and have functional poles corresponding to the functional poles of a single transistor, and also have the same working state as the single transistor, such as an on state and an off state, etc. For example, a single transistor may include a MOSFET (metal oxide semiconductor field effect transistor, MOS for short), and its functional poles may include a gate G, a source S, a drain D, and a substrate B, then the plurality of transistors connected in series and / or in parallel have a gate G, a source S, a drain D, and a substrate B corresponding to the gate G, source S, drain D, and substrate B of a single MOS, and a working state corresponding to the single MOS. The MOS may include a P-type MOS (PMOS for short) and an N-type MOS (NMOS for short).

[0122] In some embodiments, the transistor may include a control terminal, a first signal terminal, and a second signal terminal, and its working principle is that under the control of a control signal input to the control terminal, the path between the first signal terminal and the second signal terminal is turned on or off to connect or block the signal transmission between the first signal terminal and the second signal terminal. In an exemplary embodiment, the transistor may include at least one of the following: PMOS tube; NMOS tube; BJT (triode); IGBT (insulated gate bipolar transistor); GTO (gate turn-off thyristor); SCR (silicon controlled thyristor); MCT (MOS controlled thyristor); IGCT (integrated gate commutated thyristor); IEGT (electron injection enhanced gate transistor); and the like.

[0123] The embodiment of the present application provides a segmented temperature control circuit, which can be used as a bias current providing circuit for segmented temperature control of a radio frequency PA, and provides the radio frequency PA with bias currents of different magnitudes at different temperature segments. Figure 1 A schematic diagram of a principle block diagram of a specific example of a segmented temperature control circuit in an embodiment of the present application is shown. Figure 2 A schematic diagram showing a specific example of the first curve and the second curve in the embodiment of the present application.

[0124] refer to Figure 1 and Figure 2 , the segmented temperature control circuit 1000 includes:

[0125] The first temperature coefficient signal generating circuit 100 is configured to provide a first temperature coefficient signal Sig1;

[0126] The second temperature coefficient signal generating circuit 200 is configured to provide a second temperature coefficient signal Sig2; a first curve of the value of the first temperature coefficient signal Sig1 changing with temperature and a second curve of the value of the second temperature coefficient signal Sig2 changing with temperature have at least one intersection S12 at a set temperature Ta, so that the magnitude relationship between the value of the first temperature coefficient signal Sig1 and the value of the second temperature coefficient signal Sig2 changes at the set temperature Ta;

[0127] The comparison circuit 300 is configured to generate and output a first start / stop control signal outa of a first level and a second start / stop control signal outb of a second level that are inverse to each other according to a first comparison result of the first temperature coefficient signal Sig1 and the second temperature coefficient signal Sig2 when the current temperature is lower than the set temperature Ta, so that the first temperature coefficient bias circuit 400 is turned on under the control of the first start / stop control signal outa of the first level, and the second temperature coefficient bias circuit 500 is turned off under the control of the second start / stop control signal outb of the second level;

[0128] In the case where the current temperature is higher than the set temperature Ta, a first start / stop control signal outa of a second level and a second start / stop control signal outb of a first level which are inverse to each other are generated and output according to a second comparison result of the first temperature coefficient signal Sig1 and the second temperature coefficient signal Sig2, so that the first temperature coefficient bias circuit 400 is turned off under the control of the first start / stop control signal outa of the second level, and the second temperature coefficient bias circuit 500 is turned on under the control of the second start / stop control signal outb of the first level;

[0129] The first temperature coefficient bias circuit 400 is configured to be turned on or off under the control of the first start-stop control signal outa, so as to turn on or off the generation and output of the first temperature coefficient bias signal out1;

[0130] The second temperature coefficient bias circuit 500 is configured to be turned on or off under the control of the second start / stop control signal outb, so as to turn on or off the generation and output of the second temperature coefficient bias signal out2.

[0131] In the embodiment of the present application, the signal may be a current signal or a voltage signal; accordingly, the value of the signal may be a current value or a voltage value.

[0132] The temperature coefficient of a signal can be understood as the value of the signal can change with changes in temperature. For example, a negative temperature coefficient can indicate that the value of the signal decreases with increasing temperature, a positive temperature coefficient can indicate that the value of the signal increases with increasing temperature, and a zero temperature coefficient can indicate that the value of the signal does not change with increasing or decreasing temperature, that is, it remains unchanged.

[0133] In an optional implementation, the first temperature coefficient signal Sig1 may include any one of the following: a positive temperature coefficient signal; a negative temperature coefficient signal; or a zero temperature coefficient signal.

[0134] The second temperature coefficient signal Sig2 may include any one of the following: a positive temperature coefficient signal; a negative temperature coefficient signal; or a zero temperature coefficient signal.

[0135] Among them, reference Figure 2 , the first curve of the value of the first temperature coefficient signal Sig1 changing with temperature and the second curve of the value of the second temperature coefficient signal Sig2 changing with temperature can intersect at the set temperature Ta (i.e., a certain temperature), that is, at a certain temperature, the current value Is or the voltage value Vs of the first temperature coefficient signal Sig1 and the second temperature coefficient signal Sig2 are equal. It should be understood that the first curve and the second curve are not limited to Figure 2 The straight line shown in can also be an isoarc line in a parabola or hyperbola.

[0136] Then, in an example, the first temperature coefficient signal Sig1 may be a negative temperature coefficient signal, and the second temperature coefficient signal Sig2 may be a positive temperature coefficient signal or a zero temperature coefficient signal.

[0137] In other examples, the first temperature coefficient signal Sig1 may be a zero temperature coefficient signal, and the second temperature coefficient signal Sig2 may be a negative temperature coefficient signal or a positive temperature coefficient signal.

[0138] In an exemplary embodiment, the magnitude relationship between the value of the first temperature coefficient signal Sig1 and the value of the second temperature coefficient signal Sig2 changes at the set temperature Ta, which may be that when the current temperature is lower than the set temperature Ta, the current value or voltage value of the first temperature coefficient signal Sig1 is higher than the current value or voltage value of the second temperature coefficient signal Sig2; when the current temperature is higher than the set temperature Ta, the current value or voltage value of the first temperature coefficient signal Sig1 is lower than the current value or voltage value of the second temperature coefficient signal Sig2, so that the magnitude relationship between the two changes from the former being higher than the latter to the former being lower than the latter. However, this is not limited to this, and a change opposite to the above change may also occur, that is, a change from the former being lower than the latter to the former being higher than the latter.

[0139] In the embodiment of the present application, the first temperature coefficient signal Sig1 and the second temperature coefficient signal Sig2 can be current signals, i.e., the first temperature coefficient current I1 and the second temperature coefficient current I2, respectively; or they can also be voltage signals, i.e., the first temperature coefficient voltage V1 and the second temperature coefficient voltage V2, respectively. If it is a current signal, the current signal can be converted into a voltage signal first and then provided to the input end of the comparison circuit for comparison. If it is a voltage signal, it can be directly provided to the input end of the comparison circuit for comparison.

[0140] The comparison circuit 300 can compare the values ​​of the first temperature coefficient signal Sig1 and the second temperature coefficient signal Sig2. The first levels of the obtained first start-stop control signal outa and the second start-stop control signal outb can be low or high, and correspondingly, the second levels can be high or low.

[0141] In an exemplary embodiment, when the current temperature is lower than the set temperature Ta and the value of the first temperature coefficient signal Sig1 is higher than the value of the second temperature coefficient signal Sig2, a comparison produces a first comparison result of a low level, and then a low-level first start-stop control signal outa and a high-level second start-stop control signal outb are obtained through two stages of inversion.

[0142] When the current temperature is higher than the set temperature Ta and the value of the first temperature coefficient signal Sig1 is lower than the value of the second temperature coefficient signal Sig2, the comparison produces a high-level second comparison result, and then after two levels of inversion, a high-level first start-stop control signal outa and a low-level second start-stop control signal outb are obtained.

[0143] In this way, the embodiment of the present application provides a first temperature coefficient signal and a second temperature coefficient signal whose magnitude relationship changes at a set temperature through a first temperature coefficient signal generating circuit and a second temperature coefficient signal generating circuit, so that the magnitude relationship of the first temperature coefficient signal and the second temperature coefficient signal can be compared to generate a first start-stop control signal and a second start-stop control signal that are mutually inverted, so as to control one of the first temperature coefficient bias circuit and the second temperature coefficient bias circuit to be turned on and the other to be turned off, that is, one of the first temperature coefficient bias circuit and the second temperature coefficient bias circuit can be selected to work. Furthermore, the segmented temperature control circuit can provide different temperature coefficient signals, such as the first temperature coefficient bias signal and the second temperature coefficient bias signal, in different temperature segments, so that segmented temperature control bias current output can be achieved, and the requirements of the RF PA for different temperature coefficients of the bias current in different temperature segments can be met.

[0144] In an exemplary embodiment, the segmented temperature control circuit 1000 may also include other temperature coefficient signal generating circuits to provide a total of 2, 3, 4, etc., temperature coefficient signals, and the magnitude relationship between two temperature coefficient signals may change at a certain temperature. Then, multiple temperature segmentation intervals may be obtained based on multiple temperature points.

[0145] Furthermore, the segmented temperature control circuit 1000 may further include other temperature coefficient bias circuits, so as to provide a total of 2, 3, 4 or other temperature coefficient bias signals corresponding to the multiple temperature segmentation intervals.

[0146] Then, using multiple temperature coefficient signals, a set of start-stop control signals that can control the opening or closing of multiple temperature coefficient bias circuits can be generated after comparison by a comparison circuit. One of the multiple temperature coefficient bias circuits can be selected to be turned on, and the others can be turned off, so that more bias signals with different temperature coefficients in different temperature ranges can be obtained. The comparison circuit can include one or more comparators to achieve comparison of multiple groups of signals, which can be set according to actual needs.

[0147] In an optional implementation, the first temperature coefficient signal generating circuit 100 includes any one of the following: a negative temperature coefficient current source; a positive temperature coefficient current source; a zero temperature coefficient current source; a negative temperature coefficient voltage source; a positive temperature coefficient voltage source; a zero temperature coefficient voltage source;

[0148] The second temperature coefficient signal generating circuit 200 includes any one of the following: a negative temperature coefficient current source; a positive temperature coefficient current source; a zero temperature coefficient current source; a negative temperature coefficient voltage source; a positive temperature coefficient voltage source; or a zero temperature coefficient voltage source.

[0149] In the embodiments of the present application, both the current source and the voltage source can be set according to actual needs.

[0150] Figure 3 A schematic diagram of a principle block diagram of another specific example of a segmented temperature control circuit in an embodiment of the present application is shown. As shown in the figure, the first temperature coefficient signal generating circuit 100 includes a negative temperature coefficient current source, configured to provide a negative temperature coefficient current I1;

[0151] The second temperature coefficient signal generating circuit 200 includes a positive temperature coefficient current source configured to provide a positive temperature coefficient current I2;

[0152] The comparison circuit 300 is configured to compare the negative temperature coefficient current I1 and the positive temperature coefficient current I2 to generate and output a first start-stop control signal outa of a first level and a second start-stop control signal outb of a second level that are inverted to each other when the current temperature is lower than the set temperature Ta; and to generate and output a first start-stop control signal outa of a second level and a second start-stop control signal outb of a first level that are inverted to each other when the current temperature is higher than the set temperature Ta.

[0153] Figure 4 A circuit diagram of a specific example of a comparison circuit in an embodiment of the present application is shown. As shown in the figure, in an optional implementation, the comparison circuit 300 includes:

[0154] The first conversion circuit 301 is configured to determine a first input voltage Vn according to the negative temperature coefficient current I1;

[0155] The second conversion circuit 302 is configured to determine a second input voltage Vp according to the positive temperature coefficient current I2;

[0156] a two-stage operational amplifier comparator configured to compare the first input voltage Vn and the second input voltage Vp to obtain an output voltage Vout of a first level when the current temperature is lower than the set temperature Ta, and to obtain an output voltage Vout of a second level when the current temperature is higher than the set temperature Ta;

[0157] A first inverter U31 is configured to invert the output voltage Vout to obtain a second start / stop control signal outb;

[0158] The second inverter U32 is configured to invert the second start-stop control signal outb to obtain a first start-stop control signal outa.

[0159] The comparison circuit of the embodiment of the present application adopts a two-stage operational amplifier comparator, the first input terminal of the comparator is connected to a negative temperature coefficient current source, and the second input terminal of the comparator is connected to a positive temperature coefficient current source.

[0160] Then, when the current temperature is lower than the set temperature Ta, the negative temperature coefficient current I1 is higher than the positive temperature coefficient current I2, the first input voltage Vn is higher than the second input voltage Vp, and the output voltage Vout is at a low level, so that the first start-stop control signal outa is at a low level, and the second start-stop control signal outb is at a high level. Therefore, the first temperature coefficient bias circuit 400 (such as a positive temperature coefficient bias circuit) can be turned on to provide a current bias for the PA, and the second temperature coefficient bias circuit 500 (such as a zero temperature coefficient bias circuit) can be turned off.

[0161] When the current temperature is higher than the set temperature Ta, the negative temperature coefficient current I1 is lower than the positive temperature coefficient current I2, and the first input voltage Vn is lower than the second input voltage Vp. At this time, the output voltage Vout is at a high level, so that the first start-stop control signal outa is at a high level, and the second start-stop control signal outb is at a low level. Therefore, the second temperature coefficient bias circuit 500 (such as a zero temperature coefficient bias circuit) can be turned on to provide a current bias for the PA, and the first temperature coefficient bias circuit 400 (such as a positive temperature coefficient bias circuit) is turned off.

[0162] refer to Figure 4 In an optional implementation manner, the comparison circuit 300 includes a thirty-first resistor R31, a thirty-second resistor R32, a thirty-third resistor R33, a thirty-fourth resistor R34, a thirty-first NMOS tube M31, a thirty-second NMOS tube M32, a thirty-third PMOS tube M33, a thirty-fourth PMOS tube M34, a thirty-fifth NMOS tube M35, a thirty-sixth PMOS tube M36, a thirty-seventh NMOS tube M37, a first inverter U31 and a second inverter U32;

[0163] The first end of the thirty-first resistor R31 is configured to obtain a negative temperature coefficient current I1, and the first end of the thirty-third resistor R33 is configured to obtain a positive temperature coefficient current I2; the second end of the thirty-first resistor R31 is respectively connected to the first end of the thirty-second resistor R32 and the gate of the thirty-first NMOS transistor M31, and the second end of the thirty-third resistor R33 is respectively connected to the first end of the thirty-fourth resistor R34 and the gate of the thirty-second NMOS transistor M32; the second end of the thirty-second resistor R32 and the second end of the thirty-fourth resistor R34 are respectively connected to the ground terminal Gnd;

[0164] The drain of the thirty-first NMOS tube M31 is respectively connected to the drain of the thirty-third PMOS tube M33, the gate of the thirty-third PMOS tube M33, and the gate of the thirty-fourth PMOS tube M34; the drain of the thirty-second NMOS tube M32 is respectively connected to the drain of the thirty-fourth PMOS tube M34 and the gate of the thirty-sixth PMOS tube M36; the source of the thirty-third PMOS tube M33, the source of the thirty-fourth PMOS tube M34, and the source of the thirty-sixth PMOS tube M36 are respectively connected to the power supply terminal Vdd;

[0165] The source of the thirty-first NMOS tube M31 and the source of the thirty-second NMOS tube M32 are respectively connected to the drain of the thirty-fifth NMOS tube M35; the gate of the thirty-fifth NMOS tube M35 and the gate of the thirty-seventh NMOS tube M37 are respectively configured to obtain the first low-bit bias signal vbn1; the source of the thirty-fifth NMOS tube M35 and the source of the thirty-seventh NMOS tube M37 are respectively connected to the ground terminal Gnd;

[0166] The drain of the thirty-seventh NMOS tube M37 is respectively connected to the drain of the thirty-sixth PMOS tube M36 and the input end of the first inverter U31, and is configured to provide an output voltage Vout; the output end of the first inverter U31 is connected to the input end of the second inverter U32, and is configured to provide a second start-stop control signal outb; the output end of the second inverter U32 is configured to provide a first start-stop control signal outa.

[0167] In the embodiment of the present application, the thirty-first resistor R31 and the thirty-second resistor R32 may constitute the first conversion circuit 301. The thirty-fourth resistor R34 and the thirty-first NMOS transistor M31 may constitute the second conversion circuit 302. The thirty-first NMOS transistor M31 and the thirty-second NMOS transistor M32 are input pairs of transistors of the two-stage operational amplifier comparator.

[0168] Figure 5 A circuit diagram of a specific example of a negative temperature coefficient current source in an embodiment of the present application is shown. As shown in the figure, the negative temperature coefficient current source includes a high-level current mirror module 101, a self-starting module 102, a low-level current mirror module 103, a negative temperature current generating module 104, and an output module 105 respectively coupled to the high-level current mirror module 101 and the self-starting module 102, which are sequentially coupled between the power supply terminal Vdd and the ground terminal Gnd;

[0169] The output module 105 is used to replicate and output the negative temperature coefficient current I1;

[0170] The control end of the self-starting module 102 is coupled to the output end of the low-level current mirror module 103, so that during the power-on process of the negative temperature coefficient current source, the self-starting module 102 is turned on under the control of the low voltage at the output end of the low-level current mirror module 103, so as to prompt the low-level current mirror module 103 and the high-level current mirror module 101 to be turned on, so that the negative temperature coefficient current source completes the startup and the negative temperature current generating module 104 generates a first negative temperature current corresponding to the negative temperature coefficient current I1, so that the output module 105 can copy and output the negative temperature coefficient current I1.

[0171] In the embodiment of the present application, the high-level current mirror module 101 and the low-level current mirror module 103 may adopt a current mirror structure.

[0172] Then, at least two current branches from the power supply end to the ground end can be formed through the high-level current mirror module 101, the self-starting module 102, the low-level current mirror module 103 and the negative temperature current generating module 104 to generate a first negative temperature current corresponding to the negative temperature coefficient current I1. After the circuit is powered on, the self-starting module 102 is controlled to turn on, reducing the total impedance from the power supply end to the ground end, forming a small leakage current that can charge the node below the self-starting module 102, thereby prompting other modules to turn on so that the entire circuit is fully started.

[0173] Among them, the first current branch may be provided with at least the first output end of the high-order current mirror module 101, the first input end and the first output end of the self-starting module 102, the first input end and the first output end of the low-order current mirror module 103, and the first input end of the negative temperature current generating module 104. The second current branch may be provided with at least the second output end of the high-order current mirror module 101, the second input end and the second output end of the self-starting module 102, the second input end and the second output end of the low-order current mirror module 103, and the second input end of the negative temperature current generating module 104.

[0174] In the embodiment of the present application, the output module 105 can copy the first negative temperature current at a preset ratio through a current mirror structure to obtain a negative temperature coefficient current I1 and output it.

[0175] In this way, the embodiment of the present application includes a high-level current mirror module, a self-starting module, a low-level current mirror module, a negative temperature coefficient generating module and an output module through a self-starting negative temperature coefficient current source, and the control end of the self-starting module is coupled to the output end of the low-level current mirror module. After the circuit is powered on, the self-starting module can be controlled to start, thereby reducing the total impedance from the power supply end to the ground end, forming a small leakage current and prompting other modules such as the high-level current mirror module and the low-level current mirror module to start, thereby forming a self-starting negative temperature coefficient current source, without an external starting circuit, and without a zero merging point, which greatly reduces the chip area, can realize a very small miniaturized chip, and reduces power consumption.

[0176] refer to Figure 5 In an optional implementation manner, the negative temperature coefficient current source includes an eleventh PMOS tube M11, a twelfth PMOS tube M12, a thirteenth NMOS tube M13, a fourteenth NMOS tube M14, a fifteenth PMOS tube M15, a sixteenth PMOS tube M16, a seventeenth PMOS tube M17, an eighteenth PMOS tube M18, an eleventh resistor R11 and an eleventh transistor Q11;

[0177] The source of the eleventh PMOS tube M11, the source of the twelfth PMOS tube M12, and the source of the fifteenth PMOS tube M15 are respectively connected to the power supply terminal Vdd, the gate of the eleventh PMOS tube M11 is respectively connected to the gate of the twelfth PMOS tube M12, the gate of the fifteenth PMOS tube M15, the drain of the sixteenth PMOS tube M16, and the drain of the thirteenth NMOS tube M13, the drain of the eleventh PMOS tube M11 is connected to the source of the sixteenth PMOS tube M16, and the drain of the twelfth PMOS tube M12 is connected to the source of the seventeenth PMOS tube M17;

[0178] The gate of the sixteenth PMOS tube M16 is respectively connected to the source of the fourteenth NMOS tube M14 and the emitter of the eleventh transistor Q11; the gate of the seventeenth PMOS tube M17 is respectively connected to the gate of the eighteenth PMOS tube M18, the source of the thirteenth NMOS tube M13 and the first end of the eleventh resistor R11; the second end of the eleventh resistor R11, the collector of the eleventh transistor Q11 and the base of the eleventh transistor Q11 are respectively connected to the ground terminal Gnd;

[0179] The source of the eighteenth PMOS tube M18 is connected to the drain of the fifteenth PMOS tube M15 , and the drain of the eighteenth PMOS tube M18 is configured to provide a negative temperature coefficient current I1 .

[0180] In this way, the embodiment of the present application forms a cross-coupling structure by connecting the gate of M16 to the second output terminal of the low-level current mirror module 103, and connecting the gate of M17 to the first output terminal of the low-level current mirror module 103, thereby improving the anti-interference capability and circuit stability. The negative temperature coefficient current source is a negative temperature coefficient current source generating circuit with an internal startup circuit, and does not require an external startup circuit to get rid of the zero merging point, so it does not cause a part of the area and power consumption waste.

[0181] In the embodiment of the present application, the eleventh PMOS tube M11 and the twelfth PMOS tube M12 can constitute a high-level current mirror module 101. The sixteenth PMOS tube M16 and the seventeenth PMOS tube M17 can constitute a self-starting module 102. The thirteenth NMOS tube M13 and the fourteenth NMOS tube M14 can constitute a low-level current mirror module 103. The eleventh resistor R11 and the eleventh transistor Q11 can constitute a negative temperature current generating module 104. In this way, two current branches for generating the first negative temperature current are formed, which improves the stability of the first negative temperature current. And through the conduction of the thirteenth NMOS tube M13 and the fourteenth NMOS tube M14 during the power-on process of the negative temperature coefficient current source, the total impedance from the power supply end to the ground end is further reduced, thereby accelerating the startup speed of the entire circuit. The fifteenth PMOS tube M15 and the eighteenth PMOS tube M18 can constitute an output module 105.

[0182] The eleventh resistor R11 can be a single resistor, or a plurality of resistors connected in series and / or in parallel, or a passive resistor network or an active resistor network including resistors, capacitors, inductors, etc. The eleventh transistor Q11 can be a PNP transistor, which can provide a PN junction for the branch that can be normally opened (or turned on) when the circuit is operating normally. The emitter of Q11 is configured to provide the first negative temperature current, and the collector and base of Q11 are grounded. When the circuit is operating normally, the PN junction between the emitter and the base of Q11 is normally turned on, thereby providing an emitter junction forward voltage drop Veb that decreases with the increase of the ambient temperature, generating a first negative temperature current, so that the current source can generate and output the desired negative temperature coefficient current I1.

[0183] If the sizes of M11, M12, and M15 are the same, and the sizes of M16, M17, and M18 are the same, then the negative temperature coefficient current I1 = Veb 11 / R 11 ;Veb 11 is the voltage difference between the emitter E and base B of Q11, R 11 is the resistance value of the eleventh resistor R11.

[0184] Figure 6 A circuit diagram of a specific example of a positive temperature coefficient current source in an embodiment of the present application is shown. As shown in the figure, in an optional implementation, the positive temperature coefficient current source includes a twenty-first PMOS tube M21, a twenty-second PMOS tube M22, a twenty-third PMOS tube M23, a twenty-fourth PMOS tube M24, a twenty-fifth PMOS tube M25, a twenty-sixth PMOS tube M26, a twenty-seventh PMOS tube M27, a twenty-eighth PMOS tube M28, a first operational amplifier OP1, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-first transistor Q21, a twenty-second transistor Q22, and a twenty-third transistor Q23;

[0185] The source of the twenty-first PMOS tube M21, the source of the twenty-second PMOS tube M22, the source of the twenty-third PMOS tube M23, and the source of the twenty-fourth PMOS tube M24 are respectively connected to the power supply terminal Vdd; the gate of the twenty-first PMOS tube M21 is respectively connected to the gate of the twenty-second PMOS tube M22, the gate of the twenty-third PMOS tube M23, the gate of the twenty-fourth PMOS tube M24 and the output end of the first operational amplifier OP1; the drain of the twenty-first PMOS tube M21 and the source of the twenty-fifth PMOS tube M25 are respectively connected to the gate of the twenty-second PMOS tube M22, the gate of the twenty-third PMOS tube M23, the gate of the twenty-fourth PMOS tube M24 and the output end of the first operational amplifier OP1. The drain of the twenty-second PMOS tube M22 is connected to the source of the twenty-sixth PMOS tube M26, the drain of the twenty-third PMOS tube M23 is connected to the source of the twenty-seventh PMOS tube M27, and the drain of the twenty-fourth PMOS tube M24 is connected to the source of the twenty-eighth PMOS tube M28; the gate of the twenty-fifth PMOS tube M25, the gate of the twenty-sixth PMOS tube M26, the gate of the twenty-seventh PMOS tube M27, and the gate of the twenty-eighth PMOS tube M28 are respectively configured to obtain the first high-bit bias signal vbp1;

[0186] The drain of the twenty-fifth PMOS tube M25 is respectively connected to the second input terminal of the first operational amplifier OP1 and the first terminal of the twenty-first resistor R21, and the second terminal of the twenty-first resistor R21 is connected to the emitter of the twenty-first transistor Q21; the drain of the twenty-sixth PMOS tube M26 is respectively connected to the first input terminal of the first operational amplifier OP1 and the emitter of the twenty-second transistor Q22; the drain of the twenty-seventh PMOS tube M27 is connected to the first terminal of the twenty-second resistor R22, and the second terminal of the twenty-second resistor R22 is connected to the emitter of the twenty-third transistor Q23; the base and collector of the twenty-first transistor Q21, the base and collector of the twenty-second transistor Q22, and the base and collector of the twenty-third transistor Q23 are respectively connected to the ground terminal Gnd;

[0187] The drain of the twenty-eighth PMOS tube M28 is configured to provide a positive temperature coefficient current I2.

[0188] In the embodiment of the present application, the first operational amplifier OP1 can be set according to actual needs, and the present application does not limit it. The first input terminal of the first operational amplifier OP1 can be a negative input terminal, and the second input terminal can be a positive input terminal. The twenty-first transistor Q21, the twenty-second transistor Q22, and the twenty-third transistor Q23 can be PNP transistors. The positive temperature coefficient current source is a current source that uses ΔVbe to generate a positive temperature coefficient current on R21. And through the twenty-first PMOS tube M21, the twenty-second PMOS tube M22, the twenty-third PMOS tube M23, and the twenty-fourth PMOS tube M24, respectively with the twenty-fifth PMOS tube M25, the twenty-sixth PMOS tube M26, the twenty-seventh PMOS tube M27, and the twenty-eighth PMOS tube M28 form a cascode (common source and common gate) structure, which has the advantages of the cascode structure.

[0189] In an optional implementation, the first temperature coefficient bias circuit 400 includes any one of the following:

[0190] a positive temperature coefficient bias circuit configured to provide a positive temperature coefficient bias current;

[0191] a zero temperature coefficient bias circuit configured to provide a zero temperature coefficient bias current;

[0192] a negative temperature coefficient bias circuit configured to provide a negative temperature coefficient bias current;

[0193] The second temperature coefficient bias circuit 500 includes any one of the following:

[0194] a positive temperature coefficient bias circuit configured to provide a positive temperature coefficient bias current;

[0195] a zero temperature coefficient bias circuit configured to provide a zero temperature coefficient bias current;

[0196] A negative temperature coefficient bias circuit is configured to provide a negative temperature coefficient bias current.

[0197] In one example, the first temperature coefficient bias circuit 400 may be a positive temperature coefficient bias circuit, and the second temperature coefficient bias circuit 500 may be a zero temperature coefficient bias circuit. Then, in different temperature ranges, bias currents with different temperature coefficients of a positive temperature coefficient bias current and a zero temperature coefficient bias current can be provided.

[0198] In other examples, the first temperature coefficient bias circuit 400 may be a positive temperature coefficient bias circuit, and the second temperature coefficient bias circuit 500 may also be a positive temperature coefficient bias circuit. The two positive temperature coefficient bias circuits may provide bias currents with different temperature coefficients in different temperature ranges, that is, the current change rates with temperature are different. Alternatively, the first temperature coefficient bias circuit 400 and the second temperature coefficient bias circuit 500 may also be other temperature coefficient bias circuit combinations, which are not enumerated here.

[0199] Figure 7 A circuit diagram of a specific example of the first temperature coefficient bias circuit in the embodiment of the present application is shown. As shown in the figure, in an optional implementation, the first temperature coefficient bias circuit 400 includes a positive temperature coefficient bias circuit;

[0200] The positive temperature coefficient bias circuit comprises:

[0201] The positive temperature current generating circuit 401 is configured to utilize the virtual short characteristic of the operational amplifier to generate a positive temperature coefficient bias current Iout1 based on the positive temperature bias voltage vpos;

[0202] The first switch circuit 402 is configured to be turned on or off under the control of the first start / stop control signal outa, so as to turn on or off the generation and output of the positive temperature coefficient bias current Iout1.

[0203] In the embodiment of the present application, the positive temperature current generating circuit 401 and the first switch circuit 402 can be configured according to actual needs and are not limited to Figure 7 The specific circuit structure shown in .

[0204] refer to Figure 7 In an optional implementation manner, the positive temperature current generating circuit 401 includes a third operational amplifier OP3, a forty-first capacitor C41, a forty-first resistor R41, a forty-first PMOS tube M401, a forty-second PMOS tube M402, a forty-third PMOS tube M403, a forty-fourth PMOS tube M404, a forty-fifth NMOS tube M405, a forty-sixth NMOS tube M406, a forty-seventh PMOS tube M407 and a forty-eighth PMOS tube M408;

[0205] The second input terminal of the third operational amplifier OP3 is configured to obtain the positive temperature bias voltage vpos, the output terminal of the third operational amplifier OP3 is respectively connected to the first terminal of the forty-first capacitor C41, the gate of the forty-first PMOS tube M401, the gate of the forty-second PMOS tube M402 and the gate of the forty-seventh PMOS tube M407, and the first input terminal of the third operational amplifier OP3 is respectively connected to the second terminal of the forty-first capacitor C41, the drain of the forty-third PMOS tube M403 and the first terminal of the forty-first resistor R41;

[0206] The source of the 401st PMOS tube M401, the source of the 402nd PMOS tube M402, the source of the 404th PMOS tube M404 and the source of the 407th PMOS tube M407 are respectively connected to the power supply terminal Vdd; the drain of the 401st PMOS tube M401 is connected to the source of the 403rd PMOS tube M403; the gate of the 403rd PMOS tube M403 is respectively connected to the gate of the 404th PMOS tube M404, the drain of the 404th PMOS tube M404 , the drain of the 406th NMOS tube M406 and the gate of the 408th PMOS tube M408; the drain of the 402nd PMOS tube M402 is respectively connected to the drain of the 405th NMOS tube M405, the gate of the 405th NMOS tube M405 and the gate of the 406th NMOS tube M406; the second end of the 41st resistor R41, the source of the 405th NMOS tube M405 and the source of the 406th NMOS tube M406 are respectively connected to the ground terminal Gnd;

[0207] The source of the 408th PMOS tube M408 is connected to the drain of the 407th PMOS tube M407, and the drain of the 408th PMOS tube M408 is configured to provide a positive temperature coefficient bias current Iout1;

[0208] The first switch circuit 402 includes at least one of the following: a 409th NMOS transistor M409; a 410th PMOS transistor M410; a 411th PMOS transistor M411;

[0209] The gate of the 409th NMOS tube M409 is configured to obtain the first low-bit switch signal pda1, the drain of the 409th NMOS tube M409 is respectively connected to the gate of the 405th NMOS tube M405 and the gate of the 406th NMOS tube M406, and the source of the 409th NMOS tube M409 is connected to the ground terminal Gnd;

[0210] The gate of the 410th PMOS tube M410 is configured to obtain the first high-level switch signal pdb1, the drain of the 410th PMOS tube M410 is connected to the output end of the third operational amplifier OP3, and the source of the 410th PMOS tube M410 is connected to the power supply end Vdd;

[0211] The gate of the fourth PMOS tube M411 is configured to obtain the first high-level switch signal pdb1, the drain of the fourth PMOS tube M411 is respectively connected to the gate of the fourth-third PMOS tube M403 and the gate of the fourth-fourth PMOS tube M404, and the source of the fourth PMOS tube M411 is connected to the power supply terminal Vdd.

[0212] In an optional implementation, the first switch circuit 402 further includes a forty-first inverter U41; or a forty-first inverter U41 and a forty-second inverter U42;

[0213] The input end of the 41st inverter U41 is configured to obtain the first start-stop control signal outa; the output end of the 41st inverter U41 is connected to the input end of the 42nd inverter U42 and configured to provide a first high-level switch signal pdb1; the output end of the 42nd inverter U42 is configured to provide a first low-level switch signal pda1.

[0214] In the embodiment of the present application, the first input terminal of the third operational amplifier OP3 may be a negative input terminal, and the second input terminal may be a positive input terminal. The bias voltage of the third operational amplifier OP3 may be provided by the power supply terminal Vdd. By utilizing the virtual short characteristic of the third operational amplifier OP3, a positive temperature voltage corresponding to the positive temperature bias voltage vpos can be obtained at the node B1, and through the transmission of the current mirror structure, a bias current Iout1 with a positive temperature coefficient is finally generated in the cascode current source formed by M407 and M408. And through M404, M405 and M406, the circuit PSR performance is improved and the circuit stability is improved.

[0215] Figure 8 A circuit diagram of a specific example of the second temperature coefficient bias circuit in the embodiment of the present application is shown. As shown in the figure, in an optional embodiment, the second temperature coefficient bias circuit 500 includes a zero temperature coefficient bias circuit;

[0216] The zero temperature coefficient bias circuit comprises:

[0217] The zero-temperature current generating circuit 501 is configured to utilize the virtual short characteristic of the operational amplifier to generate a zero temperature coefficient bias current Iout2 based on the zero-temperature bias voltage vzero;

[0218] The second switch circuit 502 is configured to be turned on or off under the control of the second start-stop control signal outb to turn on or off the generation and output of the zero temperature coefficient bias current Iout2.

[0219] In the embodiment of the present application, the zero-temperature current generating circuit 501 and the second switch circuit 502 can be configured according to actual needs and are not limited to Figure 8The specific circuit structure shown in .

[0220] refer to Figure 8 In an optional implementation manner, the zero-temperature current generating circuit 501 includes a fourth operational amplifier OP4, a fifty-first capacitor C51, a fifty-first resistor R51, a fifth-hundred-first PMOS tube M501, a fifth-hundred-second PMOS tube M502, a fifth-hundred-third PMOS tube M503, a fifth-hundred-fourth PMOS tube M504, a fifth-hundred-fifth NMOS tube M505, a fifth-hundred-sixth NMOS tube M506, a fifth-hundred-seventh PMOS tube M507 and a fifth-hundred-eighth PMOS tube M508;

[0221] The second input end of the fourth operational amplifier OP4 is configured to obtain the zero-temperature bias voltage vzero, the output end of the fourth operational amplifier OP4 is respectively connected to the first end of the fifty-first capacitor C51, the gate of the fifty-first PMOS tube M501, the gate of the fifty-second PMOS tube M502, and the gate of the fifty-seventh PMOS tube M507, and the first input end of the fourth operational amplifier OP4 is respectively connected to the second end of the fifty-first capacitor C51, the drain of the fifty-third PMOS tube M503, and the first end of the fifty-first resistor R51;

[0222] The source of the fifth 01st PMOS tube M501, the source of the fifth 02nd PMOS tube M502, the source of the fifth 04th PMOS tube M504 and the source of the fifth 07th PMOS tube M507 are respectively connected to the power supply terminal Vdd; the drain of the fifth 01st PMOS tube M501 is connected to the source of the fifth 03rd PMOS tube M503; the gate of the fifth 03rd PMOS tube M503 is respectively connected to the gate of the fifth 04th PMOS tube M504, the drain of the fifth 04th PMOS tube M504 , the drain of the 506th NMOS tube M506 and the gate of the 508th PMOS tube M508; the drain of the 502nd PMOS tube M502 is respectively connected to the drain of the 505th NMOS tube M505, the gate of the 505th NMOS tube M505 and the gate of the 506th NMOS tube M506; the second end of the 51st resistor R51, the source of the 505th NMOS tube M505 and the source of the 506th NMOS tube M506 are respectively connected to the ground terminal Gnd;

[0223] The source of the 508th PMOS tube M508 is connected to the drain of the 507th PMOS tube M507, and the drain of the 508th PMOS tube M508 is configured to provide a zero temperature coefficient bias current Iout2;

[0224] The first switch circuit 502 includes at least one of the following: a fifth 09th NMOS transistor M509; a fifth 10th PMOS transistor M510; a fifth 11th PMOS transistor M511;

[0225] The gate of the 509th NMOS tube M509 is configured to obtain the second low-bit switch signal pda2, the drain of the 509th NMOS tube M509 is respectively connected to the gate of the 505th NMOS tube M505 and the gate of the 506th NMOS tube M506, and the source of the 509th NMOS tube M509 is connected to the ground terminal Gnd;

[0226] The gate of the fifth-one-th PMOS tube M510 is configured to obtain the second high-level switch signal pdb2, the drain of the fifth-one-th PMOS tube M510 is connected to the output end of the fourth operational amplifier OP4, and the source of the fifth-one-th PMOS tube M510 is connected to the power supply end Vdd;

[0227] The gate of the fifth PMOS tube M511 is configured to obtain the second high-level switching signal pdb2, the drain of the fifth PMOS tube M511 is respectively connected to the gate of the fifth-03rd PMOS tube M503 and the gate of the fifth-04th PMOS tube M504, and the source of the fifth-01st PMOS tube M511 is connected to the power supply terminal Vdd.

[0228] In an optional implementation manner, the first switch circuit 502 further includes a fifty-first inverter U51; or a fifty-first inverter U51 and a fifty-second inverter U52;

[0229] The input end of the fifty-first inverter U51 is configured to obtain the second start-stop control signal outb; the output end of the fifty-first inverter U51 is connected to the input end of the fifty-second inverter U52, and is configured to provide a second high-level switch signal pdb2; the output end of the fifty-second inverter U52 is configured to provide a second low-level switch signal pda2.

[0230] In the embodiment of the present application, the circuit structure of the zero temperature coefficient bias circuit can be the same as the circuit structure of the positive temperature coefficient bias circuit. The first input terminal of the fourth operational amplifier OP4 can be a negative input terminal, and the second input terminal can be a positive input terminal. The bias voltage of the fourth operational amplifier OP4 can be provided by the power supply terminal Vdd. Utilizing the virtual short characteristic of the fourth operational amplifier OP4, a zero temperature voltage corresponding to the zero temperature bias voltage vzero can be obtained at node B2, and through the transmission of the current mirror structure, a zero temperature coefficient bias current Iout2 is finally generated in the cascode current source composed of M507 and M508. And through M504, M505 and M506, the circuit PSR performance is improved and the circuit stability is improved.

[0231] Fig. 9 A circuit diagram of a specific example of a voltage-mode bandgap reference circuit in an embodiment of the present application is shown. As shown in the figure, in an optional implementation, the segmented temperature control circuit 1000 further includes a voltage-mode bandgap reference circuit (BGR) 600;

[0232] The voltage-mode bandgap reference circuit 600 includes a sixty-first PMOS transistor M61, a sixty-second PMOS transistor M62, a sixty-third PMOS transistor M63, a sixty-fourth PMOS transistor M64, a sixty-fifth PMOS transistor M65, a sixty-sixth PMOS transistor M66, a sixty-seventh PMOS transistor M67, a sixty-eighth PMOS transistor M68, a second operational amplifier OP2, a sixty-first resistor R61, a sixty-second resistor R62, a sixty-third resistor R63, a sixty-first transistor Q61, a sixty-second transistor Q62, a sixty-third transistor Q63 and a sixty-fourth transistor Q64;

[0233] The source of the sixty-first PMOS tube M61, the source of the sixty-second PMOS tube M62, the source of the sixty-third PMOS tube M63, and the source of the sixty-fourth PMOS tube M64 are respectively connected to the power supply terminal Vdd; the gate of the sixty-first PMOS tube M61 is respectively connected to the gate of the sixty-second PMOS tube M62, the gate of the sixty-third PMOS tube M63, the gate of the sixty-fourth PMOS tube M64 and the output end of the second operational amplifier OP2; the drain of the sixty-first PMOS tube M61 and the source of the sixty-fifth PMOS tube M65 are respectively connected to the gate of the sixty-second PMOS tube M62, the gate of the sixty-third PMOS tube M63, the gate of the sixty-fourth PMOS tube M64 and the output end of the second operational amplifier OP2; The gate of the sixty-fifth PMOS tube M65, the gate of the sixty-sixth PMOS tube M66, the gate of the sixty-seventh PMOS tube M67 and the gate of the sixty-eighth PMOS tube M68 are respectively configured to obtain the second high-bit bias signal vbp2;

[0234] The drain of the sixty-fifth PMOS tube M65 is respectively connected to the second input terminal of the second operational amplifier OP2 and the first terminal of the sixty-first resistor R61, and the second terminal of the sixty-first resistor R61 is connected to the emitter of the sixty-first transistor Q61; the drain of the sixty-sixth PMOS tube M66 is respectively connected to the first input terminal of the second operational amplifier OP2 and the emitter of the sixty-second transistor Q62; the drain of the sixty-seventh PMOS tube M67 is connected to the first terminal of the sixty-second resistor R62, and is configured to provide a positive temperature bias voltage vpos; the sixty-second resistor The second end of R62 is connected to the emitter of the sixty-third transistor Q63; the drain of the sixty-eighth PMOS tube M68 is connected to the first end of the sixty-third resistor R63 and is configured to provide a zero-temperature bias voltage vzero; the second end of the sixty-third resistor R63 is connected to the emitter of the sixty-fourth transistor Q64; the base and collector of the sixty-first transistor Q61, the base and collector of the sixty-second transistor Q62, the base and collector of the sixty-third transistor Q63, and the base and collector of the sixty-fourth transistor Q64 are respectively connected to the ground terminal Gnd.

[0235] In the embodiment of the present application, the second operational amplifier OP2 can be set according to actual needs, and the present application does not limit it. The first input terminal of the second operational amplifier OP2 can be a negative input terminal, and the second input terminal can be a positive input terminal. The sixty-first transistor Q61, the sixty-second transistor Q62, the sixty-third transistor Q63 and the sixty-fourth transistor Q64 can be PNP transistors. A voltage-mode bandgap reference circuit (BGR) is used to generate two reference bias voltages. By adjusting the resistance values ​​of R62 and R63, a positive temperature bias voltage vpos is obtained on R62, and a zero temperature bias voltage vzero is obtained on R63. The two bias voltages are then connected to the positive terminals of the operational amplifier inputs of the positive temperature coefficient bias circuit and the zero temperature coefficient bias circuit, respectively, and finally generate a positive temperature coefficient bias current Iout1 and a zero temperature coefficient bias current Iout2, respectively.

[0236] The embodiment of the present application further provides a radio frequency module, the radio frequency module comprising the segmented temperature control circuit and the radio frequency power amplifier PA as described in the above embodiment;

[0237] The segmented temperature control circuit is configured to output a plurality of temperature coefficient bias signals corresponding to a plurality of temperature segments one by one, so as to control the input of the radio frequency power amplifier in segments.

[0238] In an optional implementation, the plurality of temperature coefficient bias signals are bias currents.

[0239] In this way, in different temperature ranges, a suitable current or voltage with different temperature coefficients can be provided to the RF PA, so that the RF PA obtains a suitable current bias, thereby providing a suitable operating point for the RF PA, enabling it to operate with high efficiency and high linearity.

[0240] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations included in the claims. Various modifications and changes may be made on the basis of the above embodiments without departing from the scope of the present application. Similarly, the various technical features of the above embodiments may be arbitrarily combined to form other embodiments of the present application that may not be explicitly described. Therefore, the above embodiments only express several implementations of the present application and do not limit the scope of protection of the patent of this application.

Claims

1. A segmented temperature control circuit, characterized in that: The segmented temperature control circuit comprises: A first temperature coefficient signal generating circuit configured to provide a first temperature coefficient signal; A second temperature coefficient signal generating circuit is configured to provide a second temperature coefficient signal; a first curve of the value of the first temperature coefficient signal changing with temperature and a second curve of the value of the second temperature coefficient signal changing with temperature have at least one intersection point at a set temperature, so that the magnitude relationship between the value of the first temperature coefficient signal and the value of the second temperature coefficient signal changes at the set temperature; a comparison circuit configured to generate and output a first start / stop control signal of a first level and a second start / stop control signal of a second level that are inverse to each other according to a first comparison result of the first temperature coefficient signal and the second temperature coefficient signal when the current temperature is lower than the set temperature, so that the first temperature coefficient bias circuit is turned on under the control of the first start / stop control signal of the first level, and the second temperature coefficient bias circuit is turned off under the control of the second start / stop control signal of the second level; In the case where the current temperature is higher than the set temperature, according to the second comparison result of the first temperature coefficient signal and the second temperature coefficient signal, a first start-stop control signal of a second level and a second start-stop control signal of a first level which are inverse to each other are generated and output, so that the first temperature coefficient bias circuit is turned off under the control of the first start-stop control signal of the second level, and the second temperature coefficient bias circuit is turned on under the control of the second start-stop control signal of the first level; A first temperature coefficient bias circuit, configured to be turned on or off under the control of the first start / stop control signal, so as to turn on or off the generation and output of the first temperature coefficient bias signal; The second temperature coefficient bias circuit is configured to be turned on or off under the control of the second start / stop control signal to turn on or off the generation and output of the second temperature coefficient bias signal.

2. The segmented temperature control circuit according to claim 1, characterized in that: The first temperature coefficient signal generating circuit includes any one of the following: a negative temperature coefficient current source; a positive temperature coefficient current source; Zero temperature coefficient current source; negative temperature coefficient voltage source; positive temperature coefficient voltage source; Zero temperature coefficient voltage source; The second temperature coefficient signal generating circuit includes any one of the following: a negative temperature coefficient current source; Positive temperature coefficient current source; Zero temperature coefficient current source; Negative temperature coefficient voltage source; Positive temperature coefficient voltage source; Zero temperature coefficient voltage source.

3. The segmented temperature control circuit according to claim 2, characterized in that: The first temperature coefficient signal generating circuit includes a negative temperature coefficient current source configured to provide a negative temperature coefficient current; The second temperature coefficient signal generating circuit includes a positive temperature coefficient current source configured to provide a positive temperature coefficient current; The comparison circuit is configured to compare the negative temperature coefficient current and the positive temperature coefficient current so as to generate and output a first start-stop control signal of a first level and a second start-stop control signal of a second level that are inverted to each other when the current temperature is lower than the set temperature; and to generate and output a first start-stop control signal of a second level and a second start-stop control signal of a first level that are inverted to each other when the current temperature is higher than the set temperature.

4. The segmented temperature control circuit according to claim 3, characterized in that: The comparison circuit comprises: A first conversion circuit is configured to determine a first input voltage according to the negative temperature coefficient current; A second conversion circuit is configured to determine a second input voltage according to the positive temperature coefficient current; a two-stage operational amplifier comparator configured to compare the first input voltage and the second input voltage to obtain an output voltage of a first level when the current temperature is lower than the set temperature, and to obtain an output voltage of a second level when the current temperature is higher than the set temperature; a first inverter configured to invert the output voltage to obtain a second start / stop control signal; The second inverter is configured to invert the second start-stop control signal to obtain a first start-stop control signal.

5. The segmented temperature control circuit according to claim 3 or 4, characterized in that: The negative temperature coefficient current source comprises a high current mirror module, a self-starting module, a low current mirror module, a negative temperature current generating module, and an output module respectively coupled to the high current mirror module and the self-starting module. The output module is used to replicate and output a negative temperature coefficient current; The control end of the self-starting module is coupled to the output end of the low-level current mirror module, so that during the power-on process of the negative temperature coefficient current source, the self-starting module is turned on under the control of the low voltage at the output end of the low-level current mirror module, so as to prompt the low-level current mirror module and the high-level current mirror module to be turned on, so that the negative temperature coefficient current source completes the startup and the negative temperature current generating module generates a first negative temperature current corresponding to the negative temperature coefficient current, so that the output module can copy and output the negative temperature coefficient current.

6. The segmented temperature control circuit according to any one of claims 1 to 4, characterized in that: The first temperature coefficient bias circuit includes any one of the following: a positive temperature coefficient bias circuit configured to provide a positive temperature coefficient bias current; a zero temperature coefficient bias circuit configured to provide a zero temperature coefficient bias current; a negative temperature coefficient bias circuit configured to provide a negative temperature coefficient bias current; The second temperature coefficient bias circuit includes any one of the following: a positive temperature coefficient bias circuit configured to provide a positive temperature coefficient bias current; a zero temperature coefficient bias circuit configured to provide a zero temperature coefficient bias current; A negative temperature coefficient bias circuit is configured to provide a negative temperature coefficient bias current.

7. The segmented temperature control circuit according to claim 6, characterized in that: The first temperature coefficient bias circuit includes a positive temperature coefficient bias circuit; The positive temperature coefficient bias circuit comprises: a positive temperature current generating circuit configured to generate a positive temperature coefficient bias current based on a positive temperature bias voltage by utilizing a virtual short characteristic of an operational amplifier; The first switch circuit is configured to be turned on or off under the control of the first start-stop control signal to turn on or off the generation and output of the positive temperature coefficient bias current.

8. The segmented temperature control circuit according to claim 6, characterized in that: The second temperature coefficient bias circuit includes a zero temperature coefficient bias circuit; The zero temperature coefficient bias circuit comprises: a zero-temperature current generating circuit configured to generate a zero-temperature coefficient bias current based on a zero-temperature bias voltage by utilizing a virtual short characteristic of an operational amplifier; The second switch circuit is configured to be turned on or off under the control of the second start-stop control signal to turn on or off the generation and output of the zero temperature coefficient bias current.

9. The segmented temperature control circuit according to any one of claims 1 to 8, characterized in that: The segmented temperature control circuit also includes a voltage mode bandgap reference circuit; The voltage-mode bandgap reference circuit comprises a sixty-first PMOS tube, a sixty-second PMOS tube, a sixty-third PMOS tube, a sixty-fourth PMOS tube, a sixty-fifth PMOS tube, a sixty-sixth PMOS tube, a sixty-seventh PMOS tube, a sixty-eighth PMOS tube, a second operational amplifier, a sixty-first resistor, a sixty-second resistor, a sixty-third resistor, a sixty-first triode, a sixty-second triode, a sixty-third triode and a sixty-fourth triode; The source of the sixty-first PMOS tube, the source of the sixty-second PMOS tube, the source of the sixty-third PMOS tube, and the source of the sixty-fourth PMOS tube are respectively connected to the power supply terminal; the gate of the sixty-first PMOS tube is respectively connected to the gate of the sixty-second PMOS tube, the gate of the sixty-third PMOS tube, the gate of the sixty-fourth PMOS tube, and the output terminal of the second operational amplifier; the drain of the sixty-first PMOS tube is connected to the source of the sixty-fifth PMOS tube, the drain of the sixty-second PMOS tube is connected to the source of the sixty-sixth PMOS tube, the drain of the sixty-third PMOS tube is connected to the source of the sixty-seventh PMOS tube, and the drain of the sixty-fourth PMOS tube is connected to the source of the sixty-eighth PMOS tube; the gate of the sixty-fifth PMOS tube, the gate of the sixty-sixth PMOS tube, the gate of the sixty-seventh PMOS tube, and the gate of the sixty-eighth PMOS tube are respectively configured to obtain the second high-bit bias signal; The drain of the sixty-fifth PMOS tube is respectively connected to the second input terminal of the second operational amplifier and the first terminal of the sixty-first resistor, and the second terminal of the sixty-first resistor is connected to the emitter of the sixty-first transistor; the drain of the sixty-sixth PMOS tube is respectively connected to the first input terminal of the second operational amplifier and the emitter of the sixty-second transistor; the drain of the sixty-seventh PMOS tube is connected to the first terminal of the sixty-second resistor and is configured to provide a positive temperature bias voltage; the second terminal of the sixty-second resistor is connected to the emitter of the sixty-third transistor; the drain of the sixty-eighth PMOS tube is connected to the first terminal of the sixty-third resistor and is configured to provide a zero temperature bias voltage; the second terminal of the sixty-third resistor is connected to the emitter of the sixty-fourth transistor; the base and collector of the sixty-first transistor, the base and collector of the sixty-second transistor, the base and collector of the sixty-third transistor, and the base and collector of the sixty-fourth transistor are respectively connected to the ground terminal.

10. A radio frequency module, characterized in that: The radio frequency module comprises a segmented temperature control circuit and a radio frequency power amplifier as described in any one of claims 1 to 9; The segmented temperature control circuit is configured to output a plurality of temperature coefficient bias signals corresponding to a plurality of temperature segments one by one, so as to control the input of the radio frequency power amplifier in segments.

11. The radio frequency module according to claim 10, characterized in that: The plurality of temperature coefficient bias signals are bias currents.

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