Chip aging test and analysis method

Abstract

The invention relates to the technical field of chip testing, in particular to a chip aging test and analysis method, which comprises the following steps of: constructing an aging parameter matrix containing process deviation, electrical parameters and thermodynamic parameters on the basis of fusion of wafer level and packaged test data, multi-stress cooperative loading is realized through a programmable power supply and a multi-zone temperature control array, transient electric signals, thermal imaging data and leakage current frequency spectrums are acquired in real time, an electrical-thermal coupling coefficient and a process deviation sensitivity factor are extracted in a cross-dimension manner, a non-linear recession model is established, differential aging paths of chip functional blocks are evaluated, and the reliability of the chip functional blocks is improved. And based on the dynamic life prediction model and a fault early warning mechanism, generating and executing an adaptive test optimization strategy to realize early prediction and stress adjustment of multiple failure modes. According to the invention, the efficiency and accuracy of the aging test can be obviously improved, and technical support is provided for high-reliability evaluation of deep submicron and post-mole times of chips.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and particularly to a method for chip aging testing and analysis. Background Art

[0002] As the integrated circuit manufacturing process technology continues to evolve towards the nanoscale, the further reduction of device feature sizes has led to higher requirements for chip reliability. To ensure stable operation in high-frequency, high-power, and extreme temperature environments, the industry usually adopts accelerated aging tests to evaluate the potential failure modes of chips. In the chip manufacturing process, wafer-level testing can provide accurate process data such as dimensional deviation, thin film thickness distribution, doping concentration, etc., while post-packaging testing can capture the electrical, thermal, and mechanical stress effects brought about by the packaging process and changes in the working environment. By combining multiple pieces of information before and after wafer packaging, a more complete parameter basis can be provided for subsequent aging analysis.

[0003] Existing technologies often adopt accelerated aging tests under fixed conditions, such as constant temperature or constant voltage, and insufficient consideration is given to the coupling effects of various aging phenomena such as hot carriers, gate oxide degradation, and electromigration. In addition, monitoring methods that only focus on a single parameter (such as leakage current or threshold voltage) are also difficult to quickly detect and locate abnormalities during the testing process, and it is even more impossible to flexibly adjust the stress according to transient phenomena or local hot spots. Moreover, most existing life prediction models are based on static or simplified calculation of acceleration factors, and dynamic factors such as process deviations and temperature gradient evolution that occur over time and with environmental changes cannot be accurately described, resulting in limitations in prediction accuracy and reliability and making it difficult to effectively support the high-reliability requirements of chips in actual application scenarios. Summary of the Invention

[0004] The present invention provides a method for chip aging testing and analysis.

[0005] A method for chip aging testing and analysis includes the following steps:

[0006] S1: Generate a chip aging parameter matrix, where the chip aging parameter matrix includes a set of reference electrical parameters, a set of dynamic thermodynamic parameters, and a set of process deviation parameters, and the set of process deviation parameters is obtained by calculating wafer-level test data and post-packaging parameter offsets;

[0007] S2: Dynamically configure the test environment based on the aging parameter matrix, perform a multi-stress collaborative loading test, and collect test data packets, where the test data packets include transient electrical signal waveforms, thermal imaging distribution maps, and leakage current spectra;

[0008] S3: Analyze the parameter coupling characteristics of the test data packets, and extract the aging feature vectors with cross-dimensional correlation characteristics. The aging feature vectors include the electrical-thermal coupling coefficient, the process deviation sensitivity factor, and the non-linear decay index;

[0009] S4: Generate an aging test optimization strategy based on the aging feature vectors. The strategy includes a dynamic adjustment scheme for test conditions, an update instruction for the parameters of the life prediction model, and the identification results of potential failure modes.

[0010] Optionally, the S1 includes:

[0011] S11, Wafer-level test data acquisition: Before wafer dicing, use an integrated optical measurement sensor array to perform in-situ scanning on the key areas of each chip to obtain wafer-level test data. The wafer-level test data includes the measured values of the critical dimensions of the wafer, the thin film thickness distribution, and the doping concentration gradient;

[0012] S12, Detection of parameter offset after packaging: After chip packaging is completed, deploy a multi-modal sensing system to detect the parameter offset and obtain the parameter offset after packaging;

[0013] S13, Calculation of process deviation parameter set: Based on the obtained wafer-level test data and the parameter offset after packaging, generate a process deviation parameter set.

[0014] Optionally, the S1 further includes:

[0015] S14, Generation of dynamic parameter set: Based on the process deviation parameter set, dynamically generate test parameter benchmarks, including a benchmark electrical parameter set and a dynamic thermodynamics parameter set;

[0016] S15, Construction of aging parameter matrix: Integrate the outputs of S11 - S14 into a chip aging parameter matrix.

[0017] Optionally, the S2 includes:

[0018] S21, Loading and parsing of aging parameter matrix: Based on the generated three-dimensional aging parameter matrix, perform spatio-temporal parameter matching and dynamic environment configuration;

[0019] S22, Generation of multi-stress control signals: Generate cooperative loading control signals based on the parsed parameter set, including electrical stress signals and thermodynamics stress signals;

[0020] S23, Execution of multi-stress cooperative loading test: Use a closed-loop feedback mechanism to perform multi-stress loading.

[0021] Optionally, the S2 further includes:

[0022] S24, Acquisition of multi-source test data: Synchronously collect test data packets through a heterogeneous sensing system;

[0023] S25, Test data packet encapsulation and verification: Perform spatio-temporal alignment and integrity verification on the test data packet, and then encapsulate it.

[0024] Optionally, S3 includes:

[0025] S31, Spatio-temporal alignment and noise reduction of multi-source test data: Perform data preprocessing on the encapsulated test data packet to generate a preprocessed data set. The preprocessing includes spatio-temporal benchmark unification and data noise reduction;

[0026] S32, Feature extraction: Extract three types of basic features from the preprocessed data set, including electrical features, thermal features, and process deviation features;

[0027] S33: Electrical-thermal coupling coefficient calculation: Based on the extracted electrical features and thermal features, establish a quantitative model for electro-thermal interaction.

[0028] Optionally, S3 further includes:

[0029] S34: Process deviation sensitivity factor modeling: Quantify the impact of process deviation based on process deviation features and a set of process deviation parameters;

[0030] S35, Nonlinear decay index calculation: Identify the nonlinear aging effect based on the outputs of S32 - S34;

[0031] S36, Aging feature vector synthesis and verification: Integrate the outputs of S33 - S35 to generate an aging feature vector.

[0032] Optionally, S4 includes:

[0033] S41, Generation of dynamic test condition adjustment scheme: Dynamically optimize the test conditions based on the generated aging feature vector;

[0034] S42: Update of life prediction model parameters: Update the core parameters of the prediction model using the aging feature vector;

[0035] S43: Identification of potential failure modes: Based on the feature vector matching a predefined fault template library, trigger a fault warning according to the matching result.

[0036] Optionally, S4 further includes:

[0037] S44, Encapsulation and execution of optimization strategy: Integrate the outputs of S41 - S43 to generate an aging test optimization strategy and execute the optimization strategy;

[0038] S45, Feedback and iteration of strategy effect: Verify the effectiveness of the optimization strategy and dynamically correct it.

[0039] Advantages of the present invention:

[0040] In the present invention, through the coupling of wafer-level test data and the parameter offset after packaging, a multi-dimensional aging parameter matrix is established, integrating process deviation, electrical characteristics, and thermodynamic elements, significantly improving the characterization accuracy and integrity of the chip aging process. Compared with the traditional method of single stress or local parameter monitoring, this solution realizes the dual-stage data fusion before wafer and after packaging, the precise measurement and offset correction of critical dimensions, dielectric layer distribution, and doping concentration, provides a more accurate initial benchmark for multi-stress loading, and enables higher reliability and traceability for subsequent aging prediction and fault determination.

[0041] The present invention proposes a multi-stress collaborative loading and closed-loop control mechanism, which realizes the dynamic configuration of the real-time test environment under the interaction of electrical and thermal stresses. By monitoring data such as transient electrical signal waveforms, thermal imaging distributions, and leakage current spectra, the system can adjust the voltage, temperature gradient, and test cycle in a timely manner according to key information such as transient overshoot amplitude, local hot spots, and leakage current increase, which can not only prevent premature failure caused by excessive stress but also significantly improve the test efficiency. Compared with the traditional accelerated aging test methods with fixed temperature or fixed voltage, the present invention can more accurately simulate the degradation process under the actual working scenario and realize the flexible optimization of test time and test intensity.

[0042] In the present invention, through cross-dimensional feature extraction and the modeling of process deviation sensitivity factors, the non-linear degradation characteristics and coupling effects of different functional areas of the chip can be refined, so as to accurately identify common potential fault modes (such as electromigration, hot carriers, gate oxide breakdown, etc.), and combined with the dynamically updated life prediction model to achieve accurate assessment of the fault probability and failure time. At the same time, by using the automatically generated optimization instructions and fault warning mechanism, protection measures can be quickly taken during operation, significantly reducing the fault undetected rate and false alarm rate. Based on this system, the test strategy can be adaptively iterated, which not only ensures the comprehensive monitoring of complex aging behaviors but also provides an efficient, accurate, and scalable reliability assessment means for chip design and quality assurance. Brief Description of the Drawings

[0043] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only those of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0044] Figure 1 It is a schematic flowchart of the method according to the embodiment of the present invention;

[0045] Figure 2 It is a schematic flowchart of the S2 process according to the embodiment of the present invention. Detailed implementation mode

[0046] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. At the same time, it should be noted here that in order to make the embodiments more detailed, the following embodiments are the best and preferred embodiments. For some well-known technologies, those skilled in the art can also adopt other alternative methods for implementation; moreover, the accompanying drawings are only for more specifically describing the embodiments, and are not intended to specifically limit the present invention.

[0047] It should be noted that in the specification, the mention of "one embodiment", "embodiment", "exemplary embodiment", "some embodiments", etc. indicates that the described embodiment may include specific features, structures or characteristics, but not necessarily every embodiment includes such specific features, structures or characteristics. In addition, when combining embodiments to describe specific features, structures or characteristics, implementing such features, structures or characteristics in combination with other embodiments (whether explicitly described or not) should be within the knowledge of those skilled in the relevant art.

[0048] Generally, terms can be understood at least in part from their use in the context. For example, at least in part depending on the context, the term "one or more" used herein can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or characteristics in a plural sense. Additionally, the term "based on" can be understood as not necessarily intended to convey a set of exclusive factors, but rather can alternatively, at least in part depending on the context, allow for the existence of other factors that are not necessarily explicitly described.

[0049] As Figure 1 - Figure 2 shown, a chip aging test and analysis method includes the following steps:

[0050] S1: Generate a chip aging parameter matrix, which includes a set of reference electrical parameters, a set of dynamic thermodynamic parameters, and a set of process deviation parameters, where the set of process deviation parameters is obtained by calculating the wafer-level test data and the parameter offset after packaging;

[0051] S2: Dynamically configure the test environment based on the aging parameter matrix, perform a multi-stress collaborative loading test, and collect test data packets, where the test data packets include transient electrical signal waveforms, thermal imaging distribution maps, and leakage current spectra;

[0052] S3: Perform parameter coupling feature analysis on the test data packets, and extract aging feature vectors with cross-dimensional correlation characteristics, where the aging feature vectors include electrical-thermal coupling coefficients, process deviation sensitivity factors, and non-linear decay indices;

[0053] S4: Generate an aging test optimization strategy based on the aging feature vector. The strategy includes a dynamic adjustment scheme for test conditions, an update instruction for the parameters of the life prediction model, and the identification results of potential failure modes.

[0054] S1 includes:

[0055] S11, Wafer-level test data acquisition: Before wafer dicing, use an integrated optical measurement sensor array to perform in-situ scanning on the key areas of each chip to obtain wafer-level test data. The wafer-level test data includes the measured values of the critical dimensions of the wafer, the film thickness distribution, and the doping concentration gradient. The steps are as follows:

[0056] Measured value of the critical dimensions of the wafer W test : Gate line width, pitch, and contact hole diameter;

[0057] Film thickness distribution T wafer : Thickness variations of each dielectric layer and metal layer;

[0058] Doping concentration gradient D wafer : Doping concentration distribution in the source and drain regions;

[0059] The sensor array includes:

[0060] High-resolution spectral confocal sensor: Measure three-dimensional topography features with an accuracy of ±5nm;

[0061] Ellipsometric thin-film analyzer: Invert the film thickness through the reflectivity of polarized light;

[0062] Micro-area X-ray fluorescence spectrometer: Scan the doping element concentration distribution;

[0063] S12, Detection of parameter offset after packaging: After the chip packaging is completed, deploy a multi-modal sensing system to detect the parameter offset and obtain the parameter offset after packaging. The steps are as follows:

[0064] (1) Detection of electrical performance parameters:

[0065] Apply a stepped voltage signal and measure the threshold voltage V th_post and contact resistance R c_post ;

[0066] Use a time-domain reflectometer to analyze the impedance of the signal transmission path and calculate the gate oxide integrity parameter Gox post ;

[0067] (2) Detection of thermodynamic parameters: Use a micro infrared thermal imager to scan the surface temperature field of the packaging structure and extract the degradation coefficient ξ post ;

[0068] (3) Calculation of parameter offset: Combine V th_post 、Rc_post , Gox post , ξ post are respectively compared with the pre-packaging reference values (V th_pre , R c_pre , Gox pre , ξ pre ) to generate the post-packaging parameter offset ΔQ, which is expressed as:

[0069]

[0070] S13. Calculation of process deviation parameter set: Based on the post-packaging parameter offset ΔQ of the obtained wafer-level test data, a process deviation parameter set ΔP is generated. The steps are as follows:

[0071] (1) Critical dimension deviation calculation: ΔW = α × (W test - W design ), where W design is the design value, T spec is the reference thickness of the dielectric layer and the metal layer in the design specification, and D spec is the reference gradient of the doping concentration in the design specification;

[0072] (2) Electrical property deviation weighting: ΔV th adj = β × ΔV th , ΔR c adj = γ × ΔR c , where β and γ are calibrated through an accelerated aging experiment;

[0073] (3) Dielectric layer degradation factor calculation: ΔGox adj = δ × ΔGox, where δ = 0.5 × (Δξ) 0.5 ;

[0074] (4) Generate the process deviation parameter set, which is expressed as: ΔP = [ΔW, ΔV th adj , ΔR c adj , ΔGox adj .

[0075] S1 also includes:

[0076] S14. Generation of dynamic parameter set: Based on the process deviation parameter set ΔP, a test parameter reference is dynamically generated, including a reference electrical parameter set and a dynamic thermodynamics parameter set, where:

[0077] Reference electrical parameter set, which is expressed as: [V basc , f basc ;

[0078] Standard working voltage

[0079] Frequency reference f base = f nom × (1 + 0.02 × ΔR c adj );

[0080] Among them, V nom and f nom are the rated operating voltage and operating frequency, sgn(·) is the sign function, with a positive value of +1 and a negative value of -1;

[0081] Set of dynamic thermodynamic parameters, expressed as:

[0082] Temperature gradient distribution

[0083] Maximum junction temperature Tj max = Tj spec + 10 × ∣ΔV th adj ∣;

[0084] Among them, k1 and k2 are empirical constants related to the thermodynamic model, Tj spec is the maximum junction temperature allowed in the design specification, and Δξ is the calculated offset ratio of the thermal interface material degradation coefficient;

[0085] S15, construction of the aging parameter matrix: Integrate the outputs of S11 - S14 into the chip aging parameter matrix, and the specific content is as follows:

[0086] Definition of matrix structure:

[0087] Row dimension: Test time nodes (t1, t2,..., t n );

[0088] Column dimension: Parameter type (electrical, thermodynamic, process deviation);

[0089] Layer dimension: Chip functional blocks (core area, 1 / 0 area, storage area);

[0090] Data filling rule: Each element is a triple Match the wafer test data position according to the block coordinates; among them, the process deviation parameter ΔP is used as a weighting factor to correct the coupling relationship between electrical and thermodynamic parameters.

[0091] S2 includes:

[0092] S21, loading and parsing of the aging parameter matrix: Based on the generated three - dimensional aging parameter matrix, perform space - time parameter matching and dynamic environment configuration, and the steps are as follows:

[0093] Space - time parameter matching: Extract the time - node matrix slice corresponding to the current test cycle, and obtain the electrical parameter set [V basc , fbasc , a set of thermodynamic parameters and a set of process deviation parameters ΔP, and match the parameter values corresponding to each block according to the spatial coordinates of the chip functional blocks;

[0094] Dynamic environment configuration: Set V basc , f base to the voltage-frequency control register of the programmable power module;

[0095] Convert into a multi-zone temperature control instruction to drive the micro heating array to generate a target temperature gradient;

[0096] S22, Generation of multi-stress control signals: Generate a collaborative loading control signal based on the parsed parameter set, including an electrical stress signal and a thermodynamic stress signal, where;

[0097] Electrical stress signal: Generate a voltage waveform with frequency jitter:

[0098] V test (t) = V base × [1 + 0.1 × sin(2πf base t)];

[0099] Among them, V test (t) is the transient voltage signal actually applied to the chip during testing, and t is the time variable;

[0100] Superimpose a transient overshoot pulse with a pulse amplitude of 0.2 × V basc , and the width ≤ 10 ns.

[0101] Thermodynamic stress signal: According to Generate a spatially differentiated temperature control curve, and set the temperature rise rate of the core area to The I / O area is

[0102] Under the constraint of Tj max , dynamically calculate the maximum power limit of each heating unit;

[0103] S23, Execution of multi-stress collaborative loading test: Execute multi-stress loading using a closed-loop feedback mechanism, and the steps are as follows:

[0104] Initial loading stage:

[0105] Synchronously apply the electrical stress signal and the thermodynamic stress signal for t1 = 5 minutes

[0106] Real-time monitor the leakage current I leak , when I leak / I leak_base > 1.3, trigger the protection mechanism, I leak_baseis the reference leakage current reference value;

[0107] Dynamic adjustment stage:

[0108] Collect the transient electrical signal waveform once every Δt = 30 seconds, and extract the voltage overshoot amplitude V overshoot ;

[0109] According to V overshoot Dynamically adjust the temperature gradient:

[0110] is the updated temperature gradient distribution;

[0111] When a local hot spot (temperature difference > 8°C) appears in the thermal imaging map, reduce the heating power of the corresponding area by 20%.

[0112] S2 also includes:

[0113] S24, multi-source test data acquisition: Synchronously collect test data packets through a heterogeneous sensing system, including:

[0114] (1) Transient electrical signal waveform acquisition:

[0115] Use a 40GHz bandwidth high-speed oscilloscope to capture the power supply rail voltage V dd (t), clock signal CLK(t) and leakage current I leak (t);

[0116] Perform a fast Fourier transform on I leak (t) to generate a leakage current spectrum diagram I spectrum (f);

[0117] (2) Thermodynamic distribution data acquisition:

[0118] Use an infrared thermal imager (spatial resolution 5μm) to take a thermal imaging distribution map Thermal_map(x,y) of the chip surface;

[0119] Plant a micro-thermocouple at the key nodes inside the chip to collect the junction temperature data Tj core 、Tj io ;

[0120] (3) Process deviation feedback data acquisition:

[0121] Obtain the threshold voltage drift amount ΔV in real time through an on-line parameter measurement unit (OBRM) th_real ;

[0122] Compare ΔV th_real with ΔP[1] to generate a process deviation compensation coefficient η, expressed as:

[0123] ΔP[1] is the first element in the process deviation parameter set ΔP (usually corresponding to the threshold voltage shift related item);

[0124] S25, test data packet encapsulation and verification: perform time and space alignment and integrity verification on the test data packet, and encapsulate it. The verification includes:

[0125] (1) Data timestamp synchronization: add a unified time stamp to the electrical signal waveform, thermal imaging image, and leakage current spectrum with an accuracy of ≤1μs;

[0126] (2) Spatial coordinate mapping: Establish a mapping relationship between Thermal_map (x, y) and the spatial block coordinates of the chip aging parameter matrix.

[0127] (3) Data validity verification:

[0128] Calculate the electrical signal noise ratio SNR ≥ 40dB,

[0129] When the data is abnormal, the test rollback mechanism is triggered: the current cycle stress loading and data collection are re-executed.

[0130] S3 includes:

[0131] S31, multi-source test data spatiotemporal alignment and noise reduction: perform data preprocessing on the encapsulated test data packets to generate preprocessed data sets. The preprocessing includes spatiotemporal benchmark unification and data noise reduction, as follows:

[0132] (1) Unification of time and space benchmarks: Align the transient electrical signal waveform, thermal imaging distribution map, and leakage current spectrum according to a unified time scale. The alignment rules are as follows:

[0133] The accuracy of the electrical signal waveform timestamp is ≤1ns, and the thermal imaging data is interpolated and aligned according to the start time of each frame.

[0134] According to the coordinates of the chip's functional blocks (core area, 1 / 0 area, storage area), the thermal imaging pixels are bound to the electrical signal acquisition channels.

[0135] (2) Data noise reduction processing

[0136] The transient electrical signal is decomposed and denoised by wavelet packet decomposition: a 5-layer decomposition is performed using the db6 wavelet basis, retaining high-frequency components >100MHz; and removing noise components with amplitudes <3σ (σ is the standard deviation of noise);

[0137] Non-local mean filtering was applied to the thermal imaging data: the search window was 15×15 pixels, and the similarity block window was 7×7 pixels. After filtering, the temperature resolution was increased to 0.05°C.

[0138] Generate preprocessed dataset Dclean ;

[0139] S32, Feature extraction: Extract three types of basic features from the preprocessed dataset, including electrical features, thermal features, and process deviation features. The steps are as follows:

[0140] (1) Electrical dimension feature extraction:

[0141] Calculation of transient overshoot amplitude: V overshoot = max(V dd (t)) - V base ;

[0142] Main frequency offset of leakage current spectrum: Δf peak = argmax(I spectrum (f)) - f base ;

[0143] Time-varying slope of leakage current:

[0144] Generate electrical features: F electric = [V overshoot , Δf peak , Slope Ileak ;

[0145] (2) Thermal dimension feature extraction:

[0146] Calculation of thermal gradient non-linearity:

[0147] Thermal relaxation time constant: Fit the equation for the temperature decay curve T(t):

[0148] T(t) = T0 × exp(-t / τ thermal ), and extract τ thermal as a feature quantity;

[0149] Ratio of hotspot area:

[0150] Generate thermal features: F thermal = [NG, τ thermal , Hotspot_ratio];

[0151] (3) Process deviation dimension feature extraction:

[0152] Sensitivity of threshold voltage drift:

[0153] Coefficient of variation of contact resistance:

[0154] Defect density of individual electrical layers: Calculated by counting the number of local temperature anomaly regions in the thermal imaging map;

[0155] Generate process deviation characteristics:

[0156] S33: Electrical-thermal coupling coefficient calculation: Based on the extracted electrical feature F electric and thermal feature F thermal , establish a quantization model for electro-thermal interaction, the steps are as follows:

[0157] (1) Dynamic coupling degree analysis:

[0158] Calculate the time-varying correlation coefficient matrix of electrical and thermal features:

[0159] where, σ electric and σ thermal are the standard deviations of the electrical and thermal feature sets in a specific time period respectively;

[0160] Extract the main coupling coefficient: K eh = max(|C(t)|);

[0161] (2) Spatial coupling strength mapping: Calculate the electro-thermal coupling strength according to the functional blocks:

[0162]

[0163] Generate a spatial distribution map: Coupling map(x,y) = S eh (x,y);

[0164] (3) Generation of coupling coefficient set:

[0165] Integrate dynamic and spatial features: K = [K eh , max(S eh ), mean(S eh )].

[0166] S3 also includes:

[0167] S34: Modeling of process deviation sensitivity factor: Based on the process deviation feature F process and the process deviation parameter set ΔP, quantify the influence of process deviation, the steps are as follows:

[0168] (1) Multiple regression modeling:

[0169] The sensitivity analysis of electrical features is expressed as: F electric = γ0 + γ1×ΔW + γ2×ΔV th adj + ε;

[0170] The sensitivity analysis of thermal features is expressed as: F thermal = θ0 + θ1×ΔGox adj+θ2×Δξ+ε;

[0171] (2) Sensitivity factor calculation

[0172] Electrical sensitivity factor S e :

[0173] Thermal sensitivity factor S t :

[0174] Generate sensitivity factor set: S = [S e , S t , S e ×S t ;

[0175] Among them, γ0, γ1, γ2, θ0, θ1, θ2 are all coefficients of the multiple regression model, and ε is the regression residual;

[0176] S35, Nonlinear decay index calculation: Identify the nonlinear aging effect based on the outputs of S32 - S34. S32 outputs three types of basic features, S33 outputs the electrical-thermal coupling result, and S34 outputs the process deviation sensitivity factor. The steps are as follows:

[0177] Time-domain decay trajectory modeling: Establish a composite decay model for key parameters, and the model is expressed as:

[0178] y(t) = a×exp(b×t)+c×t d , where a, b, c, d are fitting parameters in the composite decay model;

[0179] The fitting objects include:

[0180] Nonlinear index generation

[0181] Define the index formula: The residual is the deviation between the fitting function and the actual data;

[0182] Generate the spatial index matrix by functional block: NRI map (x,y) = [NRI core , NRI io , NRI mem ;

[0183] S36, Aging feature vector synthesis and verification: Integrate the outputs of S33 - S35 to generate the aging feature vector. The output of S35 is the nonlinear decay index. The specific steps are as follows:

[0184] (1) Feature vector synthesis:

[0185] Combine features by functional block:

[0186] Feature_vector = [K eh , S e , NRI core , S t , NRI io , S e ×S t ;

[0187] Construct a set of spatial feature vectors: {Feature_vector(x, y) | x, y ∈ chip functional blocks}

[0188] (2) Validity verification

[0189] Mutual information check: MI(Feature vector ) ≥ 0.35;

[0190] Principal component analysis verification:

[0191] It is required that the contribution rate of the first principal component < 60%, and the feature orthogonality meets the standard

[0192] Abnormal trigger mechanism: If the check fails, trigger the S25 test rollback.

[0193] S4 includes:

[0194] S41, generation of a dynamic adjustment plan for test conditions: Based on the generated aging feature vectors, dynamically optimize the test conditions. The steps are as follows:

[0195] (1) Electrical stress adjustment:

[0196] According to the electro-thermal coupling coefficient K eh Adjust the operating voltage, expressed as:

[0197] V new = V base ×(1 + 0.1×tanh(K eh / 0.5)), where tanh(·) is the hyperbolic tangent function;

[0198] Based on the non-linear decay index, correct the frequency jitter amplitude, expressed as:

[0199]

[0200] (2) Thermodynamic stress optimization: Re-distribute the temperature gradient according to the spatial coupling strength Coupling_map(x, y), expressed as:

[0201]

[0202] Combined with NRI ioAdjust the temperature rise rate in the 1 / 0 area, expressed as:

[0203]

[0204] Among them, NRI core and NRI io are the non-linear decay indices of the core area and the I / O area respectively;

[0205] S42: Update the parameters of the life prediction model: Update the core parameters of the prediction model using the aging feature vector, and the steps are as follows:

[0206] Activation energy correction of the Arrhenius equation: According to the process deviation sensitivity factor S e Adjust the activation energy E a : Expressed as:

[0207] E a new = E a initial ×(1 + 0.15×S e );

[0208] Dynamic calculation of the voltage acceleration factor: Based on the transient overshoot amplitude V overshoot Correct the voltage acceleration factor n, expressed as:

[0209] n new is the corrected voltage acceleration factor;

[0210] Model integration and verification: Substitute the updated parameters into the life prediction equation:

[0211] Among them, A is the factor pre-calibrated by the model, k is the Boltzmann constant or the corresponding proportional constant, and MTTF is the Mean Time To Failure, the average failure time;

[0212] Verify through Monte Carlo simulation that the prediction error ≤ 8%;

[0213] S43: Identification of potential failure modes: Based on the feature vector matching the predefined failure template library, trigger a failure warning according to the matching result, and the steps are as follows:

[0214] Construction of the failure feature template:

[0215] Pre-store three types of typical failure feature vectors:

[0216] Electromigration failure: F EM = [K eh > 0.7, S e > 0.6, NRI core > 1.2];

[0217] Hot carrier degradation: F HCI = [Coupling map > 0.8, S t > 0.5, NRI io > 0.9];

[0218] Gate oxide breakdown:

[0219] Similarity matching calculation: Calculate the Euclidean distance between the current feature vector and each template:

[0220] D EM = ∥Feature_vector - F EM ∥;

[0221] D HCI = ∥Feature_vector - F HCI ∥;

[0222] D GOX = ∥Feature_vector - F GOX ∥;

[0223] Fault warning trigger:

[0224] When any distance value D < D threshold (D threshold = 0.35);

[0225] Generate an early warning signal for the corresponding fault type;

[0226] Output a fault location map, marking the coordinates (x, y) of high-risk areas.

[0227] S4 also includes:

[0228] S44, Optimization strategy encapsulation and execution: Integrate the outputs of S41 - S43, generate an aging test optimization strategy, and execute the optimization strategy. S41 outputs new electrical and thermodynamic stress conditions, S42 outputs updated life prediction model parameters and new MTTF estimation results, and S43 outputs fault identification and warning results, including possible fault types, fault warning signals, and fault location maps. The steps are as follows:

[0229] (1) Strategy instruction encoding:

[0230] Convert V new , into a control instruction set for programmable power supplies and temperature control devices;

[0231] Package the MTTF prediction result and the fault warning signal into a JSON format report;

[0232] (2) Dynamic loading and execution:

[0233] Write the instruction set into the S21 test environment configuration module of Claim 3 in real time through the FPGA control bus

[0234] When a fault warning is detected, automatically activate the S23 protection mechanism;

[0235] S45, Policy Effect Feedback and Iteration: Verify the effectiveness of the optimization policy and dynamically correct it, specifically including:

[0236] (1) Effect evaluation indicators:

[0237] Test efficiency improvement rate:

[0238] Prediction error reduction rate:

[0239] Fault missed alarm rate:

[0240] (2) Parameter iteration rules:

[0241] If the prediction error > 10%, trigger the S36 feature re-extraction process;

[0242] If the fault missed alarm rate > 5%, optimize the S34 sensitivity factor weight.

[0243] The present invention covers any substitutions, modifications, equivalent methods and solutions made within the spirit and scope of the present invention. For the public to have a thorough understanding of the present invention, specific details are described in detail in the following preferred embodiments of the present invention, and those skilled in the art can fully understand the present invention without these detailed descriptions. In addition, well-known methods, processes, procedures, components and circuits are not described in detail to avoid unnecessary confusion to the essence of the present invention.

[0244] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A method for chip aging test and analysis, characterized in that, It includes the following steps: S1: Generate a chip aging parameter matrix, which includes a set of reference electrical parameters, a set of dynamic thermodynamic parameters, and a set of process deviation parameters. The set of process deviation parameters is obtained by calculating the wafer-level test data and the parameter offset after packaging; S2: Dynamically configure the test environment based on the aging parameter matrix, perform a multi-stress collaborative loading test, and collect test data packets, which include transient electrical signal waveforms, thermal imaging distribution maps, and leakage current spectra; S3: Conduct a parameter coupling feature analysis on the test data packets, and extract aging feature vectors with cross-dimensional correlation characteristics. The aging feature vectors include electrical-thermal coupling coefficients, process deviation sensitivity factors, and non-linear decay indices; S4: Generate an aging test optimization strategy based on the aging feature vectors. The strategy includes a dynamic adjustment plan for test conditions, an update instruction for the parameters of the life prediction model, and the identification results of potential failure modes.

2. The method for chip aging test and analysis according to claim 1, wherein The S1 includes: S11, Acquisition of wafer-level test data: Before wafer dicing, use an integrated optical measurement sensor array to perform in-situ scanning on each chip to obtain wafer-level test data, which includes the measured values of wafer size, thin film thickness distribution, and doping concentration gradient; S12, Detection of parameter offset after packaging: After the chip packaging is completed, deploy a multi-modal sensing system to detect the parameter offset and obtain the parameter offset after packaging; S13, Calculation of the set of process deviation parameters: Generate a set of process deviation parameters based on the obtained wafer-level test data and the parameter offset after packaging.

3. The method for chip aging test and analysis according to claim 2, wherein The S1 further includes: S14, Generation of dynamic parameter sets: Based on the set of process deviation parameters, dynamically generate test parameter benchmarks, including a set of reference electrical parameters and a set of dynamic thermodynamic parameters; S15, Construction of the aging parameter matrix: Integrate the outputs of S11 - S14 into a chip aging parameter matrix.

4. The method for chip aging test and analysis according to claim 3, characterized in that, The S2 includes: S21, Loading and parsing of the aging parameter matrix: Based on the generated three-dimensional aging parameter matrix, perform space-time parameter matching and dynamic environment configuration; S22, Generation of multi-stress control signals: Generate collaborative loading control signals based on the parsed parameter sets, including electrical stress signals and thermodynamic stress signals; S23, Execution of multi-stress collaborative loading test: Use a closed-loop feedback mechanism to perform multi-stress loading.

5. A method for chip aging test and analysis according to claim 4, characterized in that The S2 further includes: S24, Acquisition of multi-source test data: Synchronously collect test data packets through a heterogeneous sensing system; S25, Encapsulation and verification of test data packets: Perform space-time alignment and integrity verification on the test data packets, and then encapsulate them.

6. The method for chip aging test and analysis according to claim 5, characterized in that The S3 includes: S31, Space-time alignment and noise reduction of multi-source test data: For the encapsulated test data packets, perform data preprocessing to generate a preprocessed data set. The preprocessing includes space-time reference unification and data noise reduction; S32, Feature extraction: Extract three types of basic features from the preprocessed data set, including electrical features, thermal features, and process deviation features; S33, Calculation of electrical-thermal coupling coefficients: Based on the extracted electrical features and thermal features, establish a quantitative model for electro-thermal interaction.

7. A method for chip aging test and analysis according to claim 6, characterized in that, The S3 further includes: S34, Process Deviation Sensitivity Factor Modeling: Quantify the impact of process deviations based on process deviation characteristics and the process deviation parameter set; S35, Nonlinear Decay Index Calculation: Identify the nonlinear aging effect based on the outputs of S32 - S34; S36, Aging Feature Vector Synthesis and Verification: Integrate the outputs of S33 - S35 to generate the aging feature vector.

8. A method for chip aging test and analysis according to claim 7, characterized in that, The said S4 includes: S41, Generation of Test Condition Dynamic Adjustment Scheme: Dynamically optimize the test conditions based on the generated aging feature vector; S42, Update of Life Prediction Model Parameters: Update the core parameters of the prediction model using the aging feature vector; S43, Identification of Potential Failure Modes: Based on the feature vector matching the predefined fault template library, trigger a fault warning according to the matching result.

9. A method for chip aging test and analysis according to claim 8, characterized in that, The said S4 further includes: S44, Encapsulation and Execution of Optimization Strategy: Integrate the outputs of S41 - S43 to generate an aging test optimization strategy and execute the optimization strategy; S45, Feedback and Iteration of Strategy Effect: Verify the effectiveness of the optimization strategy and dynamically correct it.

Images