Chip temperature regulation and control system and method

Abstract

The invention relates to the technical field of chip temperature control, and discloses a chip temperature regulation and control system and method, and the method comprises the steps: building a thermal field dynamic model, integrating real-time power consumption data and environment heat dissipation parameters, and generating a thermal resistance adjustment coefficient and a power consumption correction coefficient; establishing a temperature prediction network to perform multi-source temperature field prediction; a dynamic regulation and control strategy is set according to a prediction result, and heat dissipation control parameters are optimized to achieve thermal field balance control; and executing feedback calibration and model iteration. The system comprises a thermal field dynamic modeling module, a multi-source temperature field prediction module, a dynamic regulation and control strategy execution module, a feedback calibration module and an iteration module. The method can accurately predict the heat distribution of the chip, realizes real-time and intelligent temperature regulation and control, improves the performance and reliability of the chip, reduces the energy consumption, and has good adaptability and universality.

Description

Technical Field

[0001] The present invention relates to the technical field of chip temperature control, and in particular to a chip temperature control system and method. Background Art

[0002] In modern electronics, chips are core components whose performance and reliability directly impact the operation of the entire electronic system. As chip integration continues to increase and their functionality becomes increasingly complex, the heat generated by chips during operation is rapidly increasing. Failure to effectively control chip temperature can lead to a series of serious problems.

[0003] On the one hand, excessively high temperatures can lead to degraded chip performance. The electron migration rate of transistors within a chip increases with rising temperature, causing the transistor's threshold voltage to drift, which in turn affects the chip's logical operations and data processing speed. For example, in high-performance computing chips, when the temperature exceeds a certain threshold, the calculation error rate increases significantly, resulting in inaccurate calculation results and seriously affecting system efficiency. When artificial intelligence chips perform complex neural network calculations, excessively high temperatures can slow the chip's processing speed, making it unable to meet real-time requirements, reducing the responsiveness of AI applications and the user experience.

[0004] On the other hand, prolonged exposure to high temperatures can significantly shorten the lifespan of chips. High temperatures accelerate the aging and damage of chip materials. For example, chip packaging materials can crack and delaminate at high temperatures, damaging the chip's electrical connections and ultimately causing chip failure. Statistics show that for every 10°C increase in chip operating temperature, its reliability decreases by approximately 50%. For high-end chips, this not only means increased hardware costs but also high system maintenance and replacement costs. For data centers, for example, the frequent replacement of large numbers of server chips can lead to significant increases in operating costs, impacting the data center's economic efficiency and service stability.

[0005] Currently, traditional chip cooling methods mostly rely on fixed cooling strategies, such as fixed-speed fans or passive heat sinks. These methods lack the flexibility to adapt to the chip's real-time operating status and environmental changes. When the chip load is low, the fixed-speed fan continues to run at high speed, wasting energy and generating high noise levels, impacting the device's operating environment. However, when the chip load suddenly increases, these fixed cooling measures may not dissipate the heat quickly enough, causing the chip temperature to rise rapidly and making stable operation impossible.

[0006] Furthermore, existing temperature control solutions also have shortcomings in temperature prediction. They often rely solely on simple temperature sensor data, failing to fully consider the complex operating parameters of each chip's internal cores and the combined impact of environmental heat dissipation factors. This leads to inaccurate temperature predictions and the inability to implement effective cooling measures in advance, further exacerbating the risk of chip overheating. In summary, existing chip temperature control technologies are no longer able to meet the growing demand for high-performance chip cooling. A more intelligent, precise, and efficient chip temperature control system and method is urgently needed. Summary of the Invention

[0007] The object of the present invention is to provide a chip temperature control system and method to solve the problems raised in the above background technology.

[0008] To achieve the above-mentioned object, the present invention provides the following technical solution: a wind turbine bolt loosening early warning method, the method comprising:

[0009] Constructing a thermal field dynamic model, including creating a multi-physics field coupled simulation model based on the chip's physical structure and heat dissipation components; the thermal field dynamic model integrates real-time power consumption data and environmental heat dissipation parameters to generate a thermal resistance adjustment factor and a power consumption correction factor; the environmental heat dissipation parameters include heat sink efficiency, ambient temperature, and airflow rate;

[0010] Performing multi-source temperature field prediction includes establishing a temperature prediction network and obtaining thermal distribution prediction results by inputting multi-dimensional chip operating parameters and environmental heat dissipation parameters into the temperature prediction network; the multi-dimensional chip operating parameters include current, voltage, operating frequency, and thermal resistance of each core;

[0011] Setting a dynamic control strategy, including executing the dynamic control strategy according to the heat distribution prediction result output by the temperature prediction network; the dynamic control strategy includes real-time optimization of heat dissipation control parameters to achieve thermal field balance control;

[0012] Performing feedback calibration and model iteration; the feedback calibration includes periodically collecting chip surface temperature distribution data;

[0013] The calculation formula of the thermal resistance adjustment coefficient is:

[0014]

[0015] Among them, R adj (t) is the thermal resistance adjustment coefficient at time t, α is the thermal resistance basic correction amount, β i is the power consumption impact weight of the i-th core, P i (t) is the real-time power consumption of the ith core, P ref is the reference power consumption threshold, γ is the nonlinear correction index, δ is the ambient temperature difference coefficient, Tenv (t) is the real-time difference between the ambient temperature and the radiator temperature.

[0016] Preferably, the construction of the thermal field dynamic model includes: using COMSOL Multiphysics software to simulate the heat conduction and convection processes inside the chip; constructing a neural network sub-model related to power consumption and thermal resistance through TensorFlow; and using finite element analysis to dynamically optimize the heat diffusion path of the heat dissipation component.

[0017] Preferably, the integrated environmental heat dissipation parameters include synchronizing radiator efficiency data and airflow sensor data into the thermal field dynamic model in real time, and dynamically adjusting the radiator working mode; the airflow sensor data is collected through a micro-electromechanical system.

[0018] Preferably, the calculation formula of the power consumption correction coefficient is:

[0019]

[0020] Among them, P corr (t) is the power consumption correction coefficient at time t, η is the frequency-power consumption conversion factor, λ j is the frequency weight of the jth core, f j (t) is the real-time operating frequency of the j-th core, f max is the maximum allowable frequency, μ is the temperature attenuation coefficient, T j (t) is the real-time temperature of the jth core.

[0021] Preferably, the multi-dimensional chip operating parameters are synchronously collected by a chip built-in sensor and an external infrared thermal imager; and the thermal resistance value is dynamically calculated based on the thermal conductivity of the chip material and the packaging structure.

[0022] Preferably, the training process of the temperature prediction network includes:

[0023] Data collection: 10,000 sets of historical operating data are obtained from the chip control unit, including the current, voltage, frequency, temperature of each core and the working status of the heat sink;

[0024] Data annotation: annotate the thermal field distribution map corresponding to the historical operation data;

[0025] Feature extraction: performing sliding window mean filtering on the current and voltage data; normalizing the frequency data and converting it to a logarithmic scale; and performing Gaussian filtering on the temperature data for denoising.

[0026] Constructing a graph neural network: using each chip core as a graph node, the thermal coupling relationship between cores as the edge weight, inputting the feature-extracted data, and outputting the thermal field distribution prediction result;

[0027] An adversarial training strategy is used to optimize the graph neural network, and boundary condition data is generated by generating adversarial networks to enhance the generalization ability of the model.

[0028] Preferably, the prediction process of the temperature prediction network includes:

[0029] Input layer: receives real-time current, voltage, frequency and radiator efficiency data;

[0030] Graph structure construction layer: Generates a dynamic graph structure based on chip topology relationships, and node attributes include the operating parameters of each core;

[0031] Graph convolution layer: Aggregates the thermal coupling features of adjacent nodes through multi-layer graph convolution operations;

[0032] Attention mechanism layer: calculates the thermal influence weights between cores and dynamically adjusts the feature propagation path;

[0033] Output layer: Generates the chip's global temperature field distribution matrix and hotspot area probability map.

[0034] Preferably, the dynamic control strategy includes a heat dissipation control algorithm based on reinforcement learning, which learns the coordinated strategy of heat sink speed, voltage adjustment and core frequency limitation through a Q-Learning model; the reward function of the algorithm is defined as:

[0035]

[0036] Among them, ω k is the temperature penalty coefficient of the kth region, T safe is the safety temperature threshold, ρ is the power consumption change penalty factor, and ΔP(t) is the total power consumption change rate.

[0037] Preferably, the model iteration includes: updating the parameters of the thermal field dynamic model using an online Bayesian optimization method based on feedback calibration data, and retraining the graph convolution kernel weights of the temperature prediction network.

[0038] Preferably, the present invention further includes a chip temperature control system, the system comprising:

[0039] Thermal field dynamic modeling module, used to build thermal field dynamic models, create multi-physics field coupling simulation models based on the chip's physical structure and heat dissipation components, integrate real-time power consumption data and environmental heat dissipation parameters including heat sink efficiency, ambient temperature, and airflow rate, and generate thermal resistance adjustment coefficients and power consumption correction coefficients;

[0040] A multi-source temperature field prediction module is used to establish a temperature prediction network, input multi-dimensional chip operating parameters including current, voltage, operating frequency and thermal resistance of each core and environmental heat dissipation parameters into the temperature prediction network, and obtain thermal distribution prediction results;

[0041] A dynamic control strategy execution module is used to execute a dynamic control strategy based on the heat distribution prediction result output by the temperature prediction network, and optimize the heat dissipation control parameters in real time to achieve thermal field balance control;

[0042] Feedback calibration and iteration module, used to periodically collect chip surface temperature distribution data, perform feedback calibration and model iteration;

[0043] The calculation formula of the thermal resistance adjustment coefficient is:

[0044]

[0045] Among them, R adj (t) is the thermal resistance adjustment coefficient at time t, α is the thermal resistance basic correction amount, β i is the power consumption impact weight of the i-th core, P i (t) is the real-time power consumption of the ith core, P ref is the reference power consumption threshold, γ is the nonlinear correction index, δ is the ambient temperature difference coefficient, T env (t) is the real-time difference between the ambient temperature and the radiator temperature.

[0046] Compared with the prior art, the present invention has the following beneficial effects:

[0047] The present invention comprehensively considers multiple factors such as the chip's physical structure, heat dissipation component characteristics, real-time power consumption data, multi-dimensional chip operating parameters, and environmental heat dissipation parameters by constructing a thermal field dynamic model and a multi-source temperature field prediction network. By using COMSOL Multiphysics software to simulate the internal heat conduction and convection processes of the chip, combined with the power consumption-thermal resistance correlation neural network sub-model constructed by TensorFlow, the chip's thermal field characteristics can be accurately analyzed. At the same time, the multi-source temperature field prediction network achieves accurate prediction of the chip's thermal distribution through in-depth analysis of multi-dimensional data. Based on this, the dynamic control strategy can optimize the heat dissipation control parameters, such as radiator speed, voltage, and core frequency, in real time according to the prediction results, to ensure that the temperature of each area of ​​the chip is always maintained within a reasonable range, avoiding local overheating or overcooling, and greatly improving the accuracy of chip temperature control.

[0048] Precise temperature control effectively solves the problem of chip performance degradation caused by excessive temperature. By adjusting the heat dissipation strategy in real time, the chip can operate stably under different load conditions, reducing the occurrence of transistor threshold voltage drift and calculation errors, and improving the chip's logical operation and data processing speed. In high-performance computing scenarios. Traditional fixed heat dissipation strategies have the problem of energy waste, while the dynamic control strategy of the present invention can adjust the heat dissipation power according to the actual needs of the chip. When the chip load is low and the temperature is not high, the radiator speed is automatically reduced or other heat dissipation parameters are adjusted to reduce energy consumption.

[0049] The present invention features a feedback calibration and model iteration mechanism. By periodically collecting chip surface temperature distribution data, it uses an online Bayesian optimization method to update the parameters of the thermal field dynamic model and retrain the graph convolution kernel weights of the temperature prediction network. This enables the system to continuously adapt to changes in the chip's operating state and environment, such as chip aging and ambient temperature fluctuations. Over time, the system's temperature control performance not only does not decline, but instead improves through continuous learning and optimization, always maintaining optimal control results and providing a continuously stable operating environment for the chip.

[0050] This chip temperature control system and method are highly versatile and are not limited to specific chip models or electronic device types. Whether it's a single-core chip or a complex multi-core chip, whether it's used in consumer electronics or industrial control equipment, the technical solution of the present invention can be applied for effective temperature control. Precise temperature control can be achieved by simply adjusting and optimizing the thermal field dynamic model and temperature prediction network based on the physical structure and operating parameters of different chips, demonstrating broad application prospects and market value. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 This is a working principle diagram of the chip temperature control method of the present invention;

[0052] Figure 2 Working principle diagram for integration of ambient heat dissipation parameters;

[0053] Figure 3 Diagram showing the steps for collecting multi-dimensional chip operating parameters and calculating thermal resistance values;

[0054] Figure 4 Diagram of the temperature prediction network training process. DETAILED DESCRIPTION

[0055] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0056] See also Figure 1-4 The present invention provides a technical solution: a chip temperature control method, the method comprising:

[0057] Build a dynamic thermal field model: Create a multi-physics coupled simulation model based on the chip's physical structure and heat dissipation components. This model integrates real-time power consumption data and environmental heat dissipation parameters, such as heat sink efficiency, ambient temperature, and airflow rate, to generate thermal resistance adjustment coefficients and power consumption correction factors. The calculation formula for the thermal resistance adjustment coefficient is:

[0058]

[0059] Among them, R adj (t) is the thermal resistance adjustment coefficient at time t, α is the thermal resistance basic correction amount, β i is the power consumption impact weight of the i-th core, P i (t) is the real-time power consumption of the ith core, P ref is the reference power consumption threshold, γ is the nonlinear correction index, δ is the ambient temperature difference coefficient, T env (t) is the real-time difference between the ambient temperature and the heat sink temperature. This model comprehensively considers the impact of the chip's internal physical structure, the characteristics of the heat sink components, and external environmental factors on the chip's thermal field, providing basic data support for subsequent temperature control.

[0060] Multi-source temperature field prediction: A temperature prediction network is established and multi-dimensional chip operating parameters (current, voltage, operating frequency, and thermal resistance of each core) and environmental cooling parameters are input into the network to obtain thermal distribution prediction results. These operating and environmental parameters are collected from multiple sources to comprehensively reflect the chip's operating status and external environmental conditions, making temperature predictions more accurate. By analyzing and processing this data, the prediction network can estimate the chip's thermal distribution in advance, providing a basis for timely regulatory measures.

[0061] Set a dynamic control strategy: Based on the heat distribution predictions output by the temperature prediction network, a dynamic control strategy is implemented. This strategy optimizes cooling control parameters in real time to achieve thermal field balance. By dynamically adjusting cooling control parameters such as radiator speed, voltage, and core frequency, the temperature of each chip region remains within a reasonable range, preventing local overheating or overcooling and improving overall chip performance and stability.

[0062] Perform feedback calibration and model iteration: Periodically collect chip surface temperature distribution data for feedback calibration. Based on this feedback calibration data, optimize and adjust the thermal field dynamics model and temperature prediction network. For example, online Bayesian optimization methods are used to update the parameters of the thermal field dynamics model and retrain the graph convolution kernel weights of the temperature prediction network. This allows the model and network to continuously adapt to changes in the chip's operating status and environment, improving the accuracy and reliability of temperature control.

[0063] Example 1:

[0064] This embodiment describes in detail the construction process of the thermal field dynamic model. By combining multiple technical means, the accuracy of the model in simulating the chip thermal field is improved, providing a reliable model basis for subsequent precise temperature control.

[0065] Use COMSOL Multiphysics software to simulate the heat conduction and convection processes inside the chip. COMSOL Multiphysics is a powerful multi-physics simulation software. It is based on the finite element method and can accurately solve the control equations of various physical fields. When simulating heat conduction inside the chip, the thermal parameters such as thermal conductivity and specific heat capacity of different materials are defined according to the physical structure of the chip. For example, for the silicon-based material of the chip, its thermal conductivity and specific heat capacity are set. Through these parameters, the software can accurately calculate the heat conduction path and rate inside the chip. When simulating the convection process, the heat dissipation channels inside the chip and the flow of the surrounding air are considered. According to the actual heat dissipation design, the geometry and size of the heat dissipation channels and the boundary conditions such as air flow rate and temperature are set. Through simulation, the heat transfer process inside the chip can be intuitively observed, providing detailed data for analyzing the thermal characteristics of the chip.

[0066] A neural network sub-model for the power consumption-thermal resistance correlation is constructed using TensorFlow. TensorFlow is a widely used deep learning framework with powerful computing power and flexible model building capabilities. First, a large amount of chip power consumption and thermal resistance data is collected. This data includes the power consumption of each chip core under different operating conditions and the corresponding thermal resistance measurements. This data is preprocessed and divided into training, validation, and test sets. When constructing the neural network, an appropriate network structure is selected, such as a multi-layer perceptron (MLP). The MLP consists of an input layer, hidden layers, and an output layer. The input layer receives power consumption data for each chip core. The hidden layers extract and transform the data using nonlinear activation functions. The output layer outputs the corresponding thermal resistance predictions. During training, the mean squared error (MSE) is used as the loss function, and the network weights and biases are continuously adjusted through the backpropagation algorithm to minimize the error between the model's predicted values ​​and the actual thermal resistance values. After multiple iterations of training, the model learns the complex relationship between power consumption and thermal resistance, improving the accuracy of thermal resistance predictions.

[0067] Finite element analysis is used to dynamically optimize the heat diffusion path of the heat dissipation component. Finite element analysis is a numerical calculation method that discretizes the heat dissipation component into a finite number of units and obtains the heat distribution of the entire component by solving the heat conduction equation of the units. When modeling the heat dissipation component, its material properties, geometry, and boundary conditions are carefully considered. For example, for a metal heat sink, the thermal conductivity is determined based on its material. Through finite element analysis, the temperature distribution and heat diffusion path inside the heat dissipation component under different operating conditions can be calculated. Based on the analysis results, the structure of the heat dissipation component is optimized, such as adjusting parameters such as the shape, spacing, and height of the heat dissipation fins. Through multiple optimization iterations, the heat diffusion path of the heat dissipation component is made more reasonable, the heat dissipation efficiency is improved, and the temperature of the chip is reduced.

[0068] Example 2:

[0069] Heat sink efficiency data and airflow sensor data are synchronized in real time with the thermal field dynamic model to dynamically adjust the heat sink operating mode. Heat sink efficiency data is collected using specialized sensors installed at key locations on the heat sink to monitor the heat dissipation performance in real time. For example, by measuring the temperature difference between the heat sink inlet and outlet and the air flow through the heat sink, the heat dissipation power and, consequently, the heat sink efficiency are calculated. Airflow sensor data is collected using microelectromechanical systems (MEMS). MEMS technology offers the advantages of small size, low power consumption, and high accuracy, enabling precise measurement of parameters such as air flow rate and pressure. In practical applications, MEMS airflow sensors are installed in the chip's cooling duct to collect real-time airflow rate data. This data is transmitted to the thermal field dynamic model in real time via data transmission interfaces such as SPI (Serial Peripheral Interface) or I2C (Integrated Circuit Bus). The thermal field dynamic model dynamically adjusts the heat sink operating mode based on the received heat sink efficiency and airflow sensor data. When a decrease in heat sink efficiency or airflow rate is detected, the model can issue instructions to increase the heat sink speed or adjust the fan angle to enhance cooling. In this way, the thermal field dynamic model can adjust the model parameters in real time according to the actual environmental heat dissipation conditions, thereby improving the accuracy and timeliness of temperature control.

[0070] Example 3:

[0071] This embodiment describes in detail the calculation method of the power consumption correction coefficient and the method of obtaining related parameters, so that the power consumption correction coefficient can more accurately reflect the actual operation of the chip, provide more accurate data support for the thermal field dynamic model, and thus optimize the temperature control strategy.

[0072] The calculation formula for the power consumption correction factor is:

[0073]

[0074] Among them, P corr (t) is the power consumption correction coefficient at time t, η is the frequency-power consumption conversion factor, λ j is the frequency weight of the jth core, f j (t) is the real-time operating frequency of the j-th core, f max is the maximum allowable frequency, μ is the temperature attenuation coefficient, T j (t) is the real-time temperature of the jth core.

[0075] Multi-dimensional chip operating parameters are collected synchronously using built-in sensors and an external infrared thermal imager. The built-in sensors can accurately measure parameters such as current, voltage, and operating frequency of each core. These built-in sensors transmit the measurement data to the chip's control unit via an internal bus. The external infrared thermal imager measures the temperature distribution on the chip surface, thereby obtaining the real-time temperature T of each core. j (t). Infrared thermal imagers offer advantages such as non-contact operation, a wide measurement range, and fast response speed, enabling rapid and accurate acquisition of chip surface temperature information. By enabling data communication between the infrared thermal imager and the chip control unit, synchronous temperature data acquisition is achieved.

[0076] The thermal resistance value is dynamically calculated based on the thermal conductivity of the chip material and the packaging structure. The thermal conductivity of the chip material is one of the key factors affecting thermal resistance, and different chip materials have different thermal conductivities. For example, the thermal conductivity of silicon material is within a certain temperature range. The thermal resistance value is calculated using the heat conduction theory formula based on the chip packaging structure, such as the chip size and shape, as well as the thermal conductivity of the packaging material. During chip operation, the thermal conductivity of the chip material and the thermal characteristics of the packaging structure will also change due to changes in the chip's operating state and ambient temperature. Therefore, it is necessary to dynamically update the thermal resistance calculation results based on real-time monitoring data to ensure the accuracy of the thermal resistance value and provide reliable data support for the calculation of the power consumption correction factor.

[0077] Example 4:

[0078] The training process of the temperature prediction network is as follows:

[0079] ① Data Collection: 10,000 sets of historical operating data were collected from the chip control unit, including current, voltage, frequency, temperature, and heat sink operating status for each core. This data covers chip operation under different operating conditions, providing a rich sample for model training. During the data collection process, we ensured data accuracy and completeness, conducted preliminary quality checks on the collected data, and eliminated abnormal data.

[0080] ② Data annotation: Label the thermal field distribution map corresponding to historical operating data. The thermal field distribution map can intuitively reflect the temperature distribution of the chip at different times. The thermal field distribution map is generated using professional thermal imaging equipment or simulation software, and is associated with the corresponding historical operating data and annotated as label data for training the model.

[0081] ③ Feature extraction: Perform sliding window mean filtering on the current and voltage data. Sliding window mean filtering is a commonly used signal processing method. By sliding a fixed-length window on the data sequence, the average value of the data in the window is calculated to smooth the data and remove noise interference. For example, the length of the sliding window is set to X data points, and the current data I(t) is subjected to sliding window mean filtering. The filtered current data I filtered The calculation formula for (t) is:

[0082]

[0083] Normalize the frequency data and convert it to a logarithmic scale. Normalization can map frequency data of different ranges to the same interval, which is convenient for model training. Use the minimum-maximum normalization method to normalize the frequency data f(t) to the interval [0,1]. The calculation formula is:

[0084]

[0085] Among them, f min and f max are the minimum and maximum values ​​of the frequency data respectively. Then, the normalized frequency data is converted to a logarithmic scale to highlight the details of the frequency change. The converted frequency data f log (t) is:

[0086] f log (t) = log(1 + f normalized (t))

[0087] Gaussian filtering is used to denoise the temperature data. Gaussian filtering is a linear smoothing filtering method based on the Gaussian function, which can effectively remove Gaussian noise in the data.

[0088] ④ Construct a graph neural network: take each core of the chip as a graph node, the thermal coupling relationship between the cores as the edge weight, input the data after feature extraction, and output the thermal field distribution prediction result. Graph neural networks can effectively process data with complex topological structures and are suitable for analyzing the thermal coupling relationship between the cores of the chip. When constructing a graph neural network, the thermal coupling relationship between the cores is determined based on the physical structure and thermal conduction characteristics of the chip. For example, the thermal conductivity coefficient C between core i and core j is obtained through experimental measurement or theoretical analysis. ij , which is used as the edge weight. The graph neural network uses multi-layer graph convolution operations to extract and fuse features of the input data, gradually learning the distribution pattern of the chip thermal field.

[0089] ⑤ Use adversarial training strategy to optimize graph neural network: Generate boundary condition data through generative adversarial network to enhance the generalization ability of the model. Generative adversarial network (GAN) consists of generator and discriminator. The generator is used to generate boundary condition data, which simulates the operation of the chip under different boundary conditions, such as different ambient temperatures, radiator efficiency, etc. The discriminator is used to distinguish between generated data and real training data. During the training process, the generator and the discriminator compete with each other and continuously optimize their respective parameters. The generator generates more realistic boundary condition data by learning the distribution of real data. These data are added to the training set, enabling the graph neural network to learn more sample features, improve the generalization ability of the model, and enable it to accurately predict the thermal field distribution under different operating conditions. The prediction process of the temperature prediction network is as follows:

[0090] ⑥ Input layer: Receives real-time current, voltage, frequency, and heat sink efficiency data. This data is collected in real time by on-chip and external sensors and transmitted to the input layer of the temperature prediction network. The input layer preprocesses this data, such as normalizing it, to ensure it meets the network's input requirements.

[0091] ⑦ Graph Construction Layer: Generates a dynamic graph structure based on the chip topology, with node attributes containing the operating parameters of each core. The chip topology describes the connectivity and physical location relationships between the chip's cores. Based on chip design documents or actual measurements, the chip topology is obtained. In the graph construction layer, each core is treated as a graph node, and edge connections and weights are determined based on the inter-core connectivity and thermal coupling strength. Furthermore, each core's operating parameters, such as current, voltage, and frequency, are used as node attributes to construct a dynamic graph structure. This allows the graph structure to reflect the operating status of each chip core in real time.

[0092] ⑧ Graph Convolution Layer: Aggregates the thermal coupling features of adjacent nodes through multiple layers of graph convolution operations. Graph convolution is a core operation in graph neural networks. It performs convolution operations on node features on a graph structure, extracting feature information about the node and its neighbors. In the graph convolution layer, multiple layers of graph convolution operations are used to gradually aggregate the thermal coupling features of adjacent nodes. Each layer of graph convolution operations learns thermal field features at different levels, from local features to global features, enabling the model to more comprehensively understand the distribution of the chip's thermal field.

[0093] ⑨ Attention mechanism layer: Calculates the thermal influence weights between cores and dynamically adjusts feature propagation paths. The attention mechanism dynamically assigns weights based on the correlations between different nodes, highlighting the features of important nodes. In the temperature prediction network, the attention mechanism layer calculates the thermal influence weights between cores based on the operating parameters and thermal coupling relationships of each core. It assigns higher weights to core pairs with greater thermal influence, facilitating feature propagation towards these cores. This dynamically adjusts feature propagation paths and improves the model's prediction accuracy for hotspots.

[0094] ⑩ Output layer: Generates a global chip temperature distribution matrix and a hotspot probability map. After processing by the previous layers, the output layer converts the learned feature information into final prediction results. The global chip temperature distribution matrix intuitively displays the predicted temperature values ​​at each chip location, providing detailed data support for temperature control. The hotspot probability map represents the probability of each chip region becoming a hotspot, helping users quickly locate potential hotspots and take proactive cooling measures.

[0095] Example 5:

[0096] The dynamic control strategy includes a reinforcement learning-based heat dissipation control algorithm that uses a Q-Learning model to learn a coordinated strategy for heat sink speed, voltage adjustment, and core frequency limiting. Q-Learning is a value-function-based reinforcement learning algorithm that learns the Q-values ​​of state-action pairs and selects the optimal action to maximize cumulative rewards. In this embodiment, the chip's temperature and power consumption are used as inputs to the Q-Learning model, while heat sink speed adjustment, voltage adjustment, and core frequency limiting are used as the model's actions.

[0097] The design of the reward function comprehensively considers two key factors: chip temperature and power consumption. When the chip temperature exceeds the safe temperature threshold, the temperature penalty term increases, incentivizing the model to take actions to reduce the temperature. When the rate of change in total power consumption is large, the power consumption change penalty term increases to avoid over-adjustment that could lead to large fluctuations in power consumption. During training, the Q-Learning model selects an action based on the current state, observes the new state and the reward obtained after executing the action, and learns the optimal heat dissipation control strategy by continuously iteratively updating the Q value. For example, when the model detects that the temperature of a certain area of ​​the chip is close to the safe temperature threshold and the rate of change in total power consumption is small, it may choose to appropriately increase the heat sink speed instead of adjusting the core frequency, in order to minimize the impact on chip performance while controlling the temperature.

[0098] Model iteration involves updating the parameters of the thermal field dynamics model using online Bayesian optimization based on feedback calibration data, and retraining the graph convolution kernel weights of the temperature prediction network. During chip operation, the feedback calibration and iteration module periodically collects chip surface temperature distribution data. This data is acquired using high-precision temperature sensors evenly distributed at key locations on the chip surface, ensuring that the collected data accurately reflects the overall chip temperature.

[0099] Online Bayesian optimization is an optimization algorithm based on Bayes' theorem. It treats the parameters of the thermal field dynamic model as random variables and updates the probability distribution of these parameters by continuously observing and feeding back calibration data. For example, parameters such as the thermal resistance base correction and the weight of each core's power consumption in the thermal resistance adjustment coefficient calculation formula can be updated through online Bayesian optimization.

[0100] For the temperature prediction network, the graph convolution kernel weights are retrained. Based on newly collected temperature distribution data and other relevant operating parameters, the graph convolution kernel weights are updated using the backpropagation algorithm. During training, the error between the predicted temperature and the actual collected temperature is used as the loss function, and the weights are adjusted to minimize this loss function.

[0101] In actual application scenarios, such as chipsets in high-performance computing servers, the chip temperature control system and method of the present invention play an important role. During the long-term operation of the server, the chip load is constantly changing, and the ambient temperature may also fluctuate. The thermal resistance adjustment coefficient and power consumption correction coefficient are generated in real time through the thermal field dynamic modeling module, the multi-source temperature field prediction module predicts the chip thermal distribution in advance, and the dynamic control strategy execution module adjusts the heat dissipation control parameters in time according to the prediction results, such as adjusting the server cooling fan speed, chip power supply voltage and core frequency. At the same time, the feedback calibration and iteration module continuously collects temperature data for calibration and model iteration to ensure that the entire temperature control system always maintains efficient operation, ensures that the chip works within a stable temperature range, improves the performance and stability of the server, and reduces the risk of system failure due to overheating.

[0102] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus.

[0103] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A chip temperature control method, characterized in that: include: Constructing a thermal field dynamic model, including creating a multi-physics field coupled simulation model based on the chip's physical structure and heat dissipation components; the thermal field dynamic model integrates real-time power consumption data and environmental heat dissipation parameters to generate a thermal resistance adjustment factor and a power consumption correction factor; the environmental heat dissipation parameters include heat sink efficiency, ambient temperature, and airflow rate; Performing multi-source temperature field prediction includes establishing a temperature prediction network and obtaining thermal distribution prediction results by inputting multi-dimensional chip operating parameters and environmental heat dissipation parameters into the temperature prediction network; the multi-dimensional chip operating parameters include current, voltage, operating frequency, and thermal resistance of each core; Setting a dynamic control strategy, including executing the dynamic control strategy according to the heat distribution prediction result output by the temperature prediction network; the dynamic control strategy includes real-time optimization of heat dissipation control parameters to achieve thermal field balance control; Performing feedback calibration and model iteration; the feedback calibration includes periodically collecting chip surface temperature distribution data; The calculation formula of the thermal resistance adjustment coefficient is: in, R adj (t) is the thermal resistance adjustment coefficient at time t, α is the thermal resistance basic correction value, β i is the power consumption impact weight of the i-th core, P i (t) is the real-time power consumption of the i-th core, P ref is the reference power consumption threshold, γ is the nonlinear correction index, δ is the ambient temperature difference coefficient, T env (t) is the real-time difference between the ambient temperature and the radiator temperature.

2. A chip temperature control method according to claim 1, characterized in that: The construction of the thermal field dynamic model includes: using COMSOL Multiphysics software to simulate the heat conduction and convection processes inside the chip; building a neural network sub-model related to power consumption and thermal resistance through TensorFlow; and using finite element analysis to dynamically optimize the heat diffusion path of the heat dissipation component.

3. The chip temperature control method according to claim 1, characterized in that: The integrated environmental heat dissipation parameters include synchronizing radiator efficiency data and airflow sensor data into the thermal field dynamic model in real time, and dynamically adjusting the radiator working mode; the airflow sensor data is collected by a micro-electromechanical system.

4. A chip temperature control method according to claim 1, characterized in that: The calculation formula of the power consumption correction coefficient is: in, P corr (t) is the power consumption correction coefficient at time t, η is the frequency-power conversion factor, λ j is the frequency weight of the j-th core, f j (t) is the real-time operating frequency of the j-th core, f max is the maximum allowable frequency, μ is the temperature attenuation coefficient, T j (t) is the real-time temperature of the jth core.

5. The chip temperature control method according to claim 1, characterized in that: The multi-dimensional chip operating parameters are collected synchronously by the chip's built-in sensor and the external infrared thermal imager; The thermal resistance value is dynamically calculated based on the thermal conductivity of the chip material and the packaging structure.

6. The chip temperature control method according to claim 1, characterized in that: The training process of the temperature prediction network includes: Data collection: 10,000 sets of historical operating data are obtained from the chip control unit, including the current, voltage, frequency, temperature of each core and the working status of the heat sink; Data annotation: annotate the thermal field distribution map corresponding to the historical operation data; Feature extraction: performing sliding window mean filtering on the current and voltage data; normalizing the frequency data and converting it to a logarithmic scale; and performing Gaussian filtering on the temperature data for denoising. Constructing a graph neural network: using each chip core as a graph node, the thermal coupling relationship between cores as the edge weight, inputting the feature-extracted data, and outputting the thermal field distribution prediction result; An adversarial training strategy is used to optimize the graph neural network, and boundary condition data is generated by generating adversarial networks to enhance the generalization ability of the model.

7. A chip temperature control method according to claim 6, characterized in that: The prediction process of the temperature prediction network includes: Input layer: receives real-time current, voltage, frequency and radiator efficiency data; Graph structure construction layer: Generates a dynamic graph structure based on chip topology relationships, and node attributes include the operating parameters of each core; Graph convolution layer: Aggregates the thermal coupling features of adjacent nodes through multi-layer graph convolution operations; Attention mechanism layer: calculates the thermal influence weights between cores and dynamically adjusts the feature propagation path; Output layer: Generates the chip's global temperature field distribution matrix and hotspot area probability map.

8. The chip temperature control method according to claim 1, characterized in that: The dynamic control strategy includes a reinforcement learning-based heat dissipation control algorithm that uses a Q-Learning model to learn the coordinated strategy of heat sink speed, voltage adjustment, and core frequency limit. The reward function of the algorithm is defined as: in, ωk is the temperature penalty coefficient of the kth region, T safe is the safety temperature threshold, ρ is the power consumption change penalty factor, ΔP( t ) is the total power consumption change rate.

9. The chip temperature control method according to claim 1, characterized in that: The model iteration includes: updating the parameters of the thermal field dynamic model using an online Bayesian optimization method based on feedback calibration data, and retraining the graph convolution kernel weights of the temperature prediction network.

10. A chip temperature control system, characterized in that: include: Thermal field dynamic modeling module, used to build thermal field dynamic models, create multi-physics field coupling simulation models based on the chip's physical structure and heat dissipation components, integrate real-time power consumption data and environmental heat dissipation parameters including heat sink efficiency, ambient temperature, and airflow rate, and generate thermal resistance adjustment coefficients and power consumption correction coefficients; A multi-source temperature field prediction module is used to establish a temperature prediction network, input multi-dimensional chip operating parameters including current, voltage, operating frequency and thermal resistance of each core and environmental heat dissipation parameters into the temperature prediction network, and obtain thermal distribution prediction results; A dynamic control strategy execution module is used to execute a dynamic control strategy based on the heat distribution prediction result output by the temperature prediction network, and optimize the heat dissipation control parameters in real time to achieve thermal field balance control; Feedback calibration and iteration module, used to periodically collect chip surface temperature distribution data, perform feedback calibration and model iteration; The calculation formula of the thermal resistance adjustment coefficient is: in, R adj (t) is the thermal resistance adjustment coefficient at time t, α is the thermal resistance basic correction value, β i is the power consumption impact weight of the i-th core, P i (t) is the real-time power consumption of the i-th core, P ref is the reference power consumption threshold, γ is the nonlinear correction index, δ is the ambient temperature difference coefficient, T env (t) is the real-time difference between the ambient temperature and the radiator temperature.

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