Low dropout regulator

Abstract

The invention provides a low-dropout linear voltage regulator. The low-dropout linear voltage regulator comprises a voltage output end, a charge pump circuit used for providing stable high voltage and a voltage stabilization control loop. The voltage stabilization control loop comprises an NMOS output tube and an NFET. The control end of the NMOS output tube NFET is electrically connected with the charge pump circuit, and the output end of the NMOS output tube NFET is connected with the voltage output end. According to the invention, the voltage stabilization control loop adopts an NMOS output tube as an output power tube, so that the power supply rejection ratio of the linear voltage regulator is improved, and the response speed of the whole circuit is accelerated. In addition, a charge pump circuit is added, and the charge pump circuit is used for controlling the control end voltage of the NMOS power tube, so that the output voltage of the voltage stabilization control loop is adjusted. In this way, the design difficulty of an internal circuit of the output power tube is lowered, the overall small-size structure of the low dropout linear regulator is achieved, and meanwhile cost is lowered.

Description

Background Art

[0002] In the circuit design of low-dropout linear regulators, PMOS tubes are more often used as output power tubes to reduce the minimum input voltage. However, in order to improve performance and load capacity, the design often sacrifices area, which means that larger output power tubes and compensation capacitors are required.

[0003] refer to Figure 1 , is a circuit diagram of an existing low-dropout linear regulator. The low-dropout linear regulator controls the gate voltage of the output power tube by designing an error amplifier to ensure the stability of the voltage output. In addition, the commonly used output power tube is a PMOS tube. In order to achieve high PSRR (Power Supply Rejection Ratio) and high response speed, the internal circuit design is more complicated and requires a larger compensation capacitor. In addition, in order to achieve low voltage difference and other performance, the size of the PMOS power tube needs to be increased, which not only leads to a larger size of the overall low-dropout linear regulator, but also leads to an increase in cost. Despite this, the PSRR and response speed have not yet reached the ideal level. Summary of the invention

[0004] The present application provides a low-dropout linear regulator that aims to achieve high PSRR and high response speed while reducing size and cost.

[0005] The present application provides a low voltage dropout linear regulator, comprising: Voltage output terminal; A charge pump circuit for providing a stable high voltage; A voltage stabilization control loop, the voltage stabilization control loop comprising an NMOS output tube NFET; a control end of the NMOS output tube NFET is electrically connected to the charge pump circuit, and an output end of the NMOS output tube NFET is connected to the voltage output end; The control terminal voltage of the NMOS output tube NFET is controlled by the charge pump circuit to adjust the output voltage of the voltage stabilization control loop.

[0006] In the above technical solution, the voltage regulation control loop uses NMOS output tube as the output power tube, thereby improving the power supply rejection ratio of the linear regulator and accelerating the response speed of the overall circuit. In addition, by adding a charge pump circuit, the charge pump circuit is used to control the control terminal voltage of the NMOS power tube, thereby adjusting the output voltage of the voltage regulation control loop. This not only reduces the design difficulty of the internal circuit of the output power tube, but also realizes the overall small size structure of the low voltage difference linear regulator, while reducing the cost.

[0007] Optionally, the voltage stabilization control loop further includes a reference voltage terminal for providing a reference voltage, an error amplifier unit and a source follower; Wherein, the input end of the error amplifier unit is connected to the voltage output end and the reference voltage end, and is used to compare the output voltage of the voltage output end with the reference voltage to generate an error amplification signal; The control end of the source follower is connected to the output end of the error amplifier and the charge pump circuit, and the output end of the source follower is connected to the control end of the NMOS output tube, which is used to isolate the high output impedance output by the error amplifier unit and the high input capacitance input by the charge pump circuit to the NMOS output tube.

[0008] Optionally, the voltage regulation control loop also includes a feedback unit for providing a feedback voltage; the feedback unit includes a first feedback resistor RFB1, a second feedback resistor RFB2 and a feedback node FB, wherein the first feedback resistor RFB1 and the second feedback resistor RFB2 are sequentially connected in series between the output end of the NMOS output tube and the ground, and the feedback node FB is located between the first feedback resistor RFB1 and the second feedback resistor RFB2.

[0009] Optionally, the error amplifier unit includes: A first amplifier OP1, wherein a positive phase input terminal of the first amplifier OP1 is connected to a reference voltage terminal VREF, and a negative phase input terminal of the first amplifier OP1 is connected to the feedback node FB; A second amplifier OP2, wherein a positive phase input terminal and a negative phase input terminal of the second amplifier OP2 are respectively connected to the first amplifier OP1; A first NMOS transistor NM0, wherein a gate of the first NMOS transistor NM0 is connected to the output end of the second amplifier OP2, a drain of the first NMOS transistor NM0 is connected to the control end of the source follower, and a source of the first NMOS transistor NM0 is connected to the input end of the source follower.

[0010] Optionally, the voltage regulation control loop further includes a compensation unit, which is connected to the error amplifier unit and the output end of the NMOS output tube NFET and is used to compensate for the frequency of the output voltage output by the NMOS output tube.

[0011] Optionally, the compensation unit includes a Miller compensation capacitor C1 and a feedback capacitor Cfb, one end of the Miller compensation capacitor C1 is connected to the gate of the first NMOS tube NM0, and the other end is connected to the output end of the NMOS output tube NFET; one end of the feedback capacitor Cfb is connected to the output end of the NMOS output tube NFET, and the other end is connected to the negative phase input end of the first amplifier.

[0012] Optionally, the low voltage drop linear regulator also includes a clamping circuit, which is connected to the voltage output end, the charge pump circuit, the error amplifier unit and the source follower, and is used to clamp the voltage output from the charge pump circuit and the error amplifier unit to the control end of the source follower, the voltage of the control end of the NMOS output tube NFET, and is used to drive the NMOS output tube NFET to turn on.

[0013] Optionally, the low voltage difference linear regulator further includes a voltage input terminal; the clamping circuit includes a first resistor R1, a second resistor R2, a second NMOS tube NM1, a third NMOS tube NM2, a fourth NMOS tube NM3, a fifth NMOS tube NM5, a third resistor R4, a sixth NMOS tube NM4, and a seventh NMOS tube NM7; Wherein, a first end of the first resistor R1 is electrically connected to an output end of the charge pump circuit, and a second end of the first resistor R1 is electrically connected to a first end of the second resistor R2; The source of the second NMOS transistor NM1 is connected to the voltage output terminal, the drain is electrically connected to the source of the third NMOS transistor NM2, and the gate is short-circuited with its drain; The gate of the third NMOS transistor NM2 is electrically connected to the gate of the fourth NMOS transistor NM3, and the drain is connected to the second end of the second resistor R2 and short-circuits the gate thereof; The drain of the fourth NMOS transistor NM3 is connected to the source of the fifth NMOS transistor NM5, and the source is connected to the control end of the source follower through the third resistor R4; The gate of the fifth NMOS transistor NM5 is connected between the first resistor R1 and the second resistor R2, and the drain is connected to the output end of the charge pump circuit; The drain of the sixth NMOS transistor NM4 is connected to the output end of the charge pump circuit, the gate is connected to the voltage input end, and the source is connected to the source of the seventh NMOS transistor NM7; The drain of the seventh NMOS transistor NM7 is connected to the input end of the source follower, and the gate and the drain are short-circuited.

[0014] Optionally, the low voltage dropout linear regulator further includes a driving circuit, wherein the driving circuit is connected to the charge pump circuit, the clamping circuit, the source follower and the NMOS output tube NFET, and is used to drive the NMOS output tube to conduct.

[0015] Optionally, the driving circuit includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3 and a fourth resistor R3; The source of the second PMOS transistor PM2 is electrically connected to the output end of the charge pump circuit, the gate of the second PMOS transistor PM2 is electrically connected to the gate of the third PMOS transistor PM3, the drain is short-circuited with the gate and electrically connected to the gate of the first PMOS transistor PM1 and the drain of the sixth NMOS transistor NM4 through the fourth resistor R3; The source of the third PMOS transistor PM3 is electrically connected to the output end of the charge pump circuit, and the drain of the third PMOS transistor PM3 is electrically connected to the source of the first PMOS transistor PM1; The drain of the first PMOS transistor PM1 is connected to the control end of the NMOS output transistor NFET. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a circuit diagram of an existing linear voltage regulator; Figure 2 A circuit block diagram of a low voltage dropout linear regulator according to an embodiment of the present application; Figure 3 A circuit block diagram of another low voltage dropout linear regulator according to an embodiment of the present application; Figure 4 for Figure 3 The specific circuit diagram of the low voltage drop linear regulator of the embodiment of the present application is shown; Figure 5 for Figure 3 A circuit diagram of a charge pump circuit in a low voltage drop linear regulator according to an embodiment of the present application is shown; Figure 6 for Figure 5 The basic operation waveform diagram of the charge pump circuit of an embodiment of the present application is shown.

[0017] Among them, 1-charge pump circuit, 2-voltage regulation control loop, 3-error amplifier unit, 4-feedback unit, 5-compensation unit, 6-clamping circuit, 7-driving circuit, 8-voltage conversion unit. DETAILED DESCRIPTION

[0018] The present application is further described in detail below through the accompanying drawings and embodiments. Through these descriptions, the characteristics and advantages of the present application will become clearer and more specific.

[0019] The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise noted.

[0020] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0021] The low voltage drop linear regulator in the prior art controls the gate voltage of the output power tube by designing an error amplifier to ensure the stability of the voltage output. In addition, the commonly used output power tube is a PMOS tube. In order to achieve a high power supply rejection ratio and a high response speed, the internal circuit design is relatively complex and requires a larger compensation capacitor. In addition, in order to achieve low voltage drop and other performance, the size of the PMOS power tube needs to be increased, which not only leads to a larger size of the overall low voltage drop linear regulator, but also leads to an increase in cost. Despite this, the power supply rejection ratio and response speed still fail to reach the ideal level.

[0022] To this end, the embodiment of the present application provides a low-voltage dropout linear regulator, which improves the power supply rejection ratio of the linear regulator and speeds up the response speed of the overall circuit by adopting an NMOS output tube as an output power tube. In addition, by adding a charge pump circuit, the charge pump circuit is used to control the control terminal voltage of the NMOS power tube, thereby adjusting the output voltage of the voltage regulation control loop. This not only reduces the design difficulty of the internal circuit of the output power tube, but also realizes the overall small-size structure of the low-voltage dropout linear regulator, while achieving cost reduction and not increasing the minimum input voltage. The technical solution of the present application is described in detail below through specific embodiments combined with the accompanying drawings.

[0023] refer to Figure 2 As shown, the embodiment of the present application provides a low voltage difference linear regulator, including a voltage output terminal VOUT, a charge pump circuit 1 for providing a stable high voltage, and a voltage stabilization control loop 2. The voltage stabilization control loop 2 includes an NMOS output tube NFET; the control terminal NFET_G of the NMOS output tube NFET is electrically connected to the charge pump circuit 1, and the output terminal of the NMOS output tube NFET is connected to the voltage output terminal VOUT. The control terminal voltage of the NMOS output tube NFET is controlled by the charge pump circuit 1 to adjust the output voltage of the voltage stabilization control loop 2, thereby ensuring the stability of the output voltage.

[0024] In this embodiment, the voltage stabilization control loop 2 uses an NMOS output tube NFET as an output power tube. The voltage of the control terminal NFET_G of the NMOS output tube NFET is dynamically adjusted according to the feedback signal of the output voltage, which can ensure that the output voltage of the voltage output terminal VOUT is maintained at the set value, thereby achieving the stability of the output voltage. In this scheme, the NMOS output tube has a higher transconductance (gm) and a lower output resistance (Ron), which can effectively suppress the noise and interference from the input power supply, thereby improving the power supply rejection ratio and response speed of the linear regulator. For example, when the circuit frequency is 100KHz, the power supply rejection ratio can reach 50dB; or when the circuit frequency is 1MHz, the power supply rejection ratio can reach 40dB. The response speed can reach 1us. In addition, a charge pump circuit 1 is added and combined with the NMOS output power tube NFET. The charge pump circuit 1 is used to provide a stable high voltage to increase the variation range of the control terminal voltage of the NMOS output power tube NFET. In this way, while realizing the low voltage drop characteristic of the linear regulator, the design difficulty of the internal circuit of the output power tube can be reduced, which is beneficial to reducing the size of the output power tube (W / L=7000um / 0.6um), and realizing the overall small size structure and cost reduction of the low voltage drop linear regulator, and will not increase the minimum input voltage.

[0025] like Figure 3 As shown, in a specific implementation scheme, the voltage regulation control loop 2 also includes a reference voltage terminal VREF for providing a reference voltage, an error amplifier unit 3 and a source follower PM0. The input terminal of the error amplifier unit 3 is connected to the voltage output terminal VOUT and the reference voltage terminal VREF, and is used to compare the output voltage of the voltage output terminal VOUT with the reference voltage to generate an error amplification signal; the control terminal of the source follower PM0 is connected to the output terminal of the error amplifier 3 and the charge pump circuit 1, and the output terminal of the source follower PM0 is connected to the control terminal NFET_G of the NMOS output tube NFET, and is used to isolate the high output impedance output by the error amplifier unit 3 and the high input capacitance input by the charge pump circuit 1 to the NMOS output tube NFET.

[0026] In this embodiment, the error amplifier unit 3 is used to compare the output voltage with the reference voltage to generate an error signal, and amplify the error signal so as to have sufficient driving capability to control the subsequent NMOS output tube NFET. The source follower PM0 is a PMOS tube with a low input impedance, which can effectively absorb the high output impedance of the error amplifier unit 3, thereby reducing the impact on the subsequent circuit. At the same time, the source follower PM0 can also prevent the charge pump circuit 1 from inputting high input capacitance to the NMOS output tube NFET to maintain the output stability of the NMOS output tube NFET.

[0027] like Figure 4 As shown, in a specific implementation scheme, the error amplifier unit 3 includes a first amplifier OP1, a second amplifier OP2 and a first NMOS tube NM0. Among them, the positive phase input terminal of the first amplifier OP1 is connected to the reference voltage terminal VREF, and the negative phase input terminal of the first amplifier OP1 is connected to the feedback node FB. The positive phase input terminal and the negative phase input terminal of the second amplifier OP2 are respectively connected to the first amplifier OP1. The gate of the first NMOS tube NM0 is connected to the output terminal of the second amplifier OP2, the drain is connected to the control terminal of the source follower, and the source is connected to the input terminal of the source follower.

[0028] In this embodiment, the first amplifier OP1, the second amplifier OP2 and the first NMOS transistor NM0 form a basic error amplifier structure. Specifically, the difference between the feedback voltage and the reference voltage is compared by the first amplifier OP1, and then amplified to generate an error amplified voltage; the error amplified voltage is further processed by the second amplifier OP2 to provide additional gain, filtering or phase adjustment, so that the circuit has better stability and faster response speed. The first NMOS transistor NM0 is used as a power output tube, and is turned on or off by the output end of the second amplifier OP2.

[0029] Combination Figure 3 , Figure 4 As shown, in a specific implementation scheme, the voltage regulation control loop 2 also includes a feedback unit 4 for providing a feedback voltage; the feedback unit 4 includes a first feedback resistor RFB1, a second feedback resistor RFB2 and a feedback node FB, wherein the first feedback resistor RFB1 and the second feedback resistor RFB2 are sequentially connected in series between the output end of the NMOS output tube and the ground, and the feedback node FB is located between the first feedback resistor RFB1 and the second feedback resistor RFB2, and is connected to the voltage output end VOUT.

[0030] In this embodiment, the feedback unit 4 generates a feedback voltage according to the output voltage of the voltage output terminal VOUT, and forms a feedback loop with the error amplifier unit 3, the source follower PM0 and the NMOS output tube NFET. When the output voltage of the voltage output terminal VOUT is less than the set value, the corresponding feedback voltage decreases, and the error amplifier unit 3 detects the difference between the feedback voltage and the reference voltage and amplifies it, so that the output current decreases, so that the voltage of the control terminal SF_G of the source follower PM0 increases, and then the voltage of the control terminal NFET_G of the NMOS output tube NFET increases accordingly, and finally the output voltage of the voltage output terminal VOUT returns to the set value; when the output voltage of the voltage output terminal VOUT is greater than the set value, the corresponding feedback voltage decreases and increases, and the error amplifier unit 3 detects the difference between the feedback voltage and the reference voltage and amplifies it, so that the output current increases, so that the voltage of the control terminal SF_G of the source follower PM0 decreases, and then the voltage of the control terminal NFET_G of the NMOS output tube NFET decreases accordingly, and finally the output voltage of the voltage output terminal VOUT returns to the set value.

[0031] In some embodiments, the setting value is: VREF*(RFB1+RFB2) / RFB2.

[0032] In a specific implementation scheme, the voltage regulation control loop 2 further includes a compensation unit 5, which is connected to the error amplifier unit 3 and the output end of the NMOS output tube NFET, and is used to compensate for the frequency of the output voltage output by the NMOS output tube NFET. In this embodiment, by providing the compensation unit 5, the error amplifier unit 3 can be kept stable at high frequencies, thereby compensating for the frequency of the output voltage output by the NMOS output tube NFET, and improving the load transient response speed.

[0033] In a specific implementation scheme, the compensation unit 5 includes a Miller compensation capacitor C1 and a feedback capacitor Cfb, one end of the Miller compensation capacitor C1 is connected to the gate of the first NMOS tube NM0, and the other end is connected to the output end of the NMOS output tube NFET; one end of the feedback capacitor Cfb is connected to the output end of the NMOS output tube NFET, and the other end is connected to the negative phase input end of the first amplifier OP1.

[0034] Specifically, when the output voltage of the voltage output terminal VOUT changes, the change is transmitted to the gate of the first NMOS tube NM0 through the Miller compensation capacitor C1, thereby adjusting the voltage of the control terminal SF_G of the source follower PM0, and then adjusting the voltage of the control terminal NFET_G of the NMOS output tube NFET, so as to reduce the change of the output voltage of the voltage output terminal VOUT. At the same time, the change of the output voltage of the voltage output terminal VOUT is transmitted to the first amplifier OP1 through the feedback capacitor Cfb, and then through the second amplifier OP2, the first NMOS tube NM0 and the source follower PM0, so as to adjust the voltage of the control terminal NFET_G of the NMOS output tube NFET, so as to reduce the change of the output voltage of the voltage output terminal VOUT.

[0035] In this embodiment, when the output voltage of the voltage output terminal VOUT changes, a Miller compensation structure constructed by a Miller compensation capacitor C1 and a feedback capacitor Cfb is used to reduce the change in the output voltage, and the formed capacitance is 15pF, which is smaller than the size of the compensation capacitor used in the prior art, thereby reducing the overall size of the regulator, reducing the difficulty of circuit design, reducing costs, and having high reliability.

[0036] In some embodiments, the compensation unit 5 further includes a compensation resistor R0 and a zero adjustment resistor R5; the compensation resistor R0 and the zero adjustment resistor R5 are connected in series between the gate of the first NMOS transistor NM0 and the Miller compensation capacitor C1. The compensation resistor R0 and the zero adjustment resistor R5 provide partial negative feedback for the gate of the first NMOS transistor NM0, which is beneficial to the stability and linearity of the circuit.

[0037] In one possible implementation scheme, the low voltage difference linear regulator also includes a clamping circuit 6, which is connected to the voltage output terminal VOUT, the charge pump circuit 1, the error amplifier unit 3 and the source follower PM0, and is used to clamp the voltage output from the charge pump circuit 1 and the error amplifier unit 3 to the control terminal SF_G of the source follower PM0, the voltage of the control terminal NFET_G of the NMOS output tube NFET, and is used to drive the NMOS output tube NFET to turn on.

[0038] In this embodiment, since the charge pump circuit 1 provides a high voltage, if the charge pump circuit 1 is directly connected to the control terminal SF_G of the source follower PM0 and the control terminal NFET_G of the NMOS output tube NFET, it may cause overvoltage of the source follower PM0 and the NMOS output tube NFET. Therefore, a clamping circuit 6 is set to avoid damage to the source follower PM0 and the NMOS output tube.

[0039] In a specific implementation scheme, the low voltage difference linear regulator also includes a voltage input terminal PVCC. The clamping circuit 6 includes a first resistor R1, a second resistor R2, a second NMOS tube NM1, a third NMOS tube NM2, a fourth NMOS tube NM3, a fifth NMOS tube NM5, a third resistor R4, a sixth NMOS tube NM4, and a seventh NMOS tube NM7. Among them, the first end of the first resistor R1 is electrically connected to the output end of the charge pump circuit 1, and the second end of the first resistor R1 is electrically connected to the first end of the second resistor R2; the source of the second NMOS tube NM1 is connected to the voltage output terminal VOUT, the drain is electrically connected to the source of the third NMOS tube NM2, and the gate is short-circuited with its drain; the gate of the third NMOS tube NM2 is electrically connected to the gate of the fourth NMOS tube NM3, and the drain is connected to the second end of the second resistor R2 and its gate is short-circuited; the drain of the fourth NMOS tube NM3 is connected to the fifth The source of the NMOS tube NM5 is connected to the control end of the source follower PM0 through the third resistor R4; the gate of the fifth NMOS tube NM5 is connected between the first resistor R1 and the second resistor R2, and the drain is connected to the output end of the charge pump circuit 1; the drain of the sixth NMOS tube NM4 is connected to the output end of the charge pump circuit 1, the gate is connected to the voltage input end PVCC, and the source is connected to the source of the seventh NMOS tube NM7; the drain of the seventh NMOS tube NM7 is connected to the input end of the source follower PM0, and the gate and the drain are short-circuited.

[0040] In this embodiment, the first resistor R1 and the second resistor R2 are adaptive to the voltage drop generated by the voltage output terminal VOUT. At the same time, the voltage output terminal VOUT clamps the voltage of the control terminal SF_G of the source follower PM0 through the second NMOS transistor NM1, the third NMOS transistor NM2 and the fourth NMOS transistor NM3. The voltage value of the upper limit clamp is the sum of the voltage of the voltage output terminal VOUT and the gate-source voltage VGS of the second NMOS transistor NM1, which is specifically calculated according to the following formula: VOUT+VGS_NM1+VGS_NM2=V_SF_G+VGS_NM3; (1) VGS_NM1=VGS_NM2=VGS_NM3; (2) Among them, VOUT represents the voltage at the voltage output end; VGS_NM1 represents the gate-source voltage of the second NMOS tube NM1; VGS_NM2 represents the gate-source voltage of the third NMOS tube NM2; V_SF_G represents the voltage value of the upper limit clamping of the control end of the source follower PM0; VGS_NM3 represents the gate-source voltage of the fourth NMOS tube NM3.

[0041] Therefore, from formulas (1) and (2), we can obtain: V_SF_G=VOUT+VGS_NM1.

[0042] After the voltage at the control terminal SF_G of the source follower PM0 is clamped, the voltage at the control terminal NFET_G of the NMOS output tube NFET is clamped to an upper limit, and the voltage value of the upper limit clamping is the sum of the voltage at the voltage output terminal VOUT and twice the gate-source voltage VGS.

[0043] In one possible implementation, the low voltage difference linear regulator further includes a driving circuit 7, the driving circuit 7 is connected to the charge pump circuit 1, the clamping circuit, the source follower PM0 and the NMOS output tube NFET, and is used to drive the NMOS output tube NFET to turn on. In this embodiment, the driving circuit 7 is set to provide a sufficient driving signal for the NMOS output tube NFET, so that the NMOS output tube NFET can be turned on smoothly, ensuring that the subsequent circuit outputs a stable voltage.

[0044] In a specific implementation scheme, the driving circuit 7 includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3 and a fourth resistor R3. The source of the second PMOS transistor PM2 is electrically connected to the output end of the charge pump circuit 1, the gate of the second PMOS transistor PM2 is electrically connected to the gate of the third PMOS transistor PM3, the drain is short-circuited with its gate and electrically connected to the gate of the first PMOS transistor PM1 and the drain of the sixth NMOS transistor NM4 through the fourth resistor R3; the source of the third PMOS transistor PM3 is electrically connected to the output end of the charge pump circuit, the drain of the third PMOS transistor PM3 is electrically connected to the source of the first PMOS transistor PM1; the drain of the first PMOS transistor PM1 is connected to the control end NFET_G of the NMOS output transistor NFET. In this embodiment, the second PMOS transistor PM2 and the third PMOS transistor PM3 form a current mirror structure, and together with the first PMOS transistor PM1 and the fourth resistor R3, provide a pull-up driving current for the control end NFET_G of the NMOS output transistor NFET.

[0045] like Figure 4 As shown, in a specific implementation scheme, the voltage stabilization control loop 2 also includes a voltage conversion unit 8 and a control MOS tube NM6. The input end of the voltage conversion unit 8 is connected to the control end NFET_G of the NMOS output tube NFET, and is used to convert the current signal output by the NMOS output tube NFET into a voltage signal. The control end of the control MOS tube NM6 is connected to the output end of the voltage conversion unit 8, and the source and drain of the control MOS tube NM6 are respectively connected to the two ends of the compensation resistor R0, and are used to control the compensation resistor R0 according to the voltage signal.

[0046] In this embodiment, in order to ensure the stability of the voltage stabilization control loop 2 under different load conditions, the output current is detected and converted into the output voltage VSENSE through the voltage conversion unit 8, and the compensation resistor R0 is controlled by controlling the MOS tube NM6, thereby ensuring the stability of the voltage stabilization control loop 2.

[0047] like Figure 5 As shown, in a specific implementation scheme, the charge pump circuit 1 includes an eighth NMOS transistor MN11, a ninth NMOS transistor MN12, a fourth PMOS transistor MP21 and a fifth PMOS transistor MP22, wherein: The D terminal of the eighth NMOS tube MN11 is electrically connected to the voltage input terminal PVCC, the S terminal of the eighth NMOS tube MN11 is electrically connected to the G terminal of the ninth NMOS tube MN12, and the G terminal of the eighth NMOS tube MN11 is electrically connected to the S terminal of the fourth PMOS tube MP21; The D terminal of the ninth NMOS transistor MN12 is electrically connected to the voltage input terminal PVCC, and the S terminal of the ninth NMOS transistor MN12 is electrically connected to the S terminal of the fourth PMOS transistor MP21; the S terminal of the ninth NMOS transistor MN12 is electrically connected to the clock signal input negative phase terminal CLKN; The D terminal of the fourth PMOS transistor MP21 is electrically connected to the CP control signal output terminal VO_CP, and the G terminal of the fourth PMOS transistor MP21 is electrically connected to the clock signal input positive phase terminal CLK; The G terminal of the fifth PMOS tube MP22 is electrically connected to the S terminal of the fourth PMOS tube MP21, the S terminal of the fifth PMOS tube MP22 is electrically connected to the clock signal input positive phase terminal CLK, and the D terminal of the fifth PMOS tube MP22 is electrically connected to the CP control signal output terminal VO_CP.

[0048] The charge pump circuit further includes a first capacitor C10, a second capacitor C11 and a third capacitor C12, wherein: The first capacitor plate of the first capacitor C10 is electrically connected to the S terminal of the eighth NMOS transistor MN11, and the second capacitor plate of the first capacitor C10 is electrically connected to the clock signal input positive phase terminal CLK; The first capacitor plate of the second capacitor C11 is electrically connected to the voltage input terminal PVCC, and the second capacitor plate of the second capacitor C11 is electrically connected to the CP control signal output terminal VO_CP; The first capacitor plate of the third capacitor C12 is electrically connected to the S terminal of the ninth NMOS transistor MN12, and the second capacitor plate of the third capacitor C12 is electrically connected to the clock signal input negative phase terminal CLKN.

[0049] The charge pump mainly uses the charging and discharging characteristics of the capacitor to achieve voltage conversion or boosting. It is also called a switched capacitor voltage converter and is a DC-DC converter. The charge pump has the advantages of simple circuit, small size, high efficiency and low cost.

[0050] In this embodiment, Figure 6 As shown, when the potential of the clock signal input positive phase terminal CLK is low and the potential of the clock signal input negative phase terminal CLKN is high, the voltage V1 is charged to PVCC; when the clock signal input positive phase terminal CLK is high (PVCC), the voltage V1 rises to 2*PVCC, and at the same time, the CP control signal output terminal CO_CP is charged through the fifth PMOS tube MP22 to increase it to about 2*PVCC; at the same time, the voltage V2 is charged to PVCC; When the clock signal input negative phase terminal CLKN switches to high (PVCC), the voltage V2 rises to 2*PVCC, and at the same time, the CP control signal output terminal VO_CP is charged through the fourth PMOS tube MP21. This is repeated so that the voltage output by the charge pump circuit 1 is twice the voltage of the voltage input terminal PVCC, and is more stable than the voltage of the voltage input terminal PVCC.

[0051] Those skilled in the art will appreciate that the present application may be implemented as a system, method or computer program product.

[0052] Therefore, the present disclosure may be specifically implemented in the following forms, namely: it may be completely hardware, it may be completely software (including firmware, resident software, microcode, etc.), or it may be a combination of hardware and software, generally referred to herein as a "circuit", "module" or "system". In addition, in some embodiments, the present application may also be implemented in the form of a computer program product in one or more computer-readable media, and the computer-readable medium may contain computer-readable program code.

[0053] Any combination of one or more computer-readable media can be used. Computer-readable media can be computer-readable signal media or computer-readable storage media. Computer-readable storage media can be, for example, but not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any combination of the above. More specific examples (non-exhaustive list) of computer-readable storage media include: electrical connections with one or more wires, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above. In this document, computer-readable storage media can be any tangible medium containing or storing a program, which can be used by an instruction execution system, device or device or used in combination with it.

[0054] Although the embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and cannot be understood as limiting the present application. A person of ordinary skill in the art can change, modify, replace and modify the above embodiments within the scope of the present application. On this basis, a variety of replacements and improvements can be made to the present application, all of which fall within the scope of protection of the present application.

Claims

1. A low voltage dropout linear regulator, characterized in that: include: Voltage output terminal; A charge pump circuit for providing a stable high voltage; A voltage stabilization control loop, wherein the voltage stabilization control loop includes an NMOS output tube NFET; The control end of the NMOS output tube NFET is electrically connected to the charge pump circuit, and the output end of the NMOS output tube NFET is connected to the voltage output end; The control terminal voltage of the NMOS output tube NFET is controlled by the charge pump circuit to adjust the output voltage of the voltage stabilization control loop.

2. The low voltage dropout linear regulator according to claim 1, characterized in that: The voltage stabilization control loop further includes a reference voltage terminal for providing a reference voltage, an error amplifier unit and a source follower; Wherein, the input end of the error amplifier unit is connected to the voltage output end and the reference voltage end, and is used to compare the output voltage of the voltage output end with the reference voltage to generate an error amplification signal; The control end of the source follower is connected to the output end of the error amplifier and the charge pump circuit, and the output end of the source follower is connected to the control end of the NMOS output tube, which is used to isolate the high output impedance output by the error amplifier unit and the high input capacitance input by the charge pump circuit to the NMOS output tube.

3. The low voltage dropout linear regulator according to claim 2, characterized in that: The voltage regulation control loop also includes a feedback unit for providing a feedback voltage; the feedback unit includes a first feedback resistor RFB1, a second feedback resistor RFB2 and a feedback node FB, wherein the first feedback resistor RFB1 and the second feedback resistor RFB2 are sequentially connected in series between the output end of the NMOS output tube and the ground, and the feedback node FB is located between the first feedback resistor RFB1 and the second feedback resistor RFB2.

4. The low voltage dropout linear regulator according to claim 3, characterized in that: The error amplifier unit comprises: A first amplifier OP1, wherein a positive phase input terminal of the first amplifier OP1 is connected to a reference voltage terminal VREF, and a negative phase input terminal of the first amplifier OP1 is connected to the feedback node FB; A second amplifier OP2, wherein a positive phase input terminal and a negative phase input terminal of the second amplifier OP2 are respectively connected to the first amplifier OP1; A first NMOS transistor NM0, wherein a gate of the first NMOS transistor NM0 is connected to the output end of the second amplifier OP2, a drain of the first NMOS transistor NM0 is connected to the control end of the source follower, and a source of the first NMOS transistor NM0 is connected to the input end of the source follower.

5. The low voltage dropout linear regulator according to claim 4, characterized in that: The voltage regulation control loop further includes a compensation unit, which is connected to the error amplifier unit and the output end of the NMOS output tube NFET and is used to compensate for the frequency of the output voltage output by the NMOS output tube.

6. The low voltage dropout linear regulator according to claim 5, characterized in that: The compensation unit includes a Miller compensation capacitor C1 and a feedback capacitor Cfb, one end of the Miller compensation capacitor C1 is connected to the gate of the first NMOS tube NM0, and the other end is connected to the output end of the NMOS output tube NFET; one end of the feedback capacitor Cfb is connected to the output end of the NMOS output tube NFET, and the other end is connected to the negative phase input end of the first amplifier.

7. The low voltage dropout linear regulator according to claim 3, characterized in that: The low voltage difference linear regulator also includes a clamping circuit, which is connected to the voltage output terminal, the charge pump circuit, the error amplifier unit and the source follower, and is used to clamp the voltage output from the charge pump circuit and the error amplifier unit to the control terminal of the source follower, the voltage of the control terminal of the NMOS output tube NFET, and is used to drive the NMOS output tube NFET to turn on.

8. The low voltage dropout linear regulator according to claim 7, characterized in that: The low voltage difference linear regulator also includes a voltage input terminal; the clamping circuit includes a first resistor R1, a second resistor R2, a second NMOS tube NM1, a third NMOS tube NM2, a fourth NMOS tube NM3, a fifth NMOS tube NM5, a third resistor R4, a sixth NMOS tube NM4, and a seventh NMOS tube NM7; Wherein, a first end of the first resistor R1 is electrically connected to an output end of the charge pump circuit, and a second end of the first resistor R1 is electrically connected to a first end of the second resistor R2; The source of the second NMOS transistor NM1 is connected to the voltage output terminal, the drain is electrically connected to the source of the third NMOS transistor NM2, and the gate is short-circuited with its drain; The gate of the third NMOS transistor NM2 is electrically connected to the gate of the fourth NMOS transistor NM3, and the drain is connected to the second end of the second resistor R2 and short-circuits the gate thereof; The drain of the fourth NMOS transistor NM3 is connected to the source of the fifth NMOS transistor NM5, and the source is connected to the control end of the source follower through the third resistor R4; The gate of the fifth NMOS transistor NM5 is connected between the first resistor R1 and the second resistor R2, and the drain is connected to the output end of the charge pump circuit; The drain of the sixth NMOS transistor NM4 is connected to the output end of the charge pump circuit, the gate is connected to the voltage input end, and the source is connected to the source of the seventh NMOS transistor NM7; The drain of the seventh NMOS transistor NM7 is connected to the input end of the source follower, and the gate and the drain are short-circuited.

9. The low voltage dropout linear regulator according to claim 8, characterized in that: The low voltage drop linear regulator also includes a driving circuit, which is connected to the charge pump circuit, the clamp circuit, the source follower and the NMOS output tube NFET and is used to drive the NMOS output tube to conduct.

10. The low voltage dropout linear regulator according to claim 9, characterized in that: The driving circuit includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3 and a fourth resistor R3; The source of the second PMOS transistor PM2 is electrically connected to the output end of the charge pump circuit, the gate of the second PMOS transistor PM2 is electrically connected to the gate of the third PMOS transistor PM3, the drain is short-circuited with the gate and electrically connected to the gate of the first PMOS transistor PM1 and the drain of the sixth NMOS transistor NM4 through the fourth resistor R3; The source of the third PMOS transistor PM3 is electrically connected to the output end of the charge pump circuit, and the drain of the third PMOS transistor PM3 is electrically connected to the source of the first PMOS transistor PM1; The drain of the first PMOS transistor PM1 is connected to the control end of the NMOS output transistor NFET.

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