A low dropout linear regulator

Abstract

The present application provides a low dropout linear regulator, which includes a voltage output terminal, a charge pump circuit for providing a stable high voltage, and a voltage regulation control loop. The voltage regulation control loop includes an NMOS output transistor NFET. The control terminal of the NMOS output transistor NFET is electrically connected to the charge pump circuit, and the output terminal of the NMOS output transistor NFET is connected to the voltage output terminal. In the present invention, the voltage regulation control loop uses an NMOS output transistor as the output power transistor, thereby improving the power supply rejection ratio of the linear regulator and accelerating the response speed of the overall circuit. In addition, by adding a charge pump circuit, the control terminal voltage of the NMOS power transistor is controlled by the charge pump circuit, thereby regulating the output voltage of the voltage regulation control loop. This not only reduces the design difficulty of the internal circuit of the output power transistor, but also realizes the overall small-size structure of the low dropout linear regulator, and at the same time realizes the cost reduction.

Description

Background Art

[0002] In the circuit design of low-dropout linear regulators, more PMOS transistors are used as output power transistors to reduce the minimum input voltage. However, in order to improve performance and load-carrying capacity, the design often sacrifices area and other factors, which means that larger-sized output power transistors and compensation capacitors are required.

[0003] Reference Figure 1 is a circuit schematic diagram of an existing low-dropout linear regulator. This low-dropout linear regulator controls the gate voltage of the output power transistor by designing an error amplifier to ensure the stability of the voltage output. And, the commonly used output power transistor is a PMOS transistor. In order to achieve high PSRR (Power Supply Rejection Ratio) and high response speed, the internal circuit design is relatively complex and a larger compensation capacitor is required. In addition, in order to achieve performance such as low dropout, it is also necessary to increase the size of the PMOS power transistor, which not only results in a relatively large size of the overall low-dropout linear regulator but also leads to an increase in cost. Nevertheless, the PSRR and response speed still fail to reach the ideal level. Summary of the Invention

[0004] This application provides a low-dropout linear regulator aimed at achieving high PSRR and high response speed while reducing size and cost.

[0005] This application provides a low-dropout linear regulator, including:

[0006] A voltage output terminal;

[0007] A charge pump circuit for providing a stable high voltage;

[0008] A voltage regulation control loop, the voltage regulation control loop includes an NMOS output transistor NFET; the control end of the NMOS output transistor NFET is electrically connected to the charge pump circuit, and the output end of the NMOS output transistor NFET is connected to the voltage output terminal;

[0009] The control end voltage of the NMOS output transistor NFET is controlled by the charge pump circuit to adjust the output voltage of the voltage regulation control loop.

[0010] In the above technical solution, the voltage regulation control loop improves the power supply rejection ratio of the linear regulator and speeds up the response speed of the overall circuit by using an NMOS output transistor as the output power transistor. In addition, by adding a charge pump circuit, the control end voltage of the NMOS power transistor is controlled by the charge pump circuit to adjust the output voltage of the voltage regulation control loop. This not only reduces the design difficulty of the internal circuit of the output power transistor but also realizes the overall small-size structure of the low-dropout linear regulator and at the same time realizes the reduction of cost.

[0011] Optionally, the voltage stabilizing control loop further includes a reference voltage terminal for providing a reference voltage, an error amplifier unit, and a source follower;

[0012] Wherein, the input end of the error amplifier unit is connected to the voltage output end and the reference voltage terminal, and is configured to compare the output voltage of the voltage output end and the reference voltage to generate an error amplification signal;

[0013] The control end of the source follower is connected to the output end of the error amplifier and the charge pump circuit, and the output end of the source follower is connected to the control end of the NMOS output transistor, and is configured to isolate the high output impedance output by the error amplifier unit and the high input capacitance input from the charge pump circuit to the NMOS output transistor.

[0014] Optionally, the voltage stabilizing control loop further includes a feedback unit for providing a feedback voltage; the feedback unit includes a first feedback resistor RFB1, a second feedback resistor RFB2, and a feedback node FB. Wherein, the first feedback resistor RFB1 and the second feedback resistor RFB2 are sequentially connected in series between the output end of the NMOS output transistor and the ground, and the feedback node FB is located between the first feedback resistor RFB1 and the second feedback resistor RFB2.

[0015] Optionally, the error amplifier unit includes:

[0016] A first amplifier OP1, the positive input terminal of the first amplifier OP1 is connected to the reference voltage terminal VREF, and the negative input terminal of the first amplifier OP1 is connected to the feedback node FB;

[0017] A second amplifier OP2, the positive input terminal and the negative input terminal of the second amplifier OP2 are respectively connected to the first amplifier OP1;

[0018] A first NMOS transistor NM0, the gate of the first NMOS transistor NM0 is connected to the output end of the second amplifier OP2, the drain is connected to the control end of the source follower, and the source is connected to the input end of the source follower.

[0019] Optionally, the voltage stabilizing control loop further includes a compensation unit, and the compensation unit is connected to the output ends of the error amplifier unit and the NMOS output transistor NFET, and is configured to compensate the frequency of the output voltage output by the NMOS output transistor.

[0020] Optionally, the compensation unit includes a Miller compensation capacitor C1 and a feedback capacitor Cfb. One end of the Miller compensation capacitor C1 is connected to the gate of the first NMOS transistor NM0, and the other end is connected to the output terminal of the NMOS output transistor NFET. One end of the feedback capacitor Cfb is connected to the output terminal of the NMOS output transistor NFET, and the other end is connected to the negative input terminal of the first amplifier.

[0021] Optionally, the low dropout linear regulator further includes a clamping circuit. The clamping circuit is connected to the voltage output terminal, the charge pump circuit, the error amplifier unit, and the source follower, and is used to clamp the voltage output from the charge pump circuit and the error amplifier unit to the control terminal of the source follower, the voltage of the control terminal of the NMOS output transistor NFET, and is used to drive the NMOS output transistor NFET to conduct.

[0022] Optionally, the low dropout linear regulator further includes a voltage input terminal. The clamping circuit includes a first resistor R1, a second resistor R2, a second NMOS transistor NM1, a third NMOS transistor NM2, a fourth NMOS transistor NM3, a fifth NMOS transistor NM5, a third resistor R4, a sixth NMOS transistor NM4, and a seventh NMOS transistor NM7.

[0023] Wherein, the first end of the first resistor R1 is electrically connected to the output terminal of the charge pump circuit, and the second end of the first resistor R1 is electrically connected to the first end of the second resistor R2.

[0024] The source of the second NMOS transistor NM1 is connected to the voltage output terminal, the drain is electrically connected to the source of the third NMOS transistor NM2, and the gate is shorted to its drain.

[0025] The gate of the third NMOS transistor NM2 is electrically connected to the gate of the fourth NMOS transistor NM3, and the drain is connected to the second end of the second resistor R2 and shorted to its gate.

[0026] The drain of the fourth NMOS transistor NM3 is connected to the source of the fifth NMOS transistor NM5, and the source is connected to the control terminal of the source follower through the third resistor R4.

[0027] The gate of the fifth NMOS transistor NM5 is connected between the first resistor R1 and the second resistor R2, and the drain is connected to the output terminal of the charge pump circuit.

[0028] The drain of the sixth NMOS transistor NM4 is connected to the output terminal of the charge pump circuit, the gate is connected to the voltage input terminal, and the source is connected to the source of the seventh NMOS transistor NM7.

[0029] The drain of the seventh NMOS transistor NM7 is connected to the input terminal of the source follower, and its gate is shorted to its drain.

[0030] Optionally, the low dropout linear regulator further includes a driving circuit, which is connected to the charge pump circuit, the clamping circuit, the source follower, and the NMOS output transistor NFET, and is used to drive the NMOS output transistor to conduct.

[0031] Optionally, the driving circuit includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, and a fourth resistor R3;

[0032] Wherein, the source of the second PMOS transistor PM2 is electrically connected to the output terminal of the charge pump circuit, the gate of the second PMOS transistor PM2 is electrically connected to the gate of the third PMOS transistor PM3, its drain is shorted to its gate and is electrically connected to the gate of the first PMOS transistor PM1 and the drain of the sixth NMOS transistor NM4 through the fourth resistor R3;

[0033] The source of the third PMOS transistor PM3 is electrically connected to the output terminal of the charge pump circuit, and the drain of the third PMOS transistor PM3 is electrically connected to the source of the first PMOS transistor PM1;

[0034] The drain of the first PMOS transistor PM1 is connected to the control terminal of the NMOS output transistor NFET. Description of the Drawings

[0035] Figure 1 is a circuit schematic diagram of an existing linear regulator;

[0036] Figure 2 is a circuit block diagram of a low dropout linear regulator according to an embodiment of the present application;

[0037] Figure 3 is a circuit block diagram of another low dropout linear regulator according to an embodiment of the present application;

[0038] Figure 4 is Figure 3 the specific circuit diagram of the low dropout linear regulator according to the embodiment of the present application shown in;

[0039] Figure 5 is Figure 3 the circuit diagram of the charge pump circuit in the low dropout linear regulator according to the embodiment of the present application shown in;

[0040] Figure 6 is Figure 5 the basic operation waveform diagram of the charge pump circuit according to the embodiment of the present application shown in.

[0041] Among them, 1 - charge pump circuit, 2 - voltage regulation control loop, 3 - error amplifier unit, 4 - feedback unit, 5 - compensation unit, 6 - clamping circuit, 7 - drive circuit, 8 - voltage conversion unit. Specific embodiments

[0042] The present application will be further described in detail below with reference to the accompanying drawings and embodiments. Through these descriptions, the features and advantages of the present application will become more clearly defined.

[0043] The special term "exemplary" here means "serving as an example, embodiment, or illustrative". Any embodiment described as "exemplary" here does not have to be construed as superior to or better than other embodiments. Although various aspects of the embodiments are shown in the drawings, the drawings do not have to be drawn to scale unless otherwise specified.

[0044] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0045] The low-dropout linear regulator in the prior art controls the gate voltage of the output power transistor by designing an error amplifier to ensure the stability of the voltage output. And, the commonly used output power transistor is a PMOS transistor. In order to achieve a high power supply rejection ratio and a high response speed, the internal circuit design is relatively complex and a larger compensation capacitor is required. In addition, in order to achieve performance such as low dropout, it is also necessary to increase the size of the PMOS power transistor, which not only results in a larger overall size of the low-dropout linear regulator, but also increases the cost. Nevertheless, the power supply rejection ratio and the response speed still fail to reach the ideal level.

[0046] For this reason, the embodiments of the present application provide a low-dropout linear regulator, which uses an NMOS output transistor as the output power transistor, thereby improving the power supply rejection ratio of the linear regulator and accelerating the response speed of the overall circuit. In addition, by adding a charge pump circuit, the charge pump circuit is used to control the control terminal voltage of the NMOS power transistor, thereby adjusting the output voltage of the voltage regulation control loop. This not only reduces the design difficulty of the internal circuit of the output power transistor, but also realizes the overall small-size structure of the low-dropout linear regulator, while realizing cost reduction and not increasing the minimum input voltage. The technical solution of the present application will be described in detail below with reference to specific embodiments and the accompanying drawings.

[0047] Reference Figure 2As shown in the figure, an embodiment of the present application provides a low dropout linear regulator, which includes a voltage output terminal VOUT, a charge pump circuit 1 for providing a stable high voltage, and a voltage regulation control loop 2. Among them, the voltage regulation control loop 2 includes an NMOS output transistor NFET; the control terminal NFET_G of the NMOS output transistor NFET is electrically connected to the charge pump circuit 1, and the output terminal of the NMOS output transistor NFET is connected to the voltage output terminal VOUT. The control terminal voltage of the NMOS output transistor NFET is controlled by the charge pump circuit 1 to adjust the output voltage of the voltage regulation control loop 2, thereby ensuring the stability of the output voltage.

[0048] In this embodiment, the voltage regulation control loop 2 uses an NMOS output transistor NFET as the output power transistor. The control terminal voltage NFET_G of the NMOS output transistor NFET is dynamically adjusted according to the feedback signal of the output voltage, which can ensure that the output voltage of the voltage output terminal VOUT remains at the set value, thereby realizing the stability of the output voltage. In this solution, the NMOS output transistor has a relatively high transconductance (gm) and a relatively low output resistance (Ron), which can effectively suppress the noise and interference from the input power supply, so that the power supply rejection ratio and response speed of the linear regulator can be improved. For example, when the circuit frequency is 100KHz, the power supply rejection ratio can reach 50dB; or when the circuit frequency is 1MHz, the power supply rejection ratio can reach 40dB. The response speed can reach 1us. In addition, a charge pump circuit 1 is added, and the charge pump circuit 1 is combined with the NMOS output power transistor NFET. The charge pump circuit 1 is used to provide a stable high voltage to increase the change range of the control terminal voltage of the NMOS output power transistor NFET. In this way, while realizing the low dropout characteristic of the linear regulator, the design difficulty of the internal circuit of the output power transistor can be reduced, which is beneficial to reducing the size of the output power transistor (W / L = 7000um / 0.6um), and realizing the overall small size structure and cost reduction of the low dropout linear regulator without increasing the lowest input voltage.

[0049] Such as Figure 3As shown, in a specific feasible implementation, the voltage stabilizing control loop 2 further includes a reference voltage terminal VREF for providing a reference voltage, an error amplifier unit 3, and a source follower PM0. Among them, the input terminal of the error amplifier unit 3 is connected to the voltage output terminal VOUT and the reference voltage terminal VREF, and is used to compare the output voltage of the voltage output terminal VOUT and the reference voltage to generate an error amplification signal; the control terminal of the source follower PM0 is connected to the output terminal of the error amplifier 3 and the charge pump circuit 1, and the output terminal of the source follower PM0 is connected to the control terminal NFET_G of the NMOS output transistor NFET, and is used to isolate the high output impedance output by the error amplifier unit 3 and the high input capacitance input from the charge pump circuit 1 to the NMOS output transistor NFET.

[0050] In this embodiment, the error amplifier unit 3 is used to compare the output voltage and the reference voltage to generate an error signal and amplify the error signal so as to have sufficient driving ability to control the subsequent NMOS output transistor NFET. The source follower PM0 is a PMOS transistor with a low input impedance, which can effectively absorb the high output impedance of the error amplifier unit 3, thereby reducing the impact on the subsequent circuit. At the same time, the source follower PM0 can also prevent the high input capacitance input from the charge pump circuit 1 to the NMOS output transistor NFET to maintain the stability of the output of the NMOS output transistor NFET.

[0051] As Figure 4 shown, in a specific feasible implementation, the error amplifier unit 3 includes a first amplifier OP1, a second amplifier OP2, and a first NMOS transistor NM0. Among them, the positive input terminal of the first amplifier OP1 is connected to the reference voltage terminal VREF, and the negative input terminal of the first amplifier OP1 is connected to the feedback node FB. The positive input terminal and the negative input terminal of the second amplifier OP2 are respectively connected to the first amplifier OP1. The gate of the first NMOS transistor NM0 is connected to the output terminal of the second amplifier OP2, the drain is connected to the control terminal of the source follower, and the source is connected to the input terminal of the source follower.

[0052] In this embodiment, the first amplifier OP1, the second amplifier OP2, and the first NMOS transistor NM0 constitute a basic error amplifier structure. Specifically, the first amplifier OP1 compares the difference between the feedback voltage and the reference voltage and then amplifies it to generate an error amplification voltage; further, the second amplifier OP2 processes the error amplification voltage to provide additional gain, filtering, or phase adjustment, making the circuit more stable and having a faster response speed. The first NMOS transistor NM0 is used as a power output transistor and is controlled to conduct or cut off by the output terminal of the second amplifier OP2.

[0053] Combined withFigure 3 , Figure 4 As shown in Figure 4 , in a specific feasible embodiment, the voltage stabilization control loop 2 further includes a feedback unit 4 for providing a feedback voltage; the feedback unit 4 includes a first feedback resistor RFB1, a second feedback resistor RFB2, and a feedback node FB. Among them, the first feedback resistor RFB1 and the second feedback resistor RFB2 are sequentially connected in series between the output end of the NMOS output transistor and the ground, and the feedback node FB is located between the first feedback resistor RFB1 and the second feedback resistor RFB2 and is connected to the voltage output terminal VOUT.

[0054] In this embodiment, the feedback unit 4 generates a feedback voltage according to the output voltage of the voltage output terminal VOUT, and forms a feedback loop with the error amplifier unit 3, the source follower PM0, and the NMOS output transistor NFET. When the output voltage of the voltage output terminal VOUT is less than the set value, the corresponding feedback voltage decreases. The error amplifier unit 3 detects the difference between the feedback voltage and the reference voltage and amplifies it, so that the output current decreases. As a result, the voltage of the control terminal SF_G of the source follower PM0 increases, and then the voltage of the control terminal NFET_G of the NMOS output transistor NFET increases accordingly. Finally, the output voltage of the voltage output terminal VOUT returns to the set value; when the output voltage of the voltage output terminal VOUT is greater than the set value, the corresponding feedback voltage increases. The error amplifier unit 3 detects the difference between the feedback voltage and the reference voltage and amplifies it, so that the output current increases. As a result, the voltage of the control terminal SF_G of the source follower PM0 decreases, and then the voltage of the control terminal NFET_G of the NMOS output transistor NFET decreases accordingly. Finally, the output voltage of the voltage output terminal VOUT returns to the set value.

[0055] In some embodiments, the set value is: VREF*(RFB1 + RFB2) / RFB2.

[0056] In a specific feasible embodiment, the voltage stabilization control loop 2 further includes a compensation unit 5. The compensation unit 5 is connected to the output end of the error amplifier unit 3 and the NMOS output transistor NFET, and is used to compensate the frequency of the output voltage output by the NMOS output transistor NFET. In this embodiment, by setting the compensation unit 5, the error amplifier unit 3 can be kept stable at high frequencies, thereby compensating the frequency of the output voltage output by the NMOS output transistor NFET and improving the load transient response speed.

[0057] In a specific feasible embodiment, the compensation unit 5 includes a Miller compensation capacitor C1 and a feedback capacitor Cfb. One end of the Miller compensation capacitor C1 is connected to the gate of the first NMOS transistor NM0, and the other end is connected to the output end of the NMOS output transistor NFET. One end of the feedback capacitor Cfb is connected to the output end of the NMOS output transistor NFET, and the other end is connected to the negative-phase input end of the first amplifier OP1.

[0058] Specifically, when the output voltage of the voltage output terminal VOUT changes, the change is transmitted to the gate of the first NMOS transistor NM0 through the Miller compensation capacitor C1, thereby adjusting the voltage of the control terminal SF_G of the source follower PM0, and further adjusting the voltage of the control terminal NFET_G of the NMOS output transistor NFET. In this way, the change in the output voltage of the voltage output terminal VOUT is reduced. At the same time, the change in the output voltage of the voltage output terminal VOUT is transmitted to the first amplifier OP1 through the feedback capacitor Cfb, and then through the second amplifier OP2, the first NMOS transistor NM0 and the source follower PM0, thereby adjusting the voltage of the control terminal NFET_G of the NMOS output transistor NFET. In this way, the change in the output voltage of the voltage output terminal VOUT is reduced.

[0059] In this embodiment, when the output voltage of the voltage output terminal VOUT changes, a Miller compensation structure constructed by the Miller compensation capacitor C1 and the feedback capacitor Cfb is adopted to reduce the change in the output voltage. And the formed capacitance is 15 pF, which is smaller than the size of the compensation capacitor adopted in the prior art, thereby reducing the overall size of the voltage regulator, reducing the circuit design difficulty, reducing the cost, and having high reliability at the same time.

[0060] In some embodiments, the compensation unit 5 further includes a compensation resistor R0 and a zero-adjusting resistor R5. The compensation resistor R0 and the zero-adjusting resistor R5 are sequentially connected in series between the gate of the first NMOS transistor NM0 and the Miller compensation capacitor C1. The compensation resistor R0 and the zero-adjusting resistor R5 provide partial negative feedback for the gate of the first NMOS transistor NM0, which is beneficial to the stability and linearity of the circuit.

[0061] In a feasible embodiment, the low-dropout linear voltage regulator further includes a clamping circuit 6. The clamping circuit 6 is connected to the voltage output terminal VOUT, the charge pump circuit 1, the error amplifier unit 3 and the source follower PM0, and is used for clamping the voltage output from the charge pump circuit 1 and the error amplifier unit 3 to the control terminal SF_G of the source follower PM0 and the voltage of the control terminal NFET_G of the NMOS output transistor NFET, and is used for driving the NMOS output transistor NFET to conduct.

[0062] In this embodiment, since the charge pump circuit 1 provides a high voltage, if the charge pump circuit 1 is directly connected to the control terminal SF_G of the source follower PM0 and the control terminal NFET_G of the NMOS output transistor NFET, it may cause overvoltage of the source follower PM0 and the NMOS output transistor NFET. Therefore, a clamping circuit 6 is provided to avoid damage to the source follower PM0 and the NMOS output transistor.

[0063] In a specific feasible embodiment, the low dropout linear regulator further includes a voltage input terminal PVCC. The clamping circuit 6 includes a first resistor R1, a second resistor R2, a second NMOS transistor NM1, a third NMOS transistor NM2, a fourth NMOS transistor NM3, a fifth NMOS transistor NM5, a third resistor R4, a sixth NMOS transistor NM4, and a seventh NMOS transistor NM7. Among them, the first end of the first resistor R1 is electrically connected to the output terminal of the charge pump circuit 1, and the second end of the first resistor R1 is electrically connected to the first end of the second resistor R2; the source of the second NMOS transistor NM1 is connected to the voltage output terminal VOUT, the drain is electrically connected to the source of the third NMOS transistor NM2, and the gate is short-circuited to its drain; the gate of the third NMOS transistor NM2 is electrically connected to the gate of the fourth NMOS transistor NM3, and the drain is connected to the second end of the second resistor R2 and its gate is short-circuited; the drain of the fourth NMOS transistor NM3 is connected to the source of the fifth NMOS transistor NM5, and the source is connected to the control terminal of the source follower PM0 through the third resistor R4; the gate of the fifth NMOS transistor NM5 is connected between the first resistor R1 and the second resistor R2, and the drain is connected to the output terminal of the charge pump circuit 1; the drain of the sixth NMOS transistor NM4 is connected to the output terminal of the charge pump circuit 1, the gate is connected to the voltage input terminal PVCC, and the source is connected to the source of the seventh NMOS transistor NM7; the drain of the seventh NMOS transistor NM7 is connected to the input terminal of the source follower PM0, and the gate is short-circuited to the drain.

[0064] In this embodiment, the first resistor R1 and the second resistor R2 adapt to the voltage drop generated by the voltage output terminal VOUT. At the same time, the voltage output terminal VOUT, through the second NMOS transistor NM1, the third NMOS transistor NM2, and the fourth NMOS transistor NM3, jointly clamp the upper limit of the voltage of the control terminal SF_G of the source follower PM0. The upper limit clamping voltage value is the sum of the voltage of the voltage output terminal VOUT and the gate-source voltage VGS of the second NMOS transistor NM1, and is specifically calculated according to the following formula:

[0065] VOUT + VGS_NM1 + VGS_NM2 = V_SF_G + VGS_NM3; (1)

[0066] VGS_NM1 = VGS_NM2 = VGS_NM3; (2)

[0067] Among them, VOUT represents the voltage of the voltage output terminal; VGS_NM1 represents the gate-source voltage of the second NMOS transistor NM1; VGS_NM2 represents the gate-source voltage of the third NMOS transistor NM2; V_SF_G represents the voltage value for upper limit clamping at the control terminal of the source follower PM0; VGS_NM3 represents the gate-source voltage of the fourth NMOS transistor NM3.

[0068] Therefore, from formulas (1) and (2), we get: V_SF_G = VOUT + VGS_NM1.

[0069] After the voltage at the control terminal SF_G of the source follower PM0 is clamped, subsequently, the voltage at the control terminal NFET_G of the NMOS output transistor NFET is clamped at the upper limit, and the voltage value of this upper limit clamping is the sum of the voltage of the voltage output terminal VOUT and twice the gate-source voltage VGS.

[0070] In an implementable embodiment, the low-dropout linear regulator further includes a driving circuit 7. The driving circuit 7 is connected to the charge pump circuit 1, the clamping circuit, the source follower PM0, and the NMOS output transistor NFET, and is used to drive the NMOS output transistor NFET to conduct. In this embodiment, by setting the driving circuit 7 to provide a sufficient driving signal for the NMOS output transistor NFET, the NMOS output transistor NFET can conduct smoothly, ensuring the stable output voltage of the subsequent circuit.

[0071] In a specific implementable embodiment, the driving circuit 7 includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, and a fourth resistor R3. Among them, the source electrode of the second PMOS transistor PM2 is electrically connected to the output terminal of the charge pump circuit 1. The gate electrode of the second PMOS transistor PM2 is electrically connected to the gate electrode of the third PMOS transistor PM3. The drain electrode is short-circuited to its gate electrode and is electrically connected to the gate electrode of the first PMOS transistor PM1 and the drain electrode of the sixth NMOS transistor NM4 through the fourth resistor R3. The source electrode of the third PMOS transistor PM3 is electrically connected to the output terminal of the charge pump circuit. The drain electrode of the third PMOS transistor PM3 is electrically connected to the source electrode of the first PMOS transistor PM1. The drain electrode of the first PMOS transistor PM1 is connected to the control terminal NFET_G of the NMOS output transistor NFET. In this embodiment, the second PMOS transistor PM2 and the third PMOS transistor PM3 form a current mirror structure, and together with the first PMOS transistor PM1 and the fourth resistor R3, provide a pull-up driving current for the control terminal NFET_G of the NMOS output transistor NFET.

[0072] Such as Figure 4As shown, in a specific feasible implementation, the voltage stabilization control loop 2 further includes a voltage conversion unit 8 and a control MOS transistor NM6. The input end of the voltage conversion unit 8 is connected to the control end NFET_G of the NMOS output transistor NFET, and is used to convert the current signal output by the NMOS output transistor NFET into a voltage signal. The control end of the control MOS transistor NM6 is connected to the output end of the voltage conversion unit 8, and the source and drain of the control MOS transistor NM6 are respectively connected to both ends of the compensation resistor R0, and are used to control the compensation resistor R0 according to the voltage signal.

[0073] In this embodiment, in order to ensure the stability of the voltage stabilization control loop 2 under different load conditions, the output current is detected and then converted into an output voltage VSENSE through the voltage conversion unit 8, and the compensation resistor R0 is controlled through the control MOS transistor NM6, thereby ensuring the stability of the voltage stabilization control loop 2.

[0074] As Figure 5 shown, in a specific feasible implementation, the charge pump circuit 1 includes an eighth NMOS transistor MN11, a ninth NMOS transistor MN12, a fourth PMOS transistor MP21, and a fifth PMOS transistor MP22, where

[0075] The D end of the eighth NMOS transistor MN11 is electrically connected to the voltage input end PVCC, the S end of the eighth NMOS transistor MN11 is electrically connected to the G end of the ninth NMOS transistor MN12, and the G end of the eighth NMOS transistor MN11 is electrically connected to the S end of the fourth PMOS transistor MP21;

[0076] The D end of the ninth NMOS transistor MN12 is electrically connected to the voltage input end PVCC, the S end of the ninth NMOS transistor MN12 is electrically connected to the S end of the fourth PMOS transistor MP21; the S end of the ninth NMOS transistor MN12 is electrically connected to the negative phase end CLKN of the clock signal input;

[0077] The D end of the fourth PMOS transistor MP21 is electrically connected to the CP control signal output end VO_CP, and the G end of the fourth PMOS transistor MP21 is electrically connected to the positive phase end CLK of the clock signal input;

[0078] The G end of the fifth PMOS transistor MP22 is electrically connected to the S end of the fourth PMOS transistor MP21, the S end of the fifth PMOS transistor MP22 is electrically connected to the positive phase end CLK of the clock signal input, and the D end of the fifth PMOS transistor MP22 is electrically connected to the CP control signal output end VO_CP.

[0079] The charge pump circuit further includes a first capacitor C10, a second capacitor C11, and a third capacitor C12, where

[0080] The first capacitor plate of the first capacitor C10 is electrically connected to the S terminal of the eighth NMOS transistor MN11, and the second capacitor plate of the first capacitor C10 is electrically connected to the positive-phase clock signal input terminal CLK;

[0081] The first capacitor plate of the second capacitor C11 is electrically connected to the voltage input terminal PVCC, and the second capacitor plate of the second capacitor C11 is electrically connected to the CP control signal output terminal VO_CP;

[0082] The first capacitor plate of the third capacitor C12 is electrically connected to the S terminal of the ninth NMOS transistor MN12, and the second capacitor plate of the third capacitor C12 is electrically connected to the negative-phase clock signal input terminal CLKN.

[0083] The charge pump mainly utilizes the charge and discharge characteristics of capacitors to achieve voltage conversion or boost, and is also known as a switched-capacitor voltage converter, which is a type of DC-DC converter. The charge pump has the advantages of simple circuit, small size, high efficiency, and low cost.

[0084] In this embodiment, as Figure 6 shown, when the potential of the positive-phase clock signal input terminal CLK is low and the potential of the negative-phase clock signal input terminal CLKN is high, the voltage V1 is charged up to PVCC; when the potential of the positive-phase clock signal input terminal CLK is high (PVCC), the voltage V1 rises to 2*PVCC, and at the same time, the CP control signal output terminal CO_CP is charged through the fifth PMOS transistor MP22, making it rise to approximately 2*PVCC; meanwhile, the voltage V2 is charged up to PVCC;

[0085] When the potential of the negative-phase clock signal input terminal CLKN switches to high (PVCC), the voltage V2 rises to 2*PVCC, and at the same time, the CP control signal output terminal VO_CP is charged through the fourth PMOS transistor MP21. Repeating this process makes the voltage output by the charge pump circuit 1 twice the voltage of the voltage input terminal PVCC and more stable compared to the voltage of the voltage input terminal PVCC.

[0086] Those skilled in the art of the present application know that the present application can be implemented as a system, a method, or a computer program product.

[0087] Accordingly, the present disclosure may be embodied in the following forms, namely: it may be entirely hardware, entirely software (including firmware, resident software, microcode, etc.), or a combination of hardware and software, generally referred to herein as "circuit", "module" or "system". In addition, in some embodiments, the present application may also be implemented in the form of a computer program product in one or more computer-readable media, which contain computer-readable program code.

[0088] Any combination of one or more computer-readable media may be employed. The computer-readable media may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, for example - but not limited to - an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (non-exhaustive list) of the computer-readable storage medium include: an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In this document, the computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0089] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application. On this basis, various substitutions and improvements can be made to the present application, and these all fall within the protection scope of the present application.

Claims

1. A low voltage dropout linear regulator, characterized in that: include: Voltage output terminal; A charge pump circuit for providing a stable high voltage; A voltage stabilization control loop, wherein the voltage stabilization control loop includes an NMOS output tube NFET; The control end of the NMOS output tube NFET is electrically connected to the charge pump circuit, and the output end of the NMOS output tube NFET is connected to the voltage output end; Controlling the control terminal voltage of the NMOS output tube NFET by the charge pump circuit to adjust the output voltage of the voltage stabilization control loop; The voltage stabilization control loop further includes a reference voltage terminal for providing a reference voltage, an error amplifier unit and a source follower; Wherein, the input end of the error amplifier unit is connected to the voltage output end and the reference voltage end, and is used to compare the output voltage of the voltage output end with the reference voltage to generate an error amplification signal; The control end of the source follower is connected to the output end of the error amplifier and the charge pump circuit, and the output end of the source follower is connected to the control end of the NMOS output tube, for isolating the high output impedance output by the error amplifier unit and the high input capacitance input by the charge pump circuit to the NMOS output tube; The low voltage difference linear regulator also includes a clamping circuit, which is connected to the voltage output terminal, the charge pump circuit, the error amplifier unit and the source follower, and is used to clamp the voltage output from the charge pump circuit and the error amplifier unit to the control terminal of the source follower, the voltage of the control terminal of the NMOS output tube NFET, and is used to drive the NMOS output tube NFET to turn on.

2. The low voltage dropout linear regulator according to claim 1, characterized in that: The voltage regulation control loop also includes a feedback unit for providing a feedback voltage; the feedback unit includes a first feedback resistor RFB1, a second feedback resistor RFB2 and a feedback node FB, wherein the first feedback resistor RFB1 and the second feedback resistor RFB2 are sequentially connected in series between the output end of the NMOS output tube and the ground, and the feedback node FB is located between the first feedback resistor RFB1 and the second feedback resistor RFB2.

3. The low voltage dropout linear regulator according to claim 2, characterized in that: The error amplifier unit comprises: A first amplifier OP1, wherein a positive phase input terminal of the first amplifier OP1 is connected to a reference voltage terminal VREF, and a negative phase input terminal of the first amplifier OP1 is connected to the feedback node FB; A second amplifier OP2, wherein a positive phase input terminal and a negative phase input terminal of the second amplifier OP2 are respectively connected to the first amplifier OP1; A first NMOS transistor NM0, wherein a gate of the first NMOS transistor NM0 is connected to the output end of the second amplifier OP2, a drain of the first NMOS transistor NM0 is connected to the control end of the source follower, and a source of the first NMOS transistor NM0 is connected to the input end of the source follower.

4. The low voltage dropout linear regulator according to claim 3, characterized in that: The voltage regulation control loop further includes a compensation unit, which is connected to the error amplifier unit and the output end of the NMOS output tube NFET and is used to compensate for the frequency of the output voltage output by the NMOS output tube.

5. The low voltage dropout linear regulator according to claim 4, characterized in that: The compensation unit includes a Miller compensation capacitor C1 and a feedback capacitor Cfb, one end of the Miller compensation capacitor C1 is connected to the gate of the first NMOS tube NM0, and the other end is connected to the output end of the NMOS output tube NFET; one end of the feedback capacitor Cfb is connected to the output end of the NMOS output tube NFET, and the other end is connected to the negative phase input end of the first amplifier.

6. The low voltage dropout linear regulator according to claim 1, characterized in that: The low voltage difference linear regulator also includes a voltage input terminal; the clamping circuit includes a first resistor R1, a second resistor R2, a second NMOS tube NM1, a third NMOS tube NM2, a fourth NMOS tube NM3, a fifth NMOS tube NM5, a third resistor R4, a sixth NMOS tube NM4, and a seventh NMOS tube NM7; Wherein, a first end of the first resistor R1 is electrically connected to an output end of the charge pump circuit, and a second end of the first resistor R1 is electrically connected to a first end of the second resistor R2; The source of the second NMOS transistor NM1 is connected to the voltage output terminal, the drain is electrically connected to the source of the third NMOS transistor NM2, and the gate is short-circuited with its drain; The gate of the third NMOS transistor NM2 is electrically connected to the gate of the fourth NMOS transistor NM3, and the drain is connected to the second end of the second resistor R2 and short-circuits the gate thereof; The drain of the fourth NMOS transistor NM3 is connected to the source of the fifth NMOS transistor NM5, and the source is connected to the control end of the source follower through the third resistor R4; The gate of the fifth NMOS transistor NM5 is connected between the first resistor R1 and the second resistor R2, and the drain is connected to the output end of the charge pump circuit; The drain of the sixth NMOS transistor NM4 is connected to the output end of the charge pump circuit, the gate is connected to the voltage input end, and the source is connected to the source of the seventh NMOS transistor NM7; The drain of the seventh NMOS transistor NM7 is connected to the input end of the source follower, and the gate and the drain are short-circuited.

7. The low voltage dropout linear regulator according to claim 6, characterized in that: The low voltage drop linear regulator also includes a driving circuit, which is connected to the charge pump circuit, the clamp circuit, the source follower and the NMOS output tube NFET and is used to drive the NMOS output tube to conduct.

8. The low voltage dropout linear regulator according to claim 7, characterized in that: The driving circuit includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3 and a fourth resistor R3; The source of the second PMOS transistor PM2 is electrically connected to the output end of the charge pump circuit, the gate of the second PMOS transistor PM2 is electrically connected to the gate of the third PMOS transistor PM3, the drain is short-circuited with the gate and electrically connected to the gate of the first PMOS transistor PM1 and the drain of the sixth NMOS transistor NM4 through the fourth resistor R3; The source of the third PMOS transistor PM3 is electrically connected to the output end of the charge pump circuit, and the drain of the third PMOS transistor PM3 is electrically connected to the source of the first PMOS transistor PM1; The drain of the first PMOS transistor PM1 is connected to the control end of the NMOS output transistor NFET.

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