Chip burning method, electronic equipment and medium

Abstract

The invention discloses a chip burning method, which comprises the following steps of: firstly describing a configuration mirror image of a chip through a table, analyzing the table to obtain a first configuration interface, editing the configuration mirror image through the first configuration interface, then describing the configuration mirror image through a json file, analyzing the json file to obtain a second configuration interface, and programming the second configuration interface through the json file. The configuration mirror images can be spliced through the second configuration interface to obtain the configuration file, and then burning software of the chip is generated through the configuration file and used for burning the chip. According to the method, various chip burning software is generated through the configuration file, the code reuse rate is increased while the customization requirement of a user is met, the development work is simplified, and the method is wide in application range and low in development and maintenance cost and difficulty.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a chip burning method, electronic equipment and medium. Background Art

[0002] Chip burning refers to burning the chip program into the chip startup Flash to achieve chip upgrade and debugging functions, which is mostly achieved through software programs. Existing chip burning software is basically bound to the chip, that is, the same series of chips use a chip burning tool, but the chip burning tools between different series of chips are often incompatible. Therefore, when multiple product lines coexist, it is necessary to design multiple different chip burning tools, and designing the UI interface requires a lot of time and cost, and also requires a lot of maintenance and updates. Summary of the invention

[0003] In view of some or all of the problems in the prior art, the present invention provides a chip programming method in a first aspect, comprising:

[0004] Describe the chip configuration image in a table format;

[0005] Parsing the table to obtain a first configuration interface, wherein the configuration image can be edited through the first configuration interface;

[0006] Describe the configuration image in json format;

[0007] Parse the json file to obtain a second configuration interface, wherein the configuration image can be spliced ​​through the second configuration interface to obtain a configuration file;

[0008] Generate chip burning software through the configuration file; and

[0009] Use the burning software to burn the chip.

[0010] Furthermore, in the table, any configuration image includes at least one row of information, wherein the information in the table includes the name, definition, address offset, width, default value of the configuration image, and information of each field of the configuration image.

[0011] Furthermore, the information of any field includes: field name, bit segment range of the field in the configuration image, type, current value, and function description.

[0012] Further, any field of the configuration image includes one or more of the following types: chip common fields, chip unique fields, and custom fields.

[0013] Furthermore, each configuration image includes 32 bits.

[0014] Furthermore, the first configuration interface includes:

[0015] A first interface, which is used to display the structure of each configuration image; and

[0016] The second interface is displayed by selecting a field in the first interface, and the second interface is used to edit the field.

[0017] Furthermore, the first interface adopts a tree structure and includes the name, definition, address, and fields included in each configuration image.

[0018] Furthermore, the second interface includes an address offset, a bit range, a current value and a functional description of the selected field.

[0019] Furthermore, the json file includes the following information of the configuration image: name, startup address, running address, whether to verify the signature, whether to 4K align, and whether to select by default.

[0020] Furthermore, the table and the json file are parsed by a literal scripting language.

[0021] Based on the chip burning method as described above, the second aspect of the present invention provides an electronic device for chip burning, which includes a memory and a processor, wherein the memory is configured to store a computer program, and the computer program executes the chip burning method as described above when the processor is running.

[0022] The third aspect of the present invention further provides a computer-readable storage medium for chip burning, which stores a computer program. When the computer program is run on a processor, it executes the chip burning method as described above.

[0023] The present invention provides a chip burning method, which generates various chip burning software through configuration files, which not only meets the user's customization needs, but also increases the code reuse rate and simplifies the development work. If a new chip needs to be burned, it only needs to edit the table and json file to quickly adapt the chip, which greatly improves the development efficiency and reduces the development and maintenance costs and difficulties. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] To further illustrate the above and other advantages and features of various embodiments of the present invention, a more specific description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings only depict typical embodiments of the present invention and are therefore not to be considered as limiting the scope thereof. In the accompanying drawings, for clarity, identical or corresponding parts will be represented by identical or similar reference numerals.

[0025] Figure 1 A schematic flow chart showing a chip programming method according to an embodiment of the present invention;

[0026] Figure 2 A schematic diagram of a table showing one embodiment of the present invention;

[0027] Figure 3 A schematic diagram showing a first configuration interface according to an embodiment of the present invention;

[0028] Figure 4 A schematic diagram showing the Flash arrangement of a chip according to an embodiment of the present invention; and

[0029] Figure 5 A schematic diagram showing a second configuration interface according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] In the following description, the present invention is described with reference to various embodiments. However, those skilled in the art will recognize that the various embodiments can be implemented without one or more specific details or with other replacement and / or additional methods or components. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid blurring the inventive point of the present invention. Similarly, for the purpose of explanation, specific numbers and configurations are set forth to provide a comprehensive understanding of the embodiments of the present invention. However, the present invention is not limited to these specific details. In addition, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn in correct proportions.

[0031] In this specification, reference to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. The phrase "in one embodiment" appearing in various places in this specification does not necessarily all refer to the same embodiment.

[0032] It should be noted that the embodiments of the present invention describe the method steps in a specific order, but this is only for the purpose of illustrating the specific embodiment, rather than limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to actual needs.

[0033] In view of the problem that the existing chip burning software has poor versatility, the present invention provides a chip burning method, which designs different UI interactive interfaces through different templates, meets multiple needs and shortens the development cycle. The chip burning method can generate various chip burning software through configuration files, which not only meets the user's customization needs, but also increases the code reuse rate and simplifies the development work. The chip burning software usually includes multiple functions, such as image configuration generation, image splicing and image burning. In the present invention, it mainly involves image configuration generation and image splicing. Among them, the image configuration is used to configure the parameters of the image, which can configure the startup mode, startup device, startup parameters, etc., and can also be used to configure the initialization parameters of some peripherals, such as the default configuration of sensor. These parameters involve a large number of register configurations, which are obscure to users. At the same time, the parameters required for different images of different projects are different, and it is cumbersome to design an interface for each image. Based on this, in an embodiment of the present invention, an excel table is used as a configuration method of the back end to generate a UI interface and provide a rich configuration selection, which is convenient for users to use and operate, so as to realize image configuration quickly, accurately and flexibly. The flash burning file of MCU is composed of multiple internal small images. For MCU, it can be MCU OS firmware, bootloader and parameter images. For Linux system, it can be BL2, uboot, Linux kernel and file system. At the same time, under information security requirements, each image may carry a signature file. Based on this, in an embodiment of the present invention, the parameters of each component are abstracted, and each UI sub-item of the image splicing is described using a json file. In this way, the same set of codes can be used in multiple different projects, greatly improving the reuse rate of the code and improving the efficiency of chip burning. The chip burning method conforms to the MVC (model-view-control) architecture, which divides the UI tool into three parts: configuration module, user interface, and control logic. Its overall structure is clear, and each part has clear responsibilities for easy maintenance. When adding a chip model, as long as the startup scheme and the image layout are determined, the configuration model can be modified by editing the excel table and the json file to quickly adapt to the new chip.

[0034] The scheme of the present invention is further described below in conjunction with the accompanying drawings of the embodiments.

[0035] Figure 1 FIG. 1 is a flow chart showing a chip programming method according to an embodiment of the present invention. Figure 1 As shown, a chip burning method includes:

[0036] First, in step 101, the configuration image is described. Image configuration is essentially reading and writing memory and registers. At the same time, the configuration fields of each chip are different, and the configuration segments of different users of the same chip may also be different. Based on this, in the embodiment of the present invention, in order to facilitate expansion, modification, development and maintenance, each configuration image of the chip is described in a table (Excel) format. Figure 2 A schematic diagram of a table showing an embodiment of the present invention is shown. Figure 2 As shown, in one embodiment of the present invention, in the table, any configuration image includes at least one row of information, wherein the information in the table includes the name (Reg name), definition (Discription), address offset (Offset addr), width (Width), default value (Default value) of the configuration image, and information of each field of the configuration image. In one embodiment of the present invention, the information of any field includes: field name (Field name), bit segment range (Field range) of the field in the configuration image, type (Field type), current value (Field value), and function description (Field discription). In one embodiment of the present invention, each configuration item and its field in the image are described in units of 32 bits, presenting a tree structure. In one embodiment of the present invention, the fields in the excel table are divided into three cases:

[0037] Chip common fields are used by all series of chips, such as Flash configuration fields. Flash configuration is a common configuration abstracted from many projects, which can adapt to various types of Flash. It is related to the parsing of the manufacturer's program, so users cannot modify its address and length. The field description includes reference values ​​for most Flash models on the market. For Flash models that have not been adapted, it is necessary to modify the fields according to the Flash model reference data manual;

[0038] Chip-specific fields, which are unique to a particular chip, such as PLL configuration. The number and configuration of clock trees for each chip may be different. The chip-specific fields are parsed by the manufacturer's program. Users cannot modify the address and meaning, but can configure the required value according to the chip manual; and

[0039] Custom fields, i.e. user-configured fields, allow users to extend their own fields in the Excel spreadsheet, such as the MAC number of the network card and the ID of the CAN. After the custom fields are burned into the Flash, they interact with the user program and can be modified at will.

[0040] Next, in step 102, the image field is edited. The table is parsed to obtain a first configuration interface, wherein each configuration image can be edited through the first configuration interface. In one embodiment of the present invention, the front end uses a literal scripting language such as js or pyqt5 to parse the table to depict the tree structure presented therein to obtain the first configuration interface. Figure 3 FIG. 1 is a schematic diagram showing a first configuration interface of an embodiment of the present invention. Figure 3 As shown, the first configuration interface is divided into two parts, wherein the first interface (left part) is used to display the structure of each configuration image, that is, the tree structure presented in the table, which includes the name, definition, address, and fields included in each configuration image, wherein each field is an editable item, and when a field is double-clicked to select, for example, the parsed address (Address), field range (Range), value (Value) and description (Description) will be filled in and immediately drawn to obtain the second interface (right part), and the second interface provides a confirmation button for the user to modify the value and reset;

[0041] Next, in step 103, the images are spliced. The configuration image is described in json format. In one embodiment of the present invention, the json file is pre-edited according to the project (chip type), which is related to the Flash layout specified by the system. Figure 4 The following is a schematic diagram of the Flash layout of a chip according to an embodiment of the present invention. The CFG domain is the content described by the table in the above steps. In addition to the images generated separately, the Flash layout also includes a file header (ImageHeader), which is a vector table for describing the Flash layout. The structure of the file header is simplified as follows:

[0042]

[0043] The bin contains the information of each image, as follows:

[0044]

[0045] When splicing images, the burning tool can generate most of the information in the structure, such as the check value, name, offset in Flash (bin_offset), and the length of each image (bin_length), etc., while the loading address and jump address require auxiliary input. For example, the program on Flash is loaded into SRAM and then jumped to DDR for execution. This process is related to the configuration when the program is compiled. The image does not contain relevant information, and the burning tool does not know it either. Therefore, it needs to be described in the bin structure. Based on this, in an embodiment of the present invention, each spliced ​​sub-item is described by a json file, and the json file is as follows:

[0046]

[0047]

[0048] It can be seen that each json entry describes the image name, startup address, running address, whether to verify the signature, whether to 4K align, and whether to select by default. Whether to verify the signature indicates whether each image must have a signature. In actual applications, the signature is also a kind of image, and an additional signature image selection entry needs to be generated. Whether the selected attribute is related to the bin_num of the even file header, that is, it is used to tell the program how many valid images there are, and it is also used to support partial updates of the image. Whether to 4K align is related to the system, indicating whether it is burned to the address of the Flash 4k alignment.

[0049] After the description is completed, the json file is parsed by a literal scripting language such as js or pyqt5 to generate a second configuration interface, through which the configuration image can be spliced ​​to obtain a configuration file. Figure 5 FIG. 1 is a schematic diagram showing a second configuration interface according to an embodiment of the present invention. Figure 5 As shown, through the second configuration interface, you can select the configuration image to be spliced. When a configuration image is selected, its load address, i.e., jump address, can be displayed, and the splicing is completed;

[0050] Next, in step 104, the burning software is generated. The burning software of the chip is generated by the configuration file; and

[0051] Finally, in step 105, the chip is burned using the burning software.

[0052] Based on the chip burning method as described above, the present invention also provides an electronic device for chip burning, which includes a memory and a processor, wherein the memory is configured to store a computer program, and the computer program executes the chip burning method as described above when the processor is running.

[0053] In addition, the present invention also provides a computer-readable storage medium for chip burning, which stores a computer program, and the computer program executes the chip burning method as described above when running on a processor. The computer-readable storage medium can be a tangible device that can hold and store instructions used by an instruction execution device, such as an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. Specifically, the computer-readable storage medium includes, but is not limited to: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, a punch card or a protruding structure in a groove on which instructions are stored, and any suitable combination of the above.

[0054] In an embodiment of the present invention, the computer program can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device through a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer program from the network and forwards it for storage in a computer-readable storage medium in each computing / processing device.

[0055] In an embodiment of the present invention, the computer program may be an assembly instruction, an instruction set architecture (ISA) instruction, a machine instruction, a machine-dependent instruction, a microcode, a firmware instruction, a state setting data, or a source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. The computer program may be executed entirely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, the electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be executed by using the state information of the computer program to personalize the electronic circuit.

[0056] Although various embodiments of the present invention are described above, it should be understood that they are presented as examples only and not as limitations. It is obvious to those skilled in the relevant art that various combinations, modifications and changes can be made thereto without departing from the spirit and scope of the present invention. Therefore, the breadth and scope of the present invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should only be defined according to the attached claims and their equivalents.

Claims

1. A chip burning method, characterized in that: Includes steps: Describe the chip configuration image through a table; Parsing the table to obtain a first configuration interface, wherein the first configuration interface is configured to edit the configuration image; Describe the configuration image through a json file; Parse the json file to obtain a second configuration interface, wherein the second configuration interface is configured to splice the configuration image to obtain a configuration file; Generate chip burning software through the configuration file; as well as Use the burning software to burn the chip.

2. The chip programming method according to claim 1, characterized in that: Any configuration image in the table includes at least one row of information, wherein the information in the table includes the name, definition, address offset, width, default value of the configuration image, and information of each field of the configuration image.

3. The chip programming method according to claim 2, characterized in that: The information of any field includes: field name, bit range of the field in the configuration image, type, current value, and function description.

4. The chip programming method according to claim 2, characterized in that: The fields of any of the configuration images include one or more of the following types: chip common fields, chip unique fields, and custom fields.

5. The chip programming method according to claim 1, characterized in that: Each configuration image contains 32 bits.

6. The chip programming method according to claim 1, characterized in that: The first configuration interface includes: A first interface, which displays the structure of each configuration image in a tree structure, including the name, description, address, and fields included in each configuration image; and The second interface is displayed by selecting a field in the first interface. The second interface includes the address offset, bit range, current value and function description of the selected field. The current value of the field can be edited through the second interface.

7. The chip programming method according to claim 1, characterized in that: The json file includes the following information of the configuration image: name, startup address, running address, whether to verify the signature, whether to 4K align, and whether to select by default.

8. The chip programming method according to claim 1, characterized in that: The table and json file are parsed by a literal scripting language.

9. An electronic device for chip burning, characterized in that: The method comprises a memory and a processor, wherein the memory is configured to store a computer program, and the computer program executes the chip burning method according to any one of claims 1 to 8 when the processor is running.

10. A computer-readable storage medium for chip burning, characterized in that: A computer program is stored, and when the computer program is run on a processor, the chip burning method according to any one of claims 1 to 8 is executed.

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