Instruction processing method and device, electronic equipment and computer readable storage medium

Abstract

The invention provides an instruction processing method and device, electronic equipment and a computer readable storage medium, the method is applied to a first processing core in a plurality of processing cores of a many-core system, a scheduling unit, an execution unit and a reordering unit are configured in the processing core, and the scheduling unit is used for dispatching processing instructions in an instruction sequence to the execution unit out of order; the execution unit is used for executing the processing instruction to obtain an execution result; the reordering unit is used for reordering the execution results and sequentially writing the execution results back to the register; the method comprises the steps that under the condition that a first processing core receives input data of a first processing instruction, instruction fetching and decoding are conducted on the first processing instruction, and the decoded first processing instruction is obtained; under the condition that the direct execution condition is met, the execution unit executes the decoded first processing instruction; the direct execution condition includes that the input data is routed and sent to the first processing core by the execution unit of the previous processing core. According to the embodiment of the invention, the instruction processing efficiency can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to an instruction processing method and device, an electronic device, and a computer-readable storage medium. Background Art

[0002] With the rapid development of fields such as artificial intelligence, machine learning and big data, the demand for data processing is increasing, and the high-performance computing capabilities of the many-core architecture are playing an increasingly important role in data processing.

[0003] Many-core architectures in related technologies are mainly divided into two categories: one is a data flow architecture designed for data-intensive applications, which has the ability of large-scale parallel processing to improve processing efficiency; the other is a control flow architecture for general loads, which focuses on flexible task scheduling and execution, and is mainly implemented in many-core CPUs, etc. However, related technologies usually cannot take into account both the high parallel processing capability of the data flow architecture and the flexibility of the control flow architecture. Summary of the invention

[0004] The present disclosure provides an instruction processing method and device based on a many-core system, an electronic device, and a computer-readable storage medium.

[0005] In a first aspect, the present disclosure provides an instruction processing method, which is applied to a first processing core among multiple processing cores of a many-core system, wherein the processing core of the many-core system is configured with a scheduling unit, an execution unit, and a reordering unit, wherein the scheduling unit is used to dispatch processing instructions that meet execution conditions in an instruction sequence to be executed by the processing core to the execution unit in a disordered order; the execution unit is used to execute the received processing instructions to obtain execution results of the processing instructions; the reordering unit is used to reorder the execution results and sequentially write the execution results back to the register of the processing core; wherein the method comprises:

[0006] When the first processing core receives input data of a first processing instruction in the instruction sequence, fetching and decoding the first processing instruction to obtain a decoded first processing instruction;

[0007] When the first processing instruction satisfies a direct execution condition, directly executing the decoded first processing instruction through an execution unit of the first processing core to obtain a first execution result of the first processing instruction;

[0008] The direct execution condition includes: the input data of the first processing instruction is directly routed to the first processing core by the execution unit of the second processing core, wherein the second processing core is the previous processing core of the first processing core on the data pipeline path.

[0009] In a second aspect, the present disclosure provides an instruction processing device, which is applied to a first processing core among a plurality of processing cores in a multi-core system.

[0010] The processing core of the multi-core system is configured with a scheduling unit, an execution unit and a reordering unit, wherein the scheduling unit is used to dispatch processing instructions that meet the execution conditions in the instruction sequence to be executed by the processing core to the execution unit in a disordered order; the execution unit is used to execute the received processing instructions to obtain the execution results of the processing instructions; the reordering unit is used to reorder the execution results and write the execution results back to the register of the processing core in order;

[0011] The device comprises:

[0012] an instruction fetching and decoding module, configured to fetch and decode the first processing instruction to obtain the decoded first processing instruction when the first processing core receives input data of the first processing instruction in the instruction sequence;

[0013] an instruction execution module, configured to directly execute the decoded first processing instruction through an execution unit of the first processing core to obtain a first execution result of the first processing instruction when the first processing instruction meets a direct execution condition;

[0014] The direct execution condition includes: the input data of the first processing instruction is directly routed to the first processing core by the execution unit of the second processing core, wherein the second processing core is the previous processing core of the first processing core on the data pipeline path.

[0015] In a third aspect, the present disclosure provides an electronic device comprising: a plurality of processing cores; and an on-chip network configured to exchange data between the plurality of processing cores and external data; wherein one or more instructions are stored in one or more of the processing cores, and one or more of the instructions are executed by one or more of the processing cores, so that one or more of the processing cores can execute the above-mentioned instruction processing method.

[0016] In a fourth aspect, the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the above-mentioned instruction processing method when executed by a processor / processing core.

[0017] The embodiments provided by the present disclosure can realize a two-stage pipeline architecture of a data pipeline between processing cores and a CPU pipeline within a processing core; during processing, for input data that is directly routed and sent by the previous stage processing core without reordering, the corresponding first processing instruction can bypass the scheduling unit and be sent directly to the execution unit, and the execution unit directly executes the first processing instruction, thereby saving the overhead of instruction scheduling and improving the efficiency of instruction processing.

[0018] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing detailed example embodiments with reference to the accompanying drawings, in which:

[0020] Figure 1 It is a schematic diagram of a CPU pipeline in the related art;

[0021] Figure 2 A schematic diagram of a CPU pipeline execution process in the related art;

[0022] Figure 3 A schematic diagram of a data pipeline of a many-core system provided in an embodiment of the present disclosure;

[0023] Figure 4 A schematic diagram of a two-stage nested pipeline architecture of a many-core system provided in an embodiment of the present disclosure;

[0024] Figure 5 A flowchart of an instruction processing method provided by an embodiment of the present disclosure;

[0025] Figure 6 A schematic diagram of a processing process of an instruction processing method provided by an embodiment of the present disclosure;

[0026] Figure 7 A schematic diagram of a data pipeline path in a many-core system provided by an embodiment of the present disclosure;

[0027] Figure 8 A schematic diagram of interleaved execution of instructions in a processing core provided by an embodiment of the present disclosure;

[0028] Fig. 9 A schematic diagram of branch prediction provided for an embodiment of the present disclosure;

[0029] Fig.10 A block diagram of an instruction processing device provided by an embodiment of the present disclosure;

[0030] Fig.11 A block diagram of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0032] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0033] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0034] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "including" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded. "Connected" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0035] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined as such herein.

[0036] In the related art, a central processing unit (CPU) executes an instruction in a pipeline manner, and by dividing the execution process of the instruction into multiple stages, multiple instructions are allowed to be processed at different stages at the same time.

[0037] Figure 1 FIG. 1 is a schematic diagram of a CPU pipeline in the related art. Figure 1 As shown in the figure, the pipeline can be divided into several stages, including instruction fetch (IF), decode (ID), execute (EX), memory access (MEM) and write back (WB). In this way, when an instruction is executed in a certain stage, the previous instruction is already in the next stage, and subsequent instructions can also be processed in parallel, which significantly improves the instruction throughput and the overall performance of the CPU.

[0038] like Figure 1 As shown, Inst0, Inst1, Inst2, Inst3, Inst4, ... are instructions executed sequentially; t0, t1, t2, t3, t4, t5, ... are time steps. It can be seen that each instruction is executed in sequence, and different stages of different instructions are executed in parallel in each time step. For example, at t4, the write back (WB) of instruction Inst0, the memory access (MEM) of instruction Inst1, the execution (EX) of instruction Inst2, the decoding (ID) of instruction Inst3, and the instruction fetch (IF) of instruction Inst4 are executed in parallel. When the number of parallel pipelines is 5, the steady state (i.e., the pipeline is full (full pipeline)) is reached at t4.

[0039] In order to ensure the smooth execution of the CPU pipeline and solve various conflicts and risks, the CPU is equipped with a complex controller. One of the important parts is the instruction scheduling module and the reordering module (reorder buffer, ROB) that cooperate with out-of-order execution. Among them, out-of-order execution is a CPU design technology that allows instructions to be reordered based on data dependencies and resource availability instead of the original program order when executed. This method can improve instruction-level parallelism and reduce the idleness (bubbles) of the CPU pipeline, thereby improving the overall CPU throughput.

[0040] Out-of-order execution can be seen as a dynamic scheduling mechanism. During this process, the instruction scheduling module maintains an instruction window and determines the data dependencies of the instructions in the window. If the data required for an instruction is ready, the instruction can be sent to the execution stage (instruction dispatch). Otherwise, the instruction will be temporarily stored in the reservation station of the scheduling module and executed later. The reordering module can ensure that the out-of-order execution pipeline can write back the results of instruction execution sequentially (that is, to ensure the consistency of the results with the original program). Therefore, the CPU forms a pipeline execution process of out-of-order dispatch, out-of-order execution, and sequential write-back.

[0041] Figure 2 FIG. 1 is a schematic diagram of the CPU pipeline execution process in the related art. Figure 2 As shown, the instructions in the instruction sequence (such as integer addition (Integer add), integer multiplication (Integer mul), floating point multiplication (FP mul) and other instructions) are fetched F and decoded D in order (in order), and the decoded instructions are input into the instruction scheduling module SCHEDULE; the instruction scheduling module dispatches each instruction out of order (out of order), and executes each instruction in the out of order execution phase E. The number of time steps required for the execution of different instructions is different, for example Figure 2Integer addition requires 1 time step, while integer multiplication requires 4 time steps. The execution results of the instructions are input into the reordering module REORDER, and the execution results of the instructions are arranged in order after reordering, and written back to the register W in order. The execution status of the instructions can also be transmitted back to the instruction scheduling module SCHEDULE through the tag and value broadcast bus (TAG and VALUE Broadcast Bus).

[0042] In this way, the pipeline execution mechanism of the CPU can flexibly execute a variety of general-purpose programs. However, with the increasing number of data-intensive loads such as neural networks, the data flow architecture of many-core systems has continued to evolve.

[0043] Figure 3 Schematic diagram of data flow of a multi-core system provided by an embodiment of the present disclosure. Figure 3 As shown in the figure, the processing cores of the many-core system can form a data pipeline execution mode. The processing cores are connected to each other through the on-chip interconnect structure, and multiple processing cores are configured into multiple data pipelines. The processing core of the previous stage on the data pipeline sends data to one or more processing cores of the next stage. When the processing core of the next stage receives the corresponding data, it can trigger the calculation corresponding to the data.

[0044] This approach eliminates the need for complex control logic, can quickly respond to incoming data, and ensures high throughput. At the same time, the orchestration of pipelines between different processing cores can also give full play to the flexibility of each core in the many-core architecture to perform different tasks and adapt to parallel loads with different resource amounts.

[0045] However, the control cost of the control flow architecture of the CPU pipeline is high and cannot adapt to high-throughput data parallelism; while the data flow architecture of the data flow pipeline can only be customized for acceleration of specific operators and has poor flexibility. Therefore, how to effectively balance the high parallel computing capability of the data flow architecture and the flexibility of the control flow architecture has always been a major challenge facing the many-core field.

[0046] According to an instruction processing method provided in an embodiment of the present disclosure, it is possible to implement a multi-core system pipeline architecture with two layers of nested CPU control flow pipeline and data flow pipeline. While maintaining a certain degree of versatility and flexibility, it is possible to utilize the advantages of the multi-core system, enhance the capability of large-scale parallel execution, and improve instruction processing efficiency.

[0047] The instruction processing method according to the embodiment of the present disclosure can be applied to a many-core system, which can be the neuromorphic chip itself, or any electronic device such as a board, terminal device, or server including the neuromorphic chip. The present disclosure does not limit this.

[0048] In some possible implementations, multiple processing cores of the many-core system can be organized in a data flow pipeline manner, and the execution of the pipeline can be driven by data triggering to form one or more data pipeline paths. The data pipeline path includes multiple levels of processing cores, and adjacent processing cores in the multiple levels of processing cores are connected in communication in a data flow pipeline manner, that is, the output data of the previous level of processing core is used as the input data of the next level of processing core.

[0049] In some possible implementations, each processing core is organized in a CPU pipeline manner. A scheduling unit, an execution unit, and a reordering unit are configured in the processing core, wherein: the scheduling unit is used to dispatch processing instructions that meet the execution conditions in the instruction sequence to be executed by the processing core to the execution unit in a disorderly order; the execution unit is used to execute the received processing instructions to obtain the execution results of the processing instructions; the reordering unit is used to reorder the execution results and write the execution results back to the register of the processing core in order.

[0050] Among them, the scheduling unit, execution unit and reordering unit can be implemented in software or hardware, and technical personnel in this field can set them according to actual conditions; the execution condition of the processing instruction can be a data trigger condition (that is, the input data on which the processing instruction depends has been prepared) or a control trigger condition (that is, the control logic on which the processing instruction depends has been satisfied, such as an if statement). The present invention discloses the specific implementation methods of the scheduling unit, execution unit and reordering unit; the specific execution conditions of the processing instruction are not limited.

[0051] Figure 4 Schematic diagram of a two-level nested pipeline architecture of a many-core system provided by an embodiment of the present disclosure. Figure 4 As shown, the processing cores 41, 42, and 43 are organized in a data flow pipeline to form a data flow path. The output data of the processing core 41 is used as the input data of the processing core 42, and the output data of the processing core 42 is used as the input data of the processing core 43. The processing core is organized in a CPU pipeline manner. Taking the processing core 42 as an example, the processing core 42 is configured with a scheduling unit 421, an execution unit 422, and a reordering unit 423. The processing instructions in the instruction sequence to be executed by the processing core 42 are sent to the scheduling unit 421 after fetching and decoding; the scheduling unit 421 dispatches the processing instructions that meet the execution conditions to the execution unit 422 in a disordered order; the execution unit 422 executes the received processing instructions to obtain the execution results, and sends them to the reordering unit 423; the reordering unit 423 reorders the execution results of each instruction, and writes them back to the register of the processing core in sequence to complete the processing process.

[0052] In some possible implementations, the instruction sequence to be executed by the processing core 42 may include CPU control instructions, processing instructions triggered by the data flow pipeline, and one or more processing instructions for sequential execution programs or tasks stored in the core, etc. Each processing instruction in the instruction sequence is executed in the processing manner of the CPU pipeline, that is, the instruction processing process of out-of-order dispatch-out-of-order execution-sequential write back is implemented through the scheduling unit, the execution unit and the reordering unit.

[0053] Figure 5 A flowchart of an instruction processing method provided by an embodiment of the present disclosure. The instruction processing method according to an embodiment of the present disclosure can be applied to a first processing core of a many-core system, where the first processing core is one of multiple processing cores of the many-core system and is located on a data pipeline path.

[0054] In some possible implementations, such as Figure 5 As shown, the method includes:

[0055] In step S51, when the first processing core receives input data of the first processing instruction in the instruction sequence, the first processing instruction is fetched and decoded to obtain the decoded first processing instruction;

[0056] In step S52, when the first processing instruction meets the direct execution condition, the decoded first processing instruction is directly executed by the execution unit of the first processing core to obtain a first execution result of the first processing instruction;

[0057] The direct execution condition includes: input data of the first processing instruction is directly routed and sent to the first processing core by an execution unit of the second processing core, wherein the second processing core is a previous processing core of the first processing core on a data pipeline path.

[0058] For example, for the processing cores on the same data pipeline path, the execution results of the processing instructions of the previous level processing core need to be reordered by the reordering unit before being sent to the next level processing core; the next level processing core dispatches the processing instructions corresponding to the execution results out of order through the scheduling unit, and then executes them through the execution unit. This processing method requires continuous scheduling and reordering during the data flow pipeline, which is very costly.

[0059] In some possible implementations, the execution results of the processing instructions of the previous level processing core may not be reordered, but may be reordered after the execution of the next level processing core is completed, or reordered at the last level processing core of the data pipeline path, so that the multiple levels of processing cores on the data pipeline path form a larger out-of-order execution path, thereby saving the scheduling and reordering overhead and improving the efficiency of instruction processing.

[0060] In some possible implementations, a "routing" stage may be set at the last stage of the CPU pipeline in the processing core, and the "routing" stage may be implemented by configuring a routing unit in the processing core, for example, the routing unit may be implemented by directly connecting the original router in the processing core to the CPU pipeline in the processing core and controlling it through the controller in the processing core. The present disclosure does not limit this.

[0061] In some possible implementations, if the execution result of a processing instruction in a processing core is the input data of a subsequent processing core and has no dependency on other processing instructions in the processing core, it may be chosen not to input the execution result of the processing instruction into a reordering unit to implement sequential write-back, and it may be chosen to send the execution result of the processing instruction to a routing unit via a bypass that bypasses the reordering unit, and the routing unit directly routes the result to the subsequent processing core.

[0062] In some possible implementations, any processing core on the data pipeline path may be referred to as a first processing core, the previous processing core of the first processing core may be referred to as a second processing core, and the subsequent processing core of the first processing core may be referred to as a third processing core.

[0063] For the first processing core, in step S51, if the input data of the first processing instruction in the instruction sequence is received, the first processing instruction can be fetched and decoded in the CPU pipeline of the first processing core to obtain the decoded first processing instruction, and then determine whether the direct execution condition is met. Wherein, when the second processing core sends data to the first processing core, it can carry a corresponding identifier to indicate that the data is directly routed to the first processing core by the execution unit, or is sent after being written back by the reordering unit.

[0064] In some possible implementations, if the input data of the first processing instruction is directly routed to the first processing core by the execution unit of the second processing core, it is determined that the direct execution condition is met; in step S52, the decoded first processing instruction can be sent to the execution unit via a bypass bypassing the scheduling unit, and the decoded first processing instruction is directly executed by the execution unit of the first processing core to obtain a first execution result of the first processing instruction.

[0065] In some possible implementations, if the input data of the first processing instruction is written back by the reordering unit of the second processing core and then sent, it is determined that the direct execution condition is not met; the decoded first processing instruction can be sent normally to the scheduling unit and dispatched by the scheduling unit to the execution unit for execution.

[0066] According to an embodiment of the present disclosure, for input data that is directly routed and sent by the previous level processing core without reordering, the corresponding first processing instruction can bypass the scheduling unit and be sent directly to the execution unit, which directly executes the first processing instruction, thereby saving the overhead of instruction scheduling and improving the efficiency of instruction processing.

[0067] After obtaining the first execution result of the first processing instruction in step S52, the instruction processing method according to the embodiment of the present disclosure further includes:

[0068] In the case where the first execution result is input data for a second processing instruction in a third processing core, the first execution result is directly routed to the third processing core so that the third processing core executes the second processing instruction based on the first execution result,

[0069] The third processing core is a subsequent processing core of the first processing core on the data pipeline path.

[0070] That is to say, if the first processing core has a subsequent processing core in the data pipeline path, namely, a third processing core; and the first execution result of the first processing instruction is the input data of the second processing instruction in the third processing core, and the first execution result has no dependency relationship with other processing instructions in the first processing core, then the first processing core can send the first execution result to the routing unit via a bypass bypassing the reordering unit, and the routing unit directly routes it to the third processing core at the subsequent level, so that the third processing core executes the second processing instruction based on the first execution result.

[0071] In this way, the execution result as the input of the next-stage processing core can bypass the reordering unit and be directly routed to the next-stage processing core, saving the overhead of reordering the instruction execution results and improving the efficiency of instruction processing.

[0072] In some possible implementations, the instruction processing method according to the embodiment of the present disclosure further includes:

[0073] When the first execution result is not input data of the third processing core, or the first processing core is the last-level processing core on the data pipeline path, the first execution result is sent to a reordering unit of the first processing core so that the reordering unit reorders the first execution result.

[0074] That is to say, if the first execution result is not the input data of the third processing core (it is possible that the first execution result is the input data of the processing instruction of the first processing core itself), or the first processing core is the last-level processing core on the data pipeline path (that is, there is no processing core on the same data pipeline path after the first processing core), it needs to be reordered and cannot be directly routed and sent.

[0075] In this case, the first execution result may be sent to the reordering unit of the first processing core, so that the reordering unit reorders the first execution result and writes it back in sequence, and instruction processing is implemented through a conventional path.

[0076] In this way, the flexibility of instruction processing can be improved.

[0077] Figure 6 A schematic diagram of a processing procedure of an instruction processing method provided in an embodiment of the present disclosure. Figure 6 The first processing core and the second processing core on the data pipeline path are respectively shown. The first processing core and the second processing core are both provided with a CPU pipeline, including a scheduling unit, an execution unit (corresponding to Figure 6 Multiple execution stages E) and reorder units in the processing core instruction sequence; the processing instructions in the processing core instruction sequence are input into the scheduling unit after the instruction fetch stage F and the decoding stage D; they are dispatched to the execution unit for execution through the scheduling unit; the execution results are input into the reorder unit for reordering and written back to the register in sequence W.

[0078] like Figure 6 As shown, the first processing core and the second processing core are both configured with a routing unit R, and are configured with a bypass that bypasses the scheduling unit and directly connects to the execution unit, and a bypass that bypasses the reordering unit and directly connects to the routing unit R. The processing instructions and the corresponding execution results can be processed by the CPU pipeline through a conventional path, and can also bypass the scheduling unit and / or the reordering unit through a bypass as needed.

[0079] In the example, if the execution result of a processing instruction in the second processing core is the input data of the first processing core, and there is no dependency relationship with other processing instructions in the second processing core, the execution unit of the second processing core sends the execution result of the processing instruction to the routing unit via a bypass bypassing the reordering unit, and the routing unit directly routes it to the first processing core.

[0080] In the example, after receiving the input data, the first processing core fetches and decodes the first processing instruction; and determines that the first processing instruction meets the direct execution condition; sends the decoded first processing instruction to the execution unit for direct execution via a bypass bypassing the scheduling unit to obtain a first execution result.

[0081] Furthermore, if the first execution result is the third processing core ( Figure 6 If the first processing core receives the input data of the second processing instruction in the first processing core (not shown), and has no dependency relationship with other processing instructions in the first processing core, the first processing core sends the first execution result to the routing unit via a bypass bypassing the reordering unit, and the routing unit directly routes the result to the third processing core at the next level.

[0082] In the example, if the first execution result is not the input data of the third processing core, or the first processing core is the last level processing core on the data pipeline path, the first execution result reordering unit is used to reorder the first execution result and write it back to W sequentially, thereby implementing instruction processing through the conventional path.

[0083] In this way, Figure 6 In the example, the execution process of out-of-order dispatch - out-of-order execution of the second processing core - out-of-order execution of the first processing core - ... - sequential write-back of the last-level processing core of the data pipeline path is implemented, which can save the overhead of continuous instruction scheduling and reordering of instruction execution results of multiple processing cores on the data pipeline path during the data flow process, and improve the efficiency of instruction processing.

[0084] In some possible implementations, multiple data pipeline paths can be configured in a many-core system, each data pipeline path includes multiple stages of processing cores, and adjacent processing cores in the multiple stages of processing cores are communicatively connected in a data flow pipeline manner, that is, the output data of the previous stage processing core serves as the input data of the next stage processing core.

[0085] Figure 7 A schematic diagram of a data pipeline path in a multi-core system provided by an embodiment of the present disclosure. Figure 7 As shown, three data pipeline paths are set in the many-core system: path 1, path 2 and path 3. The processing cores on each path can implement instruction processing in the above manner, thereby improving processing efficiency.

[0086] In some possible implementations, the instruction sequence to be executed by the first processing core may include processing instructions for a first task and processing instructions for a second task, the processing instructions for the first task are executed by data triggering, and the processing instructions for the second task are executed by control triggering.

[0087] That is to say, the tasks executed by the first processing core can be divided into two categories. One category is tasks limited to the processing core and executed according to the normal control flow (second task). Each processing instruction of the second task is triggered for execution based on the control logic within the processing core, that is, it is executed when the control logic on which the processing instruction depends is satisfied; the other category is tasks triggered by data sent by other processing cores (first task). Each processing instruction of the first task is executed based on data triggering, that is, it is executed when the input data on which the processing instruction depends is prepared.

[0088] The processing instructions of the first task and the processing instructions of the second task are both executed in the processing mode of the CPU pipeline, that is, the instruction processing process of out-of-order dispatch-out-of-order execution-in-order write-back is realized through the scheduling unit, the execution unit and the reordering unit.

[0089] Among them, the CPU out-of-order execution, branch prediction and other technologies are essentially to solve the problem of insufficient pipeline utilization caused by data dependency or control dependency within the program. According to the embodiments of the present disclosure, by hybrid scheduling of the processing instructions of the first task and the processing instructions of the second task, the complex dependency judgment logic can be reduced while improving the pipeline utilization, thereby improving the overall processing efficiency.

[0090] In some possible implementations, the instruction processing method according to the embodiment of the present disclosure further includes:

[0091] During the execution of the processing instructions of the first task by the first processing core, if none of the processing instructions of the first task in the instruction sequence meets the data trigger condition, a third processing instruction that meets the control trigger condition in the processing instructions of the second task is fetched and decoded, and sent to the scheduling unit of the first processing core, so that the scheduling unit of the first processing core dispatches the third processing instruction and the execution unit executes it.

[0092] For example, during the execution of the processing instructions of the first task by the first processing core, if the processing instructions of the first task in the instruction sequence do not meet the data trigger conditions, that is, the input data on which the processing instructions of the first task depend are not fully prepared, and a data dependency problem is encountered, then the processing method in the related technology is to wait for the input data, resulting in idleness of the pipeline and reduced utilization.

[0093] According to an embodiment of the present disclosure, when the first task encounters a data dependency problem, a third processing instruction in the processing instruction of the second task that meets the control trigger condition can be fetched and decoded, and the decoded third processing instruction can be sent to the scheduling unit, so that the scheduling unit dispatches the third processing instruction and the execution unit executes it, thereby realizing the interleaved execution of the processing instructions of the first task and the processing instructions of the second task, thereby improving the utilization rate of the pipeline.

[0094] In some possible implementations, the instruction processing method according to the embodiment of the present disclosure further includes:

[0095] During the execution of the processing instructions of the second task by the first processing core, if none of the processing instructions of the second task in the instruction sequence meets the control trigger condition, a fourth processing instruction that meets the data trigger condition in the processing instructions of the first task is fetched and decoded, and sent to the scheduling unit of the first processing core, so that the scheduling unit of the first processing core dispatches the fourth processing instruction and the execution unit executes it.

[0096] For example, during the execution of the processing instructions of the second task by the first processing core, if the processing instructions of the second task in the instruction sequence do not meet the control trigger conditions, that is, the control logic on which the processing instructions of the second task rely are not fully satisfied, and a control dependency problem is encountered, then the processing method in the related technology is to wait for the control logic to be satisfied, resulting in idleness of the pipeline and reduced utilization.

[0097] Similar to the previous processing method, according to an embodiment of the present disclosure, when the second task encounters a control dependency problem, the fourth processing instruction in the processing instruction of the first task that meets the control trigger condition can be fetched and decoded, and the decoded fourth processing instruction can be sent to the scheduling unit, so that the scheduling unit dispatches the fourth processing instruction and the execution unit executes it, thereby realizing the interleaved execution of the processing instructions of the first task and the processing instructions of the second task, thereby improving the utilization rate of the pipeline.

[0098] Figure 8 Schematic diagram of interleaved execution of instructions in a processing core provided by an embodiment of the present disclosure. Figure 8 As shown, in the core storage of the processing core, there are multiple processing instructions of task 1 (data trigger execution) and multiple processing instructions of task 2 (control trigger execution), corresponding to Figure 8 The blue and orange lines in the diagram.

[0099] In the example, during the execution of the processing instructions of task 1 by the processing core, if there are processing instructions that meet the data trigger condition among the processing instructions of task 1, the processing instruction can be fetched and decoded and sent to the scheduling unit, so that the scheduling unit dispatches the processing instruction and the execution unit executes it to achieve regular processing; if there are no processing instructions that meet the data trigger condition among the processing instructions of task 1, a third processing instruction that meets the control trigger condition can be selected from the processing instructions of the second task, and the third processing instruction can be fetched and decoded and sent to the scheduling unit, so that the scheduling unit dispatches the third processing instruction and the execution unit executes it.

[0100] Similarly, during the execution of the processing instructions of task 2 by the processing core, if there are processing instructions that meet the control trigger condition among the processing instructions of task 2, the processing instruction can be fetched and decoded and sent to the scheduling unit, so that the scheduling unit dispatches the processing instruction and the execution unit executes it to achieve regular processing; if there are no processing instructions that meet the control trigger condition among the processing instructions of task 2, a fourth processing instruction that meets the data trigger condition can be selected from the processing instructions of the first task, the fourth processing instruction can be fetched and decoded and sent to the scheduling unit, so that the scheduling unit dispatches the fourth processing instruction and the execution unit executes it.

[0101] Since Task 1 and Task 2 are in the same out-of-order execution path, it can be considered that Task 1 and Task 2 essentially belong to the same larger task, but the mapping process divides this larger task into different parts. Therefore, the interleaved execution process does not involve context switching in the CPU pipeline.

[0102] In actual processing, it is possible that multiple processing instructions of task 1 are executed, then multiple processing instructions of task 2 are executed, and then multiple processing instructions of task 1 are executed. The present disclosure does not limit the specific number of instructions to be interleaved.

[0103] In this way, the processing instructions of the first task and the processing instructions of the second task can be interleaved, thereby improving the utilization rate of the pipeline.

[0104] In related technologies, branch prediction technology is used to solve the control dependency problem in the CPU execution process. That is, when the CPU needs to decide which branch the next instruction to be executed is based on the result of a conditional judgment, but the conditional judgment is still in the pipeline and no result is obtained, the CPU can speculatively guess a branch to execute in order to avoid the pipeline being idle. When the conditional judgment is executed, if the prediction is correct, the pipeline runs normally. If the prediction is wrong, the pipeline with the wrong execution is cleared and switched to another branch for execution, which will incur additional transfer costs.

[0105] According to the embodiment of the present disclosure, the CPU control flow pipeline is combined with the data flow pipeline to realize a two-stage pipeline architecture of the data pipeline between the processing cores and the CPU pipeline within the processing core. According to the instruction processing method of the embodiment of the present disclosure, branch prediction and execution can be realized in the processing core.

[0106] In some possible implementations, the instruction processing method according to the embodiment of the present disclosure may further include:

[0107] Upon receiving the branch prediction result sent by the second processing core routing, determine a fifth processing instruction corresponding to the branch prediction result from the instruction sequence of the first processing core, wherein the branch prediction result is used to indicate a control trigger branch predicted by a previous level processing instruction of the fifth processing instruction, and control trigger execution is performed between the previous level processing instruction and the fifth processing instruction;

[0108] fetching and decoding the fifth processing instruction, and sending the instruction to the scheduling unit of the first processing core, so that the scheduling unit of the first processing core dispatches the fifth processing instruction and the execution unit executes the fifth processing instruction;

[0109] Upon receiving the actual execution result of the previous-stage processing instruction routed and sent by the second processing core, if the actual execution result matches the branch prediction result, the execution unit of the first processing core outputs the execution result of the fifth processing instruction.

[0110] For example, for a target task triggered by a control, multiple processing instructions of the target task can be mapped to different processing cores, and the processing instructions corresponding to different execution branches corresponding to the previous level processing instructions can be mapped to different processing cores. For example, in an if statement, if condition 1 is met, instruction B is executed; else, instruction C is executed; whether condition 1 is met is the execution result of instruction A; the previous level instruction A can be mapped to processing core 0, instruction B is mapped to processing core 1, and instruction C is mapped to processing core 2.

[0111] In some possible implementations, when the previous level processing instruction in the second processing core of the previous level on the data pipeline path is not executed or is being executed but no actual execution result is obtained, if the first processing core of the next level is idle or has a low occupancy rate, the second processing core can generate a branch prediction result predicted by the previous level processing instruction, which is used to indicate the control trigger branch predicted by the previous level processing instruction of the fifth processing instruction, for example, satisfying condition 1; and route the branch prediction result to the corresponding first processing core. The branch prediction result can be generated randomly or according to preset rules. Branch prediction results can also be generated for each possible control trigger branch and routed to the corresponding processing cores respectively. The present disclosure is not limited to this.

[0112] In some possible implementations, after receiving the branch prediction result, the first processing core may determine a fifth processing instruction corresponding to the branch prediction result from the instruction sequence, such as instruction B; fetch and decode the fifth processing instruction, and send it to the scheduling unit, so that the scheduling unit dispatches the fifth processing instruction and the execution unit executes it to obtain an execution result;

[0113] In some possible implementations, after the second processing core of the previous stage completes the execution of the processing instruction of the previous stage and obtains the actual execution result, the second processing core of the previous stage may send the actual execution result to the first processing core of the next stage; after receiving the actual execution result, the first processing core may compare the actual execution result with the branch prediction result. If the actual execution result matches the branch prediction result, the execution unit of the first processing core outputs the execution result of the fifth processing instruction. On the contrary, if the actual execution result does not match the branch prediction result, the execution unit of the first processing core may discard the execution result of the fifth processing instruction.

[0114] Fig. 9 A schematic diagram of branch prediction provided by an embodiment of the present disclosure. Fig. 9As shown, processing core 0 is the previous level processing core on the data pipeline path, and processing core 1 and processing core 2 are the next level processing cores on the data pipeline path. The target task of the control trigger may include, for example, instruction A, instruction B and instruction C; the control trigger condition may be, for example, if condition 1 is satisfied, then instruction B is executed; else, instruction C is executed; and whether condition 1 is satisfied is the execution result of instruction A; the previous level instruction A may be mapped to processing core 0, instruction B is mapped to processing core 1, and instruction C is mapped to processing core 2.

[0115] In the example, when the processing core 0 does not obtain the actual execution result of instruction A, the branch prediction result can be generated in advance by the routing unit R and sent to the processing core 1 and / or the processing core 2. The branch prediction result of one of the branches can be generated randomly, or the branch prediction results of two branches can be generated at the same time, and the number of branch prediction results can be determined according to the idle conditions of the processing core 1 and the processing core 2.

[0116] In the example, for processing core 1, after receiving the branch prediction result, instruction B corresponding to the branch prediction result can be determined from the instruction sequence; instruction B is fetched and decoded and sent to the scheduling unit, so that the scheduling unit dispatches instruction B to the execution unit for execution to obtain the execution result; for processing core 2, instruction C can also be executed to obtain the execution result.

[0117] In the example, after processing core 0 obtains the actual execution result of instruction A, the actual execution result may be sent to processing core 1 and / or processing core 2. For processing core 1, after receiving the actual execution result, it may be compared with the branch prediction result. If they match, the execution result of instruction B is output; otherwise, the execution result of instruction B is discarded. Processing core 2 may perform similar processing.

[0118] In this way, when the execution of the previous level instruction in the control trigger task is completed, the execution result of the next level instruction can be quickly obtained, thereby improving the instruction execution efficiency of the control trigger task.

[0119] According to the embodiments of the present disclosure, a multi-core system pipeline architecture with two layers of nested CPU control flow pipeline and data flow pipeline can be implemented. While maintaining a certain degree of versatility and flexibility, it can utilize the advantages of the multi-core system to enhance the ability of large-scale parallel execution and improve instruction processing efficiency.

[0120] According to the instruction processing method of the embodiment of the present invention, for the input data that is directly routed and sent by the previous level processing core without reordering, the corresponding first processing instruction can bypass the scheduling unit and be directly sent to the execution unit, and the execution unit can directly execute the first processing instruction; and the execution result that serves as the input of the next level processing core can bypass the reordering unit and be directly routed and sent to the next level processing core, thereby realizing the execution process of out-of-order dispatch-out-of-order execution-out-of-order execution-sequential write back in multiple processing cores on the same data pipeline path, saving the overhead of continuous instruction scheduling and reordering of instruction execution results of multiple processing cores on the data pipeline path during the data flow process, and improving the efficiency of instruction processing.

[0121] According to the instruction processing method of the embodiment of the present disclosure, it is possible to realize the interleaved execution of the two types of processing instructions by mixed scheduling of the processing instructions in the control-triggered task and the processing instructions in the data-triggered task in the processing core, thereby improving the utilization rate of the pipeline. In addition, it is possible to map the processing instructions of different execution branches corresponding to the previous level processing instructions in the control-triggered task to different processing cores, perform branch prediction before the execution of the previous level processing instructions, and execute the next level processing instructions in advance based on the branch prediction results by the next level processing core; then compare with the actual execution results of the previous level processing instructions, retain the correct execution results, and quickly obtain the execution results of the next level instructions, thereby improving the instruction execution efficiency of the control-triggered tasks.

[0122] According to the instruction processing method of the embodiment of the present disclosure, it can be applied to the application scenario of accelerating the calculation of neural networks through a many-core system. The neural network can be any type of neural network such as an artificial neural network ANN, a spiking neural network SNN, etc. The neural network is used to perform any of the processing tasks such as image processing tasks, voice processing tasks, text processing tasks, and video processing tasks. The data processed by the neural network includes any of images, voices, texts, and videos, and the present disclosure does not limit this.

[0123] Among them, the tasks in each processing core of the many-core system can be split into sub-tasks in the processing tasks of the neural network and mapped to the processing cores. The present disclosure does not limit the specific splitting and mapping methods.

[0124] It can be understood that the above-mentioned various method embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not repeat them. It can be understood by those skilled in the art that in the above-mentioned method of the specific implementation method, the specific execution order of each step should be determined according to its function and possible internal logic.

[0125] In addition, the present disclosure also provides an instruction processing device, an electronic device, and a computer-readable storage medium, all of which can be used to implement any instruction processing method provided by the present disclosure. The corresponding technical solutions and descriptions are referred to the corresponding records in the method part and will not be repeated here.

[0126] Fig.10 A block diagram of an instruction processing device provided in an embodiment of the present disclosure.

[0127] Reference Fig.10 The embodiment of the present disclosure provides an instruction processing device, which is applied to a first processing core among multiple processing cores of a many-core system, wherein the processing core of the many-core system is configured with a scheduling unit, an execution unit and a reordering unit, wherein the scheduling unit is used to dispatch processing instructions that meet execution conditions in an instruction sequence to be executed by the processing core to the execution unit in a disorderly order; the execution unit is used to execute the received processing instructions to obtain execution results of the processing instructions; the reordering unit is used to reorder the execution results and write the execution results back to the register of the processing core in sequence; wherein the device comprises:

[0128] an instruction fetching and decoding module 61, configured to fetch and decode the first processing instruction to obtain the decoded first processing instruction when the first processing core receives input data of the first processing instruction in the instruction sequence;

[0129] The instruction execution module 62 is used to directly execute the decoded first processing instruction through the execution unit of the first processing core to obtain a first execution result of the first processing instruction when the first processing instruction meets the direct execution condition; the direct execution condition includes: the input data of the first processing instruction is directly routed to the first processing core by the execution unit of the second processing core, wherein the second processing core is the previous level processing core of the first processing core on the data pipeline path.

[0130] In some possible implementations, the device also includes: a result routing module, which is used to route the first execution result directly to the third processing core when the first execution result is input data of the second processing instruction in the third processing core, so that the third processing core executes the second processing instruction based on the first execution result, wherein the third processing core is a subsequent-level processing core of the first processing core on the data pipeline path.

[0131] In some possible implementations, the device also includes: a result sending module, which is used to send the first execution result to the reordering unit of the first processing core when the first execution result is not the input data of the third processing core, or the first processing core is the last-level processing core on the data pipeline path, so that the reordering unit reorders the first execution result.

[0132] In some possible implementations, the data pipeline path includes multiple stages of processing cores, and adjacent processing cores in the multiple stages of processing cores are communicatively connected in a data flow pipeline manner.

[0133] In some possible implementations, the instruction sequence of the first processing core includes processing instructions for a first task and processing instructions for a second task, the processing instructions for the first task are executed by data triggering, and the processing instructions for the second task are executed by control triggering, wherein the apparatus further includes:

[0134] The first interleaving module is used for fetching and decoding a third processing instruction that meets a control trigger condition in the processing instructions of the second task during the execution of the processing instructions of the first task by the first processing core, when none of the processing instructions of the first task in the instruction sequence meets a data trigger condition, and sending the instruction to the scheduling unit of the first processing core, so that the scheduling unit of the first processing core dispatches the third processing instruction and the execution unit executes the third processing instruction.

[0135] In some possible implementations, the device further includes:

[0136] The second interleaving module is used for fetching and decoding a fourth processing instruction that meets the data trigger condition in the processing instructions of the first task during the execution of the processing instructions of the second task by the first processing core, when none of the processing instructions of the second task in the instruction sequence meets the control trigger condition, and sending the instruction to the scheduling unit of the first processing core, so that the scheduling unit of the first processing core dispatches the fourth processing instruction and the execution unit executes it.

[0137] In some possible implementations, the device further includes:

[0138] an instruction determination module, configured to, upon receiving a branch prediction result sent by the second processing core routing, determine from the instruction sequence of the first processing core a fifth processing instruction corresponding to the branch prediction result, wherein the branch prediction result is used to indicate a control trigger branch predicted by a previous level processing instruction of the fifth processing instruction, and control trigger execution is performed between the previous level processing instruction and the fifth processing instruction;

[0139] an instruction sending module, configured to fetch and decode the fifth processing instruction, and send the instruction to the scheduling unit of the first processing core, so that the scheduling unit of the first processing core dispatches the fifth processing instruction and the execution unit executes the fifth processing instruction;

[0140] A result output module is used to, upon receiving the actual execution result of the previous level processing instruction sent by the second processing core routing, if the actual execution result matches the branch prediction result, the execution unit of the first processing core outputs the execution result of the fifth processing instruction.

[0141] Fig.11 A block diagram of an electronic device provided in an embodiment of the present disclosure.

[0142] Reference Fig.11 An embodiment of the present disclosure provides an electronic device, which includes multiple processing cores 1001 and an on-chip network 1002, wherein the multiple processing cores 1001 are connected to the on-chip network 1002, and the on-chip network 1002 is used to exchange data between the multiple processing cores and external data.

[0143] One or more instructions are stored in one or more processing cores 1001, and the one or more instructions are executed by one or more processing cores 1001, so that the one or more processing cores 1001 can execute the above-mentioned instruction processing method.

[0144] In some embodiments, the electronic device may be a brain-like chip. Since brain-like chips can use vectorized computing methods and need to call in parameters such as weight information of the neural network model through external memory such as double data rate (DDR) synchronous dynamic random access memory.

[0145] The present disclosure also provides a computer-readable storage medium on which a computer program is stored, wherein the computer program implements the above-mentioned instruction processing method when executed by a processor / processing core. The computer-readable storage medium may be a volatile or non-volatile computer-readable storage medium.

[0146] The embodiments of the present disclosure also provide a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above-mentioned instruction processing method.

[0147] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In a hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable storage medium, which may include a computer storage medium (or a non-transitory medium) and a communication medium (or a temporary medium).

[0148] As is known to those of ordinary skill in the art, the term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable program instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), flash memory or other memory technology, portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. In addition, it is known to those of ordinary skill in the art that communication media typically contain computer-readable program instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and may include any information delivery medium.

[0149] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0150] The computer program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed completely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be personalized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0151] The computer program product described herein may be implemented in hardware, software, or a combination thereof. In one optional embodiment, the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK), etc.

[0152] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0153] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0154] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0155] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0156] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A command processing method, characterized in that: The method is applied to a first processing core among a plurality of processing cores of a many-core system, The processing core of the multi-core system is configured with a scheduling unit, an execution unit and a reordering unit, wherein the scheduling unit is used to dispatch processing instructions that meet execution conditions in the instruction sequence to be executed by the processing core to the execution unit in a disorderly order; the execution unit is used to execute the received processing instructions to obtain the execution result of the processing instructions; The reordering unit is used to reorder the execution results and write the execution results back to the register of the processing core in sequence; Wherein, the method comprises: When the first processing core receives input data of a first processing instruction in the instruction sequence, fetching and decoding the first processing instruction to obtain a decoded first processing instruction; When the first processing instruction satisfies a direct execution condition, directly executing the decoded first processing instruction through an execution unit of the first processing core to obtain a first execution result of the first processing instruction; The direct execution condition includes: the input data of the first processing instruction is directly routed to the first processing core by the execution unit of the second processing core, wherein the second processing core is the previous processing core of the first processing core on the data pipeline path.

2. The method according to claim 1, characterized in that The method further comprises: In the case where the first execution result is input data for a second processing instruction in a third processing core, the first execution result is directly routed to the third processing core so that the third processing core executes the second processing instruction based on the first execution result, The third processing core is a subsequent processing core of the first processing core on the data pipeline path.

3. The method according to claim 2, characterized in that The method further comprises: When the first execution result is not input data of the third processing core, or the first processing core is the last-level processing core on the data pipeline path, the first execution result is sent to a reordering unit of the first processing core so that the reordering unit reorders the first execution result.

4. The method according to claim 1, characterized in that: The data pipeline path includes multiple stages of processing cores, and adjacent processing cores in the multiple stages of processing cores are communicatively connected in a data flow pipeline manner.

5. The method according to claim 1, characterized in that The instruction sequence of the first processing core includes processing instructions of a first task and processing instructions of a second task, the processing instructions of the first task are executed by data triggering, and the processing instructions of the second task are executed by control triggering, Wherein, the method further comprises: During the execution of the processing instructions of the first task by the first processing core, if none of the processing instructions of the first task in the instruction sequence meets the data trigger condition, a third processing instruction that meets the control trigger condition in the processing instructions of the second task is fetched and decoded, and sent to the scheduling unit of the first processing core, so that the scheduling unit of the first processing core dispatches the third processing instruction and the execution unit executes it.

6. The method according to claim 5, characterized in that The method further comprises: During the execution of the processing instructions of the second task by the first processing core, if none of the processing instructions of the second task in the instruction sequence meets the control trigger condition, a fourth processing instruction that meets the data trigger condition in the processing instructions of the first task is fetched and decoded, and sent to the scheduling unit of the first processing core, so that the scheduling unit of the first processing core dispatches the fourth processing instruction and the execution unit executes it.

7. The method according to claim 1, characterized in that The method further comprises: Upon receiving the branch prediction result sent by the second processing core routing, determine a fifth processing instruction corresponding to the branch prediction result from the instruction sequence of the first processing core, wherein the branch prediction result is used to indicate a control trigger branch predicted by a previous level processing instruction of the fifth processing instruction, and control trigger execution is performed between the previous level processing instruction and the fifth processing instruction; fetching and decoding the fifth processing instruction, and sending the instruction to the scheduling unit of the first processing core, so that the scheduling unit of the first processing core dispatches the fifth processing instruction and the execution unit executes the fifth processing instruction; Upon receiving the actual execution result of the previous-stage processing instruction routed and sent by the second processing core, if the actual execution result matches the branch prediction result, the execution unit of the first processing core outputs the execution result of the fifth processing instruction.

8. An instruction processing device, characterized in that: The device is applied to a first processing core among a plurality of processing cores of a many-core system, The processing core of the multi-core system is configured with a scheduling unit, an execution unit and a reordering unit, wherein the scheduling unit is used to dispatch processing instructions that meet execution conditions in the instruction sequence to be executed by the processing core to the execution unit in a disorderly order; the execution unit is used to execute the received processing instructions to obtain the execution result of the processing instructions; The reordering unit is used to reorder the execution results and write the execution results back to the register of the processing core in sequence; Wherein, the device comprises: an instruction fetching and decoding module, configured to fetch and decode the first processing instruction to obtain the decoded first processing instruction when the first processing core receives input data of the first processing instruction in the instruction sequence; an instruction execution module, configured to directly execute the decoded first processing instruction through an execution unit of the first processing core to obtain a first execution result of the first processing instruction when the first processing instruction meets a direct execution condition; The direct execution condition includes: the input data of the first processing instruction is directly routed to the first processing core by the execution unit of the second processing core, wherein the second processing core is the previous processing core of the first processing core on the data pipeline path.

9. An electronic device, characterized in that: include: Multiple processing cores; as well as An on-chip network is configured to exchange data between the multiple processing cores and external data; wherein one or more instructions are stored in one or more of the processing cores, and one or more of the instructions are executed by one or more of the processing cores, so that one or more of the processing cores can execute the instruction processing method described in any one of claims 1-7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the computer program implements the instruction processing method according to any one of claims 1 to 7.

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