Platform environment control interface verification method and device, equipment and medium

Abstract

The invention discloses a platform environment control interface verification method, apparatus and device, and a medium, which are applied to the technical field of platform environment control interface verification, and convert a platform environment control interface bus signal into an input signal of a slave model; carrying out filtering processing on the input signal to obtain a filtered signal, carrying out code element identification on the filtered signal to obtain a code element identification signal, and converting the code element identification signal into a data frame taking a byte as a unit; analyzing the data frame to obtain analysis data, and generating a return data packet based on the analysis data; performing exception processing on the output signal carrying the return data packet based on parameter configuration to obtain an exception signal; and transmitting the abnormal signal to a host based on a platform environment control interface bus so as to verify a platform environment control interface function of the host. Therefore, the abnormal response correctness of the platform environment control interface function can be verified.

Description

Technical Field

[0001] The present invention relates to the technical field of platform environment control interface verification, and in particular to a platform environment control interface verification method, device, equipment and medium. Background Art

[0002] PECI (Platform Environment Control Interface) is an important bus interface used by the management controller to monitor the CPU (Central Processing Unit). It has a simple interface and can monitor the status of each CPU through a single communication line. PECI has a timing negotiation mechanism that allows it to connect CPUs of different speeds simultaneously with a single line and communicate normally according to the actual speed of each CPU. The PECI bus uses a simple single line to communicate with multiple CPUs, which is bound to be prone to many communication anomalies. Therefore, an anomaly detection mechanism is designed to respond to anomalies.

[0003] Currently, how to verify the correctness of abnormal responses of platform environment control interface functions is a problem that those skilled in the art need to solve. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a platform environment control interface verification method, device, equipment and medium, which can verify the correctness of the abnormal response of the platform environment control interface function. The specific scheme is as follows:

[0005] In a first aspect, the present invention provides a platform environment control interface verification method, comprising:

[0006] Convert the platform environment control interface bus signal into an input signal of the slave model;

[0007] Filtering the input signal to obtain a filtered signal, performing symbol recognition on the filtered signal to obtain a symbol recognition signal, and converting the symbol recognition signal into a data frame in bytes;

[0008] Analyzing the data frame to obtain analysis data, and generating a return data packet based on the analysis data;

[0009] Performing exception processing on the output signal carrying the return data packet based on the parameter configuration to obtain an exception signal;

[0010] The abnormal signal is transmitted to the host based on the platform environment control interface bus to verify the platform environment control interface function of the host.

[0011] Optionally, performing symbol recognition on the filtered signal to obtain a symbol recognition signal includes:

[0012] Record the high level duration during the timing negotiation cycle;

[0013] Determining a signal period of the filtered signal based on the high level duration;

[0014] Code element recognition is performed based on the signal period, and the time interval between the rising edge and the falling edge of the signal after filtering is recorded during the recognition process. The code element recognition result is determined based on the time interval to obtain a code element recognition signal.

[0015] Optionally, also include:

[0016] Continuously detect the continuous high level time and continuous low level time of the signal after filtering. When the continuous low level time exceeds the preset multiple of the previous continuous high level time detected, it is determined that the message is finished, the post-message end process is carried out, and the slave model enters the idle state.

[0017] Optionally, performing exception processing on the output signal carrying the returned data packet based on the parameter configuration to obtain an exception signal includes:

[0018] When the exception handling mode determined based on the parameter configuration is a connection timeout exception, the output signal carrying the return data packet is always set to 0 to obtain an exception signal.

[0019] Optionally, also include:

[0020] In the case where the exception handling mode determined based on the parameter configuration is a bus contention exception, the host output signal is delayed based on the active delay register to simulate the bus contention and obtain an exception signal.

[0021] Optionally, performing exception processing on the output signal carrying the returned data packet based on the parameter configuration to obtain an exception signal includes:

[0022] In the case where the exception handling mode determined based on the parameter configuration is a timing negotiation exception, a timing negotiation exception is generated by configuring the first address negotiation parameter, the second address negotiation parameter and the message negotiation parameter in the timing negotiation module, and an exception signal corresponding to the output signal of the returned data packet is obtained;

[0023] The first address negotiation parameter, the second address negotiation parameter and the message negotiation parameter are respectively the time when the platform environment control interface bus is driven to output a high level in the first address negotiation phase, the second address negotiation phase and the message negotiation phase.

[0024] Optionally, analyzing the data frame to obtain analysis data includes:

[0025] Analyze the data frame to obtain the slave address, write byte length, read byte length, instruction code, write data and verification information;

[0026] Accordingly, generating a return data packet based on the analysis data includes:

[0027] When the preset verification function is started, the target verification value corresponding to the slave address, the write byte length, the read byte length, the instruction code, and the write data is calculated, the target verification value is compared with the verification information to obtain the verification result, and the end code is marked based on the verification result;

[0028] If it is determined based on the check error enabling parameter that no check error is generated, then when the preset check function is started, a correct first check value is calculated based on the slave address, the write byte length, the read byte length, the instruction code, the write data and the check information;

[0029] Calculate a correct second check value based on the completion code and the read data byte, wherein the read data byte includes the data to be returned;

[0030] If it is determined based on the check error enabling parameter that a check error is generated, then generating an erroneous first check value and / or generating an erroneous second check value;

[0031] A return data packet is generated based on the completion code, the read data byte, the first check value, and the first check value.

[0032] In a second aspect, the present invention discloses a platform environment control interface verification device, comprising:

[0033] An input signal conversion module, used for converting a platform environment control interface bus signal into an input signal of a slave model;

[0034] An input signal processing module, used for filtering the input signal to obtain a filtered signal, performing symbol recognition on the filtered signal to obtain a symbol recognition signal, and converting the symbol recognition signal into a data frame in bytes;

[0035] A data processing module, used for analyzing the data frame to obtain analysis data, and generating a return data packet based on the analysis data;

[0036] An output signal processing module, used for performing exception processing on the output signal carrying the return data packet based on parameter configuration to obtain an exception signal;

[0037] The abnormal signal transmission module is used to transmit the abnormal signal to the host based on the platform environment control interface bus to verify the platform environment control interface function of the host.

[0038] In a third aspect, the present invention discloses an electronic device, comprising:

[0039] Memory for storing computer programs;

[0040] A processor is used to execute the computer program to implement the steps of the aforementioned platform environment control interface verification method.

[0041] In a fourth aspect, the present invention discloses a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the aforementioned platform environment control interface verification method are implemented.

[0042] In a fifth aspect, the present invention provides a computer program product, comprising a computer program / instruction, which, when executed by a processor, implements the steps of the aforementioned platform environment control interface verification method.

[0043] It can be seen from the above scheme that the present invention provides a platform environment control interface verification method, including: converting a platform environment control interface bus signal into an input signal of a slave model; filtering the input signal to obtain a filtered signal and performing code element recognition on the filtered signal to obtain a code element recognition signal, and converting the code element recognition signal into a data frame in bytes; analyzing the data frame to obtain analysis data, and generating a return data packet based on the analysis data; performing exception processing on the output signal carrying the return data packet based on parameter configuration to obtain an exception signal; transmitting the exception signal to the host based on the platform environment control interface bus to verify the platform environment control interface function of the host.

[0044] It can be seen that the beneficial effect of the present invention is: converting the platform environment control interface bus signal into the input signal of the slave model, then filtering and identifying the code element to obtain the code element identification signal, and converting it into a data frame in bytes, analyzing and generating a return data packet, and performing exception processing on the output signal carrying the return data packet based on the parameter configuration to obtain an abnormal signal, which is transmitted to the host, thereby monitoring the host's verification platform environment control interface function's response to the abnormal signal. In this way, the correctness of the abnormal response of the platform environment control interface function can be verified.

[0045] Correspondingly, a platform environment control interface verification device, equipment and medium provided by the present invention also have the above-mentioned technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0047] Figure 1 A flow chart of a platform environment control interface verification method provided by an embodiment of the present invention;

[0048] Figure 2 A schematic diagram of a PECI slave model framework provided by an embodiment of the present invention;

[0049] Figure 3 A PECI bus connection diagram provided in an embodiment of the present invention;

[0050] Figure 4 A schematic diagram of a PECI signal waveform provided by an embodiment of the present invention;

[0051] Figure 5 A schematic diagram of a timing negotiation process provided by an embodiment of the present invention;

[0052] Figure 6 A schematic diagram of implementing bus contention provided by an embodiment of the present invention;

[0053] Figure 7 A schematic diagram of the structure of a platform environment control interface verification device provided by an embodiment of the present invention;

[0054] Figure 8 A structural diagram of an electronic device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0055] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0056] The terms "including" and "having" in the specification of the present invention and the above-mentioned drawings, as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but may include steps or units that are not listed.

[0057] PECI is a communication interface between Intel processors and management controllers (e.g., baseboard management controllers, BMCs). PECI provides services that allow the management controller to configure, monitor, and debug the platform by accessing various registers. A dedicated command protocol is defined, in which the management controller acts as the originator of PECI and the processor acts as the responder of PECI.

[0058] PECI is an important bus interface for monitoring CPUs in management controllers such as BMC. It has a simple interface with only one communication line. It can connect 8 CPUs at the same time to monitor the status of each CPU. PECI has a timing negotiation mechanism, which enables it to connect CPUs of different speeds simultaneously with a single line, and communicate normally according to the actual speed of each CPU. This feature effectively reduces the number of interfaces of the BMC chip. The PECI bus uses an extremely simple single line to communicate with multiple CPUs, which is bound to be prone to many communication anomalies, so an anomaly detection mechanism is designed. When designing the chip, in addition to designing the basic communication functions, the PECI module also needs to design the detection functions of these anomalies accordingly. At present, how to verify the correctness of the abnormal response of the platform environment control interface function is a problem that technicians in this field need to solve. To this end, the present invention provides a platform environment control interface verification scheme that can verify the correctness of the abnormal response of the platform environment control interface function.

[0059] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0060] Next, a platform environment control interface verification method provided by an embodiment of the present invention is introduced in detail. Figure 1 A flow chart of a platform environment control interface verification method provided by an embodiment of the present invention, the platform environment control interface verification method comprising:

[0061] Step S11: converting the platform environment control interface bus signal into an input signal of the slave model.

[0062] The slave model is a model that simulates the behavior of the CPU connected to the platform environment control interface bus. The slave model provided by the embodiment of the present invention includes a three-state signal processing module, an input signal processing module, a data processing module, an output signal processing module and an operation parameter management module.

[0063] See also Figure 2 As shown, Figure 2A schematic diagram of a PECI slave model framework provided by an embodiment of the present invention. The slave model is divided into five major functional modules, namely a three-state signal processing module, an input signal processing module, a data processing module, an output signal processing module and an operation parameter management module.

[0064] Three-state signal processing module: The PECI bus is a single-line signal, and the data transmission on the signal line is bidirectional. The corresponding IO interface is also a bidirectional interface. It is in a high-impedance state when used as an input interface, and outputs voltage according to the data state when used as an output interface. This module handles the interconnection of the PECI host interface and multiple slave interfaces to realize a one-master-multiple-slave connection mechanism. On the one hand, the three-state signal processing module converts the PECI bus signal (peci_inout) into a model input signal (peci_in) for subsequent message processing, and on the other hand, puts the model output signal (peci_out) on the PECI bus for transmission to the host.

[0065] Input signal processing module: Filters the peci_in signal, identifies the code element, and receives data, converting the input serial PECI bus signal into a data frame composed of bytes. In addition, this module also recognizes the end of the message to avoid communication anomalies that cause the module to fail to normally end the transmission process of a data frame.

[0066] Data processing module: Analyze the data frame sent by the input signal processing module, identify the slave address, instruction, write data length, read data length, check information and write data, and judge whether the received data frame is wrong according to the analysis of the message and the result of instruction execution, and generate a return data packet. This module also has a CRC module to perform CRC check on the received message and generate CRC information in the sent data frame.

[0067] Output signal processing module: converts each byte in the transmitted data frame into a serial signal (peci_out) for output. In addition, this module is responsible for the implementation of functions such as timing negotiation and imposing bus signal-related anomalies (such as bus contention).

[0068] Operation parameter management module: The model behavior can be configured through a series of parameters, such as the maximum transmission speed supported by the model, the type of exception and the exception parameters.

[0069] That is, in the embodiment of the present invention, the platform environment control interface bus signal is converted into an input signal of the slave model through the three-state signal processing module. Figure 3 As shown, Figure 3 A PECI bus connection diagram is provided for an embodiment of the present invention, wherein the slave can be understood as a slave module. The three-state signal processing module realizes a single-line interconnection between a host and multiple slaves (such as Figure 3According to the protocol, when the PECI bus is driven, when the output is 1, the bus drive is high level, and when the output is 0, the bus drive is high impedance state, that is, the following formula:

[0070] ;

[0071] At the same time, the PECI bus is pulled down (when the bus is driven in high impedance state, the signal detected by the devices on the bus is low). In this way, the signal detected by the device on the bus (peci_in) is actually the OR of the peci_out signals of all connected devices.

[0072] Step S12: filtering the input signal to obtain a filtered signal, performing symbol recognition on the filtered signal to obtain a symbol recognition signal, and converting the symbol recognition signal into a data frame in bytes.

[0073] In an optional implementation, two D flip-flops may be used to process the input signal to obtain a filtered signal, thereby alleviating signal high-frequency jitter and cross-clock domain problems.

[0074] In an optional embodiment, code element recognition is performed on the filtered signal to obtain a code element recognition signal, including: recording the high level duration in the timing negotiation period; determining the signal period of the filtered signal based on the high level duration; performing code element recognition based on the signal period, recording the time interval between the rising edge and the falling edge of the filtered signal during the recognition process, and determining the code element recognition result based on the time interval to obtain a code element recognition signal. Among them, the signal period can be 4 times the high level duration, and the time interval is less than 2 times the high level duration, then the code element value is 0; otherwise, the code element value is 1. When performing code element recognition here, using 2 times the high level duration as the dividing point to distinguish between 0 and 1 can greatly improve the signal tolerance and avoid recognition abnormalities caused by bus signal jitter.

[0075] Furthermore, the embodiment of the present invention can continuously detect the continuous high level time and continuous low level time of the signal after the filtering process. When the continuous low level time exceeds the preset multiple of the previous continuous high level time detected, it is determined that the message is over, and the post-message end process is performed, and the slave model enters the idle state. The post-message end process is a preset process designed based on demand. For example, the preset multiple is 5 times, and it is understandable that the preset multiple needs to be greater than 3 times.

[0076] In the embodiment of the present invention, the input signal processing module can be used to filter the input signal to obtain a filtered signal, and the filtered signal can be identified by code elements to obtain a code element identification signal, and the code element identification signal can be converted into a data frame in bytes. The input signal processing module includes a filtering module, a code element identification module, a data receiving module, and a message end identification module.

[0077] The filter module is used to alleviate the signal high-frequency jitter and cross-clock domain problems, synchronize the input signal to the clock domain of this module, and reduce the occurrence of metastable states. Here, the peci_in signal passes through two D flip-flops (i.e., it hits two times) for subsequent signal processing.

[0078] The code element recognition module is used to perform code element recognition. Code element recognition is to determine whether the signal carried by a signal pulse is 1 or 0. This includes two aspects: one is signal pulse recognition, and the other is signal pulse analysis. According to the PECI protocol, the value of the code element is distinguished by the duty cycle of the signal. When the output module is driven, the signal duty cycle of 0 is 25%, and the signal duty cycle of 1 is 75%. Before address and information transmission, a signal cycle timing negotiation will be performed. Figure 4 As shown, Figure 4 A schematic diagram of a PECI signal waveform provided by an embodiment of the present invention. The T0 time period is the 0th pulse cycle, and timing negotiation is performed in this cycle. At this time, the duty cycle of the signal is 25%. The symbol recognition module records the duration of the high level in this cycle, which is recorded as , then the signal period After determining the signal period, start the code element recognition. During recognition, record the time interval between the rising edge and the falling edge. If this time interval is less than , the code element value is 0; otherwise, the code element value is 1. Figure 4 In the example, the code element recognition results of the T1, T2, and T3 periods are 0, 1, and 1 respectively. As a dividing point to distinguish 0 and 1, rather than judging whether the time interval is or To distinguish between 0 and 1, the signal tolerance can be greatly improved to avoid recognition anomalies caused by bus signal jitter.

[0079] The data receiving module is used to combine the serial signal transmitted by the code element recognition signal into a data frame in bytes. After the timing negotiation is completed, every 8 signals form 1 byte and are transmitted to the data processing module.

[0080] The message end recognition module is used when an exception occurs, such as abnormal termination of data transmission or loss of code during transmission. The module will remain in a waiting state because it has not received a complete data frame. If the host transmits the next frame of data at this time, the model will work abnormally. For this reason, message end recognition is required. In this model, the continuous high level time and low level time on the PECI bus will be continuously detected. When the low level time exceeds 5 times the previous high level time detected, the message is considered to be over. Then the post-data frame transmission process is carried out, and the slave enters the idle state.

[0081] Step S13: Analyze the data frame to obtain analysis data, and generate a return data packet based on the analysis data.

[0082] The embodiment of the present invention can analyze the data frame to obtain the slave address, write byte length, read byte length, instruction code, write data and verification information; accordingly, based on the analysis data, a return data packet is generated, including: when the preset verification function is started, the slave address, write byte length, read byte length, instruction code, and target verification value corresponding to the write data are calculated, the target verification value is compared with the verification information to obtain a verification result, and an end code is marked based on the verification result; if it is determined that no verification error is generated based on the verification error enabling parameter, then when the preset verification function is started, the correct first verification value is calculated based on the slave address, write byte length, read byte length, instruction code, write data and the verification information; the correct second verification value is calculated based on the completion code and the read data byte, wherein the read data byte contains the data to be returned; if it is determined that a verification error is generated based on the verification error enabling parameter, an erroneous first verification value and / or an erroneous second verification value are generated; and a return data packet is generated based on the completion code, the read data byte, the first verification value, and the first verification value. That is, when no verification error is generated, the first verification value and the second verification value in the return data packet are correct verification values. When a checksum error occurs, an erroneous first checksum value and / or an erroneous second checksum value are used in the returned data packet. The erroneous checksum value can be used to verify whether the abnormal response of the host platform environment control interface function when the checksum is erroneous is accurate.

[0083] Further, if it is determined based on the check error enabling parameter that a check error is generated, the first check value that generates an error and / or the second check value that generates an error are determined based on the error triggering phase configuration parameter. That is, the first check value that generates an error and / or the second check value that generates an error can be determined based on the error triggering phase configuration.

[0084] In addition, in the embodiment of the present invention, the instruction code, write data length and read data length in the received data frame are analyzed to see whether they match. If they do not match or the instruction code cannot be parsed, the end code mark is not an instruction mismatch mark.

[0085] In an embodiment of the present invention, the preset check function is the awfcs function, and the check information is the awfcs byte. The host can generate erroneous check information, and when the comparison result between the target check value and the check information is inconsistent, an erroneous first check value, i.e., a completion code corresponding to the inconsistent check information, is generated, so that the host can verify the preset check function after receiving the output signal of the slave model. That is, the host cpu module generates an awfcs byte and transmits it to the slave peci module through the host peci module. The slave peci module calculates the awfcs value and compares it with the received awfcs byte to determine whether the received data frame is correct. If the comparison fails, the slave peci model will generate an erroneous first FCS byte (i.e., the first check value) and CC (end code) value (Bad Write FCS) to the host peci module. After receiving the first FCS byte and CC value, the host peci module will determine whether it is an FCS caused by an awfcs check error. If so, an awfcs check error interrupt and a corresponding interrupt status flag (Bad Write FCS interrupt) are generated. Here the host generates an erroneous AWFCS byte to verify whether the host PECI module responds correctly to the AWFCS error (can generate a corresponding interrupt and update the interrupt status flag).

[0086] FCS (Frame Check Sequence): Each PECI command requires at least one Frame Check Sequence (FCS) byte to ensure reliable data exchange between the initiator and the client. The PECI message protocol defines two FCS bytes that the client returns to the message initiator. The first FCS byte covers the client address byte, the read and write length bytes, and all bytes in the write data block. The second FCS byte covers the read response data returned by the PECI client. The FCS byte is the result of the cyclic redundancy check (CRC) for each data block.

[0087] In addition to the erroneous awfcs, there are other types of erroneous data frames, such as the read length or write length of the instruction is inconsistent with the protocol. After receiving these erroneous data frames, the slave will generate corresponding FCS (check value) and CC values. The host peci module will generate corresponding interrupts and interrupt status identifiers when receiving the FCS and CC values ​​caused by these erroneous frames. These are all verification platforms that send erroneous data frames through the host peci module, and then verify whether the host peci module responds correctly to the exception.

[0088] The embodiment of the present invention can use a data processing module to analyze the data frame to obtain analysis data, and generate a return data packet based on the analysis data. The data processing module includes a message analysis module, an instruction processing module and a CRC module.

[0089] According to the PECI protocol, the message analysis module analyzes the continuous bytes transmitted by the input signal processing module to obtain the slave address, write byte length, read byte length, instruction code, write data and check information (awfcs function). The awfcs function is Assured Write FCS, which is used to assist the slave to determine whether the received information is correct. Compared with the data packet without the awfcs function, a byte of CRC information is added at the end of the write data. This CRC information is calculated by the host using the CRC algorithm to calculate the slave address byte, write length byte, read length byte, instruction code byte and write data bytes. The PECI model calculates the CRC value of the received slave address byte, write length byte, read length byte, instruction code byte and write data bytes through the CRC module. The calculated CRC value is compared with the received awfcs byte. If they are the same, the completion code (CC) in the sent data frame is marked as Pass; otherwise, it is marked as BadWriteFCS. The awfcs function is controlled by configuring the corresponding variables in the running parameter management module. When the PECI module sends instructions with awfcs information to the slave (PECI model), the verification platform needs to configure the slave to support the awfcs function at the same time. When checking the awfcs function of the PECI module, the wrong awfcs byte can be written, and the function can be judged whether it is correct based on whether the returned end code CC is marked as BadWriteFCS.

[0090] The instruction processing module is used to perform instruction validity analysis and instruction execution. In the PECI protocol, each PECI instruction specifies a valid write length and read length. The instruction processing module analyzes whether the instruction code, write data length, and read data length in the received data frame match according to the specified values ​​in the PECI protocol. If they do not match or the instruction code cannot be parsed, the end code CC is marked as AbortFCS. When verifying the validity of the instruction, if the instruction in the test case does not match the write length or read length, the verification platform determines whether the function is correct based on whether the end code CC in the returned data packet is marked as AbortFCS.

[0091] The instruction execution module generates a data packet to be returned based on the instruction code. The data packet consists of three parts, namely the end code CC, data, and FCS. The end code CC is the result of message analysis and instruction validity analysis. The data is the instruction response message. In order to facilitate the verification platform to determine the correctness of instruction execution, the number of bytes of the data is the read length minus 1, and each byte is the instruction code plus the byte number (starting from 1). For example, if the instruction code is 0x21 and the read length is 4, the number of bytes of the data is 3, which are 0x22, 0x23, and 0x24 respectively. FCS is the CC value and the CRC value calculated by the CRC module for the data.

[0092] The CRC module is used to calculate the CRC value of a string of bytes, using the CRC8 check algorithm. This includes three values: (1) When the AWFCS function is enabled, the CRC value of the address byte, write length byte, read length byte, instruction byte, and write data byte (excluding the AWFCS byte); if the AWFCS function is not enabled, this value is not calculated; (2) The CRC value of the address byte, write length byte, read length byte, instruction byte, and write data byte (including the AWFCS byte if the AWFCS function is enabled);

[0093] (3) CRC value of the completion code and read data bytes. The CRC can be configured by running the parameter control module to generate an incorrect CRC value, and then the CRC check function of the host's PECI module can be verified.

[0094] Step S14: performing exception processing on the output signal carrying the return data packet based on the parameter configuration to obtain an exception signal.

[0095] In an optional implementation, when the exception handling mode determined based on the parameter configuration is a connection timeout exception, the output signal carrying the return data packet is always set to 0 to obtain an exception signal.

[0096] In an optional embodiment, when the exception handling mode determined based on the parameter configuration is a timing negotiation exception, a timing negotiation exception is generated by configuring the first address negotiation parameter, the second address negotiation parameter and the message negotiation parameter in the timing negotiation module, and an exception signal corresponding to the output signal of the returned data packet is obtained; wherein the first address negotiation parameter, the second address negotiation parameter and the message negotiation parameter are the time when the output is a high level when driving the platform environment control interface bus in the first address negotiation stage, the second address negotiation stage and the message negotiation stage, respectively.

[0097] Further, in an optional implementation, when the exception handling mode determined based on the parameter configuration is a bus contention exception, the host output signal is delayed based on the active delay register to simulate the bus contention to obtain an abnormal signal. The number of active delay registers can be configured, and the host output is delayed in sequence through multiple active delay registers.

[0098] In the embodiment of the present invention, in the slave model, the internal signal peci_out of the host peci module is directly introduced for processing to generate a bus contention abnormality. In the actual peci master-slave connection, there is only one connection signal, namely peci_inout. The peci_out signal inside the host is processed to generate the peci_inout signal on the host side. In the embodiment of the present invention, in order to generate a bus contention situation, a signal is added to the input end of the slave model, which is connected to the peci_out signal inside the host, and a bus contention signal is formed by delaying and widening this signal.

[0099] In the embodiment of the present invention, the output signal processing module can perform exception processing on the output signal carrying the return data packet based on the parameter configuration to obtain an exception signal, and when the exception processing mode determined based on the parameter configuration is a bus competition exception, the host output signal is delayed based on the active delay register to simulate the bus competition to obtain the exception signal. The output signal processing module includes a data sending module, a timing negotiation module and an exception generation module.

[0100] The data transmission module outputs the data packets sent by the data processing module serially byte by byte. During output, the signal cycle is the message signal cycle determined by the timing negotiation module; each time a rising edge of peci_in is detected, a bit of data is placed on the bus, that is, the bus is driven. When the output signal is 1, the duty cycle is 75%, and when the output signal is 0, the duty cycle is 25%. After sending all the data bits, wait for the message end mark. After the end mark arrives, it enters the idle state.

[0101] The timing negotiation module is used for timing negotiation. The PECI host needs to communicate with slaves of different speeds. This requires the host to perform timing negotiation with the target slave and communicate at the communication speed allowed by the target slave. Timing negotiation includes three stages, namely the first address negotiation stage, the second address negotiation stage, and the message negotiation stage. The first address negotiation stage of the host is used to wake up each slave; the second address negotiation stage is used to broadcast the destination address to each slave. All slaves drive the PECI bus and use the slowest speed of each slave for address transmission; the message negotiation stage is used to communicate with the target slave. At this time, only the slave with a matching address responds to the PECI bus activity, and other slaves enter the idle state. At this time, the communication speed is the slow value of the host and the target slave. See Figure 5 As shown, Figure 5 A schematic diagram of a timing negotiation process provided by an embodiment of the present invention. Each negotiation stage maintains a pulse cycle, at which the PECI host sends a pulse with a value of 0 (duty cycle 25%, Figure 5 middle ), after the target slave detects the rising edge, it drives the PECI bus with the shortest pulse width it supports (the three slaves correspond to Figure 5 middle , , ). The host detects the high level time t on the PECI bus and takes 4 times this time as the signal pulse period T. As mentioned above, the signal value on the PECI bus is the OR value of the output signal values ​​of all connected master / slave machines, so Figure 5 In the signal cycle T determined by the host, At this time, T is actually the communication signal cycle of the slowest master / slave. After that, the signal is transmitted in this cycle. Figure 5 The timing in the figure is a schematic diagram of the address negotiation process. For message negotiation, only the target slave with the matching address will drive the PECI bus. and (x is the target slave index).

[0102] In order to improve the flexibility of the model, three timing negotiation parameters are set, namely the first address negotiation parameter, the second address negotiation parameter and the message negotiation parameter, which correspond to the three timing negotiation stages respectively. The parameter value corresponds to the time when the model drives the PECI bus to output a high level during the timing negotiation. During the first and second address negotiation, after the rising edge of the PECI bus is detected, the time for driving the PECI bus to a high level is the time corresponding to the first and second address negotiation parameters respectively. If the destination address is consistent with the slave model address, a message negotiation pulse is responded. After the rising edge of the PECI bus is detected, the time for driving the PECI bus to a high level is the time corresponding to the message negotiation parameter. If the message address is inconsistent with the model address, no output is made.

[0103] The exception generation module triggers exceptions according to the operation parameter configuration. The exceptions supported here include connection timeout exception, bus competition exception, and timing negotiation exception.

[0104] The timeout exception means that there is no slave response on the bus. If the configuration enables the timeout exception, the peci_out signal is always set to 0; otherwise, the peci_out signal is output normally, that is, it is a normal output signal carrying the return data packet.

[0105] Bus contention abnormality means that the timing of the devices connected to the bus is inconsistent or the rising edge of the signal is inconsistent, and the output signals of each device are superimposed abnormally, resulting in abnormal signal detection. A typical situation is that when the host outputs signal 0, the signal duty cycle is 25%, but because other devices still drive the bus to a high level at the falling edge of the pulse, the signal pulse duty cycle exceeds 50% or even more, and then the signal value detected by the device on the bus is 1, that is, a detection abnormality occurs. Only consider bus contention in the host write phase. In order to simulate bus contention, the slave model delays and widens the peci_out signal inside the host and applies it to the PECI bus. Specifically, a fixed number of delay registers are set in the slave model, and the delay registers are divided into active delay registers and inactive delay registers. Number of active delay registers The number of clocks to be widened is consistent with the number of clocks from 0 to delay registers, and the rest are inactive delay registers, that is, temporarily unused delay registers. Each active delay register delays the peci_out signal inside the host by the number of clocks whose index value is added by 1. The value clock of the inactive delay register is 0. The final peci_out output by the slave model is the original peci_out signal (0 at this time) and the value of all active delay registers. Because the PECI bus signal state is the state of the connected device driver, the simulation of bus competition can be realized through this delay extension. See Figure 6 As shown, Figure 6 A schematic diagram of bus contention implementation provided by an embodiment of the present invention, in which the signal output by the host is 0 (duty cycle is 25%), and after the delay register, the signal (peci_inout) on the PECI bus becomes 1 (duty cycle exceeds 50%). Bus contention exceptions can be configured through operating parameters, and can be performed in the address sending, write length sending, read length sending, instruction sending, and write data sending stages of the host write process.

[0106] Timing negotiation anomaly means that the host detects that the message negotiation value is greater than at least one address negotiation value, that is, the speed of transmitting the message is slower than the speed of transmitting the address. There are three cases here, namely, the message negotiation value is only greater than the first address negotiation value, the message negotiation value is only greater than the second address negotiation value, and the message negotiation value is greater than both address negotiation values. Timing negotiation anomaly can be achieved by configuring the first address negotiation parameter, the second address negotiation parameter, and the message negotiation parameter in the timing negotiation module. Here, the transmission speed set by the host must be higher than the transmission speed of the slave that triggers the timing negotiation anomaly.

[0107] In an embodiment of the present invention, the operation parameter management module receives parameter input from the verification platform and controls the behavior of other modules according to these parameters. The controlled modules here are mainly the instruction processing module, the CRC module, the timing negotiation module and the exception generation module.

[0108] For the instruction processing module, the running parameter management module receives the AWFCS function enable parameters passed in by the verification platform to control whether the slave model supports the AWFCS function. For the CRC module, the running parameter management module receives the CRC error enable parameters and trigger phase parameters passed in by the verification platform to control whether a CRC error is generated and whether an error is generated in the first FCS (i.e., the first check value) or the second FCS (i.e., the second check value). For the timing negotiation module, the running parameter management module receives the first address timing parameters, the second address timing parameters, and the message timing parameters passed in by the verification platform, and passes them to the timing negotiation module for corresponding operations. The verification platform controls the maximum transmission speed of the PECI model (i.e., the slave model) or triggers a timing negotiation exception by configuring these timing parameters. For the exception generation module, the running parameter management module receives bus competition exception related parameters passed in by the verification platform, including the number of active delay registers. And the trigger stage flag is used to control the degree of competition and trigger timing of bus contention exceptions.

[0109] Step S15: Transmitting the abnormal signal to the host based on the platform environment control interface bus to verify the platform environment control interface function of the host.

[0110] Among them, the platform environment control interface function, namely the PECI module, is a logical function module implemented based on the PECI protocol. The abnormal signal can be transmitted to the host based on the platform environment control interface bus through the three-state signal processing module. The embodiment of the present invention can verify the check exception, timing negotiation exception, bus competition exception, timeout exception, etc. of the host PECI module through the slave model. When verifying the PECI module, the PECI model has an exception triggering function to verify whether the PECI module meets the design requirements of exception handling, thereby ensuring the adequacy of the verification.

[0111] It can be seen that the embodiment of the present invention converts the platform environment control interface bus signal into the input signal of the slave model, then performs filtering processing and code element recognition to obtain a code element recognition signal, and converts it into a data frame in bytes, analyzes and generates a return data packet, and performs exception processing on the output signal carrying the return data packet based on the parameter configuration to obtain an abnormal signal, which is transmitted to the host, thereby monitoring the host's verification platform environment control interface function's response to the abnormal signal. In this way, the correctness of the abnormal response of the platform environment control interface function can be verified.

[0112] In the embodiment of the present invention, the PECI model (i.e., the slave model) is divided into five large functional modules, namely, a three-state signal processing module, an input signal processing module, a data processing module, an output signal processing module, and an operation parameter management module. Modular design reduces the difficulty of debugging and improves maintainability. Optimize code element recognition and add a message end recognition mechanism. After the timing negotiation determines the signal cycle, a 50% duty cycle is used as the distinction between 0 and 1 to improve the signal tolerance. When the low level time is detected to be more than 5 times the previous high level time, the message is deemed to be over, so as to ensure that when an abnormality occurs in the host, the slave PECI model can enter the idle state normally. Provide various abnormal generation and control mechanisms, and control the abnormal triggering and triggering timing through the operation parameter control module. Specifically, the triggering and triggering form of the timing negotiation abnormality are controlled by configuring the three-stage negotiation parameters of the timing negotiation module; the competition degree and triggering timing of the bus competition abnormality are controlled by configuring the number of active delay registers Da and the triggering stage flag; and the CRC error enable parameter and the triggering stage parameter are configured to control whether a CRC error is generated and whether an error is generated in the first FCS or the second FCS.

[0113] The embodiment of the present invention designs a complete PECI model architecture and corresponding models, provides a PECI model framework with exception handling and error injection functions, a code element recognition mechanism, a message end recognition mechanism, an AWFCS function implementation method and a function verification method, a processing mechanism for AWFCS check exceptions, instruction information matching exceptions, and a timing negotiation exception based on an operation parameter management module, a bus competition exception, and a CRC check exception generation and control mechanism, which can be integrated into a chip verification platform to assist in PECI module verification. This model framework can be functionally expanded according to demand to meet the richer verification requirements of the PECI model. This embodiment adds exception handling, error injection and AWFCS functions. In addition to verifying the basic communication functions of the PECI module, the PECI module can be controlled by the verification platform to send an exception message or control the PECI model to work in an exception mode, and the correctness of the abnormal response of the PECI module can be verified. In addition, the code element recognition mechanism is optimized, the message end recognition function is added, and the stability of the PECI model operation is improved.

[0114] In this way, the PECI module is verified by simulating the behavior of the connected CPU through the PECI model. This PECI model is designed according to the slave part of the PECI communication protocol, and implements functions including signal code element analysis, timing negotiation, register reading and writing, and CRC verification. It can fully verify the functions of the PECI module. In addition to verifying the basic functions, it can also verify the anomaly detection function. In addition, in order to verify the exception handling function of the PECI module more deeply, the PECI model has configurable functions to achieve multiple verification conditions such as single exception triggering, multiple exception triggering, and random triggering.

[0115] For further information, see Figure 7 As shown, an embodiment of the present invention provides a platform environment control interface verification device, including:

[0116] An input signal conversion module 71, used to convert the platform environment control interface bus signal into an input signal of the slave model;

[0117] An input signal processing module 72, configured to filter the input signal to obtain a filtered signal, perform symbol recognition on the filtered signal to obtain a symbol recognition signal, and convert the symbol recognition signal into a data frame in bytes;

[0118] The data processing module 73 is used to analyze the data frame to obtain analysis data, and generate a return data packet based on the analysis data;

[0119] An output signal processing module 74, configured to perform exception processing on the output signal carrying the return data packet based on parameter configuration to obtain an exception signal;

[0120] The abnormal signal transmission module 75 is used to transmit the abnormal signal to the host based on the platform environment control interface bus to verify the platform environment control interface function of the host.

[0121] In an optional embodiment, the input signal processing module 72 includes a code element recognition module, which is specifically used to record the high level duration in the timing negotiation period; determine the signal period of the filtered signal based on the high level duration; perform code element recognition based on the signal period, and record the time interval between the rising edge and the falling edge of the filtered signal during the recognition process; determine the code element recognition result based on the time interval to obtain a code element recognition signal.

[0122] In an optional embodiment, the device also includes: a message end identification module, which is used to continuously detect the continuous high level time and continuous low level time of the filtered signal. When the continuous low level time exceeds a preset multiple of the previous continuous high level time detected, the message is determined to be ended, the post-message end process is performed, and the slave model enters an idle state.

[0123] In an optional implementation, the output signal processing module 74 is specifically used to: when the exception handling mode determined based on the parameter configuration is a connection timeout exception, always set the output signal carrying the return data packet to 0 to obtain an exception signal.

[0124] In an optional implementation, the output signal processing module 74 is further used to: when the exception handling mode determined based on the parameter configuration is a bus contention exception, delay the host output signal based on the active delay register to simulate bus contention to obtain an exception signal.

[0125] In an optional implementation, the output signal processing module 74 is specifically used to: when the exception handling mode determined based on the parameter configuration is a timing negotiation exception, generate a timing negotiation exception by configuring the first address negotiation parameter, the second address negotiation parameter and the message negotiation parameter in the timing negotiation module, and obtain an exception signal corresponding to the output signal of the returned data packet;

[0126] The first address negotiation parameter, the second address negotiation parameter and the message negotiation parameter are respectively the time when the platform environment control interface bus is driven to output a high level in the first address negotiation phase, the second address negotiation phase and the message negotiation phase.

[0127] In an optional implementation manner, the data processing module 73 is specifically configured to:

[0128] Analyze the data frame to obtain the slave address, write byte length, read byte length, instruction code, write data and verification information;

[0129] When the preset verification function is started, the target verification value corresponding to the slave address, the write byte length, the read byte length, the instruction code, and the write data is calculated, the target verification value is compared with the verification information to obtain the verification result, and the end code is marked based on the verification result;

[0130] If it is determined based on the check error enabling parameter that no check error is generated, then when the preset check function is started, a correct first check value is calculated based on the slave address, the write byte length, the read byte length, the instruction code, the write data and the check information;

[0131] Calculate a correct second check value based on the completion code and the read data byte, wherein the read data byte includes the data to be returned;

[0132] If it is determined based on the check error enabling parameter that a check error is generated, then generating an erroneous first check value and / or generating an erroneous second check value;

[0133] A return data packet is generated based on the completion code, the read data byte, the first check value, and the first check value.

[0134] It can be seen that the embodiment of the present invention converts the platform environment control interface bus signal into the input signal of the slave model, then performs filtering processing and code element recognition to obtain a code element recognition signal, and converts it into a data frame in bytes, analyzes and generates a return data packet, and performs exception processing on the output signal carrying the return data packet based on the parameter configuration to obtain an abnormal signal, which is transmitted to the host, thereby monitoring the host's verification platform environment control interface function's response to the abnormal signal. In this way, the correctness of the abnormal response of the platform environment control interface function can be verified.

[0135] Figure 7 The description of the features in the corresponding embodiments can be found in Figure 1 The relevant descriptions of the corresponding embodiments will not be repeated here one by one.

[0136] Figure 8 A structural diagram of an electronic device provided by an embodiment of the present invention, such as Figure 8 As shown, the electronic device includes: a memory 80 for storing a computer program;

[0137] The processor 81 is used to implement the steps of the platform environment control interface verification method of the above embodiment when executing the computer program.

[0138] The electronic device provided in this embodiment may include but is not limited to a smart phone, a tablet computer, a laptop computer or a desktop computer.

[0139] Among them, the processor 81 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 81 can be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 81 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 81 may be integrated with a graphics processing unit (GPU), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 81 may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0140] The memory 80 may include one or more computer-readable storage media, which may be non-transitory. The memory 80 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 80 is at least used to store the following computer program 801, wherein, after the computer program is loaded and executed by the processor 81, it can implement the relevant steps of the platform environment control interface verification method disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory 80 may also include an operating system 802 and data 803, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 802 may include Windows, Unix, Linux, etc. Data 803 may include but is not limited to configuration data, etc.

[0141] In some embodiments, the electronic device may further include a display screen 82 , an input / output interface 83 , a communication interface 84 , a power supply 85 , and a communication bus 86 .

[0142] Those skilled in the art will understand that Figure 8 The structure shown in the figure does not constitute a limitation on the electronic device, and may include more or fewer components than shown in the figure.

[0143] It is understandable that if the platform environment control interface verification method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the current technology or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium to execute all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, magnetic disk or optical disk and other media that can store program code.

[0144] A computer-readable storage medium provided by an embodiment of the present invention is introduced below. The computer-readable storage medium described below can be referenced to other embodiments described in this document.

[0145] An embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the platform environment control interface verification method as described above are implemented.

[0146] A computer program product provided by an embodiment of the present invention is introduced below. The computer program product described below can be referenced to other embodiments described in this document.

[0147] A computer program product includes a computer program / instruction, which implements the steps of the aforementioned platform environment control interface verification method when executed by a processor.

[0148] The platform environment control interface verification method, device, equipment and medium provided in the embodiments of the present invention are described in detail above. Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0149] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0150] The platform environment control interface verification method, device, equipment and medium provided by the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A platform environment control interface verification method, characterized in that: include: Convert the platform environment control interface bus signal into an input signal of the slave model; Filtering the input signal to obtain a filtered signal, performing symbol recognition on the filtered signal to obtain a symbol recognition signal, and converting the symbol recognition signal into a data frame in bytes; Analyzing the data frame to obtain analysis data, and generating a return data packet based on the analysis data; Performing exception processing on the output signal carrying the return data packet based on the parameter configuration to obtain an exception signal; The abnormal signal is transmitted to the host based on the platform environment control interface bus to verify the platform environment control interface function of the host.

2. The platform environment control interface verification method according to claim 1, characterized in that: Performing symbol recognition on the filtered signal to obtain a symbol recognition signal includes: Record the high level duration during the timing negotiation cycle; Determining a signal period of the filtered signal based on the high level duration; Code element recognition is performed based on the signal period, and the time interval between the rising edge and the falling edge of the signal after filtering is recorded during the recognition process. The code element recognition result is determined based on the time interval to obtain a code element recognition signal.

3. The platform environment control interface verification method according to claim 1, characterized in that: Also includes: Continuously detect the continuous high level time and continuous low level time of the signal after filtering. When the continuous low level time exceeds the preset multiple of the previous continuous high level time detected, it is determined that the message is finished, the post-message end process is carried out, and the slave model enters the idle state.

4. The platform environment control interface verification method according to claim 1, characterized in that: Based on the parameter configuration, an output signal carrying the returned data packet is subjected to exception processing to obtain an exception signal, including: When the exception handling mode determined based on the parameter configuration is a connection timeout exception, the output signal carrying the return data packet is always set to 0 to obtain an exception signal.

5. The platform environment control interface verification method according to claim 1, characterized in that: Also includes: In the case where the exception handling mode determined based on the parameter configuration is a bus contention exception, the host output signal is delayed based on the active delay register to simulate the bus contention and obtain an exception signal.

6. The platform environment control interface verification method according to claim 1, characterized in that: Based on the parameter configuration, an output signal carrying the returned data packet is subjected to exception processing to obtain an exception signal, including: In the case where the exception handling mode determined based on the parameter configuration is a timing negotiation exception, a timing negotiation exception is generated by configuring the first address negotiation parameter, the second address negotiation parameter and the message negotiation parameter in the timing negotiation module, and an exception signal corresponding to the output signal of the returned data packet is obtained; The first address negotiation parameter, the second address negotiation parameter and the message negotiation parameter are respectively the time when the platform environment control interface bus is driven to output a high level in the first address negotiation phase, the second address negotiation phase and the message negotiation phase.

7. The platform environment control interface verification method according to any one of claims 1 to 6, characterized in that: Analyzing the data frame to obtain analysis data includes: Analyze the data frame to obtain the slave address, write byte length, read byte length, instruction code, write data and verification information; Accordingly, generating a return data packet based on the analysis data includes: When the preset verification function is started, the target verification value corresponding to the slave address, the write byte length, the read byte length, the instruction code, and the write data is calculated, the target verification value is compared with the verification information to obtain the verification result, and the end code is marked based on the verification result; If it is determined based on the check error enabling parameter that no check error is generated, then when the preset check function is started, a correct first check value is calculated based on the slave address, the write byte length, the read byte length, the instruction code, the write data and the check information; Calculate a correct second check value based on the completion code and the read data byte, wherein the read data byte includes the data to be returned; If it is determined based on the check error enabling parameter that a check error is generated, then generating an erroneous first check value and / or generating an erroneous second check value; A return data packet is generated based on the completion code, the read data byte, the first check value, and the first check value.

8. A platform environment control interface verification device, characterized in that: include: An input signal conversion module, used for converting a platform environment control interface bus signal into an input signal of a slave model; An input signal processing module, used for filtering the input signal to obtain a filtered signal, performing symbol recognition on the filtered signal to obtain a symbol recognition signal, and converting the symbol recognition signal into a data frame in bytes; A data processing module, used for analyzing the data frame to obtain analysis data, and generating a return data packet based on the analysis data; An output signal processing module, used for performing exception processing on the output signal carrying the return data packet based on parameter configuration to obtain an exception signal; The abnormal signal transmission module is used to transmit the abnormal signal to the host based on the platform environment control interface bus to verify the platform environment control interface function of the host.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the platform environment control interface verification method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the platform environment control interface verification method according to any one of claims 1 to 7 are implemented.

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