Signal control method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a signal control method and device, electronic equipment and a storage medium, and the method comprises the steps: configuring each interface in a test program according to the configuration mode of each interface in a to-be-tested design, and appointing a signal contained in the interface; acquiring a first configuration parameter of a first signal in a first interface of the test program; determining a mapping strategy corresponding to the first signal according to the first configuration parameter; determining a second signal matched with the first signal in the to-be-tested design based on a mapping strategy; according to the method, the first signal and the second signal are mapped according to the first configuration parameter and the second configuration parameter of the second signal, the signal mapping efficiency is improved through a dynamic mapping mode, and then the signal control efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a signal control method, device, electronic equipment and storage medium. Background Art

[0002] In hardware functional verification, it is necessary to define a set of pins of the design under test, that is, to define an interface. For example, AXI4 and Tilelink can be defined as a set of interfaces. The interface can be used to decouple the verification code from the design under test. When writing verification code, the user does not directly operate the signals in the design under test (DUT), but the signals in the interface definition.

[0003] After that, a mapping operation is required to connect the signals in the interface definition with the signals in the DUT one by one. After the connection, the verification code operates the signals in the interface, which is equivalent to operating the signals in the DUT. In this way, through the mapping operation, this verification code can operate any DUT with the same interface, not just this one DUT.

[0004] However, existing solutions for defining interfaces, such as VirtualInterface in SystemVerilog, require static definition of each signal and manual connection of signals in the interface with signals in the DUT one by one, which increases the complexity of interface definition and interface mapping, thereby reducing the efficiency of signal control. Summary of the invention

[0005] The embodiments of the present invention provide a signal control method, device, electronic device and storage medium, which can solve the problem of high complexity of interface mapping in related technologies, resulting in reduced signal control efficiency.

[0006] In one aspect, an embodiment of the present invention discloses a signal control method, the method comprising: According to the configuration mode of each interface in the design to be tested, configure each interface in the test program and specify the signals contained in the interface; Acquire a first configuration parameter of a first signal in a first interface of the test program; Determine a mapping strategy corresponding to the first signal according to the first configuration parameter; Determine, based on the mapping strategy, a second signal in the design under test that matches the first signal; The first signal is mapped to the second signal according to the first configuration parameter and a second configuration parameter of the second signal.

[0007] Optionally, determining a mapping strategy corresponding to the first signal according to the first configuration parameter includes: In a case where the first configuration parameter includes common prefix information, determining that a mapping strategy corresponding to the first signal is prefix mapping; The determining, based on the mapping strategy, a second signal in the design to be tested that matches the first signal comprises: Based on the prefix mapping, a signal having the same configuration parameters in the design under test as other information in the first configuration parameters except the prefix information is determined as a second signal matching the first signal.

[0008] Optionally, determining a mapping strategy corresponding to the first signal according to the first configuration parameter includes: Determine a parameter matching rule according to the first configuration parameter; A mapping strategy corresponding to the first signal is determined according to the parameter matching rule.

[0009] Optionally, the mapping strategy includes dictionary mapping, and determining the second signal matching the first signal in the design to be tested based on the mapping strategy includes: According to the first configuration parameter, a second signal having a mapping relationship with the first signal is searched from a mapping dictionary; wherein the mapping dictionary is used to indicate a one-to-one mapping relationship between a signal in the test program and a signal in the design to be tested.

[0010] Optionally, configuring each interface in the test program according to the configuration mode of each interface in the design to be tested includes: In the case where the first interface in the design to be tested is a multi-level interface, configuring the signals in the interface of the corresponding level in the test program according to the configuration mode of each level in the first interface; When the first interface in the design to be tested includes at least two signals, determine the number of signals included in the first interface and the signal identifiers corresponding to the at least two signals, and configure the corresponding interface in the test program according to the number of signals and the signal identifiers.

[0011] On the other hand, an embodiment of the present invention discloses a signal control device, the device comprising: A configuration module, used to configure each interface in the test program according to the configuration mode of each interface in the design to be tested, and specify the signals included in the interface; An acquisition module, used for acquiring a first configuration parameter of a first signal in a first interface of the test program; a determination module, configured to determine a mapping strategy corresponding to the first signal according to the first configuration parameter; and determine a second signal in the design to be tested that matches the first signal based on the mapping strategy; A mapping module is used to map the first signal with the second signal according to the first configuration parameter and a second configuration parameter of the second signal.

[0012] Optionally, the determining module includes: The first determination submodule is used to determine that the mapping strategy corresponding to the first signal is prefix mapping when the first configuration parameter contains common prefix information; based on the prefix mapping, the signal with the same configuration parameters in the design to be tested as other information in the first configuration parameter except the prefix information is determined as a second signal matching the first signal.

[0013] Optionally, the determining module further includes: The second determination submodule is used to determine a parameter matching rule according to the first configuration parameter; and determine a mapping strategy corresponding to the first signal according to the parameter matching rule.

[0014] Optionally, the determining module further includes: A search module is used to search a second signal that has a mapping relationship with the first signal from a mapping dictionary according to the first configuration parameter; wherein the mapping dictionary is used to indicate a one-to-one mapping relationship between a signal in the test program and a signal in the design to be tested.

[0015] Optionally, the configuration module further includes: A first configuration submodule is used to configure the signal in the interface of the corresponding level in the test program according to the configuration mode of each level in the first interface when the first interface in the design to be tested is a multi-level interface; A third determination submodule, configured to determine, when the first interface in the design to be tested includes at least two signals, the number of signals included in the first interface and signal identifiers corresponding to the at least two signals; The second configuration submodule is used to configure the corresponding interface in the test program according to the signal quantity and the signal identifier.

[0016] On the other hand, an embodiment of the present invention further discloses an electronic device, which includes a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the aforementioned signal control method.

[0017] An embodiment of the present invention further discloses a readable storage medium. When instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device can execute the aforementioned signal control method.

[0018] The embodiments of the present invention include the following advantages: An embodiment of the present invention provides a signal control method, which configures each interface in a test program according to the configuration method of each interface in a design to be tested, and specifies the signals contained in the interface; obtains a first configuration parameter of a first signal in a first interface of the test program; determines a mapping strategy corresponding to the first signal according to the first configuration parameter; determines a second signal in the design to be tested that matches the first signal based on the mapping strategy; maps the first signal to the second signal according to the first configuration parameter and the second configuration parameter of the second signal. The embodiment of the present invention can realize dynamic mapping through the first configuration parameter and the second configuration parameter of the second signal, thereby improving the signal mapping efficiency and further improving the signal control efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0020] Figure 1 is a flow chart of steps of an embodiment of a signal control method of the present invention; Figure 2 is a structural block diagram of an embodiment of a signal control device of the present invention; Figure 3 It is a structural block diagram of an electronic device provided by an example of the present invention. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0023] Method Embodiment Reference Figure 1 , shows a flow chart of steps of an embodiment of a signal control method of the present invention, the method may specifically include the following steps: Step 101, configure each interface in the test program according to the configuration mode of each interface in the design to be tested, and specify the signals included in the interface; Step 102: Obtain a first configuration parameter of a first signal in a first interface of a test program; Step 103: Determine a mapping strategy corresponding to the first signal according to the first configuration parameter; Step 104: Determine a second signal matching the first signal in the design to be tested based on a mapping strategy; Step 105: Map the first signal and the second signal according to the first configuration parameter and the second configuration parameter of the second signal.

[0024] According to the configuration mode of each interface in the design to be tested, each interface in the test program is configured to specify the signals contained in the interface.

[0025] The DUT refers to the circuit design or implementation to be tested in prototype verification. For example, the design to be tested can be a register transfer level (RTL) circuit or other hardware design.

[0026] For example, in hardware design or system modeling, Adder is a common functional module. When defining the structure of the Adder interface using Python, the Adder module can be represented by a class, and its input, output, and functions can be defined using attributes or methods. For example, when defining the structure of the Adder interface using Python, the Adder interface usually includes input signals, output signals, and functions, where the input signals are two operands (such as a and b); the output signal is the result of addition (such as sum); and the function is to implement the addition operation.

[0027] The design under test is driven by a clock signal. The operation of the design under test can be paused by controlling the clock signal. When the input of the clock signal in the design under test is stopped, the design under test will also stop running.

[0028] The configuration of each interface in the design under test refers to setting parameters, protocols, timing, electrical characteristics, etc. for the interfaces in the design under test to ensure that the interfaces can work correctly and meet the design requirements. Interface configuration is an important part of hardware function verification and system integration, and directly affects the performance and compatibility of the design.

[0029] For example, interface configuration refers to setting relevant parameters and properties for the interface in the design to be tested so that it can communicate correctly with other modules or external devices. This is to ensure that the interface meets the design specifications and protocol requirements; optimize interface performance (such as speed, bandwidth, latency); and improve system compatibility and reliability.

[0030] Exemplarily, the content of the interface configuration may include protocol configuration, timing configuration, function configuration, address configuration, etc.

[0031] The protocol configuration refers to setting the communication protocol used by the interface, for example: 2 C configures the clock frequency (such as 100 kHz, 400 kHz) and device address; configures the clock polarity (CPOL), clock phase (CPHA), and data bit width through SPI. Configures the baud rate (such as 9600, 115200), data bits, stop bits, and parity bits through UART. Configures the link speed (such as Gen1, Gen2, Gen3) and number of channels (x1, x4, x16) through PCIe.

[0032] Timing configuration refers to setting the timing parameters of the interface to ensure that the signal is sampled and transmitted at the correct time; for example, timing configuration includes setting the clock frequency, setup time, and hold time of the interface to ensure that the data is stable at the clock edge.

[0033] Functional configuration refers to setting the functional mode and working mode of the interface, for example: configuring the pin as input, output or interrupt mode through GPIO. Exemplarily, the functional mode may include DMA configuration and interrupt configuration, wherein the DMA configuration may include data transmission mode (such as single transmission, cyclic transmission); the interrupt configuration may include interrupt trigger conditions (such as rising edge, falling edge, high level). The working mode may include whether to delay transmission, for example, in the case of selecting delayed transmission, the delay time of signal transmission may be set.

[0034] Address configuration refers to setting the address space or register map of the interface. For example, configuring the base address and address range of a peripheral through memory-mapped I / O, or configuring I / O through device address. 2 C or SPI device address.

[0035] Interface configuration methods may include hardware configuration, software configuration, firmware configuration, etc.

[0036] The hardware configuration includes jumpers or dip switches, resistor configuration, etc. Jumpers or dip switches are used to set interface parameters through physical jumpers or dip switches, and resistor configuration is used to set electrical characteristics of the interface (such as pull-up resistors and pull-down resistors) through external resistors.

[0037] Software configuration includes register configuration, configuration file, command line parameters, etc. Register configuration is to set interface parameters by writing registers, configuration file is to set interface parameters by reading configuration file, and command line parameters are to dynamically configure the interface through command line parameters.

[0038] Firmware configuration includes Bootloader and FPGA configuration. For example, Bootloader configures interface parameters when the system starts; FPGA configuration sets interface parameters through FPGA configuration files (such as bitstream).

[0039] The test program is used to test the performance or correctness of the design under test to verify whether the design under test meets the expected functional and performance requirements.

[0040] As an example, the user may write a test program in advance according to the test requirements, and divide the test program into at least one subprogram according to the dependencies and execution order of the test cases or execution flows in the test program, and each subprogram may be defined as a different interface.

[0041] Exemplarily, the signals included in the interface may include data signals, address signals, control signals, etc.

[0042] For example, data signals are used to transmit actual data content between various parts of the interface connection. In different application scenarios, the representation and meaning of data signals vary. For example, in the interface between the computer's memory and the central processing unit (CPU), the data signal may be a set of binary bits, representing a byte or word of data being processed; in the network interface, the data signal is composed of a series of data packets encapsulated according to a specific protocol, containing information such as source address, destination address, and payload.

[0043] Exemplarily, address signals are mainly used to specify the storage location or target device of data. In a system with storage function, address signals help determine the specific location where data should be read or written. For example, in a computer's memory interface, address signals are used to select a specific storage unit in the memory; in a hard disk controller interface, address signals can be used to locate a sector on the hard disk.

[0044] For example, control signals are used to coordinate and control the operation flow and timing relationship between the various parts of the interface. Control signals can indicate the direction of data transmission (read or write), start or stop an operation, indicate whether the device is ready for data exchange, etc. For example, in an SPI (Serial Peripheral Interface) communication interface, there is a chip select signal (CS) used to select a specific slave device; read and write signals (such as MOSI, MISO, which represent master-out slave-in, master-in slave-out, and the corresponding clock signal SCLK) are used to control the flow direction and transmission rhythm of data.

[0045] Signal definitions and specifications in interfaces are key to ensuring correct and stable communication between different components. Whether it is the connection between chips inside a computer or the connection between different electronic devices (such as mobile phones and chargers, computers and printers), unified signal standards and protocols need to be followed to ensure accurate information transmission and normal operation of the system.

[0046] A first configuration parameter of a first signal in a first interface of a test program is obtained.

[0047] The first interface may be any interface in each subprogram in the test program.

[0048] The first signal in the first interface can be: data signal (Data Signals), clock signal (ClockSignal), control signal (Control Signals), status signal (Status Signals), SPI (Serial Peripheral Interface), I 2C (Inter-Integrated Circuit), UART (UniversalAsynchronous Receiver / Transmitter), USB (Universal Serial Bus), PCIe (PeripheralComponent Interconnect Express), Ethernet (Ethernet), HDMI (High-DefinitionMultimedia Interface), GPIO (General Purpose Input / Output), etc.

[0049] Among them, the data signal is used to transmit actual data information, for example: parallel interface: D0, D1, D2, ..., Dn (data bus). Serial interface: TX (transmit data line), RX (receive data line).

[0050] The clock signal is used to provide a synchronous clock for synchronous data transmission. For example: SPI: SCLK (serial clock); I2C: SCL (serial clock line); PCIe: REFCLK (reference clock).

[0051] Control signals are used to control the start, end or direction of data transmission. For example: SPI: SS (chip select signal); I2C: START (start condition), STOP (stop condition); UART: RTS (request to send), CTS (clear to send).

[0052] The status signal is used to indicate the status of the interface or device, for example: GPIO: READY (ready signal); USB: VBUS (power status signal).

[0053] In the SPI interface, SCLK refers to the serial clock, MOSI refers to the master device output and slave device input, MISO refers to the master device input and slave device output, and SS refers to the chip select signal (active low).

[0054] I 2 In the C interface, SCL refers to the serial clock line; SDA refers to the serial data line.

[0055] In the UART interface, TX refers to the transmit data line; RX refers to the receive data line; RTS refers to request to send; and CTS refers to clear to send.

[0056] In the USB interface, D+ refers to the positive data line, D- refers to the negative data line, VBUS refers to the power line, and GND refers to the ground line.

[0057] In the PCIe interface, REFCLK refers to the reference clock, TX+ / - refers to the transmit differential signal, RX+ / - refers to the receive differential signal, PERST# refers to the reset signal, and WAKE# refers to the wake-up signal.

[0058] In the Ethernet interface, TX+ / - refers to the transmission of differential signals; RX+ / - refers to the reception of differential signals; MDI / MDIX refers to the automatic crossover detection signal.

[0059] In the HDMI interface, TMDS Data refers to video and audio data signals, TMDS Clock refers to the clock signal; CEC refers to the consumer electronics control signal; HPD refers to the hot plug detection signal.

[0060] In the GPIO interface, GPIOx refers to the general-purpose input / output pin; DIR refers to the direction control signal (input / output); PULLUP / PULLDOWN refers to the pull-up / pull-down resistor control signal.

[0061] The types and number of signals contained in the interface depend on the type and protocol of the interface. Common signals include data signals, clock signals, control signals, status signals, and power / ground signals.

[0062] The first configuration parameters can be used to define and control the parameters of signal behavior. These parameters ensure that the signal can transmit data correctly and meet the design requirements.

[0063] Exemplarily, the configuration parameters may be protocol-related parameters, and the protocol-related parameters include: communication protocol, data format, frame format, etc.

[0064] Among them, the communication protocol is used to define the protocol used by the interface (such as SPI, I2C, UART, PCIe).

[0065] The data format includes the data bit width (such as 8 bits, 16 bits) and the data encoding method (such as NRZ, Manchester).

[0066] The frame format includes a start bit, a stop bit, and a check bit (such as odd check or even check).

[0067] Exemplarily, the configuration parameters of the SPI interface signal may include protocol-related parameters and timing-related parameters, etc.

[0068] Among them, protocol-related parameters include clock polarity (CPOL, 0 or 1); clock phase (CPHA, 0 or 1); data bit width (8 bits), etc.

[0069] Timing-related parameters include clock frequency (1 MHz); setup time (10 ns), and hold time (10 ns).

[0070] The configuration parameters of the signals in the interface include protocol-related parameters, timing-related parameters, electrical characteristic parameters, function-related parameters, address-related parameters, and error detection and correction parameters, etc. By properly configuring these parameters, the correct transmission of the interface signals and the realization of functions can be ensured.

[0071] A mapping strategy corresponding to the first signal is determined according to the first configuration parameter.

[0072] Among them, the mapping strategy corresponding to the first signal refers to the rules and methods for corresponding and matching the first signal with the second signal in the design to be tested, so as to ensure that the signal can be correctly transmitted and processed; meet the design needs and performance requirements; and improve the compatibility and reliability of the system.

[0073] Signal mapping strategies may include signal name mapping, signal type mapping, signal timing mapping, signal function mapping, etc.

[0074] Signal name mapping refers to matching the name of the first signal in the first interface of the test program with the name in the design to be tested. For example, the first signal in the first interface of the test program is TX (transmit data line); the second signal in the design to be tested is DIN (data input line). The mapping strategy can be TX → DIN.

[0075] Signal type mapping refers to matching the type of the first signal in the first interface of the test program with the type in the design to be tested. For example, the first signal in the first interface of the test program is CLK (clock signal), and the second signal in the design to be tested is SCLK (serial clock signal). The mapping strategy is: CLK → SCLK.

[0076] Signal timing mapping refers to matching the timing of the first signal in the first interface of the test program with the timing of the second signal in the design to be tested. For example, the first signal in the first interface of the test program: clock frequency = 100 MHz, the second signal in the design to be tested: clock frequency = 50 MHz, mapping strategy: use a divider to convert 100 MHz to 50 MHz.

[0077] Signal function mapping refers to matching the function of the first signal in the first interface of the test program with the function of the second signal in the design to be tested. For example, the first signal in the first interface of the test program is RST (reset signal), the second signal in the design to be tested is RESET (reset signal), and the mapping strategy is RST → RESET.

[0078] A second signal matching the first signal in the design under test is determined based on the mapping strategy.

[0079] Among them, the second signal may include: a second signal with the same signal name as the first signal, or a second signal with the same signal type as the first signal, or a second signal with the same signal timing as the first signal, or a second signal with the same signal function as the first signal, etc.

[0080] The first signal is mapped to the second signal according to the first configuration parameter and the second configuration parameter of the second signal.

[0081] The second configuration parameters of the second signal may include protocol-related parameters, timing-related parameters, electrical characteristic parameters, function-related parameters, address-related parameters, and error detection and correction parameters.

[0082] Exemplarily, the design under test may be driven by the signal values ​​of various interfaces in the test program, and the signal values ​​may be transmitted to the design under test through the interfaces of the design under test, thereby controlling the operation of the design under test.

[0083] After obtaining the signal value of the first interface in each subroutine, the second interface matching the first interface in the design to be tested can be determined.

[0084] Different mapping methods may be used to map the first interface to the second interface, thereby determining the second interface that matches the first interface in the design to be tested.

[0085] Exemplarily, in an embodiment of the present invention, two groups of interfaces in the design to be tested, such as AXI4 and Tilelink, can be obtained separately first, that is, the interface of the design to be tested is determined, and the AXI4 interface needs to be driven by each interface in each subroutine. At this time, it is necessary to define a virtual AXI4 interface and let the verification code (each interface in each subroutine) drive this virtual AXI4 interface.

[0086] Exemplarily, the process of matching the first interface with the second interface of the design to be tested may include: obtaining the name of the first interface in the first subprogram and capturing the name of the design to be tested. When the name of the design to be tested only has a common prefix more than the name of the first interface in the first subprogram, prefix mapping may be used to match the first interface with the second interface of the design to be tested.

[0087] In an embodiment of the present invention, each interface in the test program is configured according to the configuration method of each interface in the design to be tested, and the signal contained in the interface is specified; the first configuration parameter of the first signal in the first interface of the test program is obtained; the mapping strategy corresponding to the first signal is determined according to the first configuration parameter; based on the mapping strategy, a second signal matching the first signal in the design to be tested is determined; according to the first configuration parameter and the second configuration parameter of the second signal, the first signal is mapped to the second signal. The embodiment of the present invention can realize dynamic mapping through the first configuration parameter and the second configuration parameter of the second signal, thereby improving the signal mapping efficiency and further improving the signal control efficiency.

[0088] In an optional embodiment of the present invention, determining the mapping strategy corresponding to the first signal according to the first configuration parameter may specifically include the following steps: Step 1031: When the first configuration parameter includes common prefix information, determine that the mapping strategy corresponding to the first signal is prefix mapping.

[0089] Exemplarily, when at least one signal is io_a, io_b, io_cin, io_sum, io_cout, the common prefix information can be determined as io_, or when at least one signal is inout_a, inout_b, inout_cin, inout_sum, inout_cout, the common prefix information can be determined as inout_.

[0090] When at least one signal is io_a, io_b, io_cin, io_sum, io_cout, by extracting io_a, io_b, io_cin, io_sum, io_cout, it can be determined that the common prefix information of the signals io_a, io_b, io_cin, io_sum, io_cout is io_, and the first signal can be mapped using prefix mapping.

[0091] In an optional embodiment of the present invention, determining the second signal matching the first signal in the design to be tested based on the mapping strategy may specifically include the following steps: Step 1041: Based on prefix mapping, determine a signal having the same configuration parameters in the design to be tested as other information in the first configuration parameters except the prefix information as a second signal matching the first signal.

[0092] Exemplarily, the prefix io_ is used as a mapping method to map to the DUT. When the DUT has a common prefix more than the name in the first interface in the test program, such as io_a, io_b, io_cin, io_sum, io_cout, in this case, the prefix io_ can be specified as a mapping method to map to the DUT, that is, when the common prefix can be extracted, io_ is directly used as a mapping method, so that a is connected to io_a, b is connected to io_b, cin is connected to io_cin, sum is connected to io_sum, and cout is connected to io_cout. When the prefix of the new design to be tested is not io_, but inout_a, inout_b, inout_cin, inout_sum, inout_cout, inout_ is used for mapping in order to be able to connect. That is, by identifying this prefix, the same one behind is mapped.

[0093] In an optional embodiment of the present invention, determining the mapping strategy corresponding to the first signal according to the first configuration parameter may specifically include the following steps: Step 1032: Determine a parameter matching rule according to the first configuration parameter; Step 1033: Determine a mapping strategy corresponding to the first signal according to the parameter matching rule.

[0094] A parameter matching rule is determined according to the first configuration parameter.

[0095] The parameter matching rule may be a matching rule described by any expression, for example, a matching rule described by a regular expression.

[0096] Exemplarily, parameter matching rules refer to specific rules and methods for matching source signals with target signals, including signal name matching, signal type matching, signal electrical characteristic matching, signal timing matching, and signal function matching, etc. Reasonable signal matching rules can ensure that signals can be correctly transmitted and processed to meet design needs and performance requirements.

[0097] A mapping strategy corresponding to the first signal is determined according to the parameter matching rule.

[0098] Exemplarily, when the name of the first signal in the first interface of the test program is described by a regular expression, it can be determined that the mapping strategy corresponding to the first signal is regular expression mapping.

[0099] Exemplarily, the process of mapping the first interface with the second interface of the design to be tested may include: obtaining the name of the first interface in the first subroutine, and capturing the name of the design to be tested. When the name of the design to be tested can be expressed by a regular expression, regular expression mapping can be used to map the first interface with the second interface of the design to be tested.

[0100] Exemplarily, when the signal names in the DUT can be mapped by regular expressions, and the captured names can match the names in the interface, regular expression mapping can be used. For example, the above can be matched with the regular expression r"io_(.*)", and the characters captured by the brackets just match the names in the interface. If there are multiple capture groups, they are linked into a string in order and then matched. Among them, regular expression mapping refers to writing a matching rule, and then mapping the first interface in the first subroutine with the second interface of the design to be tested. The "io_(.*)" matching pattern is to capture the (signal) after io_.

[0101] In an optional embodiment of the present invention, the mapping strategy includes dictionary mapping, and determining the second signal matching the first signal in the design to be tested based on the mapping strategy may specifically include the following steps: Step 1042: search a mapping dictionary for a second signal that has a mapping relationship with the first signal according to the first configuration parameter; wherein the mapping dictionary is used to indicate a one-to-one mapping relationship between a signal in the test program and a signal in the design to be tested.

[0102] When the mapping strategy is dictionary mapping, the second signal that has a mapping relationship with the first signal can be searched from the mapping dictionary according to the first configuration parameter, for example: {"a": "io_a", "b": "io_b", "cin": "io_cin", "cout": "io_cout"}.

[0103] The process of mapping the first interface with the second interface of the design to be tested may include: obtaining the name of the first interface in the first subroutine, capturing the name of the design to be tested, establishing a one-to-one mapping relationship by passing in a dictionary, and then matching the first interface with the second interface of the design to be tested.

[0104] For example, a one-to-one mapping relationship is established by passing in a dictionary, which is consistent with the traditional connection method (but the mapping can be achieved through multiple layers of nesting, the dictionary contains prefix mapping, and the prefix mapping includes regular expression mapping), and the mapping is completed through the dictionary in the first interface in the first subroutine.

[0105] After determining the second interface in the design under test that matches the first interface, the signal value may be input to the second interface, and the design under test may be driven to continue running until the next clock cycle edge.

[0106] Among them, the port can be assigned to the design under test, that is, each subroutine transmits the data required for the operation of the design under test to the design under test, and then the design under test can be controlled through each interface in each subroutine.

[0107] In an optional embodiment of the present invention, configuring each interface in the test program according to the configuration mode of each interface in the design to be tested may specifically include the following steps: Step 1011: when the first interface in the design to be tested is a multi-level interface, configure the signal in the interface of the corresponding level in the test program according to the configuration mode of each level in the first interface; Step 1012: When the first interface in the design to be tested includes at least two signals, determine the number of signals included in the first interface and signal identifiers corresponding to the at least two signals, and configure the corresponding interface in the test program according to the number of signals and the signal identifiers.

[0108] In the case where the first interface in the design to be tested is a multi-level interface, the signals in the interface of the corresponding level in the test program are configured according to the configuration mode of each level in the first interface.

[0109] The multi-level interface refers to defining an interface as a sub-interface in the current interface to form a multi-level interface with nested interfaces.

[0110] For example, a multi-level interface is a design method that divides an interface into multiple levels, each level being responsible for a different function or level of abstraction.

[0111] The configuration method of each level can be software configuration, etc. Software configuration includes: register configuration, configuration file, command line parameters, etc. Register configuration is to set interface parameters by writing registers, configuration file is to set interface parameters by reading configuration file, and command line parameters are to dynamically configure the interface through command line parameters.

[0112] When the first interface in the design to be tested includes at least two signals, the number of signals included in the first interface and the signal identifiers corresponding to the at least two signals are determined, and the corresponding interface in the test program is configured according to the number of signals and the signal identifiers.

[0113] The number of signals included in the first interface may be any number, for example, the first interface is defined to include 5 signals, or 10 signals, etc.

[0114] The signal identifiers corresponding to at least two signals refer to the names, numbers or symbols used to uniquely identify and distinguish different signals in hardware design, system integration or communication protocols. Signal identifiers are an important basis for signal mapping, configuration and management, ensuring that signals can be correctly identified and processed.

[0115] Exemplarily, the SPI interface signal identifiers include: SCLK (serial clock), MOSI (master device output, slave device input), MISO (master device input, slave device output), and SS (chip select signal).

[0116] Exemplarily, the UART interface signal identifiers include: TX (transmit data line), RX (receive data line), RTS (request to send), and CTS (clear to send).

[0117] In hardware functional verification, it is necessary to define a set of pins of the design to be tested, which is called an interface below. For example, AXI4 and Tilelink can be defined as a set of interfaces. Interfaces can be used to decouple the verification code from the design to be tested. When writing verification code, users do not directly operate on the signals in the DUT, but on the signals in the interface definition.

[0118] After that, a mapping operation is required to connect the signals in the interface definition with the signals in the DUT one by one. After the connection, the verification code operates the signals in the interface, which is equivalent to operating the signals in the DUT. In this way, through the mapping operation, this verification code can operate any DUT with the same interface, not just this one DUT.

[0119] However, existing solutions for defining interfaces, such as VirtualInterface in SystemVerilog, require static definition of each signal and manually connect the signals in the interface to the signals in the DUT one by one, which makes the definition and connection of more complex interfaces more complicated.

[0120] The present invention utilizes the characteristic of modern software programming languages ​​that can dynamically parse variable names, designs a new interface definition method and a method for mapping to DUT, making this process more flexible and efficient.

[0121] Use Bundle to complete the definition of a class of interfaces. For example, use Python to define the structure of the Adder interface. When defining, you only need to specify the specific signals contained in the interface.

[0122] For example, it is defined by the following code: class AdderBundle(Bundle) : a, b, cin, sum, cout = Signals(5) In the embodiment of the present invention, in the case of mapping to DUT, three mapping modes are included to quickly implement the mapping process.

[0123] Prefix mapping refers to when the DUT has only one more common prefix than the name in the definition, such as io_a, io_b, io_cin, io_sum, io_cout. In this case, you can specify the prefix io_ as the mapping method to map to the DUT without having to manually map multiple times.

[0124] Regular expression mapping means that when the signal name in the DUT can be matched by a regular expression, and the captured name can match the name in the interface, regular expression mapping can be used. For example: using the r"io_(.*)" regular expression match, the characters captured by the brackets just match the name in the interface. If there are multiple capture groups, they can be linked in order into a string and then matched.

[0125] Dictionary mapping means establishing a one-to-one mapping relationship by passing in a dictionary. This is consistent with the traditional connection method, but the mapping is completed through the dictionary in the software language. For example, {"a": "io_a", "b": "io_b", "cin": "io_cin", "cout": "io_cout"}.

[0126] Among them, the Bundle specifies the mapping mode when it is instantiated, and the mapping with the DUT is completed through the bind method in the Bundle.

[0127] The definition of a multi-level interface means that in addition to defining signals in a Bundle, another Bundle can be defined as a sub-Bundle in the current Bundle and given a name.

[0128] When a child bundle is instantiated in the current bundle, it is also necessary to specify its mapping method. After the current mapping effect is produced, the mapped name is passed to the child bundle for matching.

[0129] For example, the multi-level interface is defined by the following code: class AXI4Bundle(Bundle): aw = AXI4BundleAW.from_regex(r"aw_(?:(valid|ready)|bits_(.*))") w = AXI4BundleW.from_regex(r"w_(?:(valid|ready)|bits_(.*))") b = AXI4BundleB.from_regex(r"b_(?:(valid|ready)|bits_(.*))") ar = AXI4BundleAR.from_regex(r"ar_(?:(valid|ready)|bits_(.*))") r = RBundle.from_regex(r"r_(?:(valid|ready)|bits_(.*))") Assuming that the AXI4Bundle uses the prefix mapping method "io_", the child bundles will remove the io_ prefix and then use the regular expression method to map the child bundles. In other words, the prefix will be removed after prefix mapping, the regular expression will be converted to the captured name after mapping, and the dictionary will be converted to the name specified by the dictionary before the child bundles are mapped.

[0130] For some more complex interfaces, especially the interface names generated by Chisel, a group of signals or interfaces are often distinguished by numbers, such as signal_1, signal_2, ...signal_10. At this time, if 10 signals are defined, the definition will become complicated. The Bundle provides a signal array to complete such a definition, and the corresponding Bundle array also has a corresponding one.

[0131] These two arrays are defined using SignalList and BundleList respectively, and both need to be defined in a Bundle. When accessing, these two structures can be accessed as arrays.

[0132] For example, the array structure is defined by the following code: class MyBundle(Bundle): sl = SignalList("signal_ #", 10) bl = BundleList(SubBundle, "subbundle_ #", 10) In SignalList, you need to specify a name containing numbers, where the numbers are marked with "#", and specify the number n. The Bundle will automatically generate the specified number of signals and replace the matching name with one of 0-(n-1). You can also pass in a custom conversion function from numbers to strings to define the conversion method from numbers to strings.

[0133] In the BundleList, you need to specify the definition of the sub-bundle. This method will define a bundle list, in which the mapping method of each bundle is set to prefix matching, replacing the string after the number as the prefix. Similarly, when defining, you need to specify the prefix name containing numbers and the number.

[0134] The above definition method overcomes the original practice of statically defining all signals and provides flexible hierarchical definition and array support; the mapping method provides three dynamic mapping methods, which overcomes the original one-to-one signal connection and improves mapping efficiency.

[0135] Bundle usually refers to combining multiple signals or ports into a composite structure to facilitate modularization and reuse. For example, the Bundle class in Chisel allows users to define their own signal collections, and then pass and process these signals as a whole, improving the readability and maintainability of the code.

[0136] A Bundle is a structured definition of a collection of signals.

[0137] In the field of hardware design and programming (especially in the Chisel-based hardware construction language), Bundle is a mechanism for combining multiple related signals (or ports) into a structured data type. It is similar to the structure (struct) in software programming, which is used to define a group of logically related signals to facilitate modular design and code reuse.

[0138] Bundle can encapsulate multiple signals (such as data lines, control signals, status signals, etc.) into a whole.

[0139] Example: Define an interface that contains data, address, and valid flags.

[0140] Exemplarily, the signals in the DUT can be passed in as a list, and different ones can be passed in each time. The test program can dynamically parse the incoming signals, and determine a mapping strategy for mapping at least one signal in the interface of the design to be tested to the second interface of the test program based on the parsed signals.

[0141] In summary, an embodiment of the present invention provides a signal control method, which configures each interface in a test program according to the configuration method of each interface in a design to be tested, and specifies the signals contained in the interface; obtains a first configuration parameter of a first signal in a first interface of the test program; determines a mapping strategy corresponding to the first signal according to the first configuration parameter; determines a second signal in the design to be tested that matches the first signal based on the mapping strategy; maps the first signal to the second signal according to the first configuration parameter and the second configuration parameter of the second signal. The embodiment of the present invention can achieve dynamic mapping through the first configuration parameter and the second configuration parameter of the second signal, thereby improving the signal mapping efficiency and further improving the signal control efficiency.

[0142] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0143] Device Embodiment Reference Figure 2 , shows a structural block diagram of a signal control device of the present invention, and the device may specifically include: Configuration module 401, configured to configure each interface in the test program according to the configuration mode of each interface in the design to be tested, and specify the signals included in the interface; An acquisition module 402, configured to acquire a first configuration parameter of a first signal in a first interface of the test program; A determination module 403 is configured to determine a mapping strategy corresponding to the first signal according to the first configuration parameter; and determine a second signal in the design to be tested that matches the first signal based on the mapping strategy; The mapping module 404 is configured to map the first signal with the second signal according to the first configuration parameter and a second configuration parameter of the second signal.

[0144] Optionally, the determining module includes: The first determination submodule is used to determine that the mapping strategy corresponding to the first signal is prefix mapping when the first configuration parameter contains common prefix information; based on the prefix mapping, the signal with the same configuration parameters in the design to be tested as other information in the first configuration parameter except the prefix information is determined as a second signal matching the first signal.

[0145] Optionally, the determining module further includes: The second determination submodule is used to determine a parameter matching rule according to the first configuration parameter; and determine a mapping strategy corresponding to the first signal according to the parameter matching rule.

[0146] Optionally, the determining module further includes: A search module is used to search a second signal that has a mapping relationship with the first signal from a mapping dictionary according to the first configuration parameter; wherein the mapping dictionary is used to indicate a one-to-one mapping relationship between a signal in the test program and a signal in the design to be tested.

[0147] Optionally, the configuration module further includes: A first configuration submodule is used to configure the signal in the interface of the corresponding level in the test program according to the configuration mode of each level in the first interface when the first interface in the design to be tested is a multi-level interface; A third determination submodule, configured to determine, when the first interface in the design to be tested includes at least two signals, the number of signals included in the first interface and signal identifiers corresponding to the at least two signals; The second configuration submodule is used to configure the corresponding interface in the test program according to the signal quantity and the signal identifier.

[0148] In summary, an embodiment of the present invention provides a signal control device. During the process of signal control, each interface in the test program is configured according to the configuration method of each interface in the design to be tested, and the signal contained in the interface is specified; the first configuration parameter of the first signal in the first interface of the test program is obtained; the mapping strategy corresponding to the first signal is determined according to the first configuration parameter; based on the mapping strategy, a second signal matching the first signal in the design to be tested is determined; according to the first configuration parameter and the second configuration parameter of the second signal, the first signal is mapped to the second signal. The embodiment of the present invention can realize dynamic mapping through the first configuration parameter and the second configuration parameter of the second signal, thereby improving the signal mapping efficiency and further improving the signal control efficiency.

[0149] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0150] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0151] Regarding the processor in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0152] Reference Figure 3 , is a structural block diagram of an electronic device for data transmission in a network on chip provided by an embodiment of the present invention. Figure 3 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the signal control method of the aforementioned embodiment.

[0153] The processor may be a CPU, a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other editable devices, transistor logic devices, hardware components or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0154] The communication bus may include a path to transmit information between the memory and the communication interface. The communication bus may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 3 The fact that only one line is used in the diagram does not mean that there is only one bus or only one type of bus.

[0155] The memory may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or may be an electrically erasable programmable read-only memory (EEPROM), a compact disc (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0156] The embodiment of the present invention also provides a non-transitory computer-readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), the processor can execute Figure 1 The signal control method shown.

[0157] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0158] It should be understood by those skilled in the art that the embodiments of the present invention may be provided as methods, devices or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0159] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems) and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0160] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0161] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0162] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0163] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0164] The signal control method, device, electronic device and storage medium provided by the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A signal control method, characterized in that: The method comprises: According to the configuration mode of each interface in the design to be tested, configure each interface in the test program and specify the signals contained in the interface; Acquire a first configuration parameter of a first signal in a first interface of the test program; Determine a mapping strategy corresponding to the first signal according to the first configuration parameter; Determine, based on the mapping strategy, a second signal in the design under test that matches the first signal; The first signal is mapped to the second signal according to the first configuration parameter and a second configuration parameter of the second signal.

2. The method according to claim 1, characterized in that The determining, according to the first configuration parameter, a mapping strategy corresponding to the first signal includes: In a case where the first configuration parameter includes common prefix information, determining that a mapping strategy corresponding to the first signal is prefix mapping; The determining, based on the mapping strategy, a second signal in the design to be tested that matches the first signal comprises: Based on the prefix mapping, a signal having the same configuration parameters in the design under test as other information in the first configuration parameters except the prefix information is determined as a second signal matching the first signal.

3. The method according to claim 1, characterized in that The determining, according to the first configuration parameter, a mapping strategy corresponding to the first signal includes: Determine a parameter matching rule according to the first configuration parameter; A mapping strategy corresponding to the first signal is determined according to the parameter matching rule.

4. The method according to claim 1, characterized in that The mapping strategy includes dictionary mapping, and determining the second signal matching the first signal in the design under test based on the mapping strategy includes: According to the first configuration parameter, a second signal having a mapping relationship with the first signal is searched from a mapping dictionary; wherein the mapping dictionary is used to indicate a one-to-one mapping relationship between a signal in the test program and a signal in the design to be tested.

5. The method according to claim 1, characterized in that The configuring of each interface in the test program according to the configuration mode of each interface in the design to be tested includes: In the case where the first interface in the design to be tested is a multi-level interface, configuring the signals in the interface of the corresponding level in the test program according to the configuration mode of each level in the first interface; When the first interface in the design to be tested includes at least two signals, determine the number of signals included in the first interface and the signal identifiers corresponding to the at least two signals, and configure the corresponding interface in the test program according to the number of signals and the signal identifiers.

6. A signal control device, characterized in that: The device comprises: A configuration module, used to configure each interface in the test program according to the configuration mode of each interface in the design to be tested, and specify the signals included in the interface; An acquisition module, used for acquiring a first configuration parameter of a first signal in a first interface of the test program; a determination module, configured to determine a mapping strategy corresponding to the first signal according to the first configuration parameter; and determine a second signal in the design to be tested that matches the first signal based on the mapping strategy; A mapping module is used to map the first signal with the second signal according to the first configuration parameter and a second configuration parameter of the second signal.

7. The device according to claim 6, characterized in that The determining module comprises: The first determination submodule is used to determine that the mapping strategy corresponding to the first signal is prefix mapping when the first configuration parameter contains common prefix information; based on the prefix mapping, the signal with the same configuration parameters in the design to be tested as other information in the first configuration parameter except the prefix information is determined as a second signal matching the first signal.

8. The device according to claim 6, characterized in that The determining module further includes: The second determination submodule is used to determine a parameter matching rule according to the first configuration parameter; and determine a mapping strategy corresponding to the first signal according to the parameter matching rule.

9. An electronic device, characterized in that: The electronic device includes a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the signal control method as described in any one of claims 1 to 5.

10. A readable storage medium, characterized in that: When the instructions in the readable storage medium are executed by a processor of an electronic device, the processor is enabled to execute the signal control method as claimed in any one of claims 1 to 5.

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