Chip verification method and device, server, storage medium and program product

Abstract

The invention relates to the technical field of digital integrated circuits, and discloses a chip verification method and device, a server, a storage medium and a program product. The method comprises the steps that a pseudo-random number sequence is generated according to a pre-created pseudo-random number generation environment, and the pseudo-random number generation environment is created based on a verification platform development library and a pseudo-random number algorithm library; converting the pseudo-random number sequence into an excitation sequence, and sending the excitation sequence to the chip to be tested; receiving response data sent by the chip to be tested after responding to the excitation sequence, and comparing the response data with expected data to obtain a comparison result; and when it is determined that the to-be-tested chip does not conform to the expectation according to the comparison result, adjusting the pseudo-random number generation environment according to the comparison result until response data regenerated based on the adjusted pseudo-random number generation environment conform to the expectation. By implementing the technical scheme of the invention, the accuracy and efficiency of chip verification can be effectively improved, and the performance of the to-be-tested chip is ensured to meet the expectation.

Description

Technical Field

[0001] The present invention relates to the technical field of digital integrated circuits, and in particular to a chip verification method, device, server, storage medium and program product. Background Art

[0002] With the advancement of integrated circuit technology, the scale and complexity of chips continue to increase, and the verification process has become more complex and challenging. Effective chip verification requires the generation of a large number of test stimuli to simulate different input conditions in order to evaluate the performance and stability of the chip under various working environments.

[0003] However, the quality of test stimuli generated in current chip verification methods is often poor, and they cannot fully cover all key scenarios and boundary conditions, resulting in potential errors not being discovered in time. At the same time, relying on manual creation of test cases is inefficient and susceptible to human errors, further reducing the reliability and effectiveness of verification. As the design scale increases, verification efficiency decreases significantly, the verification cycle becomes long, and resource consumption increases. Summary of the invention

[0004] In view of this, the present invention provides a chip verification method, device, server, storage medium and program product to solve the problems of poor quality of test stimulus and low verification efficiency in the current chip verification method.

[0005] In a first aspect, the present invention provides a chip verification method, comprising: generating a pseudo-random number sequence according to a pre-created pseudo-random number generation environment, the pseudo-random number generation environment being created based on a verification platform development library and a pseudo-random number algorithm library; converting the pseudo-random number sequence into an excitation sequence, and sending the excitation sequence to a chip to be tested; receiving response data sent by the chip to be tested in response to the excitation sequence, and comparing the response data with expected data to obtain a comparison result; when it is determined according to the comparison result that the chip to be tested does not meet expectations, adjusting the pseudo-random number generation environment according to the comparison result until the response data regenerated based on the adjusted pseudo-random number generation environment meets expectations.

[0006] The chip verification method provided by the embodiment of the present invention reduces manual intervention and improves verification efficiency by automatically generating a pseudo-random number sequence. The pseudo-random number generation environment can be dynamically adjusted according to the comparison results, thereby enhancing the flexibility of verification. By comparing with the expected data, potential problems of the chip can be discovered and corrected in a timely manner to ensure that its performance meets the design requirements. At the same time, the pseudo-random number generation environment can be continuously optimized according to the comparison results, thereby improving the quality of the pseudo-random number sequence and improving the efficiency and accuracy of chip verification.

[0007] In an optional embodiment, creating a pseudo-random number generation environment includes: loading a verification platform development library and multiple predefined verification platform development components, and obtaining environment configuration information; creating a verification platform development environment based on the environment configuration information, and instantiating multiple verification platform development components; obtaining a pre-created data plane interface library, a pre-created pseudo-random number algorithm library, and a seed value; calling an initialization function in the data plane interface library to set the pseudo-random number algorithm library according to the seed value, and then obtaining the pseudo-random number generation environment.

[0008] The chip verification method provided by the embodiment of the present invention dynamically creates a verification platform development environment according to the environment configuration information, ensuring that the generated pseudo-random number generation environment can adapt to specific hardware and software configurations, thereby improving flexibility. By calling the initialization function in the data plane interface library, the pseudo-random number algorithm library can be quickly set up, reducing the tedious process of manual configuration and improving system efficiency. A variety of pseudo-random number sequences can be generated according to different seed values ​​to adapt to different verification requirements, thereby improving the randomness and diversity of the generated numbers.

[0009] In an optional embodiment, multiple verification platform development components include a pseudo-random number generation component; the pseudo-random number generation component includes an extraction digital function; generating a pseudo-random number sequence according to a pre-created pseudo-random number generation environment includes: generating a random number sequence according to the extraction digital function.

[0010] In the chip verification method provided by the embodiment of the present invention, the use of the extraction digital function can quickly generate a high-quality random number sequence, thereby reducing the time overhead in the verification process. The extraction digital function can be adjusted according to specific needs, making the pseudo-random number generation more flexible and able to meet the needs of different verification environments.

[0011] In an optional implementation, converting a pseudo-random number sequence into an excitation sequence includes: acquiring a predefined communication protocol; converting the pseudo-random number sequence into a data format corresponding to the communication protocol to obtain formatted data; and combining the formatted data to generate an excitation sequence.

[0012] The chip verification method provided by the embodiment of the present invention can ensure that the generated stimulus sequence is consistent with the specific system requirements and protocols by obtaining a predefined communication protocol, thereby improving the effectiveness of the test. The pseudo-random number sequence is converted into a data format corresponding to the communication protocol to ensure the compatibility of the data in the system and reduce potential format errors. The stimulus sequence generated using pseudo-random numbers can introduce more randomness, thereby improving the comprehensiveness of the test and the evaluation of the system robustness.

[0013] In an optional embodiment, multiple verification platform development components include a driver component; the driver component is used to convert a stimulus sequence into a signal corresponding to the interface of the chip to be tested; the stimulus sequence is sent to the chip to be tested, including: obtaining a preset sending order and a preset time interval corresponding to the stimulus sequence; based on the preset sending order and the preset time interval, sending the stimulus sequence to the chip to be tested according to the driver component.

[0014] In the chip verification method provided by the embodiment of the present invention, the driving component can convert the stimulus sequence into the signal format required by the specific interface, ensure that the stimulus can be correctly transmitted to the chip to be tested, and enhance the compatibility of the system. By presetting the sending order and time interval, accurate control of the sending of the stimulus signal can be achieved, which helps to simulate the signal interaction in actual applications and improve the authenticity of the test. The automated driving component can send the stimulus sequence quickly and accurately, saving time and manpower for manual operation and improving the efficiency of the verification process.

[0015] In an optional implementation, a feedback mechanism is obtained so that the driving component adjusts the sending order and time interval of the stimulus sequence to be sent according to the response data.

[0016] The chip verification method provided by the embodiment of the present invention can adjust the stimulus sequence according to the real-time response of the chip to be tested through the feedback mechanism, so as to ensure that the test process is more dynamic and flexible. Adjustment based on the response data can more accurately target the actual behavior of the chip and enhance the reliability and relevance of the test results. Dynamic adjustment of the stimulus sequence can reduce misjudgment caused by static transmission order or time interval, and improve the accuracy of chip performance evaluation.

[0017] In an optional embodiment, multiple verification platform development components include a monitoring component and a scoring component; receiving response data sent by the chip under test after responding to the stimulus sequence, and comparing the response data with expected data to obtain a comparison result, including: according to the monitoring component, capturing the response data sent by the chip under test after responding to the stimulus sequence; obtaining the expected data, which is generated according to a predefined verification model; according to the scoring component, comparing the response data with the expected data to obtain a comparison result.

[0018] In the chip verification method provided by the embodiment of the present invention, the monitoring component can capture the response data of the chip to be tested in real time, making the entire test process more transparent and helping to find problems in a timely manner. The scoring component can automatically compare the response data with the expected data, reducing the need for manual inspection and improving the efficiency of the verification process. By comparing with the expected data generated by the pre-defined verification model, the performance of the chip can be evaluated more accurately to ensure the reliability of the test results.

[0019] In an optional embodiment, the pseudo-random number sequence is analyzed to obtain the random characteristics corresponding to the pseudo-random number sequence; when it is determined according to the comparison result that the response data is consistent with the expected data, and the random characteristics meet the preset conditions, it is determined that the chip to be tested meets expectations; when it is determined according to the comparison result that the response data is inconsistent with the expected data, or the random characteristics do not meet the preset conditions, it is determined that the chip to be tested does not meet expectations.

[0020] The chip verification method provided by the embodiment of the present invention can more comprehensively evaluate the performance of the chip and ensure the accuracy of the test results by analyzing the randomness characteristics of the pseudo-random number sequence. The randomness characteristics can be used as an evaluation criterion to determine whether the stimulus sequence can effectively cover all possible scenarios.

[0021] In an optional embodiment, when it is determined according to the comparison result that the chip to be tested does not meet expectations, the pseudo-random number generation environment is adjusted according to the comparison result until the response data regenerated based on the adjusted pseudo-random number generation environment meets expectations, including: when it is determined that the chip to be tested does not meet expectations, based on the comparison result, at least one algorithm parameter corresponding to the pseudo-random number algorithm library is adjusted; wherein at least one algorithm parameter includes a rotation bit and / or a linear feedback bit; using an optimization algorithm to determine an optimal parameter combination from at least one adjusted algorithm parameter; adjusting the pseudo-random number algorithm library according to the optimal parameter combination to update at least one algorithm parameter; regenerating a new pseudo-random number sequence according to the updated at least one algorithm parameter; sending the new pseudo-random number sequence to the chip to be tested, and receiving new response data generated by the chip to be tested; comparing the new response data with the expected data to obtain a new comparison result; when it is determined according to the new comparison result that the chip to be tested meets expectations, stopping the test of the chip to be tested; or, when it is determined that the chip to be tested does not meet expectations, re-adjusting at least one adjusted algorithm parameter according to the new comparison result until the response data regenerated based on the adjusted pseudo-random number generation environment meets expectations.

[0022] The chip verification method provided by the embodiment of the present invention significantly improves the quality of the pseudo-random number sequence through parameter optimization and adaptive adjustment. The rotation bit and linear feedback bit parameters are optimized to ensure the uniformity, independence and periodicity of the pseudo-random number sequence, thereby improving the randomness of the sequence. This high-quality pseudo-random number sequence provides a more reliable data basis for subsequent stimulus generation, and improves the efficiency and accuracy of chip verification. By optimizing the parameters, the quality of the pseudo-random number sequence is improved, thereby improving the verification efficiency. The high-quality pseudo-random number sequence can effectively cover all functional points and potential defects of the chip, reducing the situation of repeated tests and invalid tests. In addition, with the help of adaptive adjustment, the algorithm parameters are dynamically adjusted according to the verification feedback to adapt to the changing verification environment and requirements, further improving the verification efficiency. Through these optimization measures, the coverage of verification is significantly improved. The optimization parameters not only improve the functional coverage and code coverage, but also ensure the comprehensiveness and depth of verification. In addition, the dynamic adjustment of parameters enables it to adapt to the verification requirements of different stages, further enhancing the verification coverage. The high-quality pseudo-random number sequence helps to reduce the error rate and defect density found in the verification process, and can more effectively detect chip defects and reduce the number of errors and defects. Through continuous parameter optimization and adaptive adjustment, the pseudo-random number sequence will continue to improve, thereby further reducing the error rate and defect density, and improving the reliability and stability of the chip. Through parameter optimization and adaptive adjustment, the performance and power consumption of pseudo-random number generation and verification are maintained within an acceptable range. These optimizations ensure that real-time requirements are met without negatively affecting chip performance.

[0023] In a second aspect, the present invention provides a chip verification device, including: a generation module, used to generate a pseudo-random number sequence according to a pre-created pseudo-random number generation environment, the pseudo-random number generation environment is created based on a verification platform development library and a pseudo-random number algorithm library; a conversion module, used to convert the pseudo-random number sequence into an excitation sequence, and send the excitation sequence to the chip to be tested; a comparison module, used to receive response data sent by the chip to be tested in response to the excitation sequence, and compare the response data with expected data to obtain a comparison result; a verification module, used to adjust the pseudo-random number generation environment according to the comparison result when it is determined that the chip to be tested does not meet expectations according to the comparison result, until the response data regenerated based on the adjusted pseudo-random number generation environment meets expectations.

[0024] In a third aspect, the present invention provides a server, comprising: a memory and a processor, the memory and the processor are communicatively connected to each other, computer instructions are stored in the memory, and the processor executes the chip verification method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0025] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the chip verification method of the first aspect or any corresponding embodiment thereof.

[0026] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions, wherein the computer instructions are used to enable a computer to execute the chip verification method of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 is a schematic flow chart of a chip verification method according to an embodiment of the present invention;

[0029] Figure 2 is a flow chart of another chip verification method according to an embodiment of the present invention;

[0030] Figure 3 is a schematic diagram of connecting the Mersenne Twister algorithm with the UVM environment when the pseudo-random number algorithm is the Mersenne Twister algorithm according to an embodiment of the present invention;

[0031] Figure 4 is a flow chart of another chip verification method according to an embodiment of the present invention;

[0032] Figure 5 is a structural block diagram of a chip verification device according to an embodiment of the present invention;

[0033] Figure 6 It is a schematic diagram of the hardware structure of the server according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0035] In the later stages of digital integrated circuit design, chip verification is an important step to ensure that the design meets the expected functions and technical specifications. With the continuous advancement of integrated circuit technology, the scale and complexity of chips are increasing, which makes chip verification face greater complexity and challenges. Effective chip verification usually requires the generation of a large number of test stimuli to simulate various possible input conditions, so as to verify the performance and stability of the chip under different working environments. The quality of the test stimulus directly affects the comprehensiveness and efficiency of verification.

[0036] At present, there are four main test stimulus generation methods commonly used in chip verification: First, deterministic test stimulus tests chip functions through predefined input sequences. These sequences are based on design specifications and expected behaviors, but due to the huge input space, it is difficult to cover all possible combinations. Second, random test stimulus uses random or pseudo-random number generation algorithms to generate stimulus. Although it can provide a certain degree of randomness, simple generators (such as linear congruential generators) often cannot generate high-quality pseudo-random sequences, resulting in insufficient randomness and periodicity. Third, constrained random test stimulus combines randomness with specific constraints, and ensures that the generated stimulus meets the verification goal by imposing restrictions, but its setting and implementation are relatively complex and require professional knowledge. Finally, the test stimulus generation method based on functional graph generates stimulus covering specific paths by establishing a functional graph model of the chip design. Although it can improve the coverage of specific functional paths, it is difficult to achieve comprehensive coverage of all chip functions.

[0037] Although the current test stimulus generation methods are widely used in chip verification, there are still some problems. First, the test coverage is insufficient. Due to the huge input space, it is difficult for traditional methods to achieve comprehensive coverage, which may cause some potential design defects to be overlooked. Secondly, the randomness and uniformity of many pseudo-random number generation algorithms are not ideal, and the generated test stimulus cannot fully simulate the actual random working conditions, thus affecting the reliability of the verification results. In addition, common pseudo-random number generation algorithms (such as linear congruential generators) have periodic limitations, and repeated patterns may appear when generating longer random sequences, which limits their application. Furthermore, generating a large number of test stimuli requires a lot of time and computing resources, especially in complex chip designs, making the verification process time-consuming and costly. Finally, many existing methods have poor adaptability to specific chip designs or verification targets, and often require customized development, which increases the difficulty and workload of verification.

[0038] In view of this, the technical solution of the present invention generates a pseudo-random number sequence by combining a pre-created pseudo-random number generation environment with a verification platform development library and a pseudo-random number algorithm library. The sequence is converted into an excitation sequence and sent to the chip to be tested, and the response data is received and compared with the expected data to obtain a comparison result, thereby improving the accuracy and efficiency of chip verification and reducing the omission of potential design defects.

[0039] According to an embodiment of the present invention, a chip verification method embodiment is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0040] In this embodiment, a chip verification method is provided, which can be used in a server. Figure 1 is a flow chart of a chip verification method according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0041] Step S101, generating a pseudo-random number sequence according to a pre-created pseudo-random number generation environment, where the pseudo-random number generation environment is created based on a verification platform development library and a pseudo-random number algorithm library.

[0042] The pseudo-random number generation environment is a system for generating pseudo-random numbers, which includes the necessary verification platform development library, pseudo-random number algorithm library, data plane interface library and interface, so as to effectively generate pseudo-random numbers. Specifically, the verification platform development (Universal Verification Methodology, UVW) library is a verification method library based on SystemVerilog, which is used for functional verification of chip design. It provides a complete set of verification components and structures to build a reusable and extensible verification environment. The pseudo-random number algorithm library includes pseudo-random algorithms pre-written by users in C or C++, such as the Mersenne twister algorithm, which can generate high-quality 32-bit or 64-bit pseudo-random numbers. The data plane interface library is a database that can be used with the SystemVerilog Direct Programming Interface (DPI), such as the Data Plane Interface-C Library (DPI-C), which is a C library that can be used with the SystemVerilog DPI, allowing SystemVerilog to interoperate with C code, that is, the verification platform development library can call the pseudo-random number algorithm library through the data plane interface library.

[0043] A pseudo-random number sequence is a series of numbers generated by a pseudo-random number generation algorithm. These numbers appear random, but are actually generated by a deterministic algorithm and are predictable. Specifically, set up and configure the UVM verification platform, including the necessary components and structures to ensure the reusability and extensibility of the verification environment. Import the pseudo-random number algorithm library and the data plane interface library in the verification platform to interoperate with the C code. Use the data plane interface (DPI) to call pre-written C or C++ pseudo-random number algorithms from SystemVerilog, such as the Mersenne twister algorithm. Ensure that the interface is configured correctly to facilitate data transfer. In the UVM environment, generate the required number of pseudo-random numbers. Among them, different seed values ​​can be set to obtain different random sequences.

[0044] Step S102, converting the pseudo-random number sequence into an excitation sequence, and sending the excitation sequence to the chip to be tested.

[0045] A stimulus sequence is a set of input signals or data used to drive the function of the chip under test. During the verification process, the stimulus sequence is converted from the generated pseudo-random number sequence and can be a specific test vector, control signal, or other type of data. These stimulus sequences are used to test the response of the chip to verify whether its function meets the design requirements. Specifically, the input signal format and structure required for the chip under test are determined. According to the defined stimulus format, the generated pseudo-random number sequence is mapped to the stimulus signal. The mapped pseudo-random numbers are organized into a stimulus sequence to form a series of time series data. This can be an array or a queue, where each element corresponds to a stimulus signal once.

[0046] The device under test (DUT) refers to a specific chip that is undergoing functional verification or testing. Specifically, an appropriate interface is used to send the stimulus sequence to the chip under test. For example, in a simulation tool, the input port of the DUT is driven by writing a test benchmark, the generated stimulus sequence is assigned to the input signal of the DUT, and the sending timing of the stimulus is controlled using a clock signal; or when using UVM, a driver can be created to implement the logic of sending the stimulus sequence to the DUT in the driver, and the driver will extract the stimulus signal from the stimulus queue and send it in sequence, which is not limited here.

[0047] Step S103, receiving response data sent by the chip under test after responding to the stimulus sequence, and comparing the response data with expected data to obtain a comparison result.

[0048] Response data refers to the output signal or data generated by the chip under test according to the design logic after receiving the stimulus sequence. Specifically, in the simulation environment, the output signal of the DUT can be set as a monitoring signal, and the response data can be captured using a specific module of SystemVerilog. When using UVM, the capture of the DUT output can also be achieved in the monitor, which will continuously monitor the output signal of the DUT and record it, which is not limited here.

[0049] The expected data is the expected output result of the DUT based on the design specification or functional description, and is the output condition defined by the designer or verification engineer during the design. The comparison result refers to the judgment obtained by comparing the response data with the expected data, which may include a match (Pass) and a mismatch (Fail). Specifically, in the test benchmark or UVM environment, a comparison module is created to take out the stored response data and compare it with the expected data. For example, a conditional statement can be used to determine whether the response data and the expected data are equal. If the two are equal, a "Pass" result is recorded; if they are not equal, a "Fail" result is recorded, and error information may be recorded for subsequent analysis.

[0050] Step S104, when it is determined according to the comparison result that the chip under test does not meet expectations, the pseudo-random number generation environment is adjusted according to the comparison result until the response data regenerated based on the adjusted pseudo-random number generation environment meets expectations.

[0051] Specifically, after comparing the response data with the expected data, if it is found that it does not meet expectations, the error information or debugging tool is analyzed to determine whether it is incorrect input stimulus, design defects of DUT, or problems in the test environment. At the same time, identify specific patterns or regularities in the response data to understand which inputs cause mismatches. According to the above analysis results, the pseudo-random number generation strategy can be modified, such as modifying the parameters of pseudo-random number generation to ensure that the generated stimulus signal is more likely to meet expectations, or adding constraints when generating pseudo-random numbers to ensure that the generated values ​​meet certain specific conditions, which are not limited here. In addition, according to the above analysis results, specific stimuli can also be added. For example, when it is found that certain specific inputs can produce expected responses, the probability or frequency of these inputs can be increased. Use the adjusted pseudo-random number generation environment to regenerate the stimulus sequence and send it to DUT again. Repeat the step of receiving the response data and compare it with the expected data to confirm whether the adjusted stimulus can produce an expected response. If the response still does not meet expectations, continue to analyze the comparison results and make necessary adjustments until the expected response data is obtained.

[0052] The chip verification method provided by the embodiment of the present invention reduces manual intervention and improves verification efficiency by automatically generating a pseudo-random number sequence. The pseudo-random number generation environment can be dynamically adjusted according to the comparison results, thereby enhancing the flexibility of verification. By comparing with the expected data, potential problems of the chip can be discovered and corrected in a timely manner to ensure that its performance meets the design requirements. At the same time, the pseudo-random number generation environment can be continuously optimized according to the comparison results, thereby improving the quality of the pseudo-random number sequence and improving the efficiency and accuracy of chip verification.

[0053] In this embodiment, a chip verification method is provided, which can be used in a server. Figure 2 is a flow chart of a chip verification method according to an embodiment of the present invention. Figure 2 As shown, the process includes the following steps:

[0054] Step S201, generating a pseudo-random number sequence according to a pre-created pseudo-random number generation environment, where the pseudo-random number generation environment is created based on a verification platform development library and a pseudo-random number algorithm library.

[0055] Specifically, create a pseudo-random number generation environment, including:

[0056] Step a1: load the verification platform development library and multiple predefined verification platform development components, and obtain environment configuration information.

[0057] The verification platform development component refers to various modules and classes used in the verification process, such as pseudo-random number generation component (dpi_init_genrand), driver component (driver) and monitoring component (monitor), etc. Specifically, the path of the verification platform development library is specified in the configuration file of the simulation tool, the verification platform development library is loaded according to the path of the verification platform development library, and the predefined verification component is loaded by creating a UVM component instance.

[0058] The environment configuration information is used to configure various parameters of the verification environment, such as simulation time, DUT configuration, interface parameters, etc. Specifically, the user can set the environment configuration information by editing a configuration file or providing command line parameters on the local computer, wherein the user can directly run the simulation tool on the local computer or run the simulation tool by remotely connecting to a server.

[0059] Step a2: creating a verification platform development environment according to the environment configuration information, and instantiating multiple verification platform development components.

[0060] The verification platform development environment (UVM environment) refers to the overall architecture and component set used to verify chip design. This environment integrates various verification components, configuration parameters, and test logic to achieve comprehensive verification of the chip under test. Specifically, the UVM environment is based on the UVM framework and provides a standardized component structure to facilitate the construction of a reusable and scalable verification environment. It includes multiple verification platform development components such as dpi_init_genrand, driver, monitor, etc., which are responsible for different functions, such as sending incentives, monitoring outputs, comparing results, etc.

[0061] Specifically, when building the verification platform development environment, define a verification environment class, which is used to encapsulate all verification components and related configuration logic. In this class, you can define components for management and interaction, such as agents and monitors. Instantiate these components in a specific phase (such as build_phase). The verification environment class can call the construction method of the parent class and create the required component instances according to the configuration. Each component is associated with the environment so that it can access shared data and configuration. Furthermore, in the test class, you need to create an instance of the environment, that is, instantiate the environment class defined previously, and call the relevant construction and configuration methods to ensure that the environment is ready for verification.

[0062] Step a3, obtaining a pre-created data plane interface library, a pre-created pseudo-random number algorithm library, and a seed value.

[0063] The seed value is used to initialize the pseudo-random number generator (PRNG) corresponding to the pseudo-random number algorithm library to ensure that the random number sequence generated in each simulation is repeatable. By setting the same seed value, the same random sequence can be obtained in different simulation runs. Specifically, a fixed seed value can be hard-coded directly in the simulation script, that is, the same seed value will be used for each simulation, which is suitable for situations where a fixed test scenario is required. Alternatively, the seed value can be passed through the command line parameter when starting the simulation, that is, the user can adjust the seed value at each run, which is suitable for the needs of different test scenarios. Alternatively, the seed value can be read from an external configuration file. By modifying the configuration file without changing the code, the seed value can be easily managed, which is helpful for different test configurations, which are not limited here.

[0064] Step a4, calling the initialization function in the data plane interface library to set the pseudo-random number algorithm library according to the seed value and obtain the pseudo-random number generation environment.

[0065] The initialization function is a function used to set the state of the pseudo-random number generator. For example, it can be the dpi_init_genrand function, which initializes the pseudo-random number algorithm by providing a seed value to ensure that the initial state of the random number generator is determined so that a repeatable random number sequence can be generated. Specifically, using the functions provided by the data plane interface library (such as dpi_init_genrand), the previously determined seed value is passed as a parameter. Once the initialization function is called and the seed is successfully set, the pseudo-random number generator is in a ready state. At this point, random numbers can be obtained by calling other functions that generate random numbers, and the pseudo-random number generation environment is created.

[0066] For example, Figure 3 As shown, Figure 3 It is a schematic diagram of connecting the Mersenne Twister algorithm with the UVM environment when the pseudo-random number algorithm is the Mersenne Twister algorithm.

[0067] Specifically, in the C code, the Mersenne Twister algorithm first needs to be initialized by providing a seed value to start the internal state of the algorithm. This seed value can be fixed or a random value obtained from the outside.

[0068] Implement the Mersenne Twister algorithm in C code to generate pseudo-random number sequences. Once initialized, the Mersenne Twister algorithm can generate pseudo-random numbers. These random numbers are provided to the SystemVerilog environment through the C function exported by DPI for random stimulus generation in the test.

[0069] In SystemVerilog code, use the import dpi statement to import C functions. Through these functions, SystemVerilog can call the Mersenne Twister algorithm in the C code and obtain the generated random numbers. DPI supports two directions of data transfer: from SystemVerilog to C (DPI-C import) and from C to SystemVerilog (DPI-C export).

[0070] The DPI C functions contain the specific implementation of the Mersenne Twister algorithm in the form of C functions. These functions can initialize the state of the algorithm, generate random numbers, and provide any necessary updates to the algorithm state.

[0071] Functions in the C code need to be declared as DPI exported so that SystemVerilog can call them through DPI, for example, by adding the DPIEXPORT macro in front of the C function.

[0072] In UVM, random numbers are often used to create sequences and transactions. These sequences and transactions define the type and order of stimulus sent to the DUT. For example, a sequence may contain a collection of randomly generated packets, each of which contains a random number as part of its content.

[0073] Random numbers generated from the Mersenne Twister algorithm are used by components in the UVM environment, which are used to simulate different stages in the verification process, such as sending data, monitoring transactions, and collecting results.

[0074] Specifically, the components in the UVM environment include UVM Driver components, UVM Monitor components, and UVM Agent components. Among them, the UVM Driver is responsible for sending stimulus sequences to the DUT, and can use random numbers to set the properties of the stimulus sequences, such as data values, addresses, timing, etc. The UVM Monitor component is responsible for observing the behavior of the DUT. It does not directly use random numbers, but needs to analyze the results generated by random numbers. The UVM Agent component is a component that encapsulates the driver and monitor. It can configure the behavior of these components and use random numbers to control the complexity and diversity of the test.

[0075] The chip verification method provided by the embodiment of the present invention dynamically creates a verification platform development environment according to the environment configuration information, ensuring that the generated pseudo-random number generation environment can adapt to specific hardware and software configurations, thereby improving flexibility. By calling the initialization function in the data plane interface library, the pseudo-random number algorithm library can be quickly set up, reducing the tedious process of manual configuration and improving system efficiency. A variety of pseudo-random number sequences can be generated according to different seed values ​​to adapt to different verification requirements, thereby improving the randomness and diversity of the generated numbers.

[0076] Specifically, the plurality of verification platform development components include a pseudo-random number generation component; the pseudo-random number generation component includes an extraction digital function; the above step S201 includes: generating a random number sequence according to the extraction digital function.

[0077] The extract_number function (extract_number) is used to extract the generated random numbers from the random number generator. The extract_number function extracts the random number from the internal state and returns an integer or floating point number, depending on the implementation. Since the state of the random number generator is initialized by the seed value, the sequence of random numbers generated by calling this function is predictable and can be used for testing and verification. Specifically, after initializing the pseudo-random number generator, use the extract_number function to generate random numbers. In this process, a loop may be used to extract multiple random numbers to form a random number sequence.

[0078] In the chip verification method provided by the embodiment of the present invention, the use of the extraction digital function can quickly generate a high-quality random number sequence, thereby reducing the time overhead in the verification process. The extraction digital function can be adjusted according to specific needs, making the pseudo-random number generation more flexible and able to meet the needs of different verification environments.

[0079] Step S202: convert the pseudo-random number sequence into an excitation sequence, and send the excitation sequence to the chip to be tested.

[0080] Specifically, the multiple verification platform development components include a driver component; the driver component is used to convert the stimulus sequence into a signal corresponding to the interface of the chip to be tested; the above step S202 includes:

[0081] Step S2021, obtaining a predefined communication protocol.

[0082] The communication protocol is a set of predefined rules and conventions for exchanging data with the chip under test. Specifically, the predefined communication protocol can be obtained by editing a configuration file or providing a command line parameter.

[0083] Step S2022, converting the pseudo-random number sequence into a data format corresponding to the communication protocol to obtain formatted data.

[0084] Formatted data refers to the structure of data that has been processed according to the requirements of a specific communication protocol. Specifically, the random number is converted into a specific format according to the definition of the communication protocol. For example, the random number is converted into a payload field. A complete data packet is constructed, and necessary fields (such as headers and tails) are added to the data generated by the random number to form formatted data that meets the protocol requirements.

[0085] Step S2023, combining the formatted data to generate an excitation sequence.

[0086] Specifically, multiple formatted data packets are combined in a specific order to form a complete stimulus sequence. The stimulus sequence is preprocessed as necessary, such as removing invalid stimuli under specific conditions or sorting the stimuli.

[0087] Furthermore, statistical tests (such as frequency tests, sequence correlation tests) can be used to verify the quality of the excitation sequence.

[0088] Step S2024, obtaining a preset sending order and a preset time interval corresponding to the excitation sequence.

[0089] The preset sending order refers to the order in which the predefined stimulus sequence is sent, for example, by priority or random order. The preset time interval refers to the delay time between sending each stimulus packet to ensure that the protocol timing requirements are met and signal conflicts are avoided. Specifically, the predefined preset sending order and preset time interval can be obtained by editing the configuration file or providing command line parameters.

[0090] Step S2025 , based on a preset sending order and a preset time interval, the driving component sends the stimulus sequence to the chip under test.

[0091] The driver component is used to send the stimulus sequence to the chip under test. Random numbers can be used to set the properties of the stimulus sequence, such as data value, address, timing, etc. Specifically, the driver component converts the stimulus sequence into the signal format required by the DUT and ensures the correct transmission of the signal by controlling the DUT interface. The driver component sends the stimulus signal (stimulus sequence) to the DUT according to the transmission order and time interval set above.

[0092] Step S2026: Acquire a feedback mechanism so that the driving component adjusts the sending order and time interval of the stimulus sequence to be sent according to the response data.

[0093] The feedback mechanism refers to dynamically adjusting the sending strategy of subsequent stimuli by monitoring and obtaining the response of the DUT to the sent stimulus during the test process. Specifically, the driver component reads the response of the DUT through the interface signal. The driver component will record the received response data. These data usually include response status, data value, timing information, etc. The driver component needs to parse the response data to determine whether the DUT has correctly processed the previous stimulus. Based on the analysis results, the driver component can be dynamically adjusted. Among them, this feedback mechanism is usually cyclical, and the driver component will obtain the response of the DUT after sending each stimulus, and gradually adjust the subsequent stimulus strategy.

[0094] Step S203, receiving the response data sent by the chip under test after responding to the stimulus sequence, and comparing the response data with the expected data to obtain a comparison result. Figure 1 Step S103 of the illustrated embodiment will not be described in detail here.

[0095] Step S204: when it is determined according to the comparison result that the chip under test does not meet expectations, the pseudo-random number generation environment is adjusted according to the comparison result until the response data regenerated based on the adjusted pseudo-random number generation environment meets expectations. Figure 1 Step S104 of the illustrated embodiment will not be described in detail here.

[0096] The chip verification method provided by the embodiment of the present invention can ensure that the generated stimulus sequence is consistent with the specific system requirements and protocols by obtaining a predefined communication protocol, thereby improving the effectiveness of the test. The pseudo-random number sequence is converted into a data format corresponding to the communication protocol to ensure the compatibility of the data in the system and reduce potential format errors. The stimulus sequence generated using pseudo-random numbers can introduce more randomness, thereby improving the comprehensiveness of the test and the evaluation of the robustness of the system. The drive component can convert the stimulus sequence into the signal format required by the specific interface to ensure that the stimulus can be correctly transmitted to the chip to be tested, thereby enhancing the compatibility of the system. By presetting the sending sequence and time interval, accurate control of the sending of the stimulus signal can be achieved, which helps to simulate the signal interaction in actual applications and improve the authenticity of the test. The automated drive component can send the stimulus sequence quickly and accurately, saving time and manpower for manual operation and improving the efficiency of the verification process. Through the feedback mechanism, the drive component can adjust the stimulus sequence according to the real-time response of the chip to be tested to ensure that the test process is more dynamic and flexible. Adjustment based on the response data can more accurately target the actual behavior of the chip and enhance the reliability and relevance of the test results. Dynamic adjustment of the stimulus sequence can reduce misjudgment caused by static sending sequence or time interval and improve the accuracy of chip performance evaluation.

[0097] In this embodiment, a chip verification method is provided, which can be used in a server. Figure 4 is a flow chart of a chip verification method according to an embodiment of the present invention. Figure 4 As shown, the process includes the following steps:

[0098] Step S401, generate a pseudo-random number sequence according to a pre-created pseudo-random number generation environment, the pseudo-random number generation environment is created based on the verification platform development library and the pseudo-random number algorithm library. Figure 2 Step S201 of the illustrated embodiment will not be described in detail here.

[0099] Step S402: Convert the pseudo-random number sequence into an excitation sequence, and send the excitation sequence to the chip under test. Figure 2 Step S202 of the illustrated embodiment will not be described in detail here.

[0100] Step S403, receiving response data sent by the chip under test after responding to the stimulus sequence, and comparing the response data with expected data to obtain a comparison result.

[0101] Specifically, the multiple verification platform development components include a monitoring component and a scoring component, and the above step S403 includes:

[0102] Step S4031: capturing, according to the monitoring component, response data sent by the chip under test after responding to the stimulus sequence.

[0103] The monitor component is used to capture the response of the chip under test to the stimulus sequence sent. Specifically, the monitor component monitors the output signals of the DUT in real time and captures these responses immediately after the stimulus is sent. The captured data will be passed to the subsequent processing components (such as the scoring component) for further analysis and verification.

[0104] Step S4032, obtaining expected data, where the expected data is generated according to a predefined verification model.

[0105] The verification model is a simulation model used to define and standardize the expected output that the chip under test should generate under specific input conditions, such as a golden model. Specifically, the expected data is generated according to a predefined verification model or simulation results.

[0106] Step S4033: Compare the response data with the expected data according to the scoring component to obtain a comparison result.

[0107] The scoreboard component is used to compare the response data captured from the monitoring component with the expected data item by item. Specifically, the response data captured from the monitoring component is compared with the expected data item by item, and a comparison result is generated to identify the matching between the response data and the expected data, such as successful matching and mismatching. Any mismatched response can be recorded and the cause of the error can be analyzed.

[0108] Furthermore, the test results are statistically analyzed to evaluate the performance indicators of the DUT, such as throughput and latency.

[0109] Step S4034, analyzing the pseudo-random number sequence to obtain the randomness characteristics corresponding to the pseudo-random number sequence.

[0110] Randomness refers to whether the pseudo-random number sequence used to generate the test stimulus has the required random properties, such as uniformity, independence, and periodicity, which determines whether the test stimulus can effectively cover all possible scenarios. Specifically, frequency tests can be used to check uniformity, autocorrelation tests can be used to evaluate independence, walk tests can be used to analyze sequence continuity, and chi-square tests can be used to compare actual and expected frequencies. Combining these methods, the randomness of the sequence can be fully evaluated.

[0111] Step S4035, when it is determined according to the comparison result that the response data is consistent with the expected data, and the randomness characteristic meets the preset conditions, it is determined that the chip to be tested meets expectations.

[0112] The randomness characteristic meets the preset conditions, which means that the quality of the pseudo-random number sequence is high enough to effectively cover the possible input space, so that the verification forms a closed loop and the verification can be completed. Specifically, if the response data of the DUT matches the expected data, and the randomness of the pseudo-random number sequence also meets expectations, then the verification passes and the closed-loop verification ends.

[0113] Step S4036: when it is determined according to the comparison result that the response data does not match the expected data, or the randomness characteristic does not meet the preset condition, it is determined that the chip under test does not meet expectations.

[0114] Randomness characteristics that do not meet the preset conditions mean that the pseudo-random number sequence cannot fully cover the input space or there are statistical deviations, so parameter optimization and iteration processes are required to improve the performance of the random number generator. Specifically, if the response of the DUT does not meet expectations, or the randomness of the pseudo-random number sequence does not meet expectations, then the verification fails and further analysis and iteration are required to solve the problem. At the same time, a detailed test report can be generated, including test coverage, success rate, failure rate, etc.

[0115] Furthermore, the parameters of the random number generator or the test strategy can be adjusted according to the test results, and it can be decided whether to continue the simulation or terminate the simulation.

[0116] In the chip verification method provided by the embodiment of the present invention, the monitoring component can capture the response data of the chip to be tested in real time, making the entire test process more transparent and helping to find problems in a timely manner. The scoring component can automatically compare the response data with the expected data, reducing the need for manual inspection and improving the efficiency of the verification process. By comparing with the expected data generated by a predefined verification model, the performance of the chip can be more accurately evaluated to ensure the reliability of the test results. By analyzing the randomness characteristics of the pseudo-random number sequence, the performance of the chip can be more comprehensively evaluated to ensure the accuracy of the test results. Using the randomness characteristics as an evaluation criterion can be used to determine whether the stimulus sequence can effectively cover all possible scenarios.

[0117] Step S404, when it is determined according to the comparison result that the chip under test does not meet expectations, the pseudo-random number generation environment is adjusted according to the comparison result until the response data regenerated based on the adjusted pseudo-random number generation environment meets expectations.

[0118] Specifically, the above step S404 includes:

[0119] Step S4041, when it is determined that the chip under test does not meet expectations, based on the comparison result, at least one algorithm parameter corresponding to the pseudo-random number algorithm library is adjusted; wherein the at least one algorithm parameter includes a rotation bit and / or a linear feedback bit.

[0120] At least one algorithm parameter refers to a key setting that affects the quality of pseudo-random number generation, including a rotation bit and / or a linear feedback bit. Among them, the rotation bit is used to determine the initial state or offset in the pseudo-random number generation, affecting the way the sequence is generated. The linear feedback bit is used to determine the specific position of the feedback mechanism, affecting the periodicity and randomness of the generated sequence. Specifically, by comparing the response data of the chip to be tested with the expected data, it is identified which aspects have differences (for example, uneven distribution, repeated sequences, etc.). According to the comparison results, it is determined which parameter may lead to undesirable performance. For example, if it is found that the generated random number sequence is too regular, the linear feedback bit needs to be adjusted; if the sequence is offset, the rotation bit needs to be changed. The value of the rotation bit can be increased or decreased to change the starting state of the pseudo-random number. The position of the feedback bit can be adjusted to change the characteristics of the feedback loop and increase or decrease the complexity of the sequence.

[0121] Step S4042: using an optimization algorithm, determine an optimal parameter combination from at least one adjusted algorithm parameter.

[0122] The optimization algorithm is used to find the optimal solution, such as genetic algorithm, particle swarm optimization (PSO), etc., which are not limited here. The optimal parameter combination refers to the parameter setting that can produce the best pseudo-random number performance after optimization. These parameter settings will make the generated random numbers have better statistical properties, such as more uniform distribution and higher independence. Specifically, determine the target to be optimized, such as the uniformity, periodicity and other performance indicators of pseudo-random numbers, and construct an objective function that calculates the performance score through input parameters. Specify the range of algorithm parameters to be optimized, such as the rotation bit can vary from 0 to a certain maximum value, and the selection of linear feedback bits should also be within a specific range. Select a suitable optimization algorithm based on the characteristics of the problem. For example, for complex parameter combinations, you can choose genetic algorithm or particle swarm optimization. Randomly generate multiple initial parameter combinations for evaluation during the optimization process. Use the selected optimization algorithm to iteratively adjust the parameter combination, and continuously update and improve the parameters by evaluating the objective function multiple times to find the optimal solution. For example, in genetic algorithms, you can select parameter combinations with better performance for reproduction to generate new combinations; in particle swarm optimization, adjust the position based on the historical best position of each particle and the best position of the group. Once the algorithm is finished, analyze the final parameter combination, calculate its objective function value, and confirm whether it is optimal. The determined optimal parameter combination is applied to the pseudo-random number algorithm library to generate a higher quality random number sequence.

[0123] Step S4043: adjust the pseudo-random number algorithm library according to the optimal parameter combination to update at least one algorithm parameter.

[0124] Using the optimal parameter combination previously determined by the optimization algorithm, at least one algorithm parameter of the pseudo-random number generation algorithm is updated, for example, parameters such as the update rotation bit and the linear feedback bit are updated.

[0125] Step S4044, regenerate a new pseudo-random number sequence according to the updated at least one algorithm parameter.

[0126] Once the algorithm parameters are updated, rerun the pseudo-random number generation algorithm with the new parameter settings. This will generate a new pseudo-random number sequence, which is generated based on the latest parameter combination and will have better statistical properties and adaptability.

[0127] Step S4045, sending the new pseudo-random number sequence to the chip under test, and receiving new response data generated by the chip under test.

[0128] The newly generated pseudo-random number sequence is input into the chip under test, and the chip under test will process or calculate according to these values ​​to generate new response data. The server receives the results returned by the chip under test for subsequent comparative analysis.

[0129] Furthermore, the impact of parameter adjustments can be evaluated by comparing the old and new comparison results, and the randomness of the new pseudo-random number sequence can be analyzed.

[0130] Specifically, by analyzing the verification results before and after the adjustment, we evaluate whether the parameter changes are effective, improve the expected response of the DUT, and check whether more test scenarios are covered. Analyze the newly generated pseudo-random number sequence to ensure that it has good statistical properties (such as uniformity, independence, and periodicity). These properties are very important to ensure the comprehensiveness and effectiveness of the test.

[0131] Among them, the quality of the new pseudo-random number sequence directly affects the results of verification. If the randomness is insufficient, it may lead to incomplete test coverage, thus missing potential design defects. If the analysis shows that the parameter adjustment does not achieve the expected effect or there is a problem with the pseudo-random number sequence, this will provide direction for subsequent parameter optimization and indicate where further adjustments are needed. At the same time, it can help the verification team understand the current verification status and provide a basis for subsequent decision-making. That is, by comparing the results, it can be determined whether the parameter adjustment has improved the verification pass rate, reduced the error rate, or improved other key indicators. The new sequence has better randomness, which can more effectively explore all possible states of the DUT, thereby improving the coverage of verification.

[0132] Step S4046, compare the new response data with the expected data to obtain a new comparison result.

[0133] After receiving the new response data generated by the chip under test, these data are compared with the expected data to help determine whether the chip under test works as expected. The new comparison result is a new evaluation result used to indicate whether the performance of the current chip under test meets the requirements.

[0134] Step S4047, when it is determined according to the new comparison result that the chip to be tested meets expectations, the test of the chip to be tested is stopped.

[0135] If the response data of the chip under test is found to be consistent with or very close to the expected data during the comparison, it will be confirmed that the chip meets the design requirements. In this case, the test process can be stopped, indicating that the performance of the chip has reached the standard.

[0136] Step S4048, when it is determined that the chip under test does not meet expectations, readjust at least one of the adjusted algorithm parameters according to the new comparison result until the response data regenerated based on the adjusted pseudo-random number generation environment meets expectations.

[0137] If the response data of the chip under test does not meet expectations, the previously adjusted algorithm parameters will be further adjusted based on the new comparison results. This will return to the parameter optimization process described above, trying different parameter settings to generate a new set of pseudo-random numbers, and then hopefully get response data that is more in line with expectations. This step is an iterative process, with the goal of generating new random numbers and retesting after each adjustment until the expected results are obtained.

[0138] The chip verification method provided by the embodiment of the present invention significantly improves the quality of the pseudo-random number sequence through parameter optimization and adaptive adjustment. The rotation bit and linear feedback bit parameters are optimized to ensure the uniformity, independence and periodicity of the pseudo-random number sequence, thereby improving the randomness of the sequence. This high-quality pseudo-random number sequence provides a more reliable data basis for subsequent stimulus generation, and improves the efficiency and accuracy of chip verification. By optimizing the parameters, the quality of the pseudo-random number sequence is improved, thereby improving the verification efficiency. The high-quality pseudo-random number sequence can effectively cover all functional points and potential defects of the chip, reducing the situation of repeated tests and invalid tests. In addition, with the help of adaptive adjustment, the algorithm parameters are dynamically adjusted according to the verification feedback to adapt to the changing verification environment and requirements, further improving the verification efficiency. Through these optimization measures, the coverage of verification is significantly improved. The optimization parameters not only improve the functional coverage and code coverage, but also ensure the comprehensiveness and depth of verification. In addition, the dynamic adjustment of parameters enables it to adapt to the verification requirements of different stages, further enhancing the verification coverage. The high-quality pseudo-random number sequence helps to reduce the error rate and defect density found in the verification process, and can more effectively detect chip defects and reduce the number of errors and defects. Through continuous parameter optimization and adaptive adjustment, the pseudo-random number sequence will continue to improve, thereby further reducing the error rate and defect density, and improving the reliability and stability of the chip. Through parameter optimization and adaptive adjustment, the performance and power consumption of pseudo-random number generation and verification are maintained within an acceptable range. These optimizations ensure that real-time requirements are met without negatively affecting chip performance.

[0139] In this embodiment, a chip verification device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware for a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0140] This embodiment provides a chip verification device, such as Figure 5 As shown, including:

[0141] A generation module 501 is used to generate a pseudo-random number sequence according to a pre-created pseudo-random number generation environment, where the pseudo-random number generation environment is created based on a verification platform development library and a pseudo-random number algorithm library;

[0142] A conversion module 502, used for converting a pseudo-random number sequence into an excitation sequence, and sending the excitation sequence to the chip to be tested;

[0143] The comparison module 503 is used to receive the response data sent by the chip under test after responding to the stimulus sequence, and compare the response data with the expected data to obtain a comparison result;

[0144] The verification module 504 is used to adjust the pseudo-random number generation environment according to the comparison result when it is determined that the chip under test does not meet expectations according to the comparison result, until the response data regenerated based on the adjusted pseudo-random number generation environment meets expectations.

[0145] In some optional embodiments, the above device further includes:

[0146] A loading module is used to load the verification platform development library and multiple predefined verification platform development components, and obtain environment configuration information;

[0147] A creation module is used to create a verification platform development environment according to the environment configuration information and instantiate multiple verification platform development components;

[0148] An acquisition module, used to acquire a pre-created data plane interface library, a pre-created pseudo-random number algorithm library, and a seed value;

[0149] The calling module is used to call the initialization function in the data plane interface library to obtain the pseudo-random number generation environment after setting the pseudo-random number algorithm library according to the seed value.

[0150] In some optional implementations, the generating module 501 includes:

[0151] The first generating submodule is used to generate a random number sequence according to an extraction number function.

[0152] In some optional implementations, the conversion module 502 includes:

[0153] A first acquisition submodule, used to acquire a predefined communication protocol;

[0154] A conversion submodule, used for converting the pseudo-random number sequence into a data format corresponding to the communication protocol to obtain formatted data;

[0155] The second generating submodule is used to combine the formatted data to generate an excitation sequence.

[0156] In some optional implementations, the conversion module 502 further includes:

[0157] The second acquisition submodule is used to acquire a preset sending order and a preset time interval corresponding to the excitation sequence;

[0158] The first sending submodule is used to send the stimulus sequence to the chip to be tested according to the driving component based on a preset sending order and a preset time interval.

[0159] In some optional implementations, the conversion module 502 further includes:

[0160] The third acquisition submodule is used to acquire a feedback mechanism so that the driving component adjusts the sending order and time interval of the stimulus sequence to be sent according to the response data.

[0161] In some optional implementations, the comparison module 503 includes:

[0162] The capture submodule is used to capture the response data sent by the chip under test after responding to the stimulus sequence according to the monitoring component;

[0163] A fourth acquisition submodule is used to acquire expected data, where the expected data is generated according to a predefined verification model;

[0164] The first comparison submodule is used to compare the response data with the expected data according to the scoring component to obtain a comparison result.

[0165] In some optional implementations, the comparison module 503 further includes:

[0166] An analysis submodule is used to analyze the pseudo-random number sequence to obtain the randomness characteristics corresponding to the pseudo-random number sequence;

[0167] A first determination submodule is used to determine that the chip to be tested meets expectations when it is determined according to the comparison result that the response data is consistent with the expected data and the randomness characteristic meets the preset conditions;

[0168] The second determination submodule is used to determine that the chip to be tested does not meet expectations when it is determined according to the comparison result that the response data does not match the expected data, or the randomness characteristic does not meet the preset conditions.

[0169] In some optional implementations, the verification module 504 includes:

[0170] A first adjustment submodule, configured to adjust at least one algorithm parameter corresponding to the pseudo-random number algorithm library based on the comparison result when it is determined that the chip under test does not meet expectations; wherein the at least one algorithm parameter includes a rotation bit and / or a linear feedback bit;

[0171] A third determination submodule is used to determine an optimal parameter combination from at least one adjusted algorithm parameter using an optimization algorithm;

[0172] A second adjustment submodule, used to adjust the pseudo-random number algorithm library according to the optimal parameter combination to update at least one algorithm parameter;

[0173] A third generating submodule, used to regenerate a new pseudo-random number sequence according to at least one updated algorithm parameter;

[0174] A second sending submodule is used to send a new pseudo-random number sequence to the chip under test and receive new response data generated by the chip under test;

[0175] A second comparison submodule is used to compare the new response data with the expected data to obtain a new comparison result;

[0176] The verification submodule is used to stop testing the chip to be tested when it is determined that the chip to be tested meets expectations based on new comparison results; or, when it is determined that the chip to be tested does not meet expectations, readjust at least one adjusted algorithm parameter based on new comparison results until response data regenerated based on the adjusted pseudo-random number generation environment meets expectations.

[0177] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0178] The chip verification device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0179] The chip verification device provided by the embodiment of the present invention reduces manual intervention and improves verification efficiency by automatically generating a pseudo-random number sequence. The pseudo-random number generation environment can be dynamically adjusted according to the comparison results, thereby enhancing the flexibility of verification. By comparing with the expected data, potential problems of the chip can be discovered and corrected in a timely manner to ensure that its performance meets the design requirements. At the same time, the pseudo-random number generation environment can be continuously optimized according to the comparison results, thereby improving the quality of the pseudo-random number sequence and improving the efficiency and accuracy of chip verification.

[0180] The embodiment of the present invention also provides a server having the above Figure 5 The chip verification device shown.

[0181] See also Figure 6 , Figure 6 is a schematic diagram of the structure of a server provided by an optional embodiment of the present invention, such as Figure 6As shown, the server includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. The various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process instructions executed in the server, including instructions stored in or on the memory to display graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple servers can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 6 A processor 10 is taken as an example.

[0182] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0183] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0184] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required by at least one function; the data storage area may store data created according to the use of the server, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the server via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0185] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0186] The server further comprises a communication interface 30 for the server to communicate with other devices or a communication network.

[0187] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0188] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0189] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A chip verification method, characterized in that: The method comprises: Generate a pseudo-random number sequence according to a pre-created pseudo-random number generation environment, wherein the pseudo-random number generation environment is created based on a verification platform development library and a pseudo-random number algorithm library; Converting the pseudo-random number sequence into an excitation sequence, and sending the excitation sequence to the chip to be tested; Receiving response data sent by the chip under test after responding to the stimulus sequence, and comparing the response data with expected data to obtain a comparison result; When it is determined according to the comparison result that the chip under test does not meet expectations, the pseudo-random number generation environment is adjusted according to the comparison result until response data regenerated based on the adjusted pseudo-random number generation environment meets expectations.

2. The method according to claim 1, characterized in that Create a pseudo-random number generation environment, including: Loading the verification platform development library and a plurality of predefined verification platform development components, and obtaining environment configuration information; Creating a verification platform development environment according to the environment configuration information, and instantiating the multiple verification platform development components; Get the pre-created data plane interface library, the pre-created pseudo-random number algorithm library, and the seed value; An initialization function in the data plane interface library is called to set the pseudo-random number algorithm library according to the seed value, and then obtain the pseudo-random number generation environment.

3. The method according to claim 2, characterized in that The plurality of verification platform development components include a pseudo-random number generation component; the pseudo-random number generation component includes an extract number function; Generates a pseudo-random number sequence based on a pre-created pseudo-random number generation environment, including: The random number sequence is generated according to the extract number function.

4. The method according to claim 1, characterized in that: The converting the pseudo-random number sequence into an excitation sequence comprises: Get predefined communication protocols; Converting the pseudo-random number sequence into a data format corresponding to the communication protocol to obtain formatted data; The formatted data are combined to generate the excitation sequence.

5. The method according to claim 4, characterized in that The plurality of verification platform development components include a driver component; the driver component is used to convert the stimulus sequence into a signal corresponding to the interface of the chip to be tested; Sending the stimulus sequence to the chip to be tested includes: Obtaining a preset sending order and a preset time interval corresponding to the excitation sequence; Based on the preset sending order and the preset time interval, the excitation sequence is sent to the chip under test according to the driving component.

6. The method according to claim 5, characterized in that Also includes: A feedback mechanism is obtained so that the driving component adjusts the sending order and time interval of the stimulus sequence to be sent according to the response data.

7. The method according to claim 1, characterized in that Multiple verification platform development components include monitoring components and scoring components; The receiving of response data sent by the chip under test after responding to the stimulus sequence, and comparing the response data with expected data to obtain a comparison result, includes: According to the monitoring component, capturing response data sent by the chip under test after responding to the stimulus sequence; Acquiring the expected data, where the expected data is generated according to a predefined verification model; According to the scoring component, the response data is compared with the expected data to obtain the comparison result.

8. The method according to claim 7, characterized in that Also includes: Analyzing a pseudo-random number sequence to obtain a random characteristic corresponding to the pseudo-random number sequence; When it is determined according to the comparison result that the response data is consistent with the expected data, and the randomness characteristic meets the preset condition, it is determined that the chip to be tested meets the expectations; When it is determined according to the comparison result that the response data does not match the expected data, or the randomness characteristic does not meet the preset condition, it is determined that the chip to be tested does not meet expectations.

9. The method according to claim 8, characterized in that When it is determined according to the comparison result that the chip under test does not meet expectations, adjusting the pseudo-random number generation environment according to the comparison result until response data regenerated based on the adjusted pseudo-random number generation environment meets expectations, including: When it is determined that the chip under test does not meet expectations, based on the comparison result, at least one algorithm parameter corresponding to the pseudo-random number algorithm library is adjusted; wherein at least one of the algorithm parameters includes a rotation bit and / or a linear feedback bit; Using an optimization algorithm, determining an optimal parameter combination from the adjusted at least one algorithm parameter; Adjusting the pseudo-random number algorithm library according to the optimal parameter combination to update at least one of the algorithm parameters; Regenerate a new pseudo-random number sequence according to at least one updated algorithm parameter; Sending the new pseudo-random number sequence to the chip under test, and receiving new response data generated by the chip under test; Compare the new response data with the expected data to obtain a new comparison result; When it is determined according to the new comparison result that the chip to be tested meets expectations, stopping the test on the chip to be tested; or, When it is determined that the chip under test does not meet expectations, at least one adjusted algorithm parameter is readjusted according to the new comparison result until response data regenerated based on the adjusted pseudo-random number generation environment meets expectations.

10. A chip verification device, characterized in that: The device comprises: A generation module, used to generate a pseudo-random number sequence according to a pre-created pseudo-random number generation environment, wherein the pseudo-random number generation environment is created based on a verification platform development library and a pseudo-random number algorithm library; A conversion module, used for converting the pseudo-random number sequence into an excitation sequence, and sending the excitation sequence to the chip to be tested; A comparison module, used for receiving response data sent by the chip under test after responding to the stimulus sequence, and comparing the response data with expected data to obtain a comparison result; The verification module is used to adjust the pseudo-random number generation environment according to the comparison result when it is determined that the chip under test does not meet expectations according to the comparison result, until the response data regenerated based on the adjusted pseudo-random number generation environment meets expectations.

11. A server, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the chip verification method according to any one of claims 1 to 9 by executing the computer instructions.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the chip verification method according to any one of claims 1 to 9.

13. A computer program product, characterized in that The method comprises computer instructions, wherein the computer instructions are used to cause a computer to execute the chip verification method according to any one of claims 1 to 9.

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