Image analysis system and image analysis method

Abstract

The invention provides an image analysis system and an image analysis method. The image analysis system comprises an input device, a storage device and a processing device. The input device is configured to receive line layout image information for producing a printed circuit board. The storage device is configured to access preset standard information. The processing device is electrically connected with the input device and the storage device. Wherein the processing device is configured to generate at least one piece of feature information according to the line layout image information, and the processing device is configured to compare the at least one piece of feature information with preset standard information so as to generate feasibility analysis information.

Description

Technical Field

[0001] The invention relates to a printed circuit board manufacturing technology, and in particular to an image analysis system and an image analysis method. Background Art

[0002] Electronic design automation (EDA) refers to a design method that uses computer-aided design software to complete the design process of electronic components (e.g., printed circuit boards, integrated circuits, etc.). Among them, design for manufacturability (DFM) is an important step in EDA. Specifically, the purpose of DFM is to evaluate the circuit layout parameters according to some design specifications (or design standards) to ensure that the product design can proceed smoothly during the actual manufacturing process. In this way, manufacturing problems and production costs can be reduced, and the quality and reliability of products can be improved. In order to make the results of DFM more accurate and meet user needs, it is necessary to develop an analysis system and analysis method that can accurately judge circuit layout parameters or design parameters. Summary of the invention

[0003] In some embodiments, an image analysis system is provided. The image analysis system includes an input device, a storage device, and a processing device. The input device is configured to receive a circuit layout image information for producing a printed circuit board. The storage device is configured to access a preset standard information. The processing device is electrically connected to the input device and the storage device. The processing device is configured to generate at least one feature information based on the circuit layout image information, and the processing device is configured to compare the at least one feature information with the preset standard information, thereby generating a feasibility analysis information.

[0004] In some embodiments, an analysis method is provided. The image analysis method includes: receiving a circuit layout image information for producing a printed circuit board through an input device; generating at least one feature information according to the circuit layout image information through a processing device; and comparing the at least one feature information with a preset standard information stored in a storage device through the processing device to generate feasibility analysis information.

[0005] The image analysis system and image analysis method disclosed in the present invention can be applied to the manufacturing feasibility analysis (DFM) of printed circuit boards. By analyzing the circuit layout image information of printed circuit boards, it is possible to effectively avoid design errors and manufacturing cost losses caused by subsequent defect repair or scrapping of defective products before the actual manufacturing of printed circuit boards. In order to make the features and advantages of the present invention more obvious and easy to understand, various embodiments are specifically cited below, and are described in detail as follows in conjunction with the drawings in the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The following detailed description in conjunction with the accompanying drawings of the specification can better understand the viewpoints of the embodiments of the present disclosure. It is worth noting that according to standard industrial practices, some features may not be drawn to scale. In fact, the sizes of different features may be increased or reduced in order to clearly describe.

[0007] Figure 1 is a block diagram of an image display analysis system according to some embodiments of the present disclosure;

[0008] Figure 2 is a flow chart of an image display analysis method according to some embodiments of the present disclosure;

[0009] Figure 3 is a cross-sectional schematic diagram showing a circuit pattern according to some embodiments of the present disclosure;

[0010] Figure 4 is a schematic top view showing a circuit pattern according to some embodiments of the present disclosure;

[0011] Figure 5A and Figure 5B are three-dimensional schematic diagrams showing circuit patterns according to some embodiments of the present disclosure;

[0012] Fig. 6A and Figure 6B are schematic top views of gaskets according to some embodiments of the present disclosure;

[0013] Figure 7 is a schematic top view showing a heat dissipation copper strip according to some embodiments of the present disclosure;

[0014] Fig. 8A is a schematic top view showing a guide hole according to some embodiments of the present disclosure; and

[0015] Figure 8B and Figure 8C According to other embodiments of the present disclosure, a cross-sectional schematic diagram and a top schematic diagram of a guide hole are respectively shown.

[0016] Description of reference numerals:

[0017] 1: Image analysis system

[0018] 10: Input device

[0019] 11: Storage device

[0020] 12: Processing device

[0021] 13: Output device

[0022] A1: Area

[0023] A2: Area

[0024] A3: Area

[0025] A4: Area

[0026] A5: Area

[0027] A6: Region

[0028] C: Circuit pattern

[0029] C1: Circuit pattern

[0030] C2: Circuit pattern

[0031] C3: Circuit pattern

[0032] C4: Circuit Pattern

[0033] CC1: Center of circle

[0034] CC2: Center of circle

[0035] CS: heat dissipation copper strip

[0036] d1: depth

[0037] d2: line distance

[0038] d3: Spacing

[0039] d4: Spacer spacing

[0040] d5: Spacing

[0041] H: Line height

[0042] P: Gasket

[0043] S: Substrate

[0044] S10-S16: Steps

[0045] V: Guide hole

[0046] V1: Conductive layer

[0047] V2: Conductive filling material

[0048] W1: Upper line width

[0049] W2: Lower line width

[0050] W3: Side line length

[0051] θ1: bending angle

[0052] θ20: bending angle

[0053] θ21: bending angle

[0054] θ3: Bending angle

[0055] θ40: bending angle

[0056] θ41: bending angle DETAILED DESCRIPTION

[0057] The following disclosure provides many different embodiments or examples for implementing the provided analysis system and analysis method. Specific examples of each component and its configuration are described below to simplify the embodiments of the present disclosure, and are certainly not intended to limit the present disclosure. For example, if the description mentions that a first component is formed on a second component, it may include an embodiment in which the first component and the second component are in direct contact, and it may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component are not in direct contact. In addition, the present disclosure may repeat component symbols and / or characters in different embodiments or examples. Such repetition is for simplicity and clarity, and is not used to represent the relationship between the different embodiments and / or examples discussed.

[0058] Directional terms mentioned herein, such as "up", "down", "left", "right" and the like, are with reference to the directions of the accompanying drawings. Therefore, the directional terms used are used to illustrate rather than limit the present disclosure.

[0059] In some embodiments of the present disclosure, terms such as "disposed", "connected" and the like, unless otherwise defined, may refer to two components being in direct contact, or may refer to two components not being in direct contact, wherein an additional component is located between the two structures. Terms such as "disposed", "connected" and the like may also include situations where both structures are movable or both structures are fixed.

[0060] In addition, the terms "first", "second" and similar terms mentioned in this specification or claims are used to name different components or distinguish different embodiments or ranges, and are not used to limit the upper or lower limit of the number of components, nor are they used to limit the manufacturing order or setting order of the components.

[0061] Hereinafter, "approximately", "substantially" or similar terms mean within 10%, within 5%, within 3%, within 2%, within 1%, or within 0.5% of a given value or range of values. The given numbers are approximate numbers, that is, in the absence of a specific description of "approximately" or "substantially", the meaning of "approximately" or "substantially" can still be implied.

[0062] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by those skilled in the art. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present disclosure.

[0063] In the prior art, the circuit layout of a printed circuit board (PCB) is usually performed using engineering drawing software. Specifically, the circuit layout needs to meet design specifications such as electrical rules, routing rules, surface mount technology rules (SMT rules), mask rules, and manufacturing rules to ensure that a printed circuit board that meets expectations and is reliable can be actually manufactured.

[0064] To this end, the present disclosure provides an image analysis system and an image analysis method, which can automatically determine the manufacturing feasibility of the circuit layout according to preset standards or custom standards, thereby effectively solving the above-mentioned problems. It is worth mentioning that although some design specifications in the circuit layout are mentioned above, the present disclosure is not limited to this. In other embodiments, the image analysis system and image analysis method of the present disclosure can analyze the circuit layout according to any design specification recognized by technicians in the relevant technical field.

[0065] Reference Figure 1 , which is a block diagram showing an image analysis system according to some embodiments of the present disclosure. As shown in the figure, the image analysis system 1 includes an input device 10, a storage device 11, a processing device 12 and an output device 13. In some embodiments, the image analysis system 1 and each device therein can be installed in a terminal device, a computer device and / or a server individually or in an integrated manner in the form of a combination of a software program and a physical circuit, and after being read and / or enabled, the circuit layout information used to produce a printed circuit board is subjected to manufacturing feasibility analysis.

[0066] The input device 10 is configured to receive circuit layout image information for producing printed circuit boards. In some embodiments, the circuit layout image information can be presented as a digital file of an engineering drawing software (e.g., a CAM file), and the circuit layout image information can be a two-dimensional design drawing or a three-dimensional design drawing. In some embodiments, the circuit layout image information may include drawings and parameters of substrates, circuit patterns, gaskets, guide holes, combinations thereof, and other electronic components. For example, the parameters of the substrate include substrate length, substrate width, substrate thickness, substrate shape, substrate material, combinations thereof, or other suitable parameters, but the present disclosure is not limited thereto. For example, the parameters of the circuit pattern include upper line width, lower line width, line height, line spacing, conductor material, combinations thereof, or other suitable parameters, but the present disclosure is not limited thereto. For example, the parameters of the gasket include gasket size, gasket material, combinations thereof, or other suitable parameters, but the present disclosure is not limited thereto.

[0067] In some embodiments, the input device 10 may also be configured to receive preset standard information or customized standard information. The preset standard information may include parameter thresholds corresponding to one or more of design specifications such as electrical rules, wiring rules, surface mount technology rules, solder mask / flux soldering rules, manufacturing rules, etching rules, etc. For example, the preset standard information may include line bending angle standard information, pad spacing standard information, heat dissipation copper spokes standard information, guide hole standard information, pin standard information, line size standard information, line position standard information, combinations thereof, or other suitable standard information. These standard information will be used to compare whether the line layout image information complies with design specifications such as those mentioned above. When the line layout image information does not comply with the standard information, it means that a part of the parameters of the line layout exceeds the parameter threshold, so that the part may be at risk of insufficient manufacturing feasibility.

[0068] In addition, in order to meet the design requirements of different products (for example, higher electrical requirements or specific structures), the preset standard information can be adjusted to generate customized custom standard information. Similarly, the custom information can include custom information on circuit bending angles, custom information on pad spacing, custom information on heat dissipation copper strips, custom information on guide hole shapes, custom information on pins, custom information on circuit size, custom information on circuit position, combinations thereof, or other suitable custom information.

[0069] In some embodiments, the input device 10 may be or may include a device for receiving a digital image file, such as a connector, a communication port, etc. Alternatively, the input device 10 may be or may include a device for reading a digital image file, such as a card reader, etc. In some embodiments, the input device 10 may also include an alphanumeric keyboard and a pointing device (e.g., a cursor control device), a camera device, a microphone, or a similar device for receiving voice commands, etc., but the present disclosure is not limited thereto.

[0070] The storage device 11 is configured to access preset standard information, custom standard information, and circuit layout image information. In some embodiments, the storage device 11 may include a compact disc read-only memory (CD-ROM), a hard disk drive, an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc., but the present disclosure is not limited thereto. Examples of memory may include dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, etc., but the present disclosure is not limited thereto.

[0071] The processing device 12 is electrically connected to the input device 10 and the storage device 11, and the processing device 12 is configured to generate at least one feature information according to the circuit layout image information. Specifically, the processing device 12 is configured to compare at least one feature information with preset standard information, or is configured to compare at least one feature information with custom standard information. In this article, the term "feature information" refers to the drawings and parameters of the substrate, circuit pattern, pad or other electronic components in the circuit layout image information, but the present disclosure is not limited thereto. For example, the processing device 12 can extract the upper line width, lower line width, line height, and line spacing of the circuit pattern in the circuit layout image information to generate feature information. Then, the processing device 12 determines whether these feature information meet the corresponding parameters in the preset standard information. When the upper line width of the circuit pattern does not meet the upper line width threshold in the preset standard information, it means that the circuit pattern may have a risk of insufficient manufacturing feasibility, for example, the result of over-etching is generated in the subsequent etching process. The specific operation of the comparison process for manufacturing feasibility will be further described in the analysis method below, and only the possible configurations and functions of each device are described here.

[0072] In some embodiments, the processing device 12 may include electronic components such as a processor, a computer-readable medium, and a memory to execute a computer program to implement the functions described above. Examples of processors may include a central processing unit (CPU), a multi-core CPU, a graphics processing unit (GPU), etc., but the present disclosure is not limited thereto. Examples of computer-readable media may include a compact disc read-only memory (CD-ROM), a hard drive, an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc., but the present disclosure is not limited thereto. Examples of memory may include a dynamic random access memory, a static random access memory, a flash memory, etc., but the present disclosure is not limited thereto. It is worth mentioning that the term "computer program" used herein refers to an application stored in a computer-readable medium, which can be read into a memory for processing by a processor. In some embodiments, the application may be written in any combination of one or more programming languages. Programming languages ​​include object-oriented programming languages, such as Java, Smalltalk, C++, or similar languages, and traditional procedural programming languages, such as the C programming language or similar programming languages.

[0073] The output device 13 is electrically connected to the processing device 12 and is configured to display the feasibility analysis information according to the comparison result of the processing device 12. In some embodiments, the output device 13 displays an image or output data generated by an electronic component. For example, the output device 13 may be or may include a printer, a display, a speaker, or a similar output device, wherein the display is such as a cathode ray tube (CRT), a liquid crystal display (LCD), etc. It is worth mentioning that in some embodiments, the image analysis system 1 may not have an output device 13. In these embodiments, the feasibility analysis information obtained by the image analysis system 1 can be read by other devices other than the image analysis system 1, such as a terminal device of a manufacturing system, etc.

[0074] Refer to Figure 2, which is a flow chart showing an image analysis method according to some embodiments of the present disclosure. As shown in the figure, the analysis method includes steps S10 to S16. In step S10, a circuit layout image information for producing a printed circuit board is received by an input device 10. In some embodiments, the circuit layout image information may be a digital image file that has been drawn by other drawing equipment. Alternatively, instructions may be input through the input device 10 to directly generate the circuit layout image information in a terminal device, a computer device and / or a server where the image analysis system of the present disclosure is located, and edit the circuit layout image information. In step S12, at least one feature information is generated according to the circuit layout image information by the processing device 12. In step S14, at least one feature information is compared with the preset standard information stored in the storage device by the processing device 12. In step S16, the feasibility analysis information is displayed by the output device 13 according to the comparison result of the processing device 12. Among them, the feasibility analysis information may be presented in the form of a chart, a design drawing or a text description, but the present disclosure is not limited thereto. It is worth mentioning that in some embodiments, the image analysis system 1 may not have an output device 13. Therefore, step S16 may be omitted in these embodiments.

[0075] In some embodiments, the processing device 12 may generate at least one piece of feature information according to the full-page image of the circuit layout image, or may generate at least one piece of feature information according to the partial image of the circuit layout image, but the present disclosure is not limited thereto.

[0076] In some embodiments, the processing device 12 may be an AI artificial intelligence device, and utilizes AI artificial intelligence to perform the processing of step S12 and step S14, but the present disclosure is not limited thereto.

[0077] In order to understand step S12 and step S14 more clearly, refer to Figures 3 to 8C To describe the operation of extracting feature information and comparing the feature information with preset standard information. It is worth mentioning that the manufacturing feasibility analysis operation described below is only some embodiments of the present disclosure, which is only used to make the present disclosure easier to understand, but is not intended to limit the present disclosure. In other embodiments, different feature information can be extracted to perform the manufacturing feasibility analysis operation.

[0078] like Figure 3 , which is a schematic cross-sectional view showing a circuit pattern according to some embodiments of the present disclosure. In some embodiments, the processing device 12 extracts a circuit pattern C disposed on the substrate S at a specific position (e.g., Figure 3For example, the characteristic information may include line information, and the line information defines values ​​such as upper line width W1, lower line width W2, side wall width W3, line height H, and top view side wall width d1. On the other hand, the preset standard information correspondingly includes line standard information, and the line standard information defines values ​​such as upper line width threshold, lower line width threshold, side wall width threshold, line height threshold, and top view side wall width threshold. In this case, step S12 may also include: comparing the line information with the line standard information by the processing device 12. In some embodiments, electrical rules define the electrical requirements of the circuit pattern, and the line information affects the electrical performance of the circuit. Therefore, when the above parameters are lower than the threshold (for example, the upper line width W1 is lower than the upper line width threshold), the processing device 12 may determine that the manufacturing feasibility is insufficient according to the electrical rules. In some embodiments, the electrical rules may be a calculation method specified in relevant standards such as IPC published by the Association for Connecting Electronics Industries, such as IPC-2221, IPC-2222, IPC-2223, IPC-2224, IPC-2225, IPC-2226, IPC-2227, etc., but the present disclosure is not limited thereto.

[0079] like Figure 4 As shown, it is a schematic top view of a circuit pattern according to some embodiments of the present disclosure. In some embodiments, the line information further defines a line spacing d2, and the line standard information defines a line spacing threshold. In this case, step S12 may also include: comparing the line information with the line standard information by the processing device 12. In some embodiments, the clearance rules define that the spacing between two adjacent wires in the circuit pattern shall not be less than a certain value to avoid mutual interference of electrical signals or to avoid a short circuit between two lines. Therefore, when the line spacing d2 is lower than the line spacing threshold, the processing device 12 may determine that the manufacturing feasibility is insufficient according to the clearance rules.

[0080] like Figure 4 As shown, in some embodiments, the characteristic information may also include line position information, and the preset standard information correspondingly includes line position standard information. In this case, step S12 may also include: comparing the line position information with the line position standard information by the processing device 12. In some embodiments, the safety spacing rule defines that the spacing d3 between the conductor in the circuit pattern and the periphery of the substrate shall not be less than a certain value to avoid an electrical short circuit between two conductors located in different layers along the side wall of the substrate. Therefore, when the spacing d3 between the conductor and the periphery of the substrate is lower than the threshold, the processing device 12 may determine that the manufacturing feasibility is insufficient according to the safety spacing rule.

[0081] like Figure 5A and Figure 5BAs shown, they are three-dimensional schematic diagrams showing circuit patterns according to some embodiments of the present disclosure. In some embodiments, the processing device 12 extracts characteristic information of the circuit pattern C disposed on the substrate S. For example, the characteristic information may include line bending angle information, and the preset standard information correspondingly includes line bending angle standard information. Figure 5A As shown, for example, the line bending angle information defines the bending angle θ1 of the circuit pattern C1 in the area A1, and defines the bending angle θ20 and the bending angle θ21 of the circuit pattern C2 in the area A2. Among them, the bending angle θ1 is less than 90 degrees, the bending angle θ20 is equal to 90 degrees, and the bending angle θ21 is greater than 90 degrees. In this case, step S12 may also include: comparing the line bending angle information with the line bending angle standard information by the processing device 12. In some embodiments, the routing corners rules define that the bending angle of the circuit pattern shall not be less than a right angle (that is, presenting an acute angle) to avoid the etching liquid of the subsequent etching process from falling into the corner of the circuit pattern to form an acid trap. Therefore, the processing device 12 can judge that the manufacturing feasibility of the circuit pattern C1 in the area A1 is insufficient according to the routing corner rules, and judge that the circuit pattern C2 has manufacturing feasibility in the area A2.

[0082] Similarly, if Figure 5B As shown, the line bending angle information defines the bending angle θ3 of the circuit pattern C3 in the area A3, and defines the bending angle θ40 and the bending angle θ41 of the circuit pattern C4 in the area A4. Among them, the bending angle θ3 is less than 90 degrees, the bending angle θ40 is equal to 90 degrees, and the bending angle θ41 is greater than 90 degrees. In this case, step S12 may also include: comparing the line bending angle information with the line bending angle standard information by the processing device 12. Further, the processing device 12 may determine that the manufacturing feasibility of the circuit pattern C3 in the area A3 is insufficient according to the wiring angle rule, and determine that the circuit pattern C4 has manufacturing feasibility in the area A4.

[0083] like Fig. 6A and Figure 6B As shown, they are schematic top views of gaskets according to some embodiments of the present disclosure. In some embodiments, the characteristic information may include gasket spacing information, and the preset standard information correspondingly includes gasket spacing standard information. Fig. 6AAs shown, for example, the pad spacing information defines the pad spacing d4 between two adjacent pads P, and the line standard information defines the pad spacing threshold. In this case, step S12 may also include: comparing the pad spacing information with the pad spacing standard information by the processing device 12. In some embodiments, the safety spacing rule defines that the spacing d4 between two adjacent pads must not be lower than a certain value to prevent the pad P from drifting in subsequent processes such as reflow and generating antenna effects (floating copper / solder mask silvers antennas) with other pads P (such as Figure 6B or to prevent the pad P from drifting and causing an electrical short circuit with other pads P in a subsequent process such as reflow (such as Figure 6B Therefore, when the spacer spacing d4 is lower than the spacer spacing threshold, the processing device 12 may determine that the manufacturing feasibility is insufficient according to the safety spacing rule.

[0084] like Figure 7 As shown, it is a schematic top view showing the heat dissipation copper bar according to some embodiments of the present disclosure. In some embodiments, the feature information may also include heat dissipation copper bar information, and the preset standard information correspondingly includes heat dissipation copper bar standard information. For example, the heat dissipation copper bar information defines the number of heat dissipation copper bars CS, and the heat dissipation copper bar standard information defines the number threshold of the heat dissipation copper bars. In this case, step S12 may also include: comparing the heat dissipation copper bar information with the heat dissipation copper bar standard information by the processing device 12. In some embodiments, the heat dissipation copper bar CS is used to provide sufficient thermal capacity (or heat storage) during the welding process to avoid instability or insufficient heat storage (starved thermal) during the welding process. Therefore, when the number of heat dissipation copper bars CS exceeds (for example, is lower than) the number threshold of the heat dissipation copper bars, the processing device 12 may determine that the manufacturing feasibility is insufficient.

[0085] like FIG. 8A to FIG. 8C As shown, Fig. 8A is a schematic top view showing a guide hole according to some embodiments of the present disclosure, and Figure 8B and Figure 8C 1 and 2 are schematic cross-sectional views and schematic top views of guide holes according to other embodiments of the present disclosure. In some embodiments, the feature information may include guide hole information, and the preset standard information correspondingly includes guide hole standard information. In some embodiments, the guide hole V is an interconnection element for electrical connection, which includes a conductive layer V1 extending horizontally on the surface of the substrate S and vertically on the sidewall of the through hole, and includes a conductive filling material V2 (such as a conductive filler material V2) extending vertically in the through hole. Figure 8B In the top view, the guide hole information defines the distance d5 between the center CC1 of the conductive layer V1 and the center CC2 of the conductive filling material V2 (as shown in FIG. Figure 8C), and the guide hole standard information defines a spacing threshold. In this case, step S12 may also include: comparing the guide hole information with the guide hole standard information by the processing device 12. In some embodiments, the routing guide hole type rule (routing via style) defines that the spacing d5 between the center CC1 of the conductive layer V1 and the center CC2 of the conductive filling material V2 shall not exceed a certain value to avoid the electrical properties of the guide hole V not meeting the design specifications. Therefore, when the spacing d5 between the center CC1 of the conductive layer V1 and the center CC2 of the conductive filling material V2 exceeds the spacing threshold, the processing device 12 may determine that the manufacturing feasibility is insufficient according to the routing guide hole type rule.

[0086] In some embodiments, the feature information may further include pin information, and the preset standard information includes pin standard information. For example, the pin information defines the number of clearance pads, and the pin standard information defines a threshold value for the number of clearance pads. In this case, step S12 may further include: comparing the pin information with the pin standard information by the processing device 12. In some embodiments, if the circuit layout does not set a clearance pad between the pin and the substrate, the pin will be directly connected to the voltage plane, resulting in functional failure. Therefore, when the pin information does not define sufficient clearance pads at the location of the pin, the processing device 12 may determine that the manufacturing feasibility is insufficient.

[0087] In the above, some possible embodiments of the characteristic information have been provided, but the present disclosure is not limited thereto. For those skilled in the art, various design specifications that need to be followed by the circuit layout of the printed circuit board can be used as characteristic information to determine the manufacturing feasibility. For example, the design specifications may also include short-circuitrules, SMD to corner rules, and other suitable specifications, but the present disclosure is not limited thereto.

[0088] In some embodiments, step S14 may also be replaced by the following step. The replacement step is: comparing at least one feature information with the custom standard information stored in the storage device by the processing device 12. In some cases, although the printed circuit board has met the common design specifications, it may not meet the requirements of product design. Therefore, the image analysis system and image analysis method of the present disclosure may also enable the processing device 12 to compare the feature information with the custom standard information according to the requirements of product design. Among them, the custom standard information can define various parameters similar to those mentioned above, but the present disclosure is not limited to this.

[0089] In some embodiments, the image analysis system of the present disclosure can analyze the circuit layout design before the etching process and provide modification suggestions to reduce the possibility of adverse defects or even irreparable defects in the product after etching, but the present disclosure is not limited to this.

[0090] In summary, the present disclosure can effectively avoid design errors and manufacturing cost losses caused by subsequent defect repair or defective product scrapping before the actual manufacturing of the printed circuit board by analyzing the circuit layout image information of the printed circuit board through image analysis.

[0091] Several embodiments are summarized above so that those skilled in the art can better understand the concepts of the embodiments of the present disclosure. It should be understood by those skilled in the art that other processes and structures can be designed or modified based on the embodiments of the present disclosure to achieve the same purpose and / or advantages as the embodiments introduced herein. It should also be understood by those skilled in the art that such equivalent processes and structures do not deviate from the concept and scope of the present disclosure, and can be variously changed, replaced and substituted without violating the concept and scope of the present disclosure.

Claims

1. An image analysis system, characterized in that: Include: An input device configured to receive a circuit layout image information for producing a printed circuit board; a storage device configured to store and access a preset standard information; as well as A processing device is electrically connected to the input device and the storage device, wherein the processing device is configured to generate at least one feature information according to the circuit layout image information, and the processing device is configured to compare the at least one feature information with the preset standard information to generate a feasibility analysis information.

2. The image analysis system according to claim 1, characterized in that The input device is further configured to receive a customized standard information, and the processing device is further configured to compare the at least one feature information with the customized standard information, thereby generating the feasibility analysis information. Wherein, the image analysis system further includes an output device electrically connected to the processing device, and the output device is configured to output the feasibility analysis information to an external device or display the feasibility analysis information.

3. The image analysis system according to claim 1, wherein: The processing device is configured to generate the at least one feature information according to the full-page image of the circuit layout image information.

4. The image analysis system according to claim 1, wherein: The image analysis system analyzes the circuit layout design of the printed circuit board before the etching process.

5. The image analysis system according to claim 1, wherein: The at least one characteristic information includes a line bending angle information, and the preset standard information includes a line bending angle standard information, Wherein, the processing device is configured to compare the line bending angle information with the line bending angle standard information, and generate the feasibility analysis information according to the comparison result; or The at least one characteristic information includes a line location information, and the preset standard information includes a line location standard information, Wherein, the processing device is configured to compare the line location information with the line location standard information, and generate the feasibility analysis information according to the comparison result.

6. The image analysis system according to claim 1, wherein: The at least one characteristic information includes a spacer spacing information, and the preset standard information includes a spacer spacing standard information, Wherein, the processing device is configured to compare the shim spacing information with the shim spacing standard information, and generate the feasibility analysis information according to the comparison result; or The at least one characteristic information includes heat dissipation copper bar information, and the preset standard information includes heat dissipation copper bar standard information, Wherein, the processing device is configured to compare the heat dissipation copper bar information with the heat dissipation copper bar standard information, and generate the feasibility analysis information according to the comparison result.

7. The image analysis system according to claim 1, wherein: The at least one feature information includes a guide hole information, and the preset standard information includes a guide hole standard information, Wherein, the processing device is configured to compare the guide hole information with the guide hole standard information, and generate the feasibility analysis information according to the comparison result; or The at least one characteristic information includes a pin information, and the preset standard information includes a pin standard information, Wherein, the processing device is configured to compare the pin information with the pin standard information, and generate the feasibility analysis information according to the comparison result.

8. An image analysis method, characterized in that: The following steps are involved: Receiving a circuit layout image information for producing a printed circuit board through an input device; Generate at least one feature information according to the circuit layout image information by a processing device; as well as The processing device compares the at least one characteristic information with a preset standard information stored in a storage device, thereby generating a feasibility analysis information.

9. The image analysis method according to claim 8, characterized in that: The image analysis method further comprises the following steps: Receiving a customized standard message through the input device; Comparing the at least one feature information with the customized standard information by the processing device, thereby generating the feasibility analysis information; and The feasibility analysis information is output to an external device or displayed through an output device.

10. The image analysis method according to claim 8, characterized in that: The processing device generates the at least one feature information according to the full-page image of the circuit layout image information.

11. The image analysis method according to claim 8, characterized in that: The feasibility analysis information generated by the processing device is performed on the circuit layout design before the etching process of the printed circuit board.

12. The image analysis method according to claim 8, characterized in that: The at least one characteristic information includes a line bending angle information, and the preset standard information includes a line bending angle standard information, wherein the step of comparing the at least one characteristic information with the preset standard information includes: comparing the line bending angle information with the line bending angle standard information by the processing device; and Generate the feasibility analysis information according to the comparison result by the processing device; or The at least one feature information includes a line location information, and the preset standard information includes a line location standard information, wherein the analysis method further includes: comparing the line location information with the line location standard information by the processing device; and The feasibility analysis information is generated by the processing device according to the comparison result.

13. The image analysis method according to claim 8, characterized in that: The at least one characteristic information includes a spacer spacing information, and the preset standard information includes a spacer spacing standard information, wherein the step of comparing the at least one characteristic information with the preset standard information includes: comparing the shim spacing information with the shim spacing standard information by the processing device; and Generate the feasibility analysis information according to the comparison result by the processing device; or The at least one characteristic information includes heat dissipation copper bar information, and the preset standard information includes heat dissipation copper bar standard information, wherein the step of comparing the at least one characteristic information with the preset standard information includes: Comparing the heat dissipation copper bar information with the heat dissipation copper bar standard information by the processing device; and The feasibility analysis information is generated by the processing device according to the comparison result.

14. The image analysis method according to claim 8, characterized in that: The at least one feature information includes a guide hole information, and the preset standard information includes a guide hole standard information, wherein the step of comparing the at least one feature information with the preset standard information includes: Comparing the guide hole information with the guide hole standard information by the processing device; and Generate the feasibility analysis information according to the comparison result by the processing device; or The at least one characteristic information includes a pin information, and the preset standard information includes a pin standard information, wherein the step of comparing the at least one characteristic information with the preset standard information includes: Comparing the pin information with the pin standard information by the processing device; and The feasibility analysis information is generated by the processing device according to the comparison result.

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