Refresh protection circuit and memory

Abstract

The embodiment of the invention relates to the field of semiconductor circuit design, in particular to a refresh protection circuit and a memory, and the refresh protection circuit comprises a sampling circuit which obtains a statistical address based on activation address sampling; the address processing circuit judges whether the addresses stored in the plurality of address registers comprise statistical addresses, and if the addresses stored in the plurality of address registers comprise the statistical addresses, the count value of the address counter corresponding to the address register storing the statistical addresses is + 1; if the statistical address is not included and an idle address register exists, storing the statistical address into the idle address register; if the statistical address is not included and the idle address register does not exist, generating an address replacement indication signal; the replacement circuit generates a replacement probability based on the count value of the address counter with the minimum count value, judges whether the address replacement indication signal meets the replacement probability or not, and replaces the address stored in the address register corresponding to the address counter with the minimum count value with the statistical address when the address replacement indication signal meets the replacement probability.

Description

Technical Field

[0001] The disclosed embodiments relate to the field of semiconductor circuit design, and in particular to a refresh protection circuit and a memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) stores data in a structure where one transistor is connected to one storage cell (1T1C), where the transistor is controlled by a word line (WL). When the transistor is turned on, the charge in the storage cell is shared with the charge of the bit line (BL) to read data from or write data to the target storage cell.

[0003] Frequent activation of word lines will cause charge loss in adjacent storage cells, which may cause errors in the data stored in the adjacent storage cells. For the above problem, the refresh cycle is usually used as a time unit to supplement the storage cells adjacent to the word line address that is activated the most times in a refresh cycle, thereby avoiding errors in the data stored in the memory. Summary of the invention

[0004] The embodiments of the present disclosure provide a refresh protection circuit and a memory, which are at least helpful in improving the problem of charge loss in adjacent memory cells caused by frequent activation of word lines.

[0005] On the one hand, an embodiment of the present disclosure provides a refresh protection circuit, including: a sampling circuit, configured to obtain a statistical address based on activation address sampling; an address processing circuit, including: a plurality of address registers and a plurality of address counters, wherein the plurality of address registers correspond to the plurality of address counters one by one; the address processing circuit is configured to determine whether the addresses stored in the plurality of address registers include a statistical address, and if the statistical address is included, the count value of the address counter corresponding to the address register storing the statistical address is increased by 1; if the statistical address is not included and there is an idle address register, the statistical address is stored in the idle address register, and the address counter corresponding to the address register storing the statistical address is set to 1; if the statistical address is not included and there is no idle address register, The address processing circuit is further configured to compare the count values ​​of multiple address counters to obtain the statistical address stored in the address register corresponding to the address counter with the largest count value, and obtain the count value of the address counter with the smallest count value; the replacement circuit is configured to generate a replacement probability based on the count value of the address counter with the smallest count value, and determine whether the address replacement indication signal satisfies the replacement probability. When the address replacement indication signal satisfies the replacement probability, the address stored in the address register corresponding to the address counter with the smallest count value is replaced with the statistical address; the storage circuit is used to store the statistical address stored in the address register corresponding to the address counter with the largest count value, and is configured to output the statistical address based on the refresh signal.

[0006] For the refresh protection circuit provided in this embodiment, since the address processing circuit includes the storage address replacement logic, even if the number of address registers in the address processing circuit is set to be small, the comprehensiveness of the statistics of all statistical addresses can still be guaranteed, which is at least conducive to improving the problem of charge loss in adjacent storage cells caused by frequent opening of word lines, and does not occupy too much of the memory layout area.

[0007] In some embodiments, a replacement circuit includes: a setting subcircuit configured to generate a replacement probability based on the count value of the address counter with the smallest count value; a replacement subcircuit configured to determine whether the address change indication signal satisfies the replacement probability, and when the address change indication signal satisfies the replacement probability, the address stored in the address register corresponding to the address counter with the smallest count value is replaced with a statistical address.

[0008] In some embodiments, the setting subcircuit is configured to generate the replacement probability based on the inverse of the count value+1 of the address counter having the smallest count value.

[0009] In some embodiments, the replacement circuit includes: a statistical subcircuit for receiving an address replacement indication signal, configured to count the number of address replacement indication signals to generate a statistical count value; a first signal generator, configured to generate a first preset value with an adjustable value, wherein the first preset value is adjusted based on the count value of the address counter with the smallest count value; a judgment subcircuit, connecting the statistical subcircuit and the first signal generator, configured to generate an indication signal when the size of the statistical count value is the same as the size of the first preset value, wherein the statistical subcircuit resets the statistical count value based on the indication signal, and when the indication signal is valid, the first signal generator adjusts the size of the first preset value based on the size of the count value of the address counter with the smallest current count value; a replacement subcircuit, configured to replace the address stored in the address register corresponding to the address counter with the smallest count value with the statistical address based on the indication signal.

[0010] In some embodiments, the first signal generator is configured based on an N-stage linear feedback shift register, and the linear feedback shift register shifts based on the indication signal.

[0011] In some embodiments, the number of access stages of the linear feedback shift register constituting the first signal generator is adjusted based on the count value of the address counter having the smallest count value.

[0012] In some embodiments, N is 3.

[0013] In some embodiments, the number of data generated by the linear feedback shift register is greater than the count value of the address counter with the smallest count value.

[0014] In some embodiments, an address processing circuit includes: multiple address registers and multiple address counters; a processing sub-circuit connected to the multiple address counters and the multiple address registers, configured to determine whether the addresses stored in the multiple address registers include a statistical address, and if so, the count value of the address counter corresponding to the address register storing the statistical address is +1; if the statistical address is not included and there is an idle address register, the statistical address is stored in the idle address register, and the address counter corresponding to the address register storing the statistical address is set to 1; if the statistical address is not included and there is no idle address register, an address change indication signal is generated; a comparison sub-circuit connected to the multiple address counters and the multiple address registers, configured to compare the count values ​​of the multiple address counters to obtain the statistical address stored in the address register corresponding to the address counter with the largest count value, and obtain the count value of the address counter with the smallest count value.

[0015] In some embodiments, the sampling circuit is configured to be driven based on an activation command and to generate a statistical address using an activation address corresponding to the activation command.

[0016] In some embodiments, the sampling circuit includes: a sampling counter for receiving an activation command, configured to count based on the activation command to generate an activation count value; a second signal generator, configured to generate a second preset value with an adjustable value; a sampling processor, configured to receive the second preset value, the activation count value and the activation address corresponding to the activation command, configured to generate a statistical address based on the activation address corresponding to the activation command when the size of the activation count value is the same as the size of the second preset value; wherein, when the size of the activation count value is the same as the size of the second preset value, the second signal generator adjusts the size of the second preset value, and the sampling counter resets the activation count value.

[0017] In some embodiments, the second signal generator is configured based on a linear feedback shift register of M stages, and when the activation count value is the same as the second preset value, the linear feedback shift register shifts, M≥2.

[0018] On the other hand, the embodiments of the present disclosure further provide a memory including the refresh protection circuit provided by the above embodiments, which is at least helpful in improving the problem of charge loss in adjacent memory cells caused by frequent activation of word lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, which do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, and the figures in the drawings do not constitute a scale limitation unless otherwise stated. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 A schematic diagram of the structure of a refresh protection circuit provided in one embodiment of the present disclosure;

[0021] Figure 2 A schematic diagram of the structure of an address processing circuit provided in one embodiment of the present disclosure;

[0022] Figure 3 A schematic diagram of the working principle of an address processing circuit provided in an embodiment of the present disclosure;

[0023] Figure 4 A structural schematic diagram of a replacement circuit provided by an embodiment of the present disclosure;

[0024] Figure 5 A schematic diagram of the structure of another replacement circuit provided in an embodiment of the present disclosure;

[0025] Figure 6 A schematic diagram of the structure of a linear feedback shift register provided in one embodiment of the present disclosure;

[0026] Figure 7 A schematic diagram of the jump of the output result of a 3-stage linear feedback shift register provided by an embodiment of the present disclosure;

[0027] Figure 8 A schematic diagram of the structure of a sampling circuit provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] As known from the background art, frequent activation of word lines may lead to charge loss in adjacent memory cells, which may cause errors in data stored in the adjacent memory cells.

[0029] The commonly used Row Hammer protection method currently is mainly to count the number of times the word line address is activated in a refresh cycle, and refresh the adjacent addresses of the word line addresses that are activated more times, so as to avoid errors in the data stored in the adjacent storage cells of the frequently activated word lines. However, the Row Hammer protection method based on this method requires the use of a large number of counters to count the different activated word line addresses. A large number of counters will occupy a large amount of memory layout resources, which is unacceptable for DRAM.

[0030] The embodiments of the present disclosure provide a refresh protection circuit, which is at least helpful in improving the problem of charge loss in adjacent storage cells caused by frequent activation of word lines.

[0031] Figure 1 A schematic diagram of the structure of the refresh protection circuit provided in this embodiment, Figure 2 A schematic diagram of the structure of the address processing circuit provided in this embodiment, Figure 3 A schematic diagram of the working principle of the address processing circuit provided in this embodiment, Figure 4 A schematic diagram of a replacement circuit provided in this embodiment, Figure 5 A schematic diagram of another replacement circuit provided in this embodiment, Figure 6 A schematic diagram of the structure of the linear feedback shift register provided in this embodiment, Figure 7 A schematic diagram of the jump of the output result of the three-stage linear feedback shift register provided in this embodiment, Figure 8 This is a schematic diagram of the structure of the sampling circuit provided in this embodiment. The refresh protection circuit provided in the embodiment of the present disclosure will be described in detail below in conjunction with the accompanying drawings.

[0032] refer to Figure 1 The refresh protection circuit includes: a sampling circuit 101, an address processing circuit 102, a replacement circuit 103 and a storage circuit 104.

[0033] The sampling circuit 101 is configured to obtain a statistical address based on active address sampling, wherein the active address is the address corresponding to the word line turned on by the memory, and the statistical address is obtained by sampling the active address by the sampling circuit 101 .

[0034] refer to Figure 1 and Figure 2 The address processing circuit 102 includes: a plurality of address registers 210 and a plurality of address counters 220, wherein the plurality of address registers 210 correspond one to one with the plurality of address counters 220; the address processing circuit 102 is configured to determine whether the addresses stored in the plurality of address registers 210 include a statistical address, and if so, the count value of the address counter 220 corresponding to the address register 210 storing the statistical address is increased by 1; if the statistical address is not included and there is an idle address register 210, the statistical address is stored in the idle address register 210, and the address counter 220 corresponding to the address register 210 storing the statistical address is set to 1; if the statistical address is not included and there is no idle address register 210, an address replacement indication signal is generated.

[0035] Specifically, the address processing circuit 102 has three logics for storing statistical addresses. First, if the current statistical address is already included in the multiple address registers 210, the address processing circuit 102 has already started counting the current statistical address. At this time, the count value of the address counter 220 corresponding to the address register 210 storing the current statistical address is directly increased by 1, that is, the counting of the current statistical address is completed. Second, if the current statistical address is not included in the multiple address registers 210, the address processing circuit 102 has not started counting the current statistical address. At this time, if there are still idle address registers 210 in the address processing circuit 102, the idle address register 210 is used to store the current statistical address, and the address counter 220 corresponding to the address register 210 storing the current statistical address is set to 1. Third, if the current statistical address is not included in the multiple address registers 210 and there is no idle address register in the address processing circuit 102, the address processing circuit 102 generates an address replacement indication signal to allow the subsequent circuit to determine whether to replace the address stored in the address register 210.

[0036] For the working logic of the address processing circuit 102, please refer to Figure 3 Examples 1 to 3: It should be noted that Examples 1 to 3 are provided by taking the address processing circuit 102 including 5 address registers 210 and 5 address counters 220 as examples, and do not constitute a limitation on the number of address registers 210 and address counters 220 in the address processing circuit 102.

[0037] For Example 1, assume that the five address registers 210 are used to store Address1, Address2, Address3, Address4 and Address5 respectively, and the count value of the address counter 220 corresponding to Address1 is 15, the count value of the address counter 220 corresponding to Address2 is 7, the count value of the address counter 220 corresponding to Address3 is 12, the count value of the address counter 220 corresponding to Address4 is 1, and the count value of the address counter 220 corresponding to Address5 is 3; if the statistical address sampled and obtained by the sampling circuit 101 at this time is Address1, the count value of the address counter 220 corresponding to Address1 is +1, changed to 16, and the count values ​​of the other address counters 220 remain unchanged.

[0038] For Example 2, it is assumed that the five address registers 210 are only used to store Address1, Address2 and Address3, that is, there are two idle address registers 210 among the five address registers 210, and the count value of the address counter 220 corresponding to Address1 is 15, the count value of the address counter 220 corresponding to Address2 is 7, and the count value of the address counter 220 corresponding to Address3 is 12; if the statistical address sampled and obtained by the sampling circuit 101 at this time is Address8, then Address8 is stored in the idle address register 210, and the count value of the address counter 220 corresponding to the address register 210 storing Address8 is set to 1.

[0039] For Example 3, assume that the five address registers 210 are used to store Address1, Address2, Address3, Address4 and Address5 respectively, and the count value of the address counter 220 corresponding to Address1 is 15, the count value of the address counter 220 corresponding to Address2 is 7, the count value of the address counter 220 corresponding to Address3 is 12, the count value of the address counter 220 corresponding to Address4 is 1, and the count value of the address counter 220 corresponding to Address5 is 3; if the statistical address sampled by the sampling circuit 101 is Address8 at this time, and the storage space of the address register 210 is full at this time, it is determined whether to replace the statistical address, that is, to generate an address change indication signal.

[0040] Since the address processing circuit 102 in this embodiment also involves the replacement of the address stored in the address register 210, even if the number of address registers 210 and address counters 220 is small, the activation status of all statistical addresses can still be fully monitored, which is at least helpful to improve the problem of charge loss in adjacent storage cells caused by frequent activation of word lines, and does not occupy too much memory layout area.

[0041] Continue to refer Figure 1 The replacement circuit 103 is configured to generate a replacement probability based on the count value of the address counter 220 with the smallest count value, and determine whether the address replacement indication signal satisfies the replacement probability. When the address replacement indication signal satisfies the replacement probability, the address stored in the address register 210 corresponding to the address counter 220 with the smallest count value is replaced with a statistical address.

[0042] Based on the foregoing, it can be known that when the address processing circuit 102 generates an address replacement indication signal, it is necessary to determine whether to perform statistical address replacement. For statistical address replacement, a replacement probability is generated according to the count value of the address counter 220 with the smallest count value, and based on the replacement probability, it is determined whether the address stored in the address register 210 corresponding to the address counter 220 with the smallest count value needs to be replaced.

[0043] In some embodiments, the smaller the count value, the greater the generated replacement probability, and the larger the count value, the smaller the generated replacement probability. The reason is that: the smaller the count value, the less frequent the occurrence of the stored statistical address is, and a higher replacement probability is set to replace the statistical address, and the statistical address is replaced with a high probability to ensure the comprehensiveness of counting all statistical addresses, and the count value of the address counter 220 corresponding to the address register 210 remains unchanged after the replacement; similarly, the larger the count value, the higher the probability of occurrence of the stored statistical address, and a lower replacement probability is set to replace the statistical address, and the continued counting of the statistical address is maintained with a high probability to ensure the accuracy of counting all statistical addresses, and the count value of the address counter 220 corresponding to the address register 210 remains unchanged after the replacement.

[0044] refer to Figure 1 and Figure 2 The address processing circuit 102 is further configured to compare the count values ​​of the plurality of address counters 220 to obtain the statistical address stored in the address register 210 corresponding to the address counter 220 with the largest count value, and to obtain the count value of the address counter with the smallest count value.

[0045] The storage circuit 104 is used to store the statistical address stored in the address register 210 corresponding to the address counter 220 with the largest count value. The storage circuit 104 is configured to output the statistical address based on the refresh signal.

[0046] Specifically, the address processing circuit 102 compares the count values ​​of the address counter 220 to obtain the statistical address stored in the address register 210 corresponding to the address counter 220 with the largest count value. This statistical address is stored in the storage circuit 104, and the storage circuit 104 outputs this statistical address based on the refresh signal for the memory to perform Row Hammer protection. In addition, the address processing circuit 102 is also used to obtain the count value of the address counter with the smallest count value. The purpose of obtaining this count value is to generate the replacement probability mentioned above.

[0047] In summary, for the refresh protection circuit provided in this embodiment, since the address processing circuit 102 includes storage address replacement logic, even if the number of address registers 210 in the address processing circuit 102 is set to be small, the comprehensiveness of statistics for all statistical addresses can still be guaranteed, which is at least beneficial to improving the problem of charge loss in adjacent storage cells caused by frequent opening of word lines, and does not occupy too much memory layout area.

[0048] For the address processing circuit 102, in one example, refer to Figure 2 The address processing circuit 102 includes: multiple address registers 210 and multiple address counters 220; a processing sub-circuit 230, which is connected to the multiple address counters 220 and the multiple address registers 210, and the processing sub-circuit 230 is configured to determine whether the addresses stored in the multiple address registers 210 include statistical addresses. If the statistical addresses are included, the count value of the address counter 230 corresponding to the address register 210 storing the statistical addresses is +1; if the statistical addresses are not included and there is an idle address register 210, the statistical addresses are stored in the idle address register 210, and the address counter 220 corresponding to the address register 210 storing the statistical addresses is set to 1; if the statistical addresses are not included and there is no idle address register 210, an address replacement indication signal is generated. The comparison subcircuit 240 is connected to multiple address counters 220 and multiple address registers 210. The comparison subcircuit 240 is configured to compare the count values ​​of the multiple address counters 220 to obtain the statistical address stored in the address register 220 corresponding to the address counter 210 with the largest count value, and obtain the count value of the address counter 210 with the smallest count value.

[0049] As for the replacement circuit, the replacement circuit is used to determine whether the address change indication signal satisfies the replacement probability so as to determine whether the address processing circuit 102 performs statistical address replacement.

[0050] Specifically, the replacement circuit is used to determine whether the address replacement indication signal meets the replacement probability. In some embodiments, the determination can be based on a random number. For example, assuming that the replacement probability is 67.8%, a random number is generated in the range of 0 to 1000 based on the address replacement indication signal. If the random number is less than 678, the address replacement indication signal meets the replacement probability. If the random number is greater than 678, the address replacement indication signal does not meet the replacement probability. Assuming that the replacement probability is 28%, a random number is generated in the range of 0 to 1000 based on the address replacement indication signal. If the random number is less than 280, the address replacement indication signal meets the replacement probability. If the random number is greater than 280, the address replacement indication signal does not meet the replacement probability. In other embodiments, it is also possible to determine whether the address replacement indication signal meets the replacement probability by comparing a random number with a pseudo-random number.

[0051] refer to Figure 4 In some embodiments, the replacement circuit 103 includes a setting subcircuit 310 and a replacement subcircuit 320 .

[0052] The setting subcircuit 310 is configured to generate a replacement probability based on the count value of the address counter with the smallest count value. Specifically, based on the foregoing, the smaller the count value, the larger the value of the replacement probability generated by the setting subcircuit 310, and the larger the count value, the smaller the value of the replacement probability generated by the setting subcircuit 320. The replacement subcircuit 320 is configured to determine whether the address replacement indication signal satisfies the replacement probability. When the address replacement indication signal satisfies the replacement probability, the address stored in the address register 210 corresponding to the address counter 220 with the smallest count value is replaced with the current statistical address.

[0053] In some embodiments, the setting subcircuit 310 is configured to generate a replacement probability based on the inverse of the count value of the address counter 220 with the smallest count value + 1. For example, assuming that the count value of the address counter 220 with the smallest count value is 5, the replacement probability generated by the setting subcircuit 310 is 1 / 6; assuming that the count value of the address counter 220 with the smallest count value is 17, the replacement probability generated by the setting subcircuit 310 is 1 / 18; assuming that the count value of the address counter 220 with the smallest count value is 53, the replacement probability generated by the setting subcircuit 310 is 1 / 54. In this example, the method for determining whether the address replacement indication signal satisfies the replacement probability can be: based on the address replacement indication signal, a random number is generated within the count value range of 0 to the address counter 220 with the smallest count value. If the generated random number is equal to the count value of the address counter 220 with the smallest count value, the address replacement indication signal satisfies the replacement probability.

[0054] refer to Figure 5In some embodiments, the replacement circuit 103 includes: a statistical subcircuit 410 , a first signal generator 420 , a determination subcircuit 430 , and a replacement subcircuit 440 .

[0055] The statistical subcircuit 410 is used to receive the address change indication signal and is configured to count the number of address change indication signals to generate a statistical count value. Specifically, the initial value of the statistical count value is 0, and the statistical subcircuit 410 generates a statistical count value +1 each time it receives an address change indication signal.

[0056] The first signal generator 420 is configured to generate a first preset value whose value is adjustable, and the first preset value is adjusted based on the count value of the address counter 220 with the smallest count value.

[0057] The judgment subcircuit 430 is connected to the statistical subcircuit 410 and the first signal generator 420. The judgment subcircuit 430 is configured to generate an indication signal when the size of the statistical count value is the same as the size of the first preset value, wherein the statistical subcircuit 410 resets the statistical count value based on the indication signal, and when the indication signal is valid, the first signal generator 430 adjusts the size of the first preset value based on the size of the count value of the address counter 220 with the smallest current count value.

[0058] The replacement sub-circuit 440 is configured to replace the address stored in the address register 210 corresponding to the address counter 220 with the smallest count value with the current statistical address based on the indication signal.

[0059] Specifically, the judgment subcircuit 430 is used to judge whether the statistical count value is the same as the first preset value, that is, whether the number of received address change indication signals is the same as the first preset value. If they are the same, an indication signal is generated to indicate that the address stored in the address register 210 corresponding to the address counter 220 with the smallest count value is replaced as the current statistical address, that is, by selecting one from multiple address change indication signals to replace the statistical address, whether the address change indication signal meets the replacement probability condition.

[0060] For the judgment subcircuit 430, after the judgment subcircuit 430 generates an indication signal, the statistical subcircuit 410 resets the statistical count value based on the indication signal to start executing the next round of judgment. The judgment result is used to determine whether the address stored in the address register 210 corresponding to the address counter 220 with the smallest subsequent count value needs to be replaced with the statistical address; the first signal generator 430 readjusts the size of the first preset value based on the indication signal to achieve randomness in the selection of the address replacement indication signal and improve the reliability of Row Hammer protection.

[0061] In some embodiments, reference Figure 6 and Figure 7The first signal generator is configured based on an N-stage linear feedback shift register, and the linear feedback shift register shifts based on an indication signal.

[0062] refer to Figure 6 , gn is the feedback coefficient, which can only be 0 or 1. When it is 0, it indicates that the feedback path does not exist, and when it is 1, it indicates that the feedback path exists. The feedback coefficient gn determines the algorithm for generating random numbers, which is expressed by the feedback function, that is, y = a0*x^0+a1*x^1+a2*x^2... The linear feedback function is called a linear shift feedback sequence, otherwise it is called a nonlinear feedback shift sequence. Q1, Q2, Q3...Qn are the outputs of the linear feedback shift register, M(x) is the input codeword polynomial, such as M(x) = x^4+x^1+1, indicating that the input sequence of the input end is 11001. Similarly, the structure of the linear feedback shift register can also be expressed as a polynomial G(x), called a generating polynomial: G(x) = gn*x^n+...+g1*x^1+g0.

[0063] It should be noted that the result produced by the N-stage linear feedback shift register is 2 N -1 cycle jump result, for example, the result generated by a 3-stage linear feedback shift register is 7 cycle jump results, and the result generated by a 5-stage linear feedback shift register is 31 cycle jump results.

[0064] This embodiment is specifically described by taking N=3 as an example. Figure 7 In this example, the result generated by the three-stage linear feedback shift register is 111→101→001→010→100→011→110→111. The linear feedback shift register jumps based on the indication signal, that is, each time the linear feedback shift register receives an indication signal, the output result shifts one position according to 111→101→001→010→100→011→110→111.

[0065] For the sequence when N=3, it can be regarded as a cyclic sequence of 7-5-1-2-4-3-6, in which each first preset value generated can generate an indication signal, then the number of address replacement indication signals that need to be received to complete one cycle of this cyclic sequence is 7+5+1+2+4+3+6=28, and 7 indication signals are generated, that is, the address replacement indication signal satisfies the replacement probability of 1 / 4, which can be regarded as a replacement probability of 1 / 4. Based on the foregoing, it can be seen that the smaller the count value of the address counter 220 with the smallest count value, the greater the replacement probability needs to be set. In some embodiments, the access level of the linear feedback shift register of the first signal generator 420 is adjusted based on the count value of the address counter 220 with the smallest count value.

[0066] For example, for a linear feedback shift register with N=4, it can be regarded as a 15-bit random cyclic sequence of 1 to 15, in which each first preset value generated can generate an indication signal. Then, the number of address replacement signals that need to be received to complete one cycle of this cyclic sequence is 15! = 120, and 15 indication signals are generated, that is, the address replacement indication signal satisfies the replacement probability of 1 / 8, which can be regarded as a replacement probability of 1 / 8.

[0067] For example, for a linear feedback shift register with N=5, it can be regarded as a 31-bit random cyclic sequence of 1 to 31, in which each first preset value generated can generate an indication signal. Then, the number of address replacement signals that need to be received to complete one cycle of this cyclic sequence is 31! = 496, and 31 indication signals are generated, that is, the address replacement indication signal satisfies the replacement probability of 1 / 16, which can be regarded as a replacement probability of 1 / 16.

[0068] It can be seen that the larger the access level of the linear feedback shift register is, the lower the replacement probability is, that is, the larger the count value of the address counter 220 with the smallest count value is, the larger the access level of the linear feedback shift register of the first signal generator 420 is.

[0069] Further, in some embodiments, the number of data generated by the linear feedback shift register is greater than the count value of the address counter 220 with the smallest count value. For example, a 3-stage linear feedback shift register can generate 7 data, which is suitable for the address counter 220 when the minimum count value is 1 to 6, a 4-stage linear feedback shift register can generate 15 data, which is suitable for the address counter 220 when the minimum count value is 7 to 14, and a 5-stage linear feedback shift register can generate 31 data, which is suitable for the address counter 220 when the minimum count value is 15 to 30. By setting a more conservative replacement probability, the protection accuracy of the refresh protection circuit can be further improved.

[0070] For the sampling circuit 101, the sampling circuit 101 can be set to obtain statistical addresses based on each or a preset number of activation addresses; in one example, if the sampling circuit 101 is set to obtain statistical addresses based on each activation address, based on this sampling method, the number of statistical addresses obtained is accurate, and the memory Row Hammer protection effect is good; in another example, if the sampling circuit 101 is set to obtain statistical addresses based on a preset number of activation addresses, based on this sampling method, the workload of the sampling circuit 101 is small, and the corresponding power consumption is also small. Among them, the preset number can be set to a natural number such as 5, 6, 7, etc., and the larger the preset number is set, the smaller the workload of the sampling circuit 101, and the smaller the preset number is set, the better the memory Row Hammer protection effect.

[0071] In some embodiments, reference Figure 8 The sampling circuit 101 includes: a sampling counter 110 , a second signal generator 120 and a sampling processor 130 .

[0072] The sampling counter 110 is used to receive an activation command and is configured to count based on the activation command to generate an activation count value. Specifically, the initial value of the activation count value is 0, and the activation count value is accumulated by 1 each time the sampling counter 110 receives an activation command.

[0073] The second signal generator 120 is configured to generate a second preset value with an adjustable value. Specifically, the second signal generator 120 is used to provide a second preset value, the size of which can be adjusted by a staff member or a user. The size of the second preset value, i.e., the number of the preset values, is used to determine the sampling interval of the sampling circuit 101, so that the sampling of the sampling circuit 101 has flexibility.

[0074] The sampling processor 130 is used to receive the second preset value, the activation count value and the activation address corresponding to the activation command. The sampling processor 130 is configured to generate a statistical address based on the activation address corresponding to the activation command when the size of the activation count value is the same as the size of the second preset value.

[0075] When the activation count value is the same as the second preset value, that is, the sampling circuit 101 completes one sampling to obtain a statistical address, the sampling counter 110 resets the activation count value so that the sampling circuit 101 completes the next sampling.

[0076] In some embodiments, when the size of the activation count value is the same as the size of the second preset value, the second signal generator 120 adjusts the size of the second preset value and the sampling counter 110 resets the activation count value; in this example, the statistical address sampled and obtained by the sampling circuit 101 is based on different second preset values, further improving the sampling flexibility of the sampling circuit 101.

[0077] It should be noted that, in some embodiments, the sampling circuit 101 is configured to be driven based on an activation command, and to generate a statistical address using an activation address corresponding to the activation command, for example Figure 8 Example: In other embodiments, the sampling circuit 101 can be directly configured to be driven based on the activation address, and directly generate the statistical address based on the activation address. The activation command is the Active signal of the memory, and the activation address corresponding to the activation command is the address signal of the word line to be turned on by the Active signal. The difference between the two is that the sampling circuit 101 is driven based on the Active signal or based on the address signal of the word line to be turned on by the Active signal.

[0078] In some embodiments, the second signal generator 120 is configured based on a linear feedback shift register of M stages, and when the activation count value is the same as the second preset value, the linear feedback shift register shifts, M≥2.

[0079] It should be noted that the working principle of the linear feedback shift register can be referred to the previous description and will not be repeated in this embodiment; when the size of the activation count value is the same as the size of the second preset value, the linear feedback shift register shifts to change the size of the generated second preset value, thereby achieving a pseudo-random change of the second preset value, so that the sampling of the sampling circuit 101 has randomness, and the protection result of the refresh protection circuit is more reliable.

[0080] In some embodiments, the second signal generator can also be directly set based on the random number generator, that is, the random number generated by the random number generator is directly used as the second preset value, and when the size of the activation count value is the same as the size of the second preset value, the random number generator regenerates the random number; the second signal generator 120 set by the random number generator realizes the random change of the second preset value, so that the sampling of the sampling circuit 101 has randomness, and the protection result of the refresh protection circuit is more reliable.

[0081] For the refresh protection circuit provided in this embodiment, since the address processing circuit 102 includes storage address replacement logic, even if the number of address registers 210 in the address processing circuit 102 is set to be small, the comprehensiveness of statistics for all statistical addresses can still be guaranteed, which is at least conducive to improving the problem of charge loss in adjacent storage cells caused by frequent opening of word lines, and does not occupy too much memory layout area.

[0082] It should be noted that the features disclosed in the refresh protection circuit provided in the above embodiments can be arbitrarily combined without conflict to obtain a new refresh protection circuit embodiment.

[0083] Another embodiment of the present disclosure provides a memory including the refresh protection circuit provided by the above embodiment, which is at least helpful in improving the problem of charge loss in adjacent memory cells caused by frequent activation of word lines.

[0084] The memory may be a storage unit or device based on a semiconductor device or component. For example, the memory device may be a volatile memory, such as a dynamic random access memory DRAM, a synchronous dynamic random access memory SDRAM, a double data rate synchronous dynamic random access memory DDR SDRAM, a low power double data rate synchronous dynamic random access memory LPDDR SDRAM, a graphic double data rate synchronous dynamic random access memory GDDR SDRAM, a double data rate type dual synchronous dynamic random access memory DDR2 SDRAM, a double data rate type triple synchronous dynamic random access memory DDR3 SDRAM, a double data rate fourth generation synchronous dynamic random access memory DDR4SDRAM, a thyristor random access memory TRAM, etc.; or may be a non-volatile memory, such as a phase change random access memory PRAM, a magnetic random access memory MRAM, a resistive random access memory RRAM, etc.

[0085] From the above analysis, it can be seen that since the address processing circuit includes the storage address replacement logic, even if the number of address registers in the address processing circuit is set to be small, the comprehensiveness of the statistics of all statistical addresses can still be guaranteed, which is at least conducive to improving the problem of charge loss in adjacent storage cells caused by frequent opening of word lines, and does not occupy too much memory layout area.

[0086] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A refresh protection circuit, characterized in that: include: The sampling circuit is configured to obtain a statistical address based on the activation address sampling; The address processing circuit comprises: a plurality of address registers and a plurality of address counters, wherein the plurality of address registers correspond to the plurality of address counters one by one; The address processing circuit is configured to determine whether the addresses stored in the plurality of address registers include the statistical address, and if the statistical address is included, then the count value of the address counter corresponding to the address register storing the statistical address is increased by 1; if the statistical address is not included and there is an idle address register, then the statistical address is stored in the idle address register, and the address counter corresponding to the address register storing the statistical address is set to 1; if the statistical address is not included and there is no idle address register, then an address replacement indication signal is generated; The address processing circuit is further configured to compare the count values ​​of the multiple address counters to obtain the statistical address stored in the address register corresponding to the address counter with the largest count value, and obtain the count value of the address counter with the smallest count value; a replacement circuit, configured to generate a replacement probability based on the count value of the address counter with the smallest count value, and determine whether the address replacement indication signal satisfies the replacement probability, and when the address replacement indication signal satisfies the replacement probability, replace the address stored in the address register corresponding to the address counter with the smallest count value with the statistical address; The storage circuit is used to store the statistical address stored in the address register corresponding to the address counter with the largest count value, and is configured to output the statistical address based on a refresh signal.

2. The refresh protection circuit according to claim 1, characterized in that: The replacement circuit comprises: A setting subcircuit is configured to generate a replacement probability based on the count value of the address counter with the smallest count value; The replacement subcircuit is configured to determine whether the address replacement indication signal satisfies the replacement probability, and when the address replacement indication signal satisfies the replacement probability, replace the address stored in the address register corresponding to the address counter with the smallest count value with the statistical address.

3. The refresh protection circuit according to claim 2, characterized in that: The setting sub-circuit is configured to generate the replacement probability based on a reciprocal of a count value+1 of the address counter having the smallest count value.

4. The refresh protection circuit according to claim 1, characterized in that: The replacement circuit comprises: a statistical subcircuit, used for receiving the address change indication signal, and configured to count the number of the address change indication signals to generate a statistical count value; A first signal generator is configured to generate a first preset value whose value is adjustable, wherein the first preset value is adjusted based on the count value of the address counter with the smallest count value; a judgment subcircuit, connected to the statistical subcircuit and the first signal generator, and configured to generate an indication signal when the size of the statistical count value is the same as the size of the first preset value, wherein the statistical subcircuit resets the statistical count value based on the indication signal, and when the indication signal is valid, the first signal generator adjusts the size of the first preset value based on the size of the count value of the address counter with the smallest current count value; The replacement sub-circuit is configured to replace the address stored in the address register corresponding to the address counter with the smallest count value with the statistical address based on the indication signal.

5. The refresh protection circuit according to claim 4, characterized in that: The first signal generator is arranged based on an N-stage linear feedback shift register, and the linear feedback shift register shifts based on an indication signal.

6. The refresh protection circuit according to claim 5, characterized in that: The number of access stages of the linear feedback shift register constituting the first signal generator is adjusted based on the count value of the address counter having the smallest count value.

7. The refresh protection circuit according to claim 6, characterized in that: The N is 3.

8. The refresh protection circuit according to claim 6, characterized in that: The number of data generated by the linear feedback shift register is greater than the count value of the address counter with the smallest count value.

9. The refresh protection circuit according to claim 1, characterized in that: The address processing circuit comprises: the plurality of address registers and the plurality of address counters; a processing subcircuit, connected to the plurality of address counters and the plurality of address registers, configured to determine whether the addresses stored in the plurality of address registers include the statistical address, and if so, to increase the count value of the address counter corresponding to the address register storing the statistical address by 1; if the statistical address is not included and there is an idle address register, to store the statistical address in the idle address register, and to set the address counter corresponding to the address register storing the statistical address to 1; and if the statistical address is not included and there is no idle address register, to generate an address replacement indication signal; A comparison subcircuit is connected to the multiple address counters and the multiple address registers, and is configured to compare the count values ​​of the multiple address counters to obtain the statistical address stored in the address register corresponding to the address counter with the largest count value, and to obtain the count value of the address counter with the smallest count value.

10. The refresh protection circuit according to any one of claims 1 to 9, characterized in that: The sampling circuit is configured to be driven based on an activation command and to generate the statistical address using the activation address corresponding to the activation command.

11. The refresh protection circuit according to any one of claims 1 to 9, characterized in that: The sampling circuit comprises: a sampling counter, used for receiving an activation command, and configured to count based on the activation command to generate an activation count value; A second signal generator is configured to generate a second preset value whose value is adjustable; a sampling processor, configured to receive the second preset value, the activation count value, and the activation address corresponding to the activation command, and configured to generate the statistical address based on the activation address corresponding to the activation command when the activation count value is the same as the second preset value; When the size of the activation count value is the same as the size of the second preset value, the second signal generator adjusts the size of the second preset value, and the sampling counter resets the activation count value.

12. The refresh protection circuit according to claim 11, characterized in that: The second signal generator is configured based on an M-stage linear feedback shift register, and when the activation count value is the same as the second preset value, the linear feedback shift register shifts, M≥2.

13. A memory, characterized in that: The refresh protection circuit comprises the refresh protection circuit as claimed in any one of claims 1 to 12.

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