Memory device supporting efficient erase operation and operating method thereof

Abstract

The present disclosure provides a memory device supporting efficient erase operation and an operating method thereof. The memory device includes a memory block having a plurality of string groups; and a controller configured to repeat one or more erase cycles, each erase cycle including a pulse application interval and a verify interval; a determination unit configured to determine a plurality of string groups as one of a passing string group and a failing string group in a verification interval of a previous erase cycle; and a controller configured to apply a first voltage to the drain selection line corresponding to the failed string group from a start time to a first time in a pulse application interval of a subsequent erase cycle following the previous erase cycle, a first voltage is applied to the drain selection line corresponding to the passing string group from the start time to a second time earlier than the first time, and a second voltage is applied to the drain selection line corresponding to the passing string group from the second time to the first time.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0141503, filed on October 20, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to a memory system, and in particular, to a memory device supporting an efficient erase operation and an operating method of the memory device. Background Art

[0004] A memory system is a storage device implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), etc. Memory systems are divided into volatile memory devices and non-volatile memory devices. A volatile memory device is a memory device in which the data stored therein is lost when the power supply is interrupted. Representative examples of volatile memory devices include static random access memory (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), etc. A non-volatile memory device is a memory device in which the data stored therein can be retained even when the power supply is interrupted. Representative examples of non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Flash memory is mainly divided into NOR type memory and NAND type memory.

[0005] A cell of a nonvolatile memory device is an element that can perform programming and erasing (program / erase) operations. A nonvolatile memory device can perform programming and erasing operations on a cell by changing the threshold voltage of the cell when electrons move due to a strong electric field applied to a thin oxide film of the cell.

[0006] A gate-induced drain leakage (GIDL) programming method and an incremental step pulse erase (ISPE) method may be used for an erase operation for a plurality of memory cells included in a nonvolatile memory device. The GIDL programming method includes raising the potential level of a channel of a selected memory block by an erase voltage having a high level and applied to a substrate of a memory block selected as an erase target, changing a memory cell having a programmed state into a memory cell having an erased state. The ISPE method includes gradually increasing the voltage level of an erase voltage applied to a substrate of a memory block selected as an erase target. Summary of the invention

[0007] Various embodiments of the present disclosure are intended to provide a memory device and an operating method of the memory device that are capable of adjusting whether to use a gate induced drain leakage (GIDL) programming method and an incremental step pulse erase (ISPE) method to perform an erase operation for each string when performing an erase operation on a storage block having a three-dimensional structure and including a plurality of strings.

[0008] Problems to be solved by the present disclosure are not limited to the above-mentioned problems, and other unmentioned problems will be clearly understood by those skilled in the art from the following description.

[0009] Embodiments of the present disclosure include a memory device, which may include: a memory block, including K string groups connected to multiple bit lines through K drain selection lines, respectively, and connected to a common source line through K source selection lines, respectively; and a controller: configured to repeat one or more erase cycles until an erase operation on the memory block is successful, each erase cycle including a pulse application interval and a verification interval; configured to determine the K string groups as one of a passed string group and a failed string group in a verification interval of a previous erase cycle among the erase cycles; and configured to apply a first voltage to a drain selection line corresponding to a failed string group from a start time to a first time in a pulse application interval of a subsequent erase cycle after the previous erase cycle among the erase cycles, apply a first voltage to a drain selection line corresponding to a passed string group from a start time to a second time earlier than the first time, and apply a second voltage greater than the first voltage to a drain selection line corresponding to a passed string group from a second time to the first time, wherein K may be a natural number greater than or equal to 2.

[0010] In an embodiment of the present disclosure, a method for operating a memory device includes a memory block, the memory block includes K string groups connected to a plurality of bit lines through K drain selection lines, respectively, and connected to a common source line through K source selection lines, respectively. The method for operating the memory device may include: an erase operation, repeating one or more erase cycles until an erase operation on the memory block succeeds, each erase cycle including a pulse application interval and a verification interval; a determination operation, determining the K string groups as passed string groups and failed string groups in a verification interval of a previous erase cycle among the erase cycles repeated in the erase operation; One; a first application operation, in a pulse application interval of a subsequent erase cycle after a previous erase cycle, applying a first voltage to the drain selection line corresponding to the determined failed string group from a start moment to a first moment; and a second application operation, in a pulse application interval of a subsequent erase cycle, applying a first voltage to the drain selection line corresponding to the determined pass string group from a start moment to a second moment earlier than the first moment and applying a second voltage greater than the first voltage to the drain selection line corresponding to the pass string group from the second moment to the first moment, wherein K can be a natural number greater than or equal to 2.

[0011] According to the present technology, an erase operation using the GIDL program method and the ISPE method may be performed on a memory block having a three-dimensional structure and including a plurality of strings.

[0012] Specifically, according to the present technology, an erase operation using the GIDL programming method can be applied to a corresponding storage block by checking the erase state of each string in a verification interval of a previous erase cycle first performed among erase cycles repeated according to the ISPE method and selecting each string in a pulse application interval of a subsequent erase cycle performed after the previous erase cycle based on the check result.

[0013] Therefore, a phenomenon in which memory cells included in a string determined to have passed erasure are over-erased can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1A and Figure 1B is a diagram for describing a memory device according to an embodiment of the present disclosure.

[0015] Figure 2 is a diagram for describing an erase operation using an ISPE method used in a memory device according to an embodiment of the present disclosure.

[0016] Figure 3 is a diagram for describing an erase operation performed in a memory device according to an embodiment of the present disclosure.

[0017] Figure 4A and Figure 4Bis a diagram for describing other erase operations performed in the memory device according to an embodiment of the present disclosure.

[0018] Figure 5 is a diagram for describing a controller among components of a memory device according to an embodiment of the present disclosure.

[0019] Figure 6 is a flowchart for describing the sequence of an erase operation performed in a memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] Figure 1A and Figure 1B is a diagram for describing a memory device according to an embodiment of the present disclosure.

[0021] Figure 2 is a diagram for describing an erase operation using an ISPE method used in a memory device according to an embodiment of the present disclosure.

[0022] Reference Figure 1A and Figure 1B , the memory device 150 according to an embodiment of the present disclosure may include a memory cell array 201 and a controller 202 .

[0023] The memory cell array 201 may include a plurality of memory blocks, for example, MEMORY BLOCK<1:6>. Each of the memory blocks MEMORY BLOCK<1:6> may include a plurality of memory cells. One memory block may include a plurality of pages.

[0024] A memory block can be understood as a group of non-volatile memory cells from which data can be removed together by an erase operation. From a logical point of view, each of the memory blocks may include one or more pages in which non-volatile memory cells are grouped, such as storing data together during a programming operation or outputting data together during a read operation. For example, a memory block may include multiple pages. A page may include multiple non-volatile memory cells.

[0025] From a physical perspective different from a logical perspective such as a program operation or a read operation, one memory block may include a plurality of word lines. One word line may include a plurality of nonvolatile memory cells.

[0026] In this case, according to the number of bits that can be stored or represented in a nonvolatile memory cell, a word line can correspond to at least one page. For example, when a nonvolatile memory cell is a single-layer cell (SLC) storing one bit of data, a word line can correspond to one page. When a nonvolatile memory cell is a double-layer cell (DLC) storing two bits of data, a word line can correspond to two pages. When a nonvolatile memory cell is a triple-layer cell (TLC) storing three bits of data, a word line can correspond to three pages. When a nonvolatile memory cell is a quad-layer cell (QLC) storing four bits of data, a word line can correspond to four pages. In this way, when a nonvolatile memory cell is a multi-layer cell storing five or more bits of data, a word line can correspond to five or more pages. As described above, a word line can correspond to at least one page. Therefore, in an embodiment of the present disclosure, the operation of selecting at least one logical page by selecting a word line will be described as an operation of selecting a physical page.

[0027] More specifically, each of the memory blocks MEMORY BLOCK<1:6> may include a 3-D structure. For example, each of the memory blocks MEMORY BLOCK<1:6> may include a plurality of memory cells stacked on a substrate. Therefore, each of the memory blocks may be arranged in +X direction, +Y direction, and +Z direction.

[0028] Reference Figure 1B , each of the memory blocks MEMORY BLOCK<1:6> may include a plurality of strings ST11' to ST1m' and ST21' to ST2m'. Each of the plurality of strings ST11' to ST1m' and ST21' to ST2m' may extend along a vertical direction (Z direction). In the memory block MEMORY BLOCK<1:6>, m strings may be arranged in a row direction (X direction). Figure 1B In FIG. 1 , two strings are arranged in the column direction (Y direction), but this is for clarity; three or more strings may be arranged in the column direction (Y direction). Here, m may be a natural number of 2 or more.

[0029] Each of the plurality of strings ST11 ′ to ST1m ′ and ST21 ′ to ST2m ′ may include at least one source select transistor SST, first to nth memory cells MC1 to MCn, and at least one drain select transistor DST. Here, n may be a natural number of 1 or more.

[0030] The source select transistor SST of each string may be connected between a common source line CSL and memory cells MC1 to MCn. The source select transistors of the strings arranged in the same row may be connected to the same source select line. The source select transistors of the strings ST11' to ST1m' arranged in the first row may be connected to a first source select line SSL1. The source select transistors of the strings ST21' to ST2m' arranged in the second row may be connected to a second source select line SSL2. In another embodiment, the source select transistors of the strings ST11' to ST1m' and ST21' to ST2m' may be connected together to one source select line.

[0031] First to nth memory cells MC1 to MCn of each string may be connected in series to each other between source and drain select transistors SST and DST. Gates of first to nth memory cells MC1 to MCn may be connected to first to nth word lines WL1 to WLn, respectively.

[0032] In an embodiment, at least one of the first to nth memory cells MC1 to MCn may be used as a dummy memory cell. When the dummy memory cell is set, the voltage or current of the corresponding string may be stably controlled. Therefore, the reliability of data stored in the memory block MEMORY BLOCK<1:6> may be improved.

[0033] The drain selection transistor DST of each string may be connected between the bit line BL and the memory cells MC1 to MCn. The drain selection transistors DST of the strings arranged in the row direction may be connected to the drain selection lines extending in the row direction. The drain selection transistors DST of the strings ST11' to ST1m' of the first row may be connected to the first drain selection line DSL1. The drain selection transistors DST of the strings ST21' to ST2m' of the second row may be connected to the second drain selection line DSL2.

[0034] The strings arranged along the column direction may be connected to the bit lines extending along the column direction. Figure 1B , the strings ST11' and ST21' of the first column may be connected to the first bit line BL1. The strings ST1m' and ST2m' of the m-th column may be connected to the m-th bit line BLm.

[0035] Among the strings arranged in the row direction, the memory cells connected to the same word line can configure one physical page. For example, the memory cells connected to the first word line WL1 among the strings ST11' to ST1m' of the first row can configure one physical page. The memory cells connected to the first word line WL1 among the strings ST21' to ST2m' of the second row can configure another physical page. The strings arranged in one row direction are selected by selecting one of the drain selection lines DSL1 and DSL2. One physical page of the selected string is selected by selecting one of the word lines WL1 to WLn.

[0036] In an embodiment of the present disclosure, the strings commonly connected to the drain selection lines DSL1 to DSL2 and the source selection lines SSL1 to SSL2 among the strings arranged in the row direction will be named as "string groups". According to an embodiment, the strings ST11' to ST1m' commonly connected to the first drain selection line DSL1 and the first source selection line SSL1 in the first row may be referred to as the "first string group" and may be defined as the reference numeral "ST1". In addition, the strings ST21' to ST2m' commonly connected to the second drain selection line DSL2 and the second source selection line SSL2 in the second row may be referred to as the "second string group" and may be defined as the reference numeral "ST2". For reference, in the accompanying drawings, two string groups ST1 and ST2 are included in each of the plurality of memory blocks MEMORY BLOCK<1:6>, but this is merely an embodiment. Two or more string groups may be included in each of the plurality of memory blocks MEMORY BLOCK<1:6>.

[0037] Return to reference Figure 1A , the controller 202 may control an erase operation of erasing data stored in a selected memory block among a plurality of memory blocks MEMORY BLOCK<1:6> included in the memory cell array 201 .

[0038] The controller 202 may use a GIDL programming method and an ISPE method. The GIDL programming method includes changing a memory cell having a programmed state to a memory cell having an erased state by selecting a memory block among a plurality of memory blocks MEMORY BLOCK<1:6> included in the memory cell array 201 as an erase target memory block (hereinafter referred to as an "erase selection block"), and then raising the potential level of a channel of the erase selection block by an erase voltage having a high level and applied to a substrate of the erase selection block. The ISPE method includes gradually increasing the voltage level of the erase voltage applied to a substrate of the erase selection block.

[0039] In this case, the erase operation using the GIDL programming method may be an operation of releasing electrons stored in a charge storage layer of a memory cell having a programming state among a plurality of memory cells included in an erase selection block through a high potential level of a channel and a low potential level of a corresponding word line, thereby changing the memory cell having a programming state into a memory cell having an erased state. The erase operation using the GIDL programming method is a known operation and will not be described in detail.

[0040] Reference Figures 1A to 2 , the erase operation may include multiple erase cycles EL1 to EL7. That is, the controller 202 may repeatedly perform multiple erase cycles EL1 to EL7 one by one in a set order until the erase operation on the erase selection block is completed. In this case, when the erase operation is unsuccessful within a preset number of erase cycles, the controller 202 may regard the erase operation as a failure.

[0041] exist Figure 2 In the embodiment shown, the erase operation succeeds when the seventh erase cycle EL7 among the plurality of erase cycles EL1 to EL7 is completed. That is, all the plurality of memory cells included in the erase selection block have an erased state when the seventh erase cycle EL7 among the plurality of erase cycles EL1 to EL7 is completed.

[0042] In this case, each of the multiple erase loops EL1 to EL7 may include a pulse application interval VIO and a verification interval VER. The pulse application interval VIO is performed to change a cell having a programmed state among a plurality of memory cells included in the erase selection block to a cell having an erased state. The pulse application interval VIO is performed by applying an erase voltage VERA<1:7> to a common source line CSL and a plurality of bit lines BL<1:m> in a state where a ground voltage has been applied to a plurality of word lines WL<1:n> connected to the erase selection block. The verification interval VER is performed to verify whether a cell having a programmed state among a plurality of memory cells included in the erase selection block has been changed to a cell having an erased state. The verification interval VER is performed by applying an erase verification voltage VRYE to a plurality of word lines WL<1:n> connected to the erase selection block.

[0043] In some embodiments, whenever a plurality of erase cycles EL1 to EL7 are repeated in an erase operation, the potential level of the erase voltage VERA<1:7> may be increased according to the ISPE method. In this case, the application number, pulse level, and pulse application time of each of the erase voltages VERA<1:7> used in the plurality of erase cycles EL1 to EL7, respectively, may be adjusted in various forms.

[0044] More specifically, the controller 202 according to the embodiment of the present disclosure may verify whether each of the plurality of string groups ST1 and ST2 included in the erase selection block is erased through or failed in the verification interval VER of each of the plurality of erase cycles EL1 to EL7 repeated in the erase operation. That is, the controller 202 may determine the plurality of string groups ST1 and ST2 included in the erase selection block as one of the passed string groups and the failed string groups in the verification interval VER of each of the plurality of erase cycles EL1 to EL7 repeated in the erase operation ( Figure 1A , 10).

[0045] For example, the controller 202 may determine a string group in which the number of memory cells checked as erased passed in the verification interval VER is less than the first reference number among the memory cells connected to each of the plurality of string groups ST1 and ST2 included in the erase selection block as a failed string group. Further, the controller 202 may determine the remaining string groups as passed string groups.

[0046] More specifically, the controller 202 may perform an operation of sensing the amount of voltage or current loaded on the plurality of bit lines BL<1:m> in a state where the erase verification voltage VRYE has been applied to the plurality of word lines WL<1:n> included in the erase selection block in a verification interval VER of each of the plurality of erase cycles EL1 to EL7 repeated in the erase operation. In this case, the controller 202 may determine whether each of the plurality of string groups ST1 and ST2 has been erased by repeating the method of sensing the amount of voltage or current loaded on the plurality of bit lines BL<1:m> as many times as the number of the plurality of string groups ST1 and ST2 in a state where one of the plurality of string groups ST1 and ST2 included in the erase selection block has been selected. In this case, the controller 202 may determine whether each of the plurality of string groups ST1 and ST2 has been erased by selecting each of the plurality of string groups ST1 and ST2 included in the erase selection block once according to a set order in a verification interval VER of each of the plurality of erase cycles EL1 to EL7. In addition, the controller 202 may skip determining whether each of the plurality of string groups ST1 and ST2 has been erased, according to the state of each of the plurality of string groups ST1 and ST2 included in the erase selection block. That is, the controller 202 may skip determining whether a string group that has been checked as being erased passed in the verification interval VER of a previous erase cycle that has been previously executed among the plurality of erase cycles EL1 to EL7 has been erased, in the verification interval VER of a subsequent erase cycle that is subsequently executed.

[0047] For reference, from Figure 2It can be seen that the multiple erase cycles EL1 to EL7 included in the erase operation are determined as one of the "previous" erase cycle and the "next" erase cycle. In this case, the relationship between the previous erase cycle and the next erase cycle can refer to the relationship between the erase cycle executed first and the erase cycle executed subsequently after the first erase cycle. For example, if the first erase cycle EL1 is the previous erase cycle, the next erase cycle can refer to the second erase cycle EL2 executed after the first erase cycle EL1, and will not refer to the third erase cycle EL3 to the seventh erase cycle EL7 executed after the second erase cycle EL2. If the sixth erase cycle EL6 is the previous erase cycle, the seventh erase cycle EL7 executed after the sixth erase cycle EL6 can be the next erase cycle. Therefore, the first erase cycle EL1 executed first among the multiple erase cycles EL1 to EL7 will not become the next erase cycle. The seventh erase cycle EL7 executed last will not become the previous erase cycle.

[0048] According to an embodiment, two or more erase pass groups are included in the erase selection block. For example, the previous erase cycle among the plurality of erase cycles is the third erase cycle EL3 and the erase cycle after the third erase cycle EL3 is the fourth erase cycle EL4. In this case, the controller 202 may first determine whether the first string group ST1 included in the erase selection block is erased through in the verification interval VER of the third erase cycle EL3 among the plurality of erase cycles EL1 to EL7, and then determine whether the second string group ST2 included in the erase selection block is erased through. If it has been determined in the verification interval VER of the third erase cycle EL3 that the first string group ST1 has an erase pass state, the controller 202 may skip the operation of determining whether the first string group ST1 is erased through in the fourth erase cycle EL4 after the third erase cycle EL3. That is, if it has been determined in the verification interval VER of the third erase cycle EL3 that the first string group ST1 has an erase pass status, the controller 202 can perform an operation of directly determining whether the second string group ST2 has been erased in the fourth erase cycle EL4 after the third erase cycle EL3, without first performing an operation of determining whether the first string group ST1 has been erased.

[0049] As described above, the controller 202 may determine the plurality of string groups ST1 and ST2 included in the erase selection block as one of the passed string group and the failed string group in the verification interval VER of the previous erase cycle among the plurality of erase cycles EL1 to EL7 repeated in the erase operation ( Figure 1A, 10). Then, the controller 202 may differently set the voltage applied to the drain selection line DSL corresponding to the passed string group and the voltage applied to the drain selection line DSL corresponding to the failed string group in the pulse application interval VIO of the next erase cycle after the previous erase cycle ( Figure 1A , 20 and 30).

[0050] More specifically, the controller 202 may apply a first voltage (V10) to the drain selection line DSL corresponding to the failed string group from the start time to the first time in the pulse application interval VIO of the next erase cycle. Figure 1A , 20). In addition, the controller 202 may not apply any voltage to each of the plurality of drain selection lines DSL<1:2> from the start time to the end time in the pulse application interval VIO of the next erase cycle to float the drain selection line DSL corresponding to the failed string group. For example, the first voltage may be Figure 3 The voltage Vesl may be set to a voltage level having a ground voltage or a voltage lower than the ground voltage.

[0051] In some embodiments, the controller 202 may apply a first voltage to the drain selection line DSL corresponding to the pass string group from the start time to a second time earlier than the first time in the pulse application interval VIO of the next erase cycle, and apply a second voltage greater than the first voltage to the drain selection line DSL corresponding to the pass string group from the second time to the first time ( Figure 1A , 30). In addition, the controller 202 may not apply any voltage to the drain selection line DSL corresponding to the failed string group from the first moment to the end moment in the pulse application interval VIO of the next erase cycle to float the drain selection line DSL corresponding to the failed string group.

[0052] In some embodiments, the controller 202 may apply a first voltage to the source selection line SSL corresponding to each of the plurality of string groups from the start time to the first time in the pulse application interval VIO of the next erase cycle. Further, the controller 202 may not apply any voltage to the source selection line SSL corresponding to each of the plurality of string groups from the first time to the end time to float the source selection line SSL corresponding to each of the plurality of string groups.

[0053] In some embodiments, the controller 202 may apply an erase operation voltage, such as a ground voltage, to all word lines included in the erase selection block in the pulse application interval VIO of the next erase cycle, ie, from the start time to the end time.

[0054] In some embodiments, the controller 202 may determine a plurality of string groups as one of a passed string group and a failed string group in a verification interval VER of a previous erase cycle, and may then check the erase pass strength of the passed string group.

[0055] In some embodiments, the controller 202 may determine a string group in which the number of memory cells checked as erased passed in the verification interval VER among the memory cells connected to each of the multiple string groups ST1 and ST2 included in the erase selection block is less than the first reference number as a failed string group. Further, the controller 202 may determine a string group in which the number of memory cells checked as erased passed in the verification interval VER among the memory cells connected to each of the multiple string groups ST1 and ST2 included in the erase selection block is the first reference number or more as a passed string group. In addition, the controller 202 may simultaneously determine a string group in which the number of memory cells included in the passed string group is the first reference number or more and less than the second reference number as a weak passed string group, and a string group in which the number of memory cells included in the passed string group is the second reference number or more as a strong passed string group. In this case, the second reference number may be greater than the first reference number.

[0056] In some embodiments, the controller 202 may change the time difference between the "second moment" and the "first moment" in the pulse application interval VIO of the next erase cycle based on the erase pass strength of the pass string group. The erase pass strength of the pass string group may be checked in the verification interval VER of the previous erase cycle. The second moment may be the moment when the second voltage is started to be applied to the drain selection line DSL corresponding to the pass string group in the pulse application interval VIO of the next erase cycle. The first moment may be the moment when the drain selection line DSL is floated in the pulse application interval VIO of the next erase cycle.

[0057] In some embodiments, the controller 202 may set the second moment and the first moment so that the second moment and the first moment have a "first time" difference, that is, so that for the drain selection line DSL corresponding to the strong through string group whose erase pass strength of the through string group checked in the verification interval VER of the previous erase cycle is a reference value or more, the second moment is earlier than the first moment by the first time. In addition, the controller 202 may set the second moment and the first moment so that the second moment and the first moment have a "second time" difference, that is, so that for the drain selection line DSL corresponding to the weak through string group whose erase pass strength of the through string group checked in the verification interval VER of the previous erase cycle is less than the reference value, the second moment is earlier than the first moment by the second time. In this case, the first time may be longer than the second time.

[0058] That is, the controller 202 may set the time at which the second voltage is applied to the drain selection line DSL corresponding to the strong pass string group to be earlier than the time at which the second voltage is applied to the drain selection line DSL corresponding to the weak pass string group.

[0059] In the foregoing description, the operation of "applying" a specific voltage to a specific line may refer to the operation of "driving" the specific voltage to the specific line. That is, applying a specific voltage to a specific line may refer to driving the specific voltage to the specific line so that the voltage level of the specific line is not changed due to a phenomenon such as a coupling effect, thereby maintaining a state of the specific line at a specific voltage level.

[0060] Figure 3 is a diagram for describing an erase operation performed in a memory device according to an embodiment of the present disclosure.

[0061] Reference Figure 3 , an example of a pulse application interval VIO included in a subsequent erase cycle included in an erase operation performed in a memory device according to an embodiment of the present disclosure will be described. Figure 3 Each of the plurality of memory blocks MEMORY BLOCK<1:6> includes two string groups ST1 and ST2.

[0062] Specifically, in Figure 3 In the verification interval VER of the previous erase cycle, the controller 202 may have determined that the first string group ST1 has passed the erasure and the second string group ST2 has failed the erasure. That is, the controller 202 may have checked the following state: in the verification interval VER of the previous erase cycle, the number of memory cells checked as passed by the erase among the memory cells connected to the first string group ST1 is the first reference number or more, and in the verification interval VER of the previous erase cycle, the number of memory cells checked as passed by the erase among the memory cells connected to the second string group ST2 is less than the first reference number. Therefore, the controller 202 can perform the operation of the pulse application interval VIO of the next erase cycle in the state where the first string group ST1 has been determined to be a passed string group and the second string group ST2 has been determined to be a failed string group.

[0063] The controller 202 may apply the erase voltage Vera to the plurality of bit lines BL<1:m> and the common source line CSL from the start time t0 to the end time t3 in the pulse application interval VIO of the next erase cycle. In this case, the controller 202 may need to perform a pump operation to generate the erase voltage Vera because the erase voltage Vera has a higher voltage level than the externally provided power supply. Therefore, the erase voltage Vera may have a form in which the voltage level of the erase voltage rises toward the target level of the erase voltage from the start time t0 to the rising time t4, and may have a form in which the erase voltage maintains the target level from the rising time t4 to the end time t3.

[0064] The controller 202 may apply an erase word line voltage Vewl set to have a voltage level having a ground voltage or a voltage lower than the ground voltage to the plurality of word lines WL<1:n> from the start time t0 to the end time t3 in the pulse application interval VIO of the next erase cycle.

[0065] The controller 202 can minimize the decrease in the threshold voltage level of the memory cells connected to the first string group ST1 determined to be a passed string group in the pulse application interval VIO of the next erase cycle, and only reduce the threshold voltage level of the memory cells connected to the second string group ST2 determined to be a failed string group.

[0066] More specifically, the controller 202 may apply the first voltage Vesl to the second drain selection line DSL2 and the second source selection line SSL2 corresponding to the second string group ST2 that has been determined as a failed string group in the verification interval VER of the previous erase cycle from the start time t0 to the first time t1. Further, the controller 202 may float the second drain selection line DSL2 and the second source selection line SSL2 from the first time t1 to the end time t3 in the pulse application interval VIO of the next erase cycle. In this case, the first voltage Vesl may be set to a voltage level having a ground voltage or a voltage lower than the ground voltage.

[0067] In this case, the controller 202 may set the first time t1 to be earlier than the rising time t4. To this end, based on the levels of the plurality of bit lines BL<1:m> and the common source line CSL rising to the voltage level of the erase voltage Vera between the first time t1 and the rising time t4, the levels of the second drain selection line DSL2 and the second source selection line SSL2 may rise due to a coupling effect.

[0068] In some embodiments, since the GIDL current is generated according to the voltage level rise of the erase voltage Vera applied to the plurality of bit lines BL<1:m> and the common source line CSL in the pulse application interval VIO of the next erase cycle, the voltage level of the second channel CHANNEL2 corresponding to the second string group ST2 may rise. At this time, the voltage level of the second channel CHANNEL2 may rise with a first predetermined slope according to the first voltage Vesl applied to the second drain selection line DSL2 and the second source selection line SSL2 by the controller 202 in the pulse application interval VIO of the next erase cycle from the start time t0 to the first time t1. Next, according to the level of the second drain selection line DSL2 and the second source selection line SSL2 that have been floated at the first time t1 rising due to the coupling effect, the voltage level of the second channel CHANNEL2 may also rise. When the voltage level of the second channel CHANNEL2 rises as described above, the threshold voltage level of the memory cell connected to the second string group ST2 may drop from the rising time t4 to the ending time t3. That is, since the voltage level of the second channel CHANNEL2 rises in a state where the erase word line voltage Vewl set to a voltage level having a ground voltage or a voltage lower than the ground voltage has been applied to multiple word lines WL<1:n> from the rising time t4 to the ending time t3, the electrons stored in the charge storage layer of the memory cell connected to the second string group ST2 can be released through the high voltage level of the second channel CHANNEL2.

[0069] In some embodiments, how much earlier the first time instant t1 is set than the rising time instant t4 may be predetermined according to the type of the memory device 150 or the operating characteristics of the memory device 150 .

[0070] In some embodiments, in the pulse application interval VIO of the subsequent erase cycle, the controller 202 may apply the first voltage Vesl to the first drain selection line DSL1 corresponding to the first string group ST1 determined as a passed string group in the verification interval VER of the previous erase cycle from the start time t0 to the second time t2 earlier than the first time t1. Further, the controller 202 may apply the second voltage Vder higher than the first voltage Vesl to the first drain selection line DSL1 corresponding to the first string group ST1 from the second time t2 to the first time t1. Further, the controller 202 may float the first drain selection line DSL1 from the first time t1 to the end time t3. In addition, in the pulse application interval VIO of the subsequent erase cycle, the controller 202 may apply the first voltage Vesl to the first source selection line SSL1 corresponding to the first string group ST1 from the start time t0 to the first time t1, and float the first source selection line SSL1 from the first time t1 to the end time t3.

[0071] In this case, the controller 202 may set the first time t1 to be earlier than the rising time t4, and may set the second time t2 to be earlier than the first time t1. Therefore, the first drain selection line DSL1 may be set to have a voltage level of the first voltage Vesl at the start time t0, and then may rise to a voltage level of the second voltage Vder at the second time t2, and may rise from a voltage level of the second voltage Vder due to a coupling effect based on the voltage level of the plurality of bit lines BL<1:m> and the common source line CSL rising to the erase voltage Vera between the first time t1 and the rising time t4. As described above, at the second time t2 earlier than the first time t1, the first drain selection line DSL1 may be in a state where the voltage level of the first drain selection line DSL1 has risen to a voltage level of the second voltage Vder higher than the first voltage Vesl, and the second drain selection line DSL2 may be in a state where the second drain selection line DSL2 continues to maintain the voltage level of the first voltage Vesl until the first time t1. Therefore, it can be seen that the width of the second drain selection line DSL2 is greater than the width of the first drain selection line DSL1. Here, the voltage level of the second drain select line DSL2 rises due to a coupling effect between the first time t1 and the rising time t4 , and the voltage level of the first drain select line DSL1 rises due to a coupling effect between the first time t1 and the rising time t4 .

[0072] Similar to the second channel CHANNEL2 corresponding to the second string group ST2, the voltage level of the first channel CHANNEL1 corresponding to the first string group ST1 can rise because the GIDL current is generated according to the voltage level rise of the erase voltage Vera applied to the multiple bit lines BL<1:m> and the common source line CSL in the pulse application interval VIO of the subsequent erase cycle.

[0073] However, in the pulse application interval VIO of the next erase cycle, the controller 202 applies the first voltage Vesl to the first drain selection line DSL1 only from the start time t0 to the second time t2, and applies the second voltage Vder to the first drain selection line DSL1 from the second time t2 to the first time t1. Therefore, the voltage level of the first channel CHANNEL1 may rise at the first predetermined slope only between the start time t0 and the second time t2, and may rise at the second predetermined slope between the second time t2 and the first time t1. In this case, the second predetermined slope may be less than the first predetermined slope. Since the voltage level of the second channel CHANNEL2 continues to rise at the first predetermined slope between the start time t0 and the first time t1, the first channel CHANNEL1 may be in a state where the voltage level of the first channel CHANNEL1 is lower than the voltage level of the second channel CHANNEL2 at the first time t1.

[0074] Next, according to the voltage level of the first drain selection line DSL1 that has been floated at the first moment t1 rising due to the coupling effect, the voltage level of the first channel CHANNEL1 may also rise. At this time, because the first drain selection line DSL1 is in a state where the first drain selection line DSL1 has a voltage level of the second voltage Vder higher than the voltage level of the first voltage Ves1 at the first moment t1, and the second drain selection line DSL2 is in a state where the second drain selection line DSL2 has a voltage level of the first voltage Ves1, the width of the first drain selection line DSL1 may be smaller than the width of the second drain selection line DSL2. Here, the voltage level of the first drain selection line DSL1 rises from the first moment t1 to the rising moment t4, and the voltage level of the second drain selection line DSL2 rises from the first moment t1 to the rising moment t4. That is, the width of the first channel CHANNEL1 may be smaller than the width of the second channel CHANNEL2. Here, the voltage level of the first channel CHANNEL1 rises from the first time t1 to the rising time t4, and the voltage level of the second channel CHANNEL2 rises from the first time t1 to the rising time t4.

[0075] As described above, at the first moment t1, the first channel CHANNEL1 may be in a state where the voltage level of the first channel CHANNEL1 is lower than the voltage level of the second channel CHANNEL2, and the width of the first channel CHANNEL1 may be smaller than the width of the second channel CHANNEL2. Here, the voltage level of the first channel CHANNEL1 rises from the first moment t1 to the rising moment t4, and the voltage level of the second channel CHANNEL2 rises from the first moment t1 to the rising moment t4. Therefore, between the first moment t1 and the rising moment t4, the voltage level of the second channel CHANNEL2 may rise to a level to which the threshold voltage level of the memory cell connected to the second string group ST2 may drop. On the contrary, the voltage level of the first channel CHANNEL1 does not rise to such an extent that the threshold voltage level of the memory cell connected to the first string group ST1 may drop. That is, from the rising time t4 to the ending time t3, the first channel CHANNEL1 may be in a state where the erase word line voltage Vewl set to a voltage level having a ground voltage or a voltage lower than the ground voltage has been applied to the plurality of word lines WL<1:n>, but may also be in a state where the voltage level of the first channel CHANNEL1 has not yet risen sufficiently. Therefore, the release of electrons already stored in the charge storage layer of the memory cell connected to the first string group ST1 may be minimized.

[0076] like Figure 3As shown, the controller 202 can increase the voltage level of the first drain selection line DSL1 from the voltage level of the first voltage Vesl to the voltage level of the second voltage Vder at the second time t2 in the pulse application interval VIO of the next erase cycle, but can keep the voltage level of the first source selection line SSL1 at the voltage level of the first voltage Vesl from the start time t0 to the first time t1. That is, the controller 202 can minimize the drop in the threshold voltage level of the memory cell connected to the first string group ST1 determined as the pass string group by controlling only the voltage level of the first drain selection line DSL1 in the pulse application interval VIO of the next erase cycle. The reason why this operation can be performed is the phenomenon that the voltage level of the channel is greatly changed by the GIDL current through the drain level connected to the plurality of bit lines BL<1:m>. Unlike the above embodiment, the drop in the threshold voltage level of the memory cells connected to the first string group ST1 determined as the pass string group can be minimized by controlling the voltage levels of the first drain selection line DSL1 and the first source selection line SSL1 in the pulse application interval VIO of the subsequent erase cycle.

[0077] Figure 4A and Figure 4B is a diagram for describing other erase operations performed in the memory device according to an embodiment of the present disclosure.

[0078] It can be seen that Figure 4A and Figure 4B The erase operation shown is almost similar to Figure 3 Therefore, only the erase operation will be described below. Figure 4A and Figure 4B The erase operation shown and Figure 3 The difference between the erase operations is shown.

[0079] exist Figure 3 In the process, the controller 202 determines the first string group ST1 as a passed string group by checking that the number of memory cells checked as erased passed in the verification interval VER of the previous erase cycle among the memory cells connected to the first string group ST1 is a first reference number or more, determines the second string group ST2 as a failed string group by checking that the number of memory cells checked as erased passed in the verification interval VER of the previous erase cycle among the memory cells connected to the second string group ST2 is less than the first reference number, and executes the pulse application interval VIO of the next erase cycle.

[0080] Reference Figure 4A, the controller 202 may determine the first string group ST1 as a strong passing string group in the verification interval VER of the previous erase cycle, and may perform the operation of the pulse application interval VIO of the next erase cycle in a state where the second string group ST2 has been determined as a failed string group.

[0081] That is, the controller 202 may have checked the following state: the number of memory cells checked as erased passed in the verification interval VER of the previous erase cycle among the memory cells connected to the first string group ST1 is a second reference number greater than the first reference number. Therefore, the first string group ST1 may be in a state where the first string group ST1 has been determined to be a strong passed string group.

[0082] Therefore, the controller 202 can set the time difference between the second moment t2' and the first moment t1 to the first time tD1, the second moment t2' is the moment when the second voltage Vder begins to be applied to the first drain selection line DSL1 corresponding to the first string group ST1 determined as a strong pass string group, and the first moment t1 is the moment when the first drain selection line DSL1 is floated.

[0083] Compare Figure 3 and Figure 4A It can be seen that the second moment t2' corresponding to the case where the first string group ST1 has been determined as a "strong passing string group" is earlier than the second moment t2 corresponding to the case where the first string group ST1 has been determined as a "passing string group", that is, the time difference between the second moment t2' and the first moment t1 is longer than the time difference between the second moment t2 and the first moment t1.

[0084] As described above, if the controller 202 advances the time when the "second moment" starts in the pulse application interval VIO of the next erase cycle (t2→t2'), the interval length at which the voltage level of the first channel CHANNEL1 corresponding to the first string group ST1 determined as the "strong passing string group" rises at the first predetermined slope will be reduced compared to the voltage level of the first channel CHANNEL1 corresponding to the first string group ST1 determined as the "passing string group". At the same time, the interval length at which the voltage level of the first channel CHANNEL1 corresponding to the first string group ST1 determined as the "strong passing string group" rises at the second predetermined slope will increase. Therefore, at the first moment t1, the voltage level of the first channel CHANNEL1 corresponding to the first string group ST1 determined as the "strong passing string group" will be lower than the voltage level of the first channel CHANNEL1 corresponding to the first string group ST1 determined as the "passing string group". Therefore, at the rising time t4, the voltage level of the first channel CHANNEL1 corresponding to the first string group ST1 determined as the "strong pass string group" will be lower than the voltage level of the first channel CHANNEL1 corresponding to the first string group ST1 determined as the "pass string group" (that is, the level corresponding to the second time t2).

[0085] Therefore, between the rising time t4 and the ending time t3, the rate at which electrons stored in the charge storage layer of the memory cell connected to the first string group ST1 determined as the “strong pass string group” are released is lower than the rate at which electrons stored in the charge storage layer of the memory cell connected to the first string group ST1 determined as the “pass string group” are released. That is, the degree to which the threshold voltage level of the memory cell connected to the first string group ST1 determined as the “strong pass string group” drops can be lower than the degree to which the threshold voltage level of the memory cell connected to the first string group ST1 determined as the “pass string group” drops.

[0086] Reference Figure 4B , the controller 202 may determine the first string group ST1 as a weak pass string group in the verification interval VER of the previous erase cycle. Further, the controller 202 may perform the operation of the pulse application interval VIO of the next erase cycle in a state where the second string group ST2 has been determined as a failed string group.

[0087] That is, the controller 202 may have checked the following state: the number of memory cells checked as erased passed in the verification interval VER of the previous erase cycle among the memory cells connected to the first string group ST1 is less than the second reference number greater than the first reference number. Therefore, the first string group ST1 may be in a state where the first string group ST1 has been determined to be a weakly passed string group.

[0088] Therefore, the controller 202 can set the time difference between the second moment t2" and the first moment t1 to the second time tD2. The second moment t2" is the moment when the second voltage Vder begins to be applied to the first drain selection line DSL1 corresponding to the first string group ST1 determined to be a weak pass string group. The first moment t1 is the moment when the first drain selection line DSL1 is floated.

[0089] Compare Figure 3 and Figure 4B It can be seen that the second moment t2" corresponding to the case where the first string group ST1 has been determined as a "weak passing string group" is later than the second moment t2 corresponding to the case where the first string group ST1 has been determined as a "passing string group". That is, the time difference between the second moment t2" and the first moment t1 is shorter than the time difference between the second moment t2 and the first moment t1.

[0090] As described above, if the controller 202 postpones the time when the “second time” starts in the pulse application interval VIO of the next erase cycle (t2→t2”), the interval length in which the voltage level of the first channel CHANNEL1 corresponding to the first string group ST1 determined as the “weak passing string group” rises at the first predetermined slope will increase compared to the voltage level of the first channel CHANNEL1 corresponding to the first string group ST1 determined as the “passing string group”. At the same time, the interval length in which the voltage level of the first channel CHANNEL1 corresponding to the first string group ST1 determined as the “weak passing string group” rises at the second predetermined slope will increase. will decrease. Therefore, at the first moment t1, the voltage level of the first channel CHANNEL1 corresponding to the first string group ST1 determined as the "weak passing string group" will become higher than the voltage level of the first channel CHANNEL1 corresponding to the first string group ST1 determined as the "passing string group". Therefore, at the rising moment t4, the voltage level of the first channel CHANNEL1 corresponding to the first string group ST1 determined as the "weak passing string group" will become higher than the voltage level of the first channel CHANNEL1 corresponding to the first string group ST1 determined as the "passing string group" (that is, the level corresponding to the second moment t2).

[0091] Therefore, between the rising time t4 and the ending time t3, the rate at which electrons stored in the charge storage layer of the memory cell connected to the first string group ST1 determined as the “weak pass string group” are released is greater than the rate at which electrons stored in the charge storage layer of the memory cell connected to the first string group ST1 determined as the “pass string group” are released. That is, the degree to which the threshold voltage level of the memory cell connected to the first string group ST1 determined as the “weak pass string group” drops may be higher than the degree to which the threshold voltage level of the memory cell connected to the first string group ST1 determined as the “pass string group” drops.

[0092] Compare Figure 4A and Figure 4B , the controller 202 may set the time difference between the second moment t2' and the first moment t1 to the first time tD1. The second moment t2' is the moment when the second voltage Vder begins to be applied to the first drain selection line DSL1 corresponding to the first string group ST1 determined to be a strong pass string group. The first moment t1 is the moment when the first drain selection line DSL1 is floated. Further, the controller 202 may set the time difference between the second moment t2" and the first moment t1 to the second time tD2. The second moment t2" is the moment when the second voltage Vder begins to be applied to the first drain selection line DSL1 corresponding to the first string group ST1 determined to be a weak pass string group. The first moment t1 is the moment when the first drain selection line DSL1 is floated. In this case, it can be seen that the first time tD1 is longer than the second time tD2.

[0093] The controller 202 may change the time difference between the "second moment" and the "first moment". The "second moment" is the moment when the second voltage starts to be applied to the drain selection line DSL corresponding to the pass string group. The "first moment" is the moment when the drain selection line DSL is floated. The change of the time difference may be performed by checking the erase pass strength of the pass string group checked in the verification interval VER of the previous erase cycle and changing the "second moment" in the pulse application interval VIO of the next erase cycle based on the checked erase pass strength.

[0094] That is, the controller 202 can set the moment when the second voltage is applied to the drain selection line DSL corresponding to the relatively strong pass string group, so that the moment when the second voltage is applied to the drain selection line DSL corresponding to the pass string group is relatively earlier than the moment when the second voltage is applied to the drain selection line DSL corresponding to the weak pass string group.

[0095] Figure 5 is a diagram for describing a controller among components of a memory device according to an embodiment of the present disclosure. Figure 5 , the memory device 150 may include a memory cell array 201 and a control unit 202. The control unit 202 may include a control operation unit 309 and a control logic unit 302. The control operation unit 309 may include a page buffer unit 304, a checker (or check unit) 303, a data input and output (input / output) circuit 305, a voltage supply circuit 306, and an address decoder 307. The control operation unit 309, the control logic unit 302, the page buffer unit 304, and the check unit 303 include all circuits, systems, software, firmware, and devices required for their respective operations and functions.

[0096] The memory cell array 201 may include a plurality of memory blocks, for example, MEMORY BLOCK<1:6>. The plurality of memory blocks MEMORY BLOCK<1:6> may be connected to the address decoder 307 through row lines RL. The plurality of memory blocks MEMORY BLOCK<1:6> may be connected to the page buffer unit 304 through bit lines BL1 to BLm. Each of the memory blocks MEMORY BLOCK<1:6> may include a plurality of memory cells.

[0097] The address decoder 307 included in the control operation unit 309 may be connected to the memory cell array 201 through the row line RL. The row line RL may include at least one source selection line SSL1, SSL2, a plurality of word lines WL<1:n>, at least one drain selection line DSL1, DSL2, and a common source line CSL.

[0098] The control operation unit 309 may perform an erase operation on a memory block (i.e., an erase selection block) selected as an erase target among a plurality of memory blocks MEMORYBLOCK<1:6> in response to erase operation signals EOP1 and EOP2. In this case, the erase operation on the erase selection block may include a plurality of erase cycles EL1 to EL7. The control operation unit 309 may drive the memory cell array 201. For example, the control operation unit 309 may apply various operating voltages to the row lines RL and the bit lines BL1 to BLm, or may release the voltages applied to the row lines RL and the bit lines BL1 to BLm.

[0099] The address decoder 307 may be configured to operate in response to the control of the control logic unit 302. The address decoder 307 may receive the address RADD and the first erase operation signal EOP1 from the control logic unit 302.

[0100] The address decoder 307 may be configured to decode the block address of the received address RADD. The address decoder 307 may select at least one memory block among the memory blocks MEMORY BLOCK<1:6> according to the decoded block address. The address decoder 307 may be configured to decode the row address of the received address RADD. The address decoder 307 may select at least one word line among the word lines of the selected memory block according to the decoded row address. The address decoder 307 may apply the voltage VOP provided by the voltage supply circuit 306 to each of the drain selection lines DSL<1:2>, the plurality of word lines WL<1:n>, the source selection lines SSL<1:2>, and the common source lines CSL included in the erase selection block in response to the first erase operation signal EOP1. For example, the address decoder 307 may select one of the plurality of string groups included in the erase selection block, and may apply the voltage VOP provided by the voltage supply circuit 306 to each of the drain selection lines and the source selection lines corresponding to the selected string group.

[0101] The voltage supply circuit 306 in the control operation unit 309 may be configured to generate a plurality of operation voltages Vop by utilizing an external power supply voltage. The voltage supply circuit 306 may operate in response to the control of the control logic unit 302. Specifically, the voltage supply circuit 306 according to an embodiment of the present disclosure may generate an erase voltage Vera, a first voltage Vesl, a second voltage Vder, and an erase word line voltage Vewl in response to a second erase operation signal EOP2 included in the operation signal OP_SIG applied by the control logic unit 302. Further, the voltage supply circuit 306 may send the erase voltage Vera, the first voltage Vesl, the second voltage Vder, and the erase word line voltage Vewl to the address decoder 307.

[0102] In an embodiment, the voltage supply circuit 306 may regulate an external supply voltage to generate an internal supply voltage.

[0103] In an embodiment, the voltage supply circuit 306 may generate a plurality of operating voltages Vop by utilizing an external power supply voltage or an internal power supply voltage.

[0104] The voltage supply circuit 306 may include a plurality of pumping capacitors receiving an internal power supply voltage to generate a plurality of operating voltages Vop having various voltage levels. The plurality of operating voltages Vop may be generated by selectively activating the plurality of pumping capacitors in response to the control of the control logic unit 302 .

[0105] The generated operating voltage Vop may be supplied to the memory cell array 201 through the address decoder 307. For example, the voltage supply circuit 306 may adjust a level and a supply time of each operating voltage Vop in response to the operation signal OP_SIG.

[0106] The page buffer unit 304 may include a plurality of page buffers PB1 to PBm. The plurality of page buffers PB1 to PBm may be connected to the memory cell array 201 through a plurality of bit lines BL1 to BLm, respectively. The plurality of page buffers PB1 to PBm may operate under the control of the control logic unit 302 .

[0107] The plurality of page buffers PB1 to PBm may communicate data DATA with the data input / output circuit 157. During a program operation, the plurality of page buffers PB1 to PBm may receive data DATA to be stored through the data input / output circuit 305 and the data lines DL.

[0108] After the program operation starts, the plurality of page buffers PB1 to PBm may store data DATA received from the outside through the data input / output circuit 305, and may transmit a program enable voltage or a program inhibit voltage to the bit lines BL1 to BLm in response to the stored data DATA. For example, the program enable voltage may be a logic low level, i.e., 0V, and the program inhibit voltage may be a logic high level, i.e., a power supply voltage.

[0109] After the read operation starts, the plurality of page buffers PB1 to PBm may sense data DATA based on the voltage or current of the bit lines BL1 to BLm, which is determined based on the threshold voltage of the memory cell of the selected page. Further, the plurality of page buffers PB1 to PBm may transmit the sensed data DATA to the data input / output circuit 305 through the data line DL.

[0110] The data input / output circuit 305 may include a plurality of input / output buffers receiving data DATA input thereto. During a program operation, the data input / output circuit 305 may receive data DATA to be stored from the outside. During a read operation, the data input / output circuit 305 may output data DATA transmitted from a plurality of page buffers PB1 to PBm included in the page buffer unit 304 to the outside.

[0111] The inspection unit 303 may determine whether the number of bit lines connected to cells having a threshold voltage level equal to or higher than the erase target level among the bit lines selected in the page buffer unit 304 is less than a set number in the verification interval VER included in the erase operation. Further, the inspection unit 303 may generate a comparison signal having a PASS value or a FAIL value based on the result of the determination. For example, when the number of bit lines connected to cells having a threshold voltage level less than the erase target level among the bit lines selected in the page buffer unit 304 is less than a set number, the inspection unit 303 may generate a comparison signal having a FAIL value and output the comparison signal to the control logic unit 302. For example, when the number of bit lines connected to cells having a threshold voltage level less than the erase target level among the bit lines selected in the page buffer unit 304 is a set number or more, the inspection unit 303 may generate a comparison signal having a PASS value and output the comparison signal to the control logic unit 302. In this case, referring to Figures 1A to 3 , the set quantity may refer to one of a first reference quantity and a second reference quantity.

[0112] The control logic unit 302 may be connected to the address decoder 307, the voltage supply circuit 306, the page buffer unit 304, the data input / output circuit 305, and the check unit 303 included in the control operation unit 309. The control logic unit 302 may be configured to control the overall operation of the memory device 150. The control logic unit 302 may operate in response to a command CMD from an external device.

[0113] The control logic unit 302 may control the control operation unit 309 by generating various signals in response to the command CMD and the address ADDR. For example, the control logic unit 302 may generate an operation signal OPSIG, an address RADD, a read and write control signal PBSIGNALS, a verification reference signal VRYBIT, and erase operation signals EOP1, EOP2 in response to the command CMD and the address ADDR. The control logic unit 302 may output the operation signal OPSIG including the second erase operation signal EOP2 to the voltage supply circuit 306, may output the address RADD and the first erase operation signal EOP1 to the address decoder 307, may output the read and write control signal PBSIGNALS to the page buffer unit 304, and may output the quantity information signal REF_INFO to the inspection unit 303. In addition, the control logic unit 302 may determine the result of the verification interval included in each of the plurality of erase loops EL1 to EL7 in response to the comparison signal having the PASS value or the FAIL value output by the inspection unit 303.

[0114] More specifically, refer to Figures 1A to 3, the control logic unit 302 may determine the plurality of string groups ST1 and ST2 included in the erase selection block as one of a pass string group and a fail string group in a verification interval VER of a previous erase cycle among a plurality of erase cycles EL1 to EL7 repeated in the erase operation. Further, the control logic unit 302 may generate erase operation signals EOP1 and EOP2 whose values ​​are adjusted based on the determination result, and may output the erase operation signals EOP1 and EOP2 to the control operation unit 309.

[0115] The control logic unit 302 may determine a string group in which the number of memory cells checked as erased passed in the verification interval VER of the previous erase cycle is less than the first reference number among the memory cells connected to each of the plurality of string groups ST1 and ST2 included in the erase selection block as a failed string group. Further, the control logic unit 302 may determine the remaining string groups as passed string groups.

[0116] When all of the plurality of string groups ST1 and ST2 included in the erase selection block are checked as passed string groups in the verification interval VER of the previous erase loop, the control logic unit 302 may generate the erase operation signals EOP1 and EOP2 having the first value.

[0117] In response to the erase operation signals EOP1 and EOP2 having the first value generated from the control logic unit 302, the control operation unit 309 may terminate the erase operation without entering the next erase cycle. That is, if the control logic unit 302 generates the erase operation signals EOP1 and EOP2 having the first value, this may mean that all the multiple string groups ST1 and ST2 included in the erase selection block are determined as passed string groups in the verification interval VER of the previous erase cycle. Therefore, this may refer to a state where it is no longer necessary to perform an erase cycle at the end of the verification interval VER of the previous erase cycle. To this end, the control operation unit 309 may terminate the erase operation without entering the next erase cycle in response to the erase operation signals EOP1 and EOP2 having the first value. For example, in Figure 3 In the verification interval VER of the seventh erase loop EL7 shown, all the plurality of string groups ST1 and ST2 included in the erase selection block may be determined as passed string groups. Therefore, the control operation unit 309 may terminate the erase operation without performing an erase cycle at the end of the seventh erase loop EL7.

[0118] When all of the plurality of string groups ST1 and ST2 included in the erase selection block are checked as failed string groups in the verification interval VER of the previous erase loop, the control logic unit 302 may generate the erase operation signals EOP1 and EOP2 having the second value.

[0119] In response to the erase operation signals EOP1 and EOP2 having the second value being generated from the control logic unit 302, the control operation unit 309 may apply the first voltage Vesl to each of the plurality of drain selection lines DSL<1:2> respectively corresponding to the plurality of string groups ST1 and ST2 included in the erase selection block from the start moment to the first moment in the pulse application interval VIO of the subsequent erase cycle. That is, if the control logic unit 302 generates the erase operation signals EOP1 and EOP2 having the second value, this may mean that all the plurality of string groups ST1 and ST2 included in the erase selection block are determined as failed string groups in the verification interval VER of the previous erase cycle. Therefore, it is necessary to normally perform an erase operation on each of the plurality of string groups ST1 and ST2 included in the erase selection block in the pulse application interval VIO of the subsequent erase cycle. That is, it is necessary to lower the threshold voltage level of the memory cell connected to each of the plurality of string groups ST1 and ST2. To this end, in response to the erase operation signals EOP1 and EOP2 having the second value, the control operation unit 309 may apply the first voltage Vesl to each of the plurality of drain selection lines DSL<1:2> respectively corresponding to the plurality of string groups ST1 and ST2 included in the erase selection block from the start time to the first time in the pulse application interval VIO of the subsequent erase cycle.

[0120] When some of the plurality of string groups ST1 and ST2 included in the erase selection block are checked as passed string groups and the remaining string groups are checked as failed string groups in the verification interval VER of the previous erase loop, the control logic unit 302 may generate the erase operation signals EOP1 and EOP2 having the third value.

[0121] In response to the generation of the erase operation signals EOP1 and EOP2 having the third value from the control logic unit 302, the control operation unit 309 may determine each of the plurality of string groups ST1 and ST2 included in the erase selection block as one of the pass string group and the fail string group. In this case, the control operation unit 309 may need to prevent the threshold voltage level of the memory cell connected to the pass string group from decreasing. To this end, the control operation unit 309 may apply the first voltage Vesl to the drain selection line corresponding to the pass string group from the start moment to the second moment in the pulse application interval VIO of the next erase cycle, and apply the second voltage Vder to the drain selection line corresponding to the pass string group from the second moment to the first moment. In addition, the control operation unit 309 may need to reduce the threshold voltage level of the memory cell connected to the fail string group. To this end, the control operation unit 309 may apply the first voltage Vesl to the drain selection line corresponding to the fail string group from the start moment to the first moment in the pulse application interval VIO of the next erase cycle. In addition, the control operation unit 309 may not apply any voltage to each of the multiple drain selection lines DSL<1:2> corresponding to the multiple string groups ST1 and ST2 included in the erase selection block, respectively, from the first moment to the end moment in the pulse application interval VIO of the next erase cycle, so that the multiple drain selection lines DSL<1:2> float.

[0122] In response to the erase operation signals EOP1 and EOP2 having the second value or the third value, the control operation unit 309 may apply a first voltage to the source selection line SSL corresponding to each of the plurality of string groups from the start time to the first time in the pulse application interval VIO of the subsequent erase cycle. Further, the control operation unit 309 may not apply any voltage to the source selection line SSL corresponding to each of the plurality of string groups from the first time to the end time to float the source selection line SSL.

[0123] In response to the erase operation signals EOP1 and EOP2 having the second value or the third value, the control operation unit 309 may apply an erase operation voltage, such as a ground voltage, to all word lines included in the erase selection block in the pulse application interval VIO of the subsequent erase cycle, i.e., from the start time to the end time.

[0124] After determining the plurality of string groups ST1 and ST2 as one of a passed string group and a failed string group in the verification interval VER of the previous erase loop, the control logic unit 302 may check the erase pass strength of the passed string group.

[0125] The control logic unit 302 can change the time difference between the "second moment" and the "first moment" in the pulse application interval VIO of the next erase cycle based on the erase pass strength of the pass string group that has been checked in the verification interval VER of the previous erase cycle. Here, the "second moment" is the moment when the second voltage begins to be applied to the drain selection line DSL corresponding to the pass string group, and the "first moment" is the moment when the drain selection line DSL is floated. To this end, the control logic unit 302 can determine each of the multiple string groups ST1 and ST2 as one of a strong pass string group and a weak pass string group. For a strong pass string group, the erase pass strength of the pass string group that has been checked in the verification interval VER of the previous erase cycle is a reference value or greater. For a weak pass string group, the erase pass strength of the pass string group that has been checked in the verification interval VER of the previous erase cycle is less than the reference value. Further, the control logic unit 302 can generate erase operation signals EOP1 and EOP2 whose values ​​are adjusted based on the determination result.

[0126] The control logic unit 302 may determine a string group in which the number of memory cells checked as erased passed in the verification interval VER of the previous erase cycle among the memory cells connected to each of the multiple string groups ST1 and ST2 included in the erase selection block is less than the first reference number as a failed string group. Further, the control logic unit 302 may determine a string group in which the number of memory cells checked as erased passed in the verification interval VER of the previous erase cycle among the memory cells connected to each of the multiple string groups ST1 and ST2 included in the erase selection block is the first reference number or more as a passed string group. In addition, the control logic unit 302 may simultaneously determine a string group in which the number of memory cells checked as erased passed in the verification interval VER of the previous erase cycle is the first reference number or more and less than the second reference number among the passed string groups as a weak passed string group, and determine a string group in which the number of memory cells checked as erased passed in the verification interval VER of the previous erase cycle is the second reference number or more as a strong passed string group. In this case, the second reference number may be greater than the first reference number.

[0127] When all of the plurality of string groups ST1 and ST2 included in the erase selection block are checked as passed string groups in the verification interval VER of the previous erase loop, the control logic unit 302 may generate the erase operation signals EOP1 and EOP2 having the first value.

[0128] In response to the erase operation signals EOP1 and EOP2 having the first value being generated from the control logic unit 302, the control operation unit 309 may terminate the erase operation without entering a subsequent erase cycle.

[0129] When all of the plurality of string groups ST1 and ST2 included in the erase selection block are checked as failed string groups in the verification interval VER of the previous erase loop, the control logic unit 302 may generate the erase operation signals EOP1 and EOP2 having the second value.

[0130] In response to the erase operation signals EOP1 and EOP2 having the second value generated from the control logic unit 302, the control operation unit 309 may apply a first voltage Vesl to each of a plurality of drain selection lines DSL<1:2> respectively corresponding to a plurality of string groups ST1 and ST2 included in the erase selection block from the start time to the first time in the pulse application interval VIO of the subsequent erase cycle.

[0131] When some of the multiple string groups ST1 and ST2 included in the erase selection block are checked as weak pass string groups, some of the multiple string groups ST1 and ST2 included in the erase selection block are checked as strong pass string groups, and the remaining string groups are checked as failed string groups, the control logic unit 302 can generate erase operation signals EOP1 and EOP2 having a fourth value in the verification interval VER of the previous erase cycle.

[0132] In response to the generation of the erase operation signals EOP1 and EOP2 having the fourth value from the control logic unit 302, the control operation unit 309 may determine each of the plurality of string groups ST1 and ST2 included in the erase selection block as one of a weak pass string group, a strong pass string group, and a fail string group. In this case, the control operation unit 309 may need to strongly prevent the threshold voltage level of the memory cell connected to the strong pass string group from decreasing. To this end, the control operation unit 309 may apply a first voltage Vesl to the drain selection line corresponding to the pass string group from the start moment to a second moment earlier than the first moment by a first time in the pulse application interval VIO of the latter erase cycle, and apply a second voltage Vder to the drain selection line corresponding to the pass string group from the second moment to the first moment. In addition, the control operation unit 309 may need to slightly prevent the threshold voltage level of the memory cell connected to the weak pass string group from decreasing. To this end, the control operation unit 309 may apply a first voltage Vesl to the drain selection line corresponding to the pass string group from the start moment to the second moment that is a second time earlier than the first moment in the pulse application interval VIO of the next erase cycle, and apply a second voltage Vder to the drain selection line corresponding to the pass string group from the second moment to the first moment. In this case, the first time may be longer than the second time. That is, the control operation unit 309 may operate so that the moment when the second voltage is applied to the drain selection line DSL corresponding to the strong pass string group is earlier than the moment when the second voltage is applied to the drain selection line DSL corresponding to the weak pass string group. In addition, the control operation unit 309 may need to reduce the threshold voltage level of the memory cell connected to the failed string group. To this end, the control operation unit 309 may apply a first voltage Vesl to the drain selection line corresponding to the failed string group from the start moment to the first moment in the pulse application interval VIO of the next erase cycle.

[0133] In response to the erase operation signals EOP1 and EOP2 having the second value or the fourth value, the control operation unit 309 may apply a first voltage to the source selection line SSL corresponding to each of the plurality of string groups from the start time to the first time in the pulse application interval VIO of the subsequent erase cycle. Further, the control operation unit 309 may not apply any voltage to the source selection line SSL corresponding to each of the plurality of string groups from the first time to the end time so that the source selection line SSL floats.

[0134] In response to the erase operation signals EOP1 and EOP2 having the second value or the fourth value, the control operation unit 309 may apply an erase operation voltage, such as a ground voltage, to all word lines included in the erase selection block in the pulse application interval VIO of the subsequent erase cycle, i.e., from the start time to the end time.

[0135] Figure 6is a flowchart for describing the sequence of an erase operation performed in a memory device according to an embodiment of the present disclosure.

[0136] Reference Figure 6 , an erase command and an erase address may be input to the memory device 150 (S10).

[0137] In response to inputting the erase command and the erase address in S10 , one of the plurality of memory blocks MEMORY BLOCK<1:6> may be selected as an erase selection block, and an operation of a pulse application interval VIO included in an erase cycle may be performed on the erase selection block ( S20 ).

[0138] In S20, in the case of a through string group, among the multiple string groups ST1 and ST2 included in the erase selection block, a first voltage Vesl can be applied to the drain selection line DSL corresponding to the through string group from the start moment to the second moment in the pulse application interval VIO, and a second voltage Vder can be applied to the drain selection line DSL corresponding to the through string group from the second moment to the first moment in the pulse application interval VIO.

[0139] In S20, in case of a failed string group, among the plurality of string groups ST1 and ST2 included in the erase selection block, a first voltage Ves1 may be applied to a drain selection line DSL corresponding to the failed string group from a start time to a first time in a pulse application interval VIO.

[0140] In S20 , in a case where the first erase loop EL1 among the plurality of erase loops EL1 to EL7 is first performed, all of the plurality of string groups ST1 and ST2 included in the erase selection block may be determined as failed string groups.

[0141] After S20 , an operation of a verification interval VER included in the erase loop may be performed ( S30 ).

[0142] In S30 , each of the plurality of string groups ST1 and ST2 included in the erase selection block may be determined as one of a pass string group and a fail string group.

[0143] It may be checked whether all of the plurality of string groups ST1 and ST2 included in the erase selection block in S30 have been determined as pass string groups ( S40 ).

[0144] When all of the plurality of string groups ST1 and ST2 included in the erase selection block are determined as passed string groups in S30 (Yes in S40 ), the erase operation may be terminated by determining that the erase operation on the erase selection block has succeeded.

[0145] When at least one of the plurality of string groups ST1 and ST2 included in the erase selection block is checked as a failed string group in S30 (No in S40), the count value of the current erase cycle may be increased (S50). In this case, when the erase operation is unsuccessful in the first erase cycle EL1, the count value of the current erase cycle may be increased from the first erase cycle EL1 to the second erase cycle EL2 in S50.

[0146] After S50, it may be checked whether the count value of the current erase loop is the maximum count value of the erase loop (S60).

[0147] When the count value of the current erase loop is the maximum count value of the erase loop in S60 ("Yes" in S60), it may be determined that the erase operation on the erase selection block has failed, and then the erase operation may be terminated.

[0148] When the count value of the current erase loop is not the maximum count value of the erase loop in S60 (No in S60), S20 to S60 of the current erase loop (eg, the second erase loop EL2) may be sequentially performed.

[0149] Although various embodiments of the present disclosure have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention as defined in the appended claims. In addition, these embodiments may be combined to form additional embodiments.

Claims

1. A memory device, comprising: A memory block including K string groups, wherein the K string groups are respectively connected to a plurality of bit lines through K drain selection lines and are respectively connected to a common source line through K source selection lines; and A controller: repeating one or more erase cycles until the erase operation on the storage block is successful, each erase cycle including a pulse application interval and a verification interval; determining the K string groups as one of a pass string group and a fail string group in a verification interval of a previous erase cycle among the erase cycles; and applying a first voltage to a drain selection line corresponding to the fail string group from a start time to a first time in a pulse application interval of a subsequent erase cycle after the previous erase cycle among the erase cycles, applying the first voltage to a drain selection line corresponding to the pass string group from the start time to a second time earlier than the first time, and applying a second voltage greater than the first voltage to a drain selection line corresponding to the pass string group from the second time to the first time, Wherein K is a natural number greater than or equal to 2.

2. The memory device of claim 1 , wherein the controller comprises: A control operation unit is configured to repeatedly perform the erase cycle on the storage block in response to an erase operation signal; as well as The control logic unit determines each of the K string groups as one of a failed string group and a passed string group in a verification interval of the previous erase cycle, and generates an erase operation signal having an adjusted value based on a result of the determination.

3. The memory device of claim 2, wherein the control logic unit: determining a string group, among the memory cells connected to each of the K string groups, in which the number of memory cells checked as erased in the verification interval of the previous erase cycle is less than a first reference number, as the failed string group, and The remaining string groups are determined as the passing string groups.

4. The memory device of claim 3, wherein the control logic unit: During the verification interval of the previous erase cycle, When all the string groups in the K string groups are determined as the passing string groups, an erase operation signal having a first value is generated, When all the string groups in the K string groups are determined to be the failed string groups, an erase operation signal having a second value is generated, and When some of the K string groups are determined as the passed string groups and the remaining string groups are determined as the failed string groups, an erase operation signal having a third value is generated.

5. The memory device according to claim 4, wherein the control operation unit: terminating the erase operation in response to the first value of the erase operation signal without entering the next erase cycle, applying the first voltage to each of the K drain selection lines from the start time to the first time in response to a second value of the erase operation signal, and In response to the third value of the erase operation signal, each of the K string groups is determined as one of the pass string group and the fail string group, the first voltage is applied to the drain selection line corresponding to the pass string group from the start time to the second time, the second voltage is applied to the drain selection line corresponding to the pass string group from the second time to the first time, and the first voltage is applied to the drain selection line corresponding to the fail string group from the start time to the first time.

6. The memory device of claim 2, wherein the control logic unit: Check the erase pass strength of the pass string group, and The time difference between the first time and the second time is changed based on the result of the checking.

7. The memory device according to claim 6, wherein the control logic unit determines each of the pass string groups as a strong pass string group whose erase pass strength is a reference value or more and a weak pass string group whose erase pass strength is less than the reference value in a verification interval of the previous erase cycle, and generates an erase operation signal with an adjusted value based on a result of the determination.

8. The memory device of claim 7, wherein the control logic unit: determining a string group, among the memory cells connected to each of the K string groups, in which the number of memory cells checked as erased in the verification interval of the previous erase cycle is less than a first reference number, as the failed string group, determining a string group in which the number of memory cells checked as being erased passed is the first reference number or more as the passed string group, determining a string group in which the number of memory cells checked as being erased passed is less than a second reference number among the pass string groups as the weak pass string group, and A string group in which the number of memory cells checked as being erased passed among the pass string groups is the second reference number or more is determined as the strong pass string group.

9. The memory device of claim 8, wherein the control logic unit: When all the string groups in the K string groups are checked as the passed string groups in the verification interval of the previous erase cycle, an erase operation signal having a first value is generated, When all the string groups in the K string groups are checked as the failed string groups in the verification interval of the previous erase cycle, an erase operation signal having a second value is generated, and When some of the K string groups are determined as the weak passing string groups in the verification interval of the previous erase cycle, other some of the K string groups are determined as the strong passing string groups in the verification interval of the previous erase cycle, and the remaining string groups are determined as the failed string groups in the verification interval of the previous erase cycle, an erase operation signal having a fourth value is generated.

10. The memory device according to claim 9, wherein the control operation unit: terminating the erase operation in response to the first value of the erase operation signal without entering the next erase cycle, applying the first voltage to each of the K drain selection lines from the start time to the first time in response to a second value of the erase operation signal, and In response to a fourth value of the erase operation signal, each of the K string groups is determined as one of the weak pass string group, the strong pass string group, and the fail string group, the first voltage is applied to the drain selection line corresponding to the strong pass string group from the start time to a second time that is a first time earlier than the first time, the second voltage is applied to the drain selection line corresponding to the strong pass string group from the second time to the first time, the first voltage is applied to the drain selection line corresponding to the weak pass string group from the start time to a second time that is a second time earlier than the first time, the second voltage is applied to the drain selection line corresponding to the weak pass string group from the second time to the first time, and the first voltage is applied to the drain selection line corresponding to the fail string group from the start time to the first time, and The first time is longer than the second time.

11. The memory device of claim 1 , wherein the controller: applying the first voltage to each of the K source selection lines from the start time to the first time in a pulse application interval of the subsequent erase cycle, and In a state where each of the K drain selection lines and the K source selection lines has been floated, an erase voltage is applied to the plurality of bit lines and the common source line from the first time to an end time.

12. The memory device of claim 11, wherein: The first voltage has a voltage level of a ground voltage or a voltage lower than the ground voltage, and The second voltage has a voltage level higher than the ground voltage and has a voltage level lower than the erase voltage.

13. A method for operating a memory device, the memory device comprising K string groups respectively connected to a plurality of bit lines through K drain selection lines and respectively connected to a common source line through K source selection lines, the method comprising: An erase operation, repeating one or more erase cycles until the erase operation on the storage block is successful, each erase cycle including a pulse application interval and a verification interval; A determination operation of determining the K string groups as one of a pass string group and a fail string group in a verification interval of a previous erase cycle among erase cycles repeated in the erase operation; a first application operation of applying a first voltage to a drain selection line corresponding to the determined failed string group from a start time to a first time in a pulse application interval of a subsequent erase cycle after the previous erase cycle; as well as a second application operation, in the pulse application interval of the latter erase cycle, applying the first voltage to the drain selection line corresponding to the determined pass string group from the start time to a second time earlier than the first time, and applying a second voltage greater than the first voltage to the drain selection line corresponding to the pass string group from the second time to the first time, Wherein K is a natural number greater than or equal to 2.

14. The operating method according to claim 13, wherein the determining operation comprises: determining a string group in which the number of memory cells checked as erased in the verification interval of the previous erase cycle is less than a first reference number among the memory cells connected to each of the K string groups as the failed string group, and The remaining string groups are determined as the passing string groups.

15. The operating method according to claim 13, wherein: The determining operation includes checking the erase pass strength of the pass string group, and The second applying operation includes changing the time difference between the first time and the second time based on the erase pass strength of the pass string group that has been checked.

16. The operating method according to claim 15, wherein the determining operation comprises: determining a string group, among the memory cells connected to each of the K string groups, in which the number of memory cells checked as erased in the verification interval of the previous erase cycle is less than a first reference number, as the failed string group, determining a string group in which the number of memory cells checked as being erased passed is the first reference number or more as the passed string group, determining a string group in which the number of memory cells checked as being erased passed is less than a second reference number among the pass string groups as a weak pass string group, and A string group in which the number of memory cells checked as being erased passed among the pass string groups is the second reference number or more is determined as a strong pass string group.

17. The operating method according to claim 16, wherein the second applying operation comprises: Applying the first voltage to the drain selection line corresponding to the determined strong pass string group from the start time to a second time that is a first time earlier than the first time, and applying the second voltage to the drain selection line corresponding to the strong pass string group from the second time to the first time; Applying the first voltage to the drain selection line corresponding to the determined weak pass string group from the start time to a second time that is a second time earlier than the first time, and applying the second voltage to the drain selection line corresponding to the weak pass string group from the second time to the first time; as well as applying the first voltage to the drain selection line corresponding to the determined failed string group from the start time to the first time, and The first time is longer than the second time.

18. The operating method according to claim 17, further comprising: When all the string groups in the K string groups are checked as the passed string groups in the verification interval of the previous erase cycle, an erase operation signal having a first value is generated, When all the string groups in the K string groups are checked as the failed string groups in the verification interval of the previous erase cycle, an erase operation signal having a second value is generated, When some of the K string groups are determined as the weakly passed string groups in the verification interval of the previous erase cycle, other of the K string groups are determined as the strongly passed string groups in the verification interval of the previous erase cycle, and the remaining string groups are determined as the failed string groups in the verification interval of the previous erase cycle, an erase operation signal having a fourth value is generated, terminating the erase operation in response to the first value of the erase operation signal without entering the next erase cycle, applying the first voltage to each of the K drain selection lines from the start time to the first time in response to a second value of the erase operation signal, and In response to a fourth value of the erase operation signal, each of the K string groups is determined to be one of the weak-pass string group, the strong-pass string group, and the fail string group.

19. The operating method according to claim 13, further comprising: applying the first voltage to each of the K drain selection lines from the start time to the first time in a pulse application interval of the subsequent erase cycle; as well as An erase voltage is applied to the plurality of bit lines and the common source line from the first time to an end time in a pulse application interval of the subsequent erase cycle in a state where each of the K drain select lines and the K source select lines has been floated.

20. The operating method according to claim 13, wherein: The first voltage has a voltage level of a ground voltage or a voltage lower than the ground voltage, and The second voltage has a voltage level higher than the ground voltage and has a voltage level lower than the erase voltage.

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