VDT function test system and method of storage device, terminal equipment and storage medium

Abstract

The invention relates to the technical field of storage testing, in particular to a VDT function testing system and method of a storage device, terminal equipment and a storage medium. The test system comprises a system processor and a storage device, the system processor and the storage device are connected through at least one power supply line, a power supply management chip is arranged on the power supply line, a control pin of the power supply management chip is connected with the system processor, and a voltage output pin of the power supply management chip is connected with the storage device; the power management chip is used for receiving the control signal from the system processor and generating a fluctuation test voltage output to the storage device according to the control signal so as to carry out a voltage detection function test. Through the test system, developers can perform perfect VDT (Voltage Detection) function test in an early research and development stage, the code structure design of the storage device is optimized and adjusted in time, and the research and development cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of storage test technology, and in particular to a VDT function test system, method, terminal equipment and storage medium for a storage device. Background Art

[0002] The existing normal or abnormal voltage tests are generally based on user scenarios, covering abnormal power-off test scenarios (such as VCC dropping from 3.3V to 0V) and normal voltage range fluctuation scenarios (such as VCC fluctuating between 3.3V and 2.7V or between 2.7 and 2.4). There are no use cases designed from the perspective of firmware VDT (Voltage Detector) function verification. Therefore, the current firmware development cannot verify the reliability of UFS (embedded storage) in VDT ​​detection and the robustness of the test firmware code. Summary of the invention

[0003] In view of this, the embodiments of the present application provide a VDT function test system, method, terminal device and storage medium for a storage device, which can effectively solve the problem of verifying the reliability of UFS in VDT ​​detection during firmware development.

[0004] In a first aspect, an embodiment of the present application provides a VDT function test system for a storage device, including a system processor and a storage device, wherein the system processor and the storage device are connected via at least one power supply line;

[0005] A power management chip is provided on the power supply line, a control pin of the power management chip is connected to the system processor, and a voltage output pin of the power management chip is connected to the storage device;

[0006] The power management chip is used to receive a control signal from the system processor, and generate a fluctuating test voltage output to the storage device according to the control signal to perform a voltage detection function test.

[0007] In some embodiments, three power supply lines are connected between the storage device and the system processor.

[0008] In a second aspect, the present application further provides a VDT function test method for a storage device, which is applied to the test system, and the system processor executes the method, and the method includes:

[0009] After determining the current test item, an enable signal is sent to the power management chip on the power supply circuit to be tested;

[0010] According to a preset voltage fluctuation model, controlling the fluctuating voltage output by the power management chip to the storage device;

[0011] According to the test items, test result data is obtained from the test system.

[0012] In some embodiments, the voltage fluctuation model includes a fluctuation voltage, a holding time, a fluctuation period, and a fluctuation number;

[0013] According to a preset voltage fluctuation model, controlling the fluctuating voltage outputted by the power management chip to the storage device includes:

[0014] The system processor sends a control signal to the power management chip through the bus interface to control the power management chip to output the fluctuating voltage to the storage device, and controls the fluctuating voltage to return to a normal value after maintaining the maintaining time;

[0015] The operation of the system processor sending a control signal to the power management chip through the bus interface is executed at intervals of the fluctuation period until the number of executions is equal to the number of fluctuations.

[0016] In some embodiments, the system processor sends a control signal to the power management chip through a bus interface to control the power management chip to output the fluctuating voltage to the storage device, including:

[0017] Determine the type of the power supply circuit where the power management chip is located, and determine the corresponding voltage range according to the type of the power supply circuit;

[0018] Determine the address of the voltage setting register, set the registration value within the voltage range, and send the registration value as a control signal to the power management chip. The power management chip configures the registration value to the address of the voltage setting register to output the fluctuating voltage.

[0019] In some embodiments, the fluctuation voltage is less than a threshold detection voltage of a voltage detector in the storage device and greater than a power-off detection voltage.

[0020] In some embodiments, determining the current test item includes:

[0021] Determine the target parameters and work scenarios for testing;

[0022] The step of obtaining test result data from the test system according to the test item includes:

[0023] The detection value fed back by the voltage detector in the storage device is obtained, and the working data of the test system under the working scenario is determined, and the working data and the detection value are the test result data.

[0024] In some embodiments, the system processor sends an enable signal to a power management chip on a power supply line to be tested, including:

[0025] The system processor sends a selection signal to the voltage selection interface of the power management chip through the bus interface to set the voltage type corresponding to the power management chip;

[0026] The system processor sends an enable signal to the enable interface of the power management chip through the bus interface to activate the power management chip.

[0027] In a third aspect, the present application further provides a terminal device, the terminal device comprising a processor and a memory, the memory storing a computer program, and the processor being used to execute the computer program to implement the VDT functional testing method of the storage device.

[0028] In a fourth aspect, the present application further provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed on a processor, the VDT functional testing method of the storage device is implemented.

[0029] The embodiments of the present application have the following beneficial effects:

[0030] This application sets a power management chip on the power supply line, allowing developers to control the power management chip through the system processor in the test system to simulate voltage fluctuations. Through this test system, developers can perform comprehensive VDT function tests in the early R&D stage, timely optimize and adjust the firmware code structure design, and reduce R&D costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 A schematic diagram of a VDT function test system for a storage device according to an embodiment of the present application is shown;

[0033] Figure 2 A schematic diagram of the structure of a power management chip according to an embodiment of the present application is shown;

[0034] Figure 3 A schematic diagram of a VDT function test method for a storage device according to an embodiment of the present application is shown;

[0035] Figure 4The voltage fluctuation waveform diagram of the embodiment of the present application is shown;

[0036] Figure 5 A schematic diagram of a voltage control relationship in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0038] The components of the embodiments of the present application generally described and shown in the drawings herein may be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0039] Hereinafter, the terms "including", "having" and their cognates that can be used in various embodiments of the present application are intended only to indicate specific features, numbers, steps, operations, elements, components or a combination of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or a combination of the foregoing items or increasing the possibility of one or more features, numbers, steps, operations, elements, components or a combination of the foregoing items. In addition, the terms "first", "second", "third" and the like are only used to distinguish descriptions and cannot be understood as indicating or implying relative importance.

[0040] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meanings as those generally understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meanings as the contextual meanings in the relevant technical field and will not be interpreted as having idealized meanings or overly formal meanings unless clearly defined in the various embodiments of the present application.

[0041] The present application provides a test system and a VDT function test method for a storage device applied on the test system. In view of the fact that current firmware cannot test and verify the reliability of UFS (embedded storage) in performing VDT (voltage detection) and test the robustness of firmware code on the development side, a power management chip is set on the power supply line between VDT ​​and the system processor, so that developers can control the voltage detected by VDT in the development scenario, and test various projects through a voltage fluctuation model to realize the performance of embedded storage in various scenarios.

[0042] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0043] Figure 1 The structure of a VDT function test system for a storage device is shown, comprising: a storage device 100 and a system processor 200, wherein the system processor 200 and the storage device 100 are connected via at least one power supply line. A voltage detector is provided in the storage device 100 to provide a voltage detection function.

[0044] A power management chip 300 is provided on the power supply line, a control pin of the power management chip 300 is connected to the system processor 200 , and a voltage output pin of the power management chip 300 is connected to the storage device 100 .

[0045] The power management chip 300 is used to receive a control signal from the system processor 200, and generate a fluctuating test voltage output to the storage device 100 according to the control signal. The fluctuating voltage will be detected by the voltage detector in the storage device 100, and the voltage detector will perform corresponding processing according to the voltage fluctuation. The tester collects the read and write data in the storage device 100, and can test the voltage detection function of the voltage detector.

[0046] There may be multiple power supply lines, each of which has a voltage supply line of a different specification. Figure 1 In the figure, three power supply lines are taken as an example, indicating that there may be a first power supply line, a second power supply line and a third power supply line, and each power supply line is provided with a power management chip 300 to control the voltage on the three lines.

[0047] The three power supply lines are of different types. The first power supply line, the second power supply line and the third power supply line can be VCC, VCCQ or VCCQ2 respectively. Different power supply lines have different power supply voltage ranges. For example, the power supply voltage of VCC is about 3.3V or 2.5V, the power supply voltage of VCCQ is about 1.2V, and the power supply voltage of VCCQ2 is about 1.8V. Different lines have different voltages, and the voltage control requirements for testing are also different.

[0048] The control pin of the power management chip 300 is connected to the system processor 200 , the voltage output pin of the power management chip 300 is connected to the storage device 100 , and the voltage input pin of the power management chip 300 is connected to the system processor 200 .

[0049] The power management chip 300 is used to receive a control signal from the system processor, and adjust the fluctuating voltage output to the storage device according to the control signal.

[0050] Exemplary, such as Figure 2 As shown, one possible structure of the power management chip 300 is shown. Figure 2 The power management chip in the example is used as an example, where the EN (enable) pin, SCL (I 2 C clock) pin, SDA (I 2 The SCL (data) pin and the VSEL (select) pin are used to connect to the system processor 200 to receive the control signal of the system processor 200, so that the voltage received by the storage device 100 can be controlled according to the predetermined test program. 2 C control pin, used to control the voltage.

[0051] The storage device 100 is used to detect voltage fluctuations. For some embedded storage devices, when the voltage drops to a certain value, it will cause voltage instability. The storage device 100 is used to suspend the read and write operations of the storage device when a low voltage is detected. The VDT function test method of the storage device of this embodiment is used to test whether the voltage detection effect of the storage device 100 is accurate, which can ensure that the embedded storage device can accurately perform read and write operations in some common scenarios even if the voltage is unstable.

[0052] The VDT function testing method of the storage device is described below in conjunction with some specific embodiments.

[0053] Figure 3 A schematic flow chart of a VDT function test method for a storage device according to an embodiment of the present application is shown. The method exemplarily comprises the following steps:

[0054] Step S100, after determining the current test item, sending an enable signal to the power management chip on the power supply circuit to be tested.

[0055] The testing method of this embodiment is applied to the aforementioned testing system, and is mainly aimed at testing of storage devices. Before testing, the test items need to be determined.

[0056] The test items are determined according to the test purpose. For example, if the detection function of the voltage detector in the storage device is to be tested, it is necessary to test whether the voltage detector can detect fluctuations under different voltage fluctuations in various usage scenarios.

[0057] If you want to test the robustness of the voltage detector, you should mainly check whether it can operate normally after the voltage returns to normal from abnormality.

[0058] If reliability is to be tested, voltage fluctuations need to be performed during the reading, writing, initialization and other tasks of the storage device, and it is determined whether the reading, writing, initialization and other tasks of the storage device are performed correctly without omission errors.

[0059] Therefore, targeted testing is required for different test purposes, and for this purpose, the test items need to be determined.

[0060] Specifically, it is necessary to determine the target parameters and working scenarios of the test. For example, for the test detection function, it is necessary to obtain feedback data when the voltage detector detects voltage anomalies. For robustness, it is necessary to obtain normal data before the test and test data after recovery from abnormal voltage, and compare the normal data with the test data.

[0061] The working scenario refers to the common working environment or work task scenario for the storage device.

[0062] After determining the target parameters and working scenarios of the test, specific test operations can be performed in the working scenarios, and the final test data can be obtained according to the target parameters required.

[0063] When the test starts, the system processor sends an enable signal to the power management chip on the power supply line to be tested to activate the power management chip.

[0064] It is understandable that if the power management chip is not activated, the data configured in the power management chip will not take effect.

[0065] For details, please refer to Figure 2 As shown, the power management chip has an EN pin and a VSEL pin, which are used to receive selection instructions and activation instructions from the system processor. The system processor exchanges data with the EN pin and the VSEL pin through corresponding interface functions.

[0066] Among them, the VSEL interface function is designed with two parameters. The first parameter is VSEL Pin, which is used to select which power supply line voltage to activate, that is, to select whether to control the VCC voltage or the voltage of VCCQ or VCCQ2. Taking the control of VCC voltage as an example, the parameter "VSEL--VCC_VSEL Pin" corresponding to VCC can be transmitted to select the set voltage parameter. The second parameter "VCC_VSEL" is used to set the value used to select the VCC register. This value can enable or cancel the selected state of the specified register. The above parameters are illustrative of the control of VCC voltage as an example. The parameter name can change according to the actual situation. For example, the parameter "VSEL--VCC_VSEL Pin" indicates the selection of the pin corresponding to the VCC voltage output by the VSEL pin. Different pins will select different registers. The register contains the set data to control the output voltage.

[0067] Taking the control of VCC voltage as an example, the EN interface function also has two corresponding parameters, one is VCC_ENPin, which means to pass the parameter to the EN pin, and the other is VCC_EN corresponding to the settable value Disable or Enable, that is, to power on or off VCC. This ensures that the data is transmitted to the correct location and performs the corresponding activation or deactivation operation.

[0068] The above VSEL and EN interface functions are used to select the corresponding registers in the power management chip to set the power on or off state, but the control of the specific voltage value in the register also requires the design of the I2C Control interface function to achieve the purpose of voltage regulation by modifying the I2C Register (registered value). For the specific regulation of the voltage of VCC, VCCQ or VCCQ2, the corresponding structures of these three voltage settings can be separately controlled.

[0069] Through the control of the above two pins, combined with the I2C Control interface, the power management chip that needs to be controlled can be activated to accurately control the power management chips in multiple lines. For example, if the voltage of VCC is set, the power management chips located at VCCQ and VCCQ2 will not be set with voltage. After the power management chip is activated, the set voltage can take effect.

[0070] Step S200: controlling the fluctuating voltage outputted by the power management chip to the storage device according to a preset voltage fluctuation model.

[0071] The voltage fluctuation model is a model that controls voltage fluctuations during the test process. For a storage device, when the voltage drops to a certain threshold value X, the detection function will be triggered, such as Figure 4As shown in FIG. 1 , it is a voltage fluctuation waveform. When the voltage starts to fluctuate from the normal voltage and is lower than the threshold value X, it will be detected. The voltage fluctuation model is a model established to cause such fluctuation.

[0072] Specifically, the voltage fluctuation model includes the fluctuation voltage, the maintenance time, the fluctuation period and the fluctuation number.

[0073] The fluctuating voltage is the voltage value to which the voltage needs to be adjusted, the maintaining time is the time to maintain the fluctuating voltage at this value, the fluctuation cycle is how often the fluctuation occurs, and the number of fluctuations is how many times the above parameters need to be fluctuated.

[0074] These parameters can be pre-set according to the actual situation. According to the different test items mentioned above, the parameter sizes set here will also be different, and there may even be multiple voltage fluctuation models. For example, if you want to perform a stress test, you can set multiple models, in which the fluctuation voltage can be the same, but the maintenance time and fluctuation period can be reduced successively, so that the voltage fluctuation brings more and more detection pressure to the voltage detector of the model, which is convenient for detecting the upper limit of the pressure of the voltage detector.

[0075] After determining the above data, the system processor sends a control signal to the power management chip through the bus interface to control the power management chip to output a fluctuating voltage to the storage device and control the fluctuating voltage to return to a normal value after a maintenance time. The bus interface may be an I2C interface.

[0076] The above operation is performed at intervals of the fluctuation period until the number of executions is equal to the number of fluctuations, during which the test data can be collected.

[0077] like Figure 4 As shown in the figure, it is a schematic diagram of a voltage fluctuation model. In this model, the time from the voltage starting to drop to returning to normal is 2.5 microseconds, the time below the threshold value X is 1 microsecond, and 2.5 microseconds is the fluctuation cycle. After one cycle, the next voltage drop operation is performed. A fluctuation will produce the following Figure 4 If the waveform shown in the figure fluctuates 10 times, 10 waveforms will be generated continuously. Figure 4 The waveform shown.

[0078] The control signal sent to the power management chip through the I2C interface is also controlled by the designed I2CControl (control interface) interface function. Specifically, the function achieves the purpose of regulating voltage by modifying the I2C Register (registration code).

[0079] The voltage detector has a threshold detection voltage and a power-off detection voltage. When the voltage fluctuation is less than the threshold detection voltage, it will be detected as a fluctuation, but when the voltage is less than the power-off detection voltage, it will be directly detected as a power-off. Therefore, in addition to being less than the threshold detection voltage of the voltage detector, the fluctuation voltage must also be greater than the power-off detection voltage. If the fluctuation voltage is too small, it will be detected as a power-off, and the detection function of the voltage detector will not be triggered. This setting can prevent the power-off from being triggered.

[0080] After the voltage fluctuation model is determined, during the test process, corresponding voltage fluctuation control can be performed according to the voltage fluctuation model, which is specifically manifested in controlling the fluctuating voltage output by the power management chip to the storage device.

[0081] First, it will determine the type of power supply circuit where the power management chip is located, and determine the voltage range based on the type of power supply circuit.

[0082] The address of the voltage setting register is determined, a registration value within the voltage range is set, and the registration value is sent to the power management chip as a control signal. The power management chip configures the registration value to the address of the voltage setting register to output a fluctuating voltage.

[0083] Exemplary Figure 5 As shown in the figure, an adjustable voltage table that can be used in this embodiment shows the relevant rules table for controlling the VCC voltage to the power-on standard voltage of 3.3V. As long as the corresponding relationship in the table is followed, the corresponding value is set in the VOUT_BANK_L[1:0] of the register address specified in the power management chip to control the output fluctuation voltage range. Figure 5 Taking register address 0x1D as an example, the corresponding rule table is given. There are 8 bits in the address, of which b[0] and b[1] are VOUT_BANK_L[1:0], which are used to store data for controlling the voltage range. By setting data in these two bits, the voltage range can be configured.

[0084] It is stated in the VOUT_BANK_L[1:0] row that when the value is 00, the corresponding voltage range is 0.303125V to 0.7V, when the value is 01, the voltage range is 0.60625V to 1.4V, when the value is 10, the voltage range is 1.2125V to 2.8V, and when the value is 11, the voltage range is 2.425V to 5.6V.

[0085] First, the VSEL corresponding to VCC can be selected through the preset function, and then the currently set voltage VOUT_BANK_L[1:0] can be read through the I2C Control interface to determine whether it is in the voltage range of 2.425V to 5.6V of VCC. That is, determine whether its value is 11. If it is not 11, it is configured to 11, so that the set voltage range is consistent with the voltage range of VCC.

[0086] For specific voltage settings, there are also corresponding registers for configuration. Similar to the configuration of the voltage range, specific voltage settings can be made by setting the values ​​in the corresponding registers. For example, another register with a register address of 0x11 can be set as a voltage setting register, which is specifically used to set the voltage size. The voltage size can be changed by changing the value in the voltage setting register. When setting a specific voltage, the set value and voltage also have similar corresponding rules as when setting the voltage range, which are not listed here one by one.

[0087] After confirming that the selected voltage range and the set voltage value are correct, the voltage fluctuation is controlled by enabling the power management chip. The subsequent voltage adjustment only needs to follow the design of the model and control the I2C Control interface to modify the registration value to control the voltage within the range of 2.425V to 5.6V, thus completing the output of the fluctuating voltage.

[0088] It can be understood that the above is an example of configuring the VCC voltage range and voltage. For VCCQ and VCCQ2, there are similar control methods, which will not be repeated here.

[0089] Step S300: acquiring test result data from the test system according to the test item.

[0090] After the voltage fluctuation is controlled through the above steps, the test item can be executed, and then the test result data under the test item can be obtained from the test system and the storage device.

[0091] The detection value fed back by the voltage detector in the storage device can be obtained, and the working data of the test system in the working scenario can be determined. The working data and the detection value are the test result data.

[0092] Working data refers to the result of reading and writing by the storage device, and the detection value refers to the detection result of voltage fluctuation.

[0093] For example, the test of the detection function of the voltage detector is mainly used for white box or gray box testing of the self-verification of the VDT function of the storage device. The storage device needs to cooperate in adding relevant information about the voltage detector detection, and query the VDT detection situation before the test starts. After the multiple scenarios + VDT test is completed, the voltage detector detection situation information is queried once, and the detection information before and after is compared. This can effectively analyze whether the storage device successfully detects and takes corresponding measures when the voltage detector occurs. It is also possible to adjust the voltage of the voltage fluctuation model, such as setting the pull-down voltage to be above the threshold detection voltage, which will not trigger the VDT of the storage device. Combined with the comparison of information before and after the test, the expected result is that there is no change in the VDT detection information, thereby achieving the purpose of self-verification of the hardware VDT detection capability of the storage device.

[0094] For another example, for the test of reliable data writing, when voltage fluctuations occur, if the writing is successful, the storage device should ensure data reliability, and the verification data should be the data successfully written; if the writing fails, the verification data should be the original data that was normally written last time; BOOT and RPMB writing need to ensure data reliability; based on the above requirements, the test can obtain data such as the amount and integrity of data written during voltage fluctuations, thereby verifying whether the storage device's ability to reliably write data during voltage fluctuations meets the requirements.

[0095] Similarly, for other test items, corresponding test results can be obtained through similar test methods, which will not be described in detail here.

[0096] Based on these test results, the contents of concern to the test items can be analyzed and the effectiveness of the current storage device can be determined. It can be seen that the solution of this embodiment allows developers to customize test methods and complete test operations concisely and efficiently, so that developers can have a relatively complete verification test of the VDT function in the early stage of the product and timely optimize and adjust the code structure design.

[0097] This embodiment further provides a terminal device, which includes a processor and a memory, wherein the memory stores a computer program, and the processor is used to execute the computer program to implement the VDT function test method of the storage device.

[0098] This embodiment further provides a computer-readable storage medium storing a computer program. When the computer program is executed on a processor, the VDT function test method of the storage device is implemented.

[0099] Among them, the processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including a central processing unit (CPU), a graphics processor (GPU), a network processor (NP), a digital signal processor (DSP), an application-specific integrated circuit (AS chip), a field programmable gate array (FPGA) or at least one of other programmable logic devices, discrete gates or transistor logic devices, and discrete hardware components. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc., which can implement or execute the disclosed methods, steps and logic block diagrams in the embodiments of the present application.

[0100] The memory may be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc. The memory is used to store a computer program, and the processor may execute the computer program accordingly after receiving an execution instruction.

[0101] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram and / or the flow diagram, and the combination of boxes in the structure diagram and / or the flow diagram, can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0102] In addition, the functional modules or units in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0103] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a smart phone, a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the various embodiments of the present application.

[0104] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A VDT function test system for a storage device, characterized in that: comprising a system processor and a storage device, wherein the system processor and the storage device are connected via at least one power supply line; A power management chip is provided on the power supply line, a control pin of the power management chip is connected to the system processor, and a voltage output pin of the power management chip is connected to the storage device; The power management chip is used to receive a control signal from the system processor, and generate a fluctuating test voltage output to the storage device according to the control signal to perform a voltage detection function test.

2. The VDT functional test system for a storage device according to claim 1, characterized in that: Three power supply lines are connected between the storage device and the system processor.

3. A VDT function test method for a storage device, characterized in that: Applied to the test system according to claim 1 or 2, the system processor executes the method, the method comprising: After determining the current test item, an enable signal is sent to the power management chip on the power supply circuit to be tested; According to a preset voltage fluctuation model, controlling the fluctuating voltage output by the power management chip to the storage device; According to the test items, test result data is obtained from the test system.

4. The VDT function test method of the storage device according to claim 3, characterized in that: The voltage fluctuation model includes the fluctuation voltage, the maintenance time, the fluctuation period and the fluctuation times; According to a preset voltage fluctuation model, controlling the fluctuating voltage outputted by the power management chip to the storage device includes: The system processor sends a control signal to the power management chip through the bus interface to control the power management chip to output the fluctuating voltage to the storage device, and controls the fluctuating voltage to return to a normal value after maintaining the maintaining time; The operation of the system processor sending a control signal to the power management chip through the bus interface is executed at intervals of the fluctuation period until the number of executions is equal to the number of fluctuations.

5. The VDT function test method of the storage device according to claim 4, characterized in that: The system processor sends a control signal to the power management chip through a bus interface to control the power management chip to output the fluctuating voltage to the storage device, including: Determine the type of the power supply circuit where the power management chip is located, and determine the corresponding voltage range according to the type of the power supply circuit; Determine the address of the voltage setting register, set the registration value within the voltage range, and send the registration value as a control signal to the power management chip. The power management chip configures the registration value to the address of the voltage setting register to output the fluctuating voltage.

6. The VDT function test method of the storage device according to claim 4, characterized in that: The fluctuation voltage is smaller than a threshold detection voltage of a voltage detector in the storage device and larger than a power-off detection voltage.

7. The VDT function test method of the storage device according to claim 3, characterized in that: Determining the current test items includes: Determine the target parameters and work scenarios for testing; The step of obtaining test result data from the test system according to the test item includes: The detection value fed back by the voltage detector in the storage device is obtained, and the working data of the test system under the working scenario is determined, and the working data and the detection value are the test result data.

8. The VDT function test method of the storage device according to claim 3, characterized in that: The system processor sends an enable signal to a power management chip on a power supply line to be tested, including: The system processor sends a selection signal to the voltage selection interface of the power management chip through the bus interface to set the voltage type corresponding to the power management chip; The system processor sends an enable signal to the enable interface of the power management chip through the bus interface to activate the power management chip.

9. A terminal device, characterized in that: The terminal device comprises a processor and a memory, wherein the memory stores a computer program, and the processor is used to execute the computer program to implement the VDT function test method of the storage device according to any one of claims 3 to 8.

10. A computer-readable storage medium, characterized in that: The device stores a computer program, which, when executed on a processor, implements the VDT function test method for a storage device according to any one of claims 3 to 8.

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