Connecting plate of flash memory chip, preparation method of connecting plate and flash memory chip

Abstract

The invention provides a connecting plate of a flash memory chip, a preparation method of the connecting plate and the flash memory chip, and relates to the technical field of semiconductors. The connecting plate comprises an insulating layer which is provided with a first surface and a second surface which are opposite; the semiconductor substrate is arranged on the first surface of the insulating layer; and the conductive layer is arranged on the second surface of the insulating layer, the conductive layer comprises a plurality of conductive sheets with different shapes, and the conductive sheets are distributed at different positions of the second surface of the insulating layer, so that a bonding pad of the flash memory chip is coupled to an external pin through the conductive sheets, and the proportion of a bonding wire crossing the flash memory chip is reduced. The signal on the bonding pad of the flash memory chip is connected to the external pin through the conducting strip of the conducting layer of the connecting plate, the proportion across the flash memory chip can be reduced, the line arc is low, and the packaging risk is low.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a connection board of a flash memory chip, a method for preparing the connection board, and a flash memory chip. Background Art

[0002] In the field of semiconductor technology, static memory (such as flash memory chips) plays a vital role in recording and storing data. It is widely used in many industries such as computers, communications, consumer electronics, and automotive electronics, and has become one of the core components of modern technology. With the continuous development of technology, the packaging design of flash memory chips is also being optimized to improve performance and meet the growing application needs.

[0003] However, when the pad design of the flash memory chip is located on one side of the frame (Lead Frame), and the signal is connected to the external pin outside the frame through the welding wire, for example, when the pad located on one side of the frame is connected to the external pin on the other side of the frame through the welding wire, it is usually necessary to span more than 90% of the length of the flash memory chip. This design will cause the arc length of the welding wire to be too long and the height to be high, increasing the risk of wire punching or wire collapse during the packaging process. At the same time, this structure will increase the overall package thickness, thereby affecting the compactness and reliability of the package.

[0004] How to reduce the proportion of wire bonds across flash memory chips and reduce packaging risks is an urgent problem to be solved. Summary of the invention

[0005] The present disclosure provides a connection board for a flash memory chip and a preparation method thereof, and a flash memory chip, which reduce the cross-flash memory chip ratio at least to a certain extent, have low line arcs, low packaging risks, and can also reduce packaging thickness and improve packaging compactness and reliability.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0007] According to one aspect of the present disclosure, there is provided a connection board for a flash memory chip, comprising: an insulating layer 142 having a first surface and a second surface relative to each other; a semiconductor substrate 143 disposed on the first surface of the insulating layer 142; and a conductive layer 141 disposed on the second surface of the insulating layer 142, wherein the conductive layer 141 comprises a plurality of conductive sheets of different shapes, wherein the conductive sheets are distributed at different positions on the second surface of the insulating layer 142, so that the pads 120 of the flash memory chip 110 are coupled to the external pins 206 through the conductive sheets, so as to reduce the proportion of the bonding wires across the flash memory chip 110.

[0008] In one embodiment of the present disclosure, the insulating layer 142 includes a first insulating layer, and the first insulating layer is a polymer material layer or an oxide layer.

[0009] In one embodiment of the present disclosure, the insulating layer 142 includes: a first insulating layer having a first surface and a second surface relative to each other, the second surface of the first insulating layer being the second surface of the insulating layer 142; a second insulating layer disposed on the first surface of the first insulating layer; wherein the first insulating layer is a polymer material layer, and the second insulating layer is an oxide layer.

[0010] In one embodiment of the present disclosure, the connecting plate 140 further includes: a third insulating layer 144 disposed on the conductive layer 141 , wherein the third insulating layer 144 is a polymer material layer.

[0011] In one embodiment of the present disclosure, a plurality of position marks 1416 are provided on the conductive sheet, and the position marks 1416 are used to locate the wire bonding position so that the conductive sheet is coupled to the pad 120 of the flash memory chip 110 or the external pin 206 at the position marks 1416 .

[0012] In one embodiment of the present disclosure, the width of the conductive sheet at the position mark 1416 is greater than the width of the conductive sheet at a position where the position mark 1416 is not marked.

[0013] In one embodiment of the present disclosure, the conductive sheet includes one or more of an L-shaped conductive sheet 1411, a straight-line conductive sheet 1412, a U-shaped conductive sheet 1413, and a 『-shaped conductive sheet 1414.

[0014] In one embodiment of the present disclosure, the conductive sheet includes an L-shaped conductive sheet 1411, a straight-line conductive sheet 1412, a U-shaped conductive sheet 1413 and a "-shaped conductive sheet 1414, a plurality of the L-shaped conductive sheets 1411 and a plurality of the straight-line conductive sheets 1412 are located inside the "-shaped conductive sheet 1413", and a plurality of spaced-apart balancing sheets 1415 are provided at the opening of the "-shaped conductive sheet 1413".

[0015] In one embodiment of the present disclosure, the semiconductor substrate 143 is a bare silicon wafer or a bare wafer, and the bare silicon wafer is a P-type silicon wafer or an N-type silicon wafer.

[0016] According to another aspect of the present disclosure, a flash memory chip is also provided, including a chip body and a connecting board of the flash memory chip in any of the above-mentioned embodiments, the connecting board 140 having a first surface and a second surface relative to each other, the chip body being arranged on the first surface of the connecting board 140, the connecting board 140 being coupled to the chip body, and the overall size of the connecting board 140 being smaller than the overall size of the chip body.

[0017] In one embodiment of the present disclosure, the connection plate 140 is located at the center of the chip body.

[0018] In one embodiment of the present disclosure, the connecting board 140 further includes: a first connection point group 201 and a second connection point group 202, wherein the first connection point group 201 and the second connection point group 202 are arranged on the second surface of the connecting board 140 and distributed on both sides of the second surface of the connecting board 140, and the first connection point group 201 and the second connection point group 202 both include a plurality of connection points 203, and the connection points 203 are coupled to the conductive layer 141 of the connecting board 140; the chip body includes a plurality of solder pads 120, and the plurality of solder pads 120 are arranged on the side of the surface of the chip body close to the first surface of the connecting board 140; the distance between the plurality of solder pads 120 and the first connection point group 201 is less than the distance to the second connection point group 202, and M of the plurality of solder pads 120 are coupled to the connection points 203 in the first connection point group 201, and the M of the solder pads 120 in the first connection point group 201 are coupled to the connection points 203 in the first connection point group 201. The connection point 203 is coupled to the connection point 203 in the second connection point group 202 through the conductive layer 141; the flash memory chip 110 also includes: a first pin group 204 and a second pin group 205, the first pin group 204 and the second pin group 205 are distributed on two opposite sides of the chip body, the first pin group 204 and the second pin group 205 each include a plurality of external pins 206, the distance between the first pin group 204 and the plurality of solder pads 120 is less than the distance between the second pin group 205 and the plurality of solder pads 120, K solder pads 120 among the plurality of solder pads 120 are coupled to the external pins 206 in the first pin group 204, and the connection point 203 in the second connection point group 202 is coupled to the external pin 206 in the second pin group 205; wherein M and K are both integers greater than or equal to 1, and the sum of M and K is less than or equal to the total number of the plurality of solder pads 120.

[0019] In one embodiment of the present disclosure, the multiple external pins 206 in the first pin group 204 and the multiple solder pads 120 are evenly distributed in a straight line, and two solder pads 120 located on the outside of the multiple solder pads 120 are respectively coupled to the two external pins 206 located on the outside of the first pin group 204, the multiple external pins 206 in the first pin group 204 and K solder pads 120 among the multiple solder pads 120 correspond one by one along the length direction of the chip body, and the solder wires coupled between each group of corresponding solder pads 120 and the external pins 206 are parallel to the length direction of the chip body.

[0020] In one embodiment of the present disclosure, the connection board 140 further includes: a plurality of connection points 203, the plurality of connection points 203 are arranged on the second surface of the connection board 140 and distributed on the outer edge of the connection board 140, and the connection points 203 are coupled to the conductive layer 141 of the connection board 140; the flash memory chip 110 further includes: a first pin group 204 and a second pin group 205, the first pin group 204 and the second pin group 205 are distributed on opposite sides of the chip body, and the first pin group 204 and the second pin group 205 each include a plurality of external pins 206; the chip body includes a plurality of pads 120, the plurality of pads 120 20 is arranged on the surface side of the first surface of the chip body close to the connecting board 140, the multiple solder pads 120 are located between the first pin group 204 and the second pin group 205, T solder pads 120 among the multiple solder pads 120 are coupled to some external pins 206 in the first pin group 204, E solder pads 120 among the multiple solder pads 120 are coupled to some external pins 206 in the second pin group 205, and Q solder pads 120 among the multiple solder pads 120 are coupled to the connection point 203; wherein T, E and Q are all integers greater than or equal to 1, and the sum of T, E and Q is less than or equal to the total number of the multiple solder pads 120.

[0021] According to another aspect of the present disclosure, a method for preparing a connecting plate is also provided, including: providing a semiconductor substrate 143; coating an insulating layer solution on the semiconductor substrate 143, and performing a curing treatment to form an insulating layer 142; coating a photoresist on the insulating layer 142, and performing exposure, development, electroplating, photoresist removal, and etching through a mask to form a conductive layer 141.

[0022] In one embodiment of the present disclosure, after coating the insulating layer solution on the semiconductor substrate 143 and performing a curing treatment to form the insulating layer 142, the method for preparing the connecting plate further includes: forming a connecting layer between the insulating layer 142 and the conductive layer 141; wherein the connecting layer includes a first metal layer 1610 and a second metal layer 1620, the first metal layer 1610 is made of titanium, and the second metal layer 1620 is made of copper.

[0023] In one embodiment of the present disclosure, the conductive layer 141 includes a plurality of conductive sheets of different shapes, including one or more of an L-shaped conductive sheet 1411, a straight-line conductive sheet 1412, a U-shaped conductive sheet 1413 and a 『-shaped conductive sheet 1414, and the conductive sheet is a copper sheet.

[0024] In an embodiment of the present disclosure, a connection board of a flash memory chip includes an insulating layer, a semiconductor substrate and a conductive layer. The insulating layer has a first surface and a second surface relative to each other; the semiconductor substrate is arranged on the first surface of the insulating layer; the conductive layer is arranged on the second surface of the insulating layer, and the conductive layer includes a plurality of conductive sheets of different shapes, which are distributed at different positions on the second surface of the insulating layer, so that the pads of the flash memory chip are coupled to the external pins through the conductive sheets, so as to reduce the proportion of the welding wires crossing the flash memory chip. The present disclosure connects the signals on the pads of the flash memory chip to the external pins through the conductive sheets of the conductive layer in the connecting board, for example, the pads on one side of the frame are connected to the external pins on the other side of the frame through the conductive sheets. Thereby, the length of the welding wire used for coupling between the pads and the external pins is shortened, the proportion of crossing the flash memory chip is reduced, the wire arc is low, and the packaging risk is low.

[0025] Furthermore, the conductive layer includes a plurality of conductive sheets of different shapes, which are distributed at different positions on the second surface of the insulating layer. With this layout, the pads of the flash memory chip can be coupled to external pins at any position through the conductive sheets of the connecting board as needed, thereby expanding the application range of the connecting board. The insulating layer can reduce the risk of high temperature leakage.

[0026] Furthermore, the present disclosure reduces the thickness of the connection plate formed by arranging an insulating layer and a conductive layer on a semiconductor substrate, thereby reducing the thickness of the package and improving the compactness and reliability of the package.

[0027] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0029] Figure 1 A schematic diagram showing a flash memory chip and pad locations.

[0030] Figure 2 A connection diagram of a flash memory chip provided by an embodiment of the present disclosure is shown.

[0031] Figure 3 A schematic diagram of the structure of a connection board of a flash memory chip provided in one embodiment of the present disclosure is shown.

[0032] Figure 4 A schematic structural diagram of a connection board of a flash memory chip provided in another embodiment of the present disclosure is shown.

[0033] Figure 5 A schematic structural diagram of a connection board of a flash memory chip provided in yet another embodiment of the present disclosure is shown.

[0034] Figure 6 A schematic structural diagram of a connection board of a flash memory chip provided in yet another embodiment of the present disclosure is shown.

[0035] Figure 7 A schematic structural diagram of a connection board of a flash memory chip provided in yet another embodiment of the present disclosure is shown.

[0036] Figure 8 A schematic structural diagram of a connection board of a flash memory chip provided in yet another embodiment of the present disclosure is shown.

[0037] Fig. 9 A schematic structural diagram of a connection board of a flash memory chip provided in yet another embodiment of the present disclosure is shown.

[0038] Fig.10 A schematic structural diagram of a conductive layer provided in one embodiment of the present disclosure is shown.

[0039] Fig.11 A schematic structural diagram of a conductive layer provided in another embodiment of the present disclosure is shown.

[0040] Fig.12 A schematic structural diagram of a conductive layer provided in yet another embodiment of the present disclosure is shown.

[0041] Fig.13 A schematic diagram of a structure in which a flash memory chip is connected to a connection board according to an embodiment of the present disclosure is shown.

[0042] Fig.14 A schematic diagram of a structure in which a flash memory chip is connected to a connection board according to an embodiment of the present disclosure is shown.

[0043] Fig.15 A flow chart of a method for preparing a connecting plate provided in an embodiment of the present disclosure is shown.

[0044] Fig.16 A schematic diagram of a preparation process of a connecting plate provided in an embodiment of the present disclosure is shown.

[0045] The reference numerals are described as follows:

[0046] 110, flash memory chip; 120, solder pad; 130, frame; 140, connecting board; 141, conductive layer; 1410, copper layer; 1411, L-shaped conductive sheet; 1412, straight conductive sheet; 1413, U-shaped conductive sheet; 1414, 『-shaped conductive sheet; 1415, balance sheet; 1416, position mark; 142, insulating layer; 1421, silicon oxide insulating layer; 1422, polyimide layer; 143, semiconductor substrate; 1431, silicon substrate; 144, third insulating layer; 201, first connection point group; 202, second connection point group; 203, connection point; 204, first pin group; 205, second pin group; 206, external pin; 1610, first metal layer; 1620, second metal layer; 1630, photoresist layer; 1640, RDL layer. DETAILED DESCRIPTION

[0047] The preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0048] The terms "first" and "second" in this document are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly stated that it is a limitation.

[0049] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0050] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed.

[0051] As used in the present disclosure, the term "semiconductor substrate 143" refers to a material on which subsequent materials are added or otherwise disposed. The semiconductor substrate 143 may also be referred to as a core layer. The material disposed on the semiconductor substrate 143 (e.g., the first surface and the second surface of the semiconductor substrate 143) may be patterned or may remain unpatterned. In addition, the semiconductor substrate 143 may be a silicon substrate 1431, a silicon carbon substrate, a gallium nitride substrate, a gallium arsenide substrate, etc., and the material type of the semiconductor substrate 143 may be determined according to the application scenario.

[0052] As used in the present disclosure, the term "layer" refers to a portion of a material including an area having a thickness, and a layer may extend over the entirety of a lower or upper structure, or may have a range that is less than the range of a lower or upper structure. In addition, a layer may be a region of a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. The semiconductor substrate 143 may be a layer, which may include one or more layers, and / or may have one or more layers thereon, above, and / or below. A layer may include a plurality of layers. For example, the insulating layer 142 may include a first insulating layer and a second insulating layer.

[0053] As used in the present disclosure, “connector plate 140” has a plurality of material layers oriented vertically on a laterally oriented semiconductor substrate 143, such that the material layers extend in a vertical direction relative to the semiconductor substrate 143. As used herein, the term “vertical / vertically” means perpendicular to a lateral surface of the semiconductor substrate 143.

[0054] As used herein, the terms “horizontal / horizontally / lateral / laterally” represent a lateral surface parallel to the semiconductor substrate 143, such as a relative first surface or a second surface of the insulating layer 142, i.e., a surface defined by a plane containing a first direction D1 and a second direction D2 in the drawings; and the terms “vertical” or “vertically” represent a lateral surface perpendicular to the insulating layer 142, such as a direction represented by a third direction D3 in the drawings.

[0055] It should be noted that the bonding wire refers to a metal wire used to connect the flash memory chip 110 and the external circuit (such as the pin of the external circuit, referred to as the external pin 206) during the electronic packaging process. It can be made of materials such as gold, silver, and aluminum, and has good conductivity and a high melting point to ensure that a stable electrical connection can be maintained when the electronic device is working.

[0056] In the field of semiconductor technology, Figure 1 As shown, when the pad 120 of the flash memory chip 110 is located on one side of the flash memory chip 110, since the flash memory chip 110 is mounted on the frame 130, the pad 120 of the flash memory chip 110 is also located on one side of the frame 130, and the external pins 206 (pin 1, pin 2, pin 3, pin 4) located on one side of the frame 130 are coupled to the pad 120 on the flash memory chip 110 through welding wires. The external pins 206 (pin 5, pin 6, pin 7, pin 8) located on the other side of the frame 130 are coupled to the pad 120 on the flash memory chip 110 through welding wires. When the welding wire connects the signal to the external pins 206 (pin 5, pin 6, pin 7, pin 8) on the other side of the frame 130, the welding wire is usually required to span more than 90% of the length of the entire flash memory chip 110. This design will cause the arc length of the welding wire to be too long and the height to be high, increasing the risk of wire punching or wire collapse during the packaging process. At the same time, this structure will increase the thickness of the overall package, thereby affecting the compactness and reliability of the package.

[0057] In the related art, the above problem is solved by modifying the flash memory chip 110 to add a pad 120, which will increase the size of the flash memory chip 110 and increase the cost.

[0058] The connection board 140 in the present disclosure can be used to connect different chips, interconnect lines, and change the connection position of the pad 120 to enhance the packaging performance of the centralized circuit. Figure 2 As shown, the present disclosure adds a connection board 140 on the flash memory chip 110 to replace the longer bonding wires to connect the signal to the external pins 206 on the other side of the frame 130 , thereby reducing the ratio across the flash memory chip 110 .

[0059] In one embodiment, the connecting plate 140 is a substrate-type adapter plate, which is made by a lamination process (laminate). For example, the lamination process can be a tenting process or a modified semi-additive process (MSAP process).

[0060] The inventors have found that the substrate-type adapter board made by lamination process is complicated in process and large in size, which is not conducive to packaging. In the flash memory chip 110 with high density interconnection requirements, the use of the substrate-type adapter board to change the position of the pad 120 cannot meet the connection requirements of the high-performance flash memory chip 110.

[0061] In order to solve the above problems, the present disclosure provides a connection board 140 of a flash memory chip 110, which includes an insulating layer 142 having a first surface and a second surface opposite to each other; a semiconductor substrate 143, which is disposed on the first surface of the insulating layer 142; and a conductive layer 141, which is disposed on the second surface of the insulating layer 142. The conductive layer 141 includes a plurality of conductive sheets of different shapes, which are distributed at different positions on the second surface of the insulating layer 142, so that the pads 120 of the flash memory chip 110 are coupled to the external pins 206 through the conductive sheets, so as to reduce the proportion of the bonding wires across the flash memory chip 110. The present disclosure can not only meet the requirements of the flash memory chip 110 in terms of size, but also meet the requirements of high-density interconnection. Since the conductive layer 141 includes multiple conductive sheets, and the conductive sheets are distributed at different positions of the insulating layer 142, the flash memory chip 110 can connect the signal on the pad 120 of the flash memory chip 110 to the external pin 206 at different positions through the conductive sheet of the conductive layer 141 of the connecting board 140 according to different needs, and there is no crossing of the welding wires coupling the external pin 206 and the connecting board 140, thereby reducing coupling interference, thereby achieving further improvement in the performance of the flash memory chip 110 while meeting the size requirements of the flash memory chip 110.

[0062] In addition, since the conductive layer 141 of the connection board 140 has a plurality of conductive sheets with different shapes and distribution positions, the application range of the connection board 140 can be increased. In other words, the connection board 140 can be used on different types of flash memory chips 110 .

[0063] In the embodiment of the present disclosure, the thickness of the connection plate 140 formed by providing an insulating layer 142 and a conductive layer 141 on a semiconductor substrate 143 is small, thereby reducing the thickness of the package and improving the compactness and reliability of the package.

[0064] The present disclosure is described in detail below with reference to the accompanying drawings and embodiments.

[0065] Figure 3 A schematic diagram showing the structure of a connection board of a flash memory chip provided by an embodiment of the present disclosure is shown in FIG. Figure 3 As shown, the connection board 140 of the flash memory chip 110 includes a conductive layer 141 , an insulating layer 142 and a semiconductor substrate 143 .

[0066] In the present disclosure, the first direction D1 is the long side direction of the connecting plate 140 , the second direction D2 is the short side direction of the connecting plate 140 , and the third direction D3 is the thickness direction of the connecting plate 140 , wherein the first direction, the second direction and the third direction are perpendicular to each other.

[0067] The insulating layer 142 has a first surface and a second surface relative to each other; the first surface and the second surface are surfaces arranged along the third direction D3. The insulating layer 142 can be an oxide layer, or a polymer material layer. Exemplarily, the material of the oxide layer can include any one of silicon oxide (such as silicon dioxide), titanium oxide, aluminum oxide, zirconium oxide, copper oxide and chromium oxide. The material of the polymer material layer can include any one of polyethylene, polyvinyl chloride, polytetrafluoroethylene and polyimide. It should be noted that the oxide layer is made of an oxide material. The polymer material layer is made of a polymer material.

[0068] The semiconductor substrate 143 is disposed on the first surface of the insulating layer 142; the semiconductor substrate 143 is the supporting portion of the connecting plate 140, and can support other connecting layers (such as the conductive layer 141 and the insulating layer 142). The shape of the semiconductor substrate 143 can be a rectangular block. The material of the semiconductor substrate 143 can be any one of silicon, silicon carbon, gallium nitride and gallium arsenide, and the material type of the semiconductor substrate 143 can be determined according to the application scenario. The semiconductor substrate 143 can be a bare silicon wafer or a bare wafer, and the bare silicon wafer can be a P-type silicon wafer or an N-type silicon wafer. It should be noted that the P-type silicon wafer is manufactured by doping a trivalent element (such as boron) into a silicon crystal, and the N-type silicon wafer is manufactured by doping a pentavalent element (such as phosphorus) into a silicon crystal.

[0069] The conductive layer 141 is disposed on the second surface of the insulating layer 142. The conductive layer 141 may include a plurality of conductive sheets of different shapes, which are distributed at different positions on the second surface of the insulating layer 142, so that the flash memory chip 110 is coupled to the conductive sheets from at least one direction of the connecting plate 140. It should be noted that there is a gap between any two adjacent conductive sheets among the plurality of conductive sheets.

[0070] The material of the conductive layer 141 may include one or more combinations of copper, silver, and gold. In the embodiment of the present disclosure, the conductive layer 141 may be a patterned circuit layer formed by etching according to actual needs.

[0071] It should be noted that, in order to increase the adhesion between the conductive layer 141 and the insulating layer 142, a first metal layer 1610 and a second metal layer 1620 may be sputtered (a semiconductor process) between the conductive layer 141 and the insulating layer 142. The first metal layer 1610 is made of titanium, and the second metal layer 1620 is made of copper. Exemplarily, in the third direction D3, the insulating layer 142, the first metal layer 1610, the second metal layer 1620 and the conductive layer 141 are distributed from bottom to top.

[0072] It should be noted that the connection board 140 in the embodiment of the present disclosure is made by making an insulating layer 142 and a conductive layer 141 on a semiconductor substrate 143 (such as a silicon wafer), that is, a redistribution layer (RDL) is made on the semiconductor substrate 143, and the insulating layer 142 and the conductive layer 141 are the made redistribution layers, so the thickness of the connection board 140 is very small. For example, the thickness of the connection board 140 is between 200 microns and 800 microns (0.2 mm to 0.8 mm), so that the package thickness can be reduced and the compactness and reliability of the package can be improved.

[0073] The connection board 140 of the disclosed embodiment can not only meet the requirements of the flash memory chip 110 in terms of size, but also meet the requirements of high-density interconnection. Since the conductive layer 141 includes a plurality of conductive sheets, and the conductive sheets are distributed at different positions of the insulating layer 142, the pads 120 and the external pins 206 of the flash memory chip 110 can be connected to different or the same conductive sheets on the connection board 140 from different positions according to the requirements, and there is no crossover of the bonding wires used for connection, thereby reducing coupling interference, thereby achieving the performance of the flash memory chip 110 is further improved under the premise of meeting the size requirements of the flash memory chip 110.

[0074] In addition, since the conductive layer 141 of the connection board 140 has a plurality of conductive sheets with different shapes and distribution positions, the application range of the connection board 140 can be increased. In other words, the connection board 140 can be used on different types of flash memory chips 110 .

[0075] In the embodiment of the present disclosure, the thickness of the connection plate 140 formed by providing an insulating layer 142 and a conductive layer 141 on a semiconductor substrate 143 is small, thereby reducing the thickness of the package and improving the compactness and reliability of the package.

[0076] In the disclosed embodiment, the flash memory chip 110 uses the connecting board 140 to replace the longer welding wires to connect the signal to the external pins 206 on the other side of the frame 130, which can reduce the ratio of the flash memory chip 110 across the flash memory chip 110, reduce wire arcs, and reduce packaging risks.

[0077] In an exemplary embodiment, the insulating layer 142 may include a first insulating layer, and the first insulating layer is a polymer material layer or an oxide layer. Exemplarily, the first insulating layer is a polyimide layer 1422 or a silicon oxide insulating layer 1421 .

[0078] In one embodiment, if Figure 4 As shown, the first insulating layer is a silicon oxide insulating layer 1421, the semiconductor substrate 143 is a silicon substrate 1431, and the conductive layer 141 is a copper layer 1410. The connecting board 140 of a flash memory chip 110 provided in an embodiment of the present disclosure may include a silicon substrate 1431, a silicon oxide insulating layer 1421 and a copper layer 1410 arranged from bottom to top along a third direction D3.

[0079] The connecting plate 140 in the embodiment of the present disclosure has a simple structure and is easy to manufacture. By connecting the connecting plate 140 in the embodiment of the present disclosure to the flash memory chip 110, the ratio of the flash memory chip 110 crossing can be reduced, the arc is reduced, and the packaging risk is low.

[0080] In another embodiment, if Figure 5 As shown, the first insulating layer is a polyimide layer 1422 (also called a PI insulating layer), the semiconductor substrate 143 is a silicon substrate 1431, and the conductive layer 141 is a copper layer 1410. The connecting board 140 of a flash memory chip 110 provided in an embodiment of the present disclosure may include a silicon substrate 1431, a polyimide layer 1422 and a copper layer 1410 arranged from bottom to top along a third direction D3.

[0081] The embodiment of the present disclosure sets a polyimide layer 1422 between the conductive layer 141 and the semiconductor substrate 143, which solves the problem of high temperature leakage risk of the silicon oxide insulating layer 1421. By connecting the connection board 140 of the embodiment of the present disclosure to the flash memory chip 110, the ratio of crossing the flash memory chip 110 can be reduced, the line arc is low, and the packaging risk is low.

[0082] In another exemplary embodiment, the insulating layer 142 may include a first insulating layer and a second insulating layer. The first insulating layer has a first surface and a second surface opposite to each other, and the second surface of the first insulating layer is the second surface of the insulating layer 142; the second insulating layer is disposed on the first surface of the first insulating layer; wherein the first insulating layer is a polymer material layer, and the second insulating layer is an oxide layer. For example, Figure 6 As shown, the first insulating layer is a polyimide layer 1422, and the second insulating layer is a silicon oxide insulating layer 1421. A connection board 140 of a flash memory chip 110 provided in an embodiment of the present disclosure may include a silicon substrate 1431, a silicon oxide insulating layer 1421, a polyimide layer 1422, and a copper layer 1410 arranged from bottom to top along a third direction D3.

[0083] In the embodiment of the present disclosure, a polymer material layer and an oxide layer are disposed between the conductive layer 141 and the semiconductor substrate 143 , which can further enhance the insulation effect.

[0084] The embodiment of the present disclosure sets a polyimide layer 1422 and a silicon oxide insulating layer 1421 between the conductive layer 141 and the semiconductor substrate 143, which solves the problem of high temperature leakage risk of the silicon oxide insulating layer 1421. By connecting the connection board 140 of the embodiment of the present disclosure to the flash memory chip 110, the ratio of crossing the flash memory chip 110 can be reduced, the arc is low, and the packaging risk is low.

[0085] In another exemplary embodiment, the connection plate 140 may further include a third insulating layer 144 disposed on the conductive layer 141. That is, the third insulating layer 144 is disposed on a side of the conductive layer 141 away from the insulating layer 142. The third insulating layer 144 is a polymer material layer. Exemplarily, the third insulating layer 144 is a polyimide layer 1422.

[0086] In the embodiment of the present disclosure, a third insulating layer 144 is provided on the conductive layer 141 to prevent the conductive layer 141 from being exposed to the outside, thereby solving the risk of short circuit caused by metallic foreign matter.

[0087] In the disclosed embodiment, the third insulating layer 144 extends downward along the third direction D3 and fills between two adjacent conductive sheets on the conductive layer 141, so as to further isolate the two adjacent conductive sheets, reduce the coupling between the conductive sheets, and further improve the working performance of the connecting board 140 and the flash memory chip 110 using the connecting board 140.

[0088] In one embodiment, if Figure 7 As shown, the connecting board 140 may further include a third insulating layer 144, the semiconductor substrate 143 is a silicon substrate 1431, and the conductive layer 141 is a copper layer 1410. The connecting board 140 of a flash memory chip 110 provided in an embodiment of the present disclosure may include a silicon substrate 1431, a silicon oxide insulating layer 1421, a copper layer 1410 and a third insulating layer 144 arranged from bottom to top along a third direction D3, wherein the third insulating layer 144 may be a polyimide layer 1422, but the embodiments of the present disclosure are not limited thereto.

[0089] The third insulating layer 144 of the embodiment of the present disclosure is used to protect the conductive layer 141 and prevent the conductive layer 141 from being exposed, thereby solving the problem of short circuit risk caused by foreign matter in the conductive layer 141 .

[0090] In another embodiment, if Figure 8As shown, the connecting board 140 may further include a third insulating layer 144, the semiconductor substrate 143 is a silicon substrate 1431, and the conductive layer 141 is a copper layer 1410. The connecting board 140 of a flash memory chip 110 provided in an embodiment of the present disclosure may include a silicon substrate 1431, a polyimide layer 1422, a copper layer 1410 and a third insulating layer 144 arranged from bottom to top along a third direction D3, wherein the third insulating layer 144 is a polyimide layer 1422, but the embodiments of the present disclosure are not limited to this.

[0091] The third insulating layer 144 of the embodiment of the present disclosure is used to protect the conductive layer 141 and prevent the conductive layer 141 from being exposed, thereby solving the problem of short circuit risk caused by the presence of foreign matter in the conductive layer 141. The polyimide layer 1422 located between the silicon substrate 1431 and the copper layer 1410 can effectively prevent the risk of high-temperature leakage.

[0092] In yet another embodiment, Fig. 9 As shown, the connecting board 140 may also include a third insulating layer 144, the semiconductor substrate 143 is a silicon substrate 1431, and the conductive layer 141 is a copper layer 1410. The connecting board 140 of a flash memory chip 110 provided in an embodiment of the present disclosure may include a silicon substrate 1431, a silicon oxide insulating layer 1421, a polyimide layer 1422, a copper layer 1410 and a third insulating layer 144 arranged from bottom to top along a third direction D3, wherein the third insulating layer 144 is a polyimide layer 1422.

[0093] The third insulating layer 144 of the embodiment of the present disclosure is used to protect the conductive layer 141 and prevent the conductive layer 141 from being exposed, thereby solving the problem of short circuit risk caused by the presence of foreign matter in the conductive layer 141. The polyimide layer 1422 located between the silicon substrate 1431 and the copper layer 1410 can effectively prevent the risk of high-temperature leakage.

[0094] The stacked structure of the connection plate 140 is described above, and the conductive layer 141 of the connection plate 140 is described below through exemplary embodiments.

[0095] like Figure 10-12 As shown, the conductive layer 141 may include a plurality of conductive sheets of different shapes, and the conductive sheets are distributed at different positions on the second surface of the insulating layer 142. It should be noted that, Figures 10 to 12 It is a schematic diagram of the gradual improvement of the conductive layer 141 disclosed in the present invention.

[0096] like Fig.10 As shown, the third insulating layer 144 covers the conductive layer 141 (due to being covered, Fig.10 ), a window is opened on the third insulating layer 144 ( Fig.10The rectangular frame in the figure is used as a wire bonding pad and NiAu (nickel-gold alloy) is electroplated to complete the wire bonding Pod. It should be noted that the wire bonding Pod is located on the connecting plate 140, not the pad 120 on the flash memory chip 110. Fig.10 It is only a schematic diagram, and the third insulating layer 144 covers the conductive layer 141. Since the conductive sheet is located at a higher position, the conductive sheet protrusion can be seen. In addition, according to the design dimension diagram of the conductive layer 141, the position of the conductive sheet can be determined, thereby determining the position of the window. In order to improve the insulation performance of the insulating layer 142 of the above embodiment at high temperature to avoid high temperature leakage, the following is provided: Fig.11 The conductive layer 141 structure shown in FIG. A polyimide layer 1422 and a silicon oxide insulating layer 1421 are arranged between the conductive layer 141 and the semiconductor substrate 143. The polyimide layer 1422 has excellent high temperature resistance and excellent electrical insulation, thereby improving the high temperature insulation of the insulating layer 142 and eliminating the high temperature leakage phenomenon. In order to reduce the metal coverage and accurately determine the wire bonding position, the following is provided: Fig.12 The conductive layer 141 is shown.

[0097] In an exemplary embodiment, if Fig.12 As shown, the conductive layer 141 may include a plurality of conductive sheets of different shapes, which are distributed at different positions on the second surface of the insulating layer 142. A plurality of position marks 1416 are provided on the conductive sheets, and the position marks 1416 are used to locate the wire bonding positions so that the conductive sheets are coupled to the pads 120 or the external pins 206 of the flash memory chip 110 at the position marks 1416.

[0098] Exemplarily, the width of the conductive sheet at the position mark 1416 is greater than the width of the conductive sheet at the position mark 1416 that is not marked. Adding the position mark 1416, that is, making a special mark on the wire bonding position, is convenient for the operation of the packaging wire bonding equipment (Wire Bonding, WB). After adding the position mark 1416, the coverage of the metal material of the conductive layer 141 can be reduced while meeting the requirements. Since the width of the conductive sheet at the position mark 1416 is greater than the width of other positions of the conductive sheet (the position where the position mark 1416 is not marked), the risk of warpage after wafer thinning can be reduced. It should be noted that the wafer can be a wafer for making a semiconductor substrate 143.

[0099] In one embodiment, if Fig.12 As shown, the conductive sheet may include one or more of an L-shaped conductive sheet 1411, a straight-line conductive sheet 1412, a U-shaped conductive sheet 1413 and a 『-shaped conductive sheet 1414, but the embodiments of the present disclosure are not limited thereto, and the conductive sheet of the required shape can be designed according to requirements.

[0100] The straight conductive sheet 1412 parallel to the first direction D1 facilitates coupling the pad 120 on the flash memory chip 110 located at one end of the straight conductive sheet 1412 with the external pin 206 outside the flash memory chip 110 / frame 130 located at the other end of the straight conductive sheet 1412 (see FIG. Fig.14 ). It should be noted that the frame 130 is an indispensable part of the integrated circuit packaging process, and is responsible for connecting the flash memory chip 110 to the interface of the external circuit. For example, the flash memory chip 110 is connected to the external circuit interface by connecting the external pin 206. The straight conductive sheet 1412 can connect multiple welding wires extending in the same direction (for example, along the first direction D1) together, and can also connect multiple welding wires extending in multiple directions together.

[0101] The U-shaped conductive sheet 1413 facilitates connecting multiple welding wires located outside the U-shaped conductive sheet 1413. Similarly, the '-shaped conductive sheet 1414 and the L-shaped conductive sheet 1411 can also connect multiple welding wires together to achieve signal transmission without the phenomenon of multiple welding wires crossing, thereby facilitating the packaging of the flash memory chip 110 while reducing interference.

[0102] For example, Fig.13 As shown, Fig.13 The connection lines in the figure are used to represent welding wires. The pads 120 on one side of the flash memory chip 110 can be connected to the external pins 206 at various positions through the conductive layer 141 of the connecting board 140 to avoid crossing between the welding wires. It should be noted that the welding pads 120 on one side of the flash memory chip 110 can also be connected to the position where the flash memory chip 110 needs to be connected (except for the overlap between the connecting board 140 and the flash memory chip 110) through the conductive layer 141 of the connecting board 140, so as to further avoid crossing between the welding wires.

[0103] In the embodiment of the present disclosure, multiple conductive sheets are distributed at different positions on the second surface of the insulating layer 142, thereby avoiding the intersection of multiple welding wires to the greatest extent, facilitating the subsequent packaging of the flash memory chip 110, and not easily generating electromagnetic interference, thereby increasing the performance of the flash memory chip 110.

[0104] In the embodiment of the present disclosure, the number of the position marks 1416 is not limited in the embodiment of the present disclosure and can be set according to the actual application scenario and specific application experience. For example, at least two position marks 1416 are set on each conductive sheet.

[0105] In the present disclosure, Fig.14 As shown, a position mark 1416 is added to the conductive sheet, and the conductive sheet connects the signal on one side of the flash memory chip 110 to the external pin 206 on the other side of the frame 130, thereby reducing the ratio across the flash memory chip 110, reducing wire arcs, and reducing packaging risks.

[0106] The disclosed embodiment does not specifically limit the method of adding the position mark 1416. For example, the RDL wiring is specially designed to add the position mark 1416. The position mark 1416 is added to the layer structure on the mask for manufacturing the conductive layer 141, so that the manufactured conductive layer 141 also carries the position mark 1416. The position mark 1416 facilitates the WB packaging operation, improves production efficiency, and reduces production costs.

[0107] It should be noted that during the wire bonding process, a wire bonding pad is made at the required position mark 1416 and NiAu is electroplated. Electroplating NiAu can provide good electrical performance, thermal stability and reliable mechanical adhesion.

[0108] In another embodiment, if Fig.12 As shown, the conductive sheet includes an L-shaped conductive sheet 1411, a straight-line conductive sheet 1412, a U-shaped conductive sheet 1413 and a "-shaped conductive sheet 1414, a plurality of L-shaped conductive sheets 1411 and a plurality of straight-line conductive sheets 1412 are located inside the "-shaped conductive sheet 1413", and a plurality of spaced-apart balancing sheets 1415 are provided at the opening of the "-shaped conductive sheet 1413.

[0109] In the embodiment of the present disclosure, the manufacturing method of the balancing sheet 1415 is the same as the manufacturing method of the conductive sheet, and the material of the balancing sheet 1415 can also be the same as that of the conductive sheet, and it is used to balance the conductive layer 141. Fig.12 As shown, when the U-shaped conductive sheet 1413 is relatively large (for example, the U-shaped conductive sheet 1413 surrounds more than 70% of the area of ​​the conductive layer 141), a plurality of balancing sheets 1415 are arranged at the opening of the U-shaped conductive sheet 1413 to support other layers (for example, the third insulating layer 144) located along the third direction D3 of the conductive layer 141 or a packaging shell for encapsulating the flash memory chip 110.

[0110] The conductive layer 141 is described above, and the following describes how to perform Pod bonding on the connection board 140 .

[0111] In one embodiment, Figure 7 and Fig.10 The combined connecting plate 140 is described, the third insulating layer 144 is covered on the copper layer 1410, and a window is opened on the third insulating layer 144 ( Fig.10 The rectangular frame in the figure is used as a wire bonding pad and NiAu is electroplated to complete the wire bonding Pod. It should be noted that the position of the conductive sheet can be determined according to the design dimension drawing of the conductive layer 141, thereby determining the position of the window.

[0112] In order to improve the insulation performance of the insulation layer 142 of the above embodiment at high temperatures and to avoid high temperature leakage, the next embodiment is provided.

[0113] In one embodiment, Figure 6 and Fig.11 Taking the combined connecting plate 140 as an example, a polyimide layer 1422 and a silicon oxide insulating layer 1421 are arranged between the copper layer 1410 and the silicon substrate 1431. The polyimide layer 1422 has excellent high temperature resistance and excellent electrical insulation, thereby improving the high temperature insulation of the insulating layer 142 and there is no high temperature leakage phenomenon.

[0114] In another embodiment, in order to prevent the copper layer 1410 from being exposed, Figure 6 A third insulating layer 144 is added on the basis of Fig. 9 The structure of the connecting plate 140 shown in FIG. A window is opened on the third insulating layer 144 ( Fig.10 The third insulating layer 144 is used to protect the copper layer 1410 and prevent the copper layer 1410 from being exposed, thereby solving the problem of short circuit risk caused by foreign matter in the conductive layer 141.

[0115] The connection plate 140 manufactured in the above two embodiments can improve the high-temperature insulation of the insulating layer 142 and does not cause high-temperature leakage.

[0116] like Fig.11 Since the conductive layer 141 shown in the figure has no WB wire pad, the WB equipment cannot accurately locate the wire bonding point (i.e., the wire bonding position) during the packaging operation. Fig.11 To solve the problem of the conductive layer 141, the following embodiments are provided.

[0117] In one embodiment, Figure 5 and Fig.12 The combined connecting plate 140 is explained, a position mark 1416 is added to the conductive sheet of the conductive layer 141, and a special mark for the wire bonding position of the position mark 1416 is added to facilitate the packaging WB operation. After adding the position mark 1416, the coverage of the metal material of the conductive layer 141 can be reduced while meeting the requirements. Since the width of the conductive sheet at the position mark 1416 is greater than the width of other positions of the conductive sheet (the position where the position mark 1416 is not marked), the risk of warping after wafer thinning can be reduced. It should be noted that the wafer can be a wafer for making a semiconductor substrate 143.

[0118] In the embodiment of the present disclosure, in order to prevent the conductive layer 141 from being exposed to the outside, Figure 5 A third insulating layer 144 is added on the basis of.

[0119] In another embodiment, Figure 6 and Fig.12The combined connecting plate 140 is explained, and a position mark 1416 is added to the conductive sheet of the conductive layer 141, and a special mark for the wire bonding position of the position mark 1416 is added to facilitate the packaging WB operation. After adding the position mark 1416, the coverage of the metal material of the conductive layer 141 can be reduced while meeting the requirements. Since the width of the conductive sheet of the position mark 1416 is greater than the width of other positions of the conductive sheet, the risk of warping after wafer thinning can be reduced. It should be noted that the wafer can be a wafer for making a semiconductor substrate 143.

[0120] In the embodiment of the present disclosure, in order to prevent the conductive layer 141 from being exposed to the outside, Figure 6 A third insulating layer 144 is added on the basis of.

[0121] The connection plates 140 manufactured in the above four embodiments can improve the high-temperature insulation of the insulating layer 142 , and there is no high-temperature leakage phenomenon.

[0122] It should be noted that the connection board 140 disclosed in the present invention is not limited to being applied to static memory, but can also be applied to other chips.

[0123] Based on the same inventive concept, the present disclosure also provides a flash memory chip 110, which includes the connection board 140 in the above embodiment, as described in the following embodiment. Therefore, the implementation of the flash memory chip 110 embodiment can refer to the implementation of the above connection board 140 embodiment, and the repeated parts will not be repeated.

[0124] A flash memory chip 110 provided in an embodiment of the present disclosure includes a chip body and a connecting plate 140 of the flash memory chip 110 in the above-mentioned embodiment, the connecting plate 140 having a first surface and a second surface opposite to each other, the chip body being arranged on the first surface of the connecting plate 140, the connecting plate 140 being coupled to the chip body, and the overall size of the connecting plate 140 being smaller than the overall size of the chip body. It should be noted that the chip body can be understood as the flash memory chip 110 not including the connecting plate 140. The flash memory chip 110 in the related art does not have the connecting plate 140, so the chip body is used here to refer to the flash memory chip 110 not including the connecting plate 140.

[0125] In the disclosed embodiment, the overall size of the connecting plate 140 is smaller than the overall size of the chip body, that is, the length of the connecting plate 140 is smaller than the length of the chip body, and the width of the connecting plate 140 is smaller than the width of the chip body. It should be noted that the connecting plate 140 and the chip body are connected by welding wires to facilitate signal transmission.

[0126] The present disclosure does not limit the location of the connection plate 140 on the chip body, as long as it can achieve no or less crossover of the welding wires used for connection and a low arc. For example, the connection plate 140 is located at the center of the chip body. Fig.13 and Fig.14 As shown, the connecting plate 140 is located at the center of the chip body, which can make the welding wires gather toward the center and the wire arc is low, so that the size of the connecting plate 140 can be further reduced, and the number of connecting plates 140 produced on the same wafer can be increased, thereby reducing production costs.

[0127] It should be noted that the geometric center of the connecting plate 140 and the geometric center of the flash memory chip 110 are distributed vertically along the third direction D3.

[0128] In one embodiment, the insulating layer 142 includes a first insulating layer, and the first insulating layer is a polymer material layer or an oxide layer.

[0129] In one embodiment, the insulating layer 142 includes: a first insulating layer having a first surface and a second surface opposite to each other, the second surface of the first insulating layer being the second surface of the insulating layer 142; a second insulating layer disposed on the first surface of the first insulating layer; wherein the first insulating layer is a polymer material layer, and the second insulating layer is an oxide layer. Exemplarily, the first insulating layer is a polyimide layer 1422, and the second insulating layer is a silicon oxide insulating layer 1421.

[0130] In one embodiment, the connecting plate 140 further includes: a third insulating layer 144 disposed on the conductive layer 141 , wherein the third insulating layer 144 is a polymer material layer.

[0131] In one embodiment, a plurality of position marks 1416 are disposed on the conductive sheet, and the position marks 1416 are used to locate the bonding position so that the conductive sheet is coupled to the pad 120 of the flash memory chip 110 or the external pin 206 at the position mark 1416 .

[0132] In one embodiment, the width of the conductive sheet at the position mark 1416 is greater than the width of the conductive sheet at a position where the position mark 1416 is not marked.

[0133] In one embodiment, the conductive sheet includes one or more of an L-shaped conductive sheet 1411, a straight-line conductive sheet 1412, a U-shaped conductive sheet 1413, and a '-shaped conductive sheet 1414.

[0134] In one embodiment, the conductive sheet includes an L-shaped conductive sheet 1411, a straight-line conductive sheet 1412, a U-shaped conductive sheet 1413 and a "-shaped conductive sheet 1414, a plurality of L-shaped conductive sheets 1411 and a plurality of straight-line conductive sheets 1412 are located inside the U-shaped conductive sheet 1413, and a plurality of spaced-apart balancing sheets 1415 are provided at the opening of the U-shaped conductive sheet 1413.

[0135] In one embodiment, the semiconductor substrate 143 is a bare silicon wafer or a bare wafer, and the bare silicon wafer may be a P-type silicon wafer or an N-type silicon wafer.

[0136] In one embodiment, the connecting board 140 may further include: a first connection point group 201 and a second connection point group 202, the first connection point group 201 and the second connection point group 202 are arranged on the second surface of the connecting board 140 and distributed on both sides of the second surface of the connecting board 140, the first connection point group 201 and the second connection point group 202 both include a plurality of connection points 203, the connection points 203 are coupled to the conductive layer 141 of the connecting board 140, it should be noted that, in some embodiments, the connection points 203 are coupled to the position marks 1416 of the conductive sheets of the conductive layer 141; the chip body includes a plurality of solder pads 120, the plurality of solder pads 120 are arranged on the surface side of the chip body close to the first surface of the connecting board 140; the distance from the plurality of solder pads 120 to the first connection point group 201 is less than the distance to the second connection point group 202, and M of the plurality of solder pads 120 are connected to the first connection point group 201. The connection point 203 is coupled, and the connection point 203 in the first connection point group 201 is coupled to the connection point 203 in the second connection point group 202 through the conductive layer 141; the flash memory chip 110 also includes: a first pin group 204 and a second pin group 205, the first pin group 204 and the second pin group 205 are distributed on opposite sides of the chip body, the first pin group 204 and the second pin group 205 both include multiple external pins 206, the distance between the first pin group 204 and the multiple pads 120 is smaller than the distance between the second pin group 205 and the multiple pads 120, K pads 120 out of the multiple pads 120 are coupled to the external pins 206 in the first pin group 204, and the connection point 203 in the second connection point group 202 is coupled to the external pin 206 in the second pin group 205; wherein M and K are both integers greater than or equal to 1, and the sum of M and K is less than or equal to the total number of the multiple pads 120.

[0137] In the embodiment of the present disclosure, there is no specific limitation on the number of M and K, and they can be adaptively determined according to needs.

[0138] For example, Figure 2As shown, M=4, K=4, there are a total of 10 solder pads 120 on the chip body, and a first connection point group 201 and a second connection point group 202 are arranged on the second surface (e.g., the top surface) of the connecting board 140. The first connection point group 201 and the second connection point group 202 are distributed on both sides of the second surface of the connecting board 140. That is to say, the first connection point group 201 and the second connection point group 202 are distributed on both sides of the top surface of the connecting board 140, and the first connection point group 201 and the second connection point group 202 both include multiple connection points 203. A plurality of solder pads 120 are arranged on one side of the surface of the first surface of the chip body close to the connecting board 140; a distance between the plurality of solder pads 120 and the first connection point group 201 is smaller than a distance between the plurality of solder pads 120 and the second connection point group 202, four solder pads 120 among the plurality of solder pads 120 are coupled to a connection point 203 in the first connection point group 201, and a connection point 203 in the first connection point group 201 is coupled to a connection point 203 in the second connection point group 202 through a conductive layer 141. It should be noted that the coupling between the connection point 203 in the first connection point group 201 and the connection point 203 in the second connection point group 202 is achieved through a conductive sheet in the conductive layer 141. The flash memory chip 110 also includes: a first pin group 204 (pin 1, pin 2, pin 3, pin 4) and a second pin group 205 (pin 5, pin 6, pin 7, pin 8). The first pin group 204 and the second pin group 205 are distributed on opposite sides of the chip body. The first pin group 204 and the second pin group 205 both include multiple external pins 206. The distance between the first pin group 204 and the multiple solder pads 120 is smaller than the distance between the second pin group 205 and the multiple solder pads 120. Four solder pads 120 among the multiple solder pads 120 are coupled to the external pins 206 in the first pin group 204, and the connection point 203 in the second connection point group 202 is coupled to the external pin 206 in the second pin group 205. The multiple solder pads 120 are coupled to the external pins 206 in the second pin group 205 located at a farther distance through the connecting board 140, spanning the flash memory chip 110, thereby reducing the proportion of spanning the flash memory chip 110, with low wire arc and low packaging risk. In addition, the connecting plate 140 has a heat dissipation function, which can accelerate the heat dissipation of the flash memory chip 110 and ensure the working performance of the flash memory chip 110.

[0139] It should be noted that the connection point 203 is a point connected to the conductive sheet in the conductive layer 141 (such as the bonding Pod at the bonding position mentioned above).

[0140] In order to increase the packaging strength of the flash memory chip 110, the flash memory chip 110 may further include a frame 130 for mounting the chip body, the chip body is configured on the frame 130, and the frame 130 is used to support the chip body, thereby increasing the mechanical strength of the flash memory chip 110 and reducing the probability of damage to the flash memory chip 110. The embodiment of the present disclosure can connect the signal to the external pin 206 outside the frame 130 through the connecting board 140, reduce the proportion of the flash memory chip 110, reduce the arc, and reduce the packaging risk.

[0141] To further reduce packaging risks, such as Figure 2 As shown, the plurality of external pins 206 and the plurality of pads 120 in the first pin group 204 are evenly distributed in a straight line, and the two pads 120 located on the outside of the plurality of pads 120 are respectively coupled to the two external pins 206 located on the outside of the first pin group 204, and the plurality of external pins 206 in the first pin group 204 and the K (for example, Figure 2 The plurality of pads 120 correspond to each other along the length direction of the chip body (for example, the first direction D1), and the bonding wires coupled between each group of corresponding pads 120 and the external pins 206 are parallel to the length direction of the chip body. It should be noted that the plurality of external pins 206 in the first pin group 204 and the corresponding pads 120 are aligned along the length direction of the chip body, which can not only shorten the length of the bonding wires used for coupling between the plurality of external pins 206 in the first pin group 204 and the corresponding pads 120, save production costs, but also reduce packaging risks.

[0142] The above exemplary embodiment is an implementation form of the present disclosure, and the present disclosure is not limited thereto. For example, another implementation form of the present disclosure is as follows: Fig.13 As shown, multiple pads 120 on the chip body are located on one side of the chip body, and the bonding wires on the pads 120 can be coupled to external pins 206 (pin 1, pin 2, pin 3, pin 4, pin 5, pin 6, pin 7 and pin 8) distributed on both sides of the pads 120 through the connecting board 140.

[0143] In one embodiment, the connection board 140 may further include: a plurality of connection points 203, which are arranged on the second surface of the connection board 140 and distributed on the outer edge of the connection board 140, and the connection points 203 are coupled to the conductive layer 141 of the connection board 140. It should be noted that in some embodiments, the connection points 203 are located at the position mark 1416 of the conductive sheet of the conductive layer 141. Fig.13 As shown, the connection points 203 are distributed at the outer edge of the connection board 140, which is conducive to connecting the external pins 206, thereby reducing the proportion of the pads 120 connecting the external pins 206 across the flash memory chip 110, reducing line arcs and packaging risks.

[0144] The flash memory chip 110 further includes: a first pin group 204 and a second pin group 205 . The first pin group 204 and the second pin group 205 are distributed on two opposite sides of the chip body. The first pin group 204 and the second pin group 205 both include a plurality of external pins 206 .

[0145] The chip body includes a plurality of solder pads 120, and the plurality of solder pads 120 are arranged on a surface side of the first surface of the chip body close to the connecting board 140, and the plurality of solder pads 120 are located between the first pin group 204 and the second pin group 205. T solder pads 120 among the plurality of solder pads 120 are coupled to some external pins 206 in the first pin group 204, E solder pads 120 among the plurality of solder pads 120 are coupled to some external pins 206 in the second pin group 205, and Q solder pads 120 among the plurality of solder pads 120 are coupled to the connection point 203; wherein T, E and Q are all integers greater than or equal to 1, and the sum of T, E and Q is less than or equal to the total number of the plurality of solder pads 120.

[0146] In the embodiments of the present disclosure, there is no limitation on the number of T, E and Q. They can be set according to actual application scenarios and specific application experience.

[0147] In the embodiment of the present disclosure, a connection board 140 is added to the chip body to connect signals, the proportion of bonding wires crossing the flash memory chip 110 is low, wire arc is low, and packaging risk is low.

[0148] Based on the same inventive concept, the present disclosure also provides a method for preparing a connecting plate 140, as described in the following embodiment. Therefore, the implementation of the preparation method embodiment can refer to the implementation of the connecting plate 140 embodiment described above, and the repeated parts will not be repeated.

[0149] Fig.15 FIG. 1 is a flow chart of a method for preparing a connecting plate according to an embodiment of the present disclosure. Fig.15 As shown, a method for preparing a connecting plate 140 provided in the present disclosure may include the following S1501 to S1503.

[0150] S1501, provide a semiconductor substrate 143.

[0151] In the embodiment of the present disclosure, the semiconductor substrate 143 may be any one of a silicon substrate 1431 , a silicon carbon substrate, a gallium nitride substrate and a gallium arsenide substrate, and the material type of the semiconductor substrate 143 may be determined according to the application scenario.

[0152] Exemplarily, the semiconductor substrate 143 may be a bare silicon wafer or a bare wafer, and the bare silicon wafer may be a P-type silicon wafer or an N-type silicon wafer.

[0153] S1502 , coating an insulating layer solution on the semiconductor substrate 143 , and performing a curing treatment to form an insulating layer 142 .

[0154] In the embodiment of the present disclosure, the insulating layer solution is a solution for forming the insulating layer 142. The embodiment of the present disclosure does not limit the specific solution. For example, the insulating layer solution may be a polyimide (PI) solution.

[0155] S1503 , coating photoresist on the insulating layer 142 , and performing exposure, development, electroplating, photoresist removal, and etching through a mask to form a conductive layer 141 .

[0156] In one embodiment, after coating the insulating layer solution on the semiconductor substrate 143 and performing a curing treatment to form the insulating layer 142 (i.e., S1502) as described above, the method for preparing the connecting plate 140 further includes: forming a connecting layer between the insulating layer 142 and the conductive layer 141; wherein the connecting layer includes a first metal layer 1610 and a second metal layer 1620, the first metal layer 1610 is made of titanium, and the second metal layer 1620 is made of copper.

[0157] Exemplarily, the first metal layer 1610 and the second metal layer 1620 are sputtered on the insulating layer 142 to form a connection layer, and photoresist is coated on the connection layer, and exposure, development, electroplating, photoresist removal, and etching are performed through a mask to form a conductive layer 141.

[0158] In the embodiment of the present disclosure, the adhesion between the insulating layer 142 and the conductive layer 141 produced by the subsequent process can be increased by sputtering the first metal layer 1610 and the second metal layer 1620 on the insulating layer 142. The good adhesion between the insulating layer 142 and the conductive layer 141 helps to ensure the stability of the electrical connection, avoid poor electrical contact due to poor adhesion, and thus improve the conductivity and reliability of the circuit. It can also effectively prevent interlayer separation caused by mechanical stress or thermal expansion difference, thereby extending the service life of the connecting plate 140.

[0159] Among them, the conductive layer 141 may include multiple conductive sheets of different shapes, and the conductive sheets may include one or more of an L-shaped conductive sheet 1411, a straight-line conductive sheet 1412, a U-shaped conductive sheet 1413 and a 『-shaped conductive sheet 1414, and the conductive sheets are copper sheets.

[0160] It should be noted that the mask is a mask corresponding to the conductive layer 141 on the connecting plate 140 in the embodiment of the present disclosure. Through the mask and subsequent processes, the conductive layer 141 including a plurality of conductive sheets of different shapes in the embodiment of the present disclosure can be formed.

[0161] In the embodiment of the present disclosure, in order to further increase the adhesion between the insulating layer 142 and the conductive layer 141, the material of the second metal layer 1620 attached to the conductive layer 141 is the same as the material of the conductive layer 141. For example, the material of the second metal layer 1620 is copper, and the material of the conductive layer 141 is also copper, thereby increasing the adhesion between the insulating layer 142 and the conductive layer 141.

[0162] For example, Fig.16 As shown, the preparation process of the connecting plate 140 may include the following steps A1 to A9.

[0163] Step A1, coating a polyimide (PI) solution on the silicon substrate 1431 to form a PI coating.

[0164] In the disclosed embodiment, a PI solution is coated on the silicon substrate 1431 to make a polyimide coating, so as to improve the high-temperature insulation of the connecting plate 140 and solve the problem of high-temperature leakage.

[0165] It should be noted that the silicon substrate 1431 may be covered with the silicon dioxide insulating layer 1421 or may not be covered with the silicon dioxide insulating layer 1421 .

[0166] Step A2, curing the PI coating to form a polyimide layer 1422.

[0167] In the disclosed embodiment, curing the PI coating is beneficial to enhancing the stability of the polyimide layer 1422 .

[0168] Step A3: Sputtering is performed on the polyimide layer 1422 to sequentially form a first metal layer 1610 and a second metal layer 1620 (ie, a connection layer). The connection layer is used to improve the adhesion between the polyimide layer 1422 and the conductive layer 141 to be fabricated.

[0169] In the embodiment of the present disclosure, the first metal layer 1610 may be made of titanium, the second metal layer 1620 may be made of the same material as the conductive layer 141 , and the second metal layer 1620 may be made of copper.

[0170] Step A4: spin-coat (cover) a layer of photoresist (PR) on the second metal layer 1620 to form a photoresist layer 1630 .

[0171] Step A5: Expose the photoresist layer 1630 using a mask.

[0172] Step A6, developing the exposed photoresist layer 1630 using a developer.

[0173] In the embodiment of the present disclosure, during the development process, the photoresist layer 1630 will form a groove structure that is consistent with the shape of the conductive layer 141 according to the different exposure patterns. The principle of this process is based on the selective exposure and development of the photoresist in the photolithography process. After the exposed photoresist is developed, the unexposed part will be removed, leaving a groove corresponding to the pattern. The shape of this groove accurately matches the structure of the conductive layer 141, forming a template for subsequent metal electroplating.

[0174] Step A7, performing electroplating on the developed photoresist layer 1630 to form an RDL layer 1640 .

[0175] In the embodiment of the present disclosure, metal electroplating can be performed in the above-mentioned grooves to form a conductive layer 141 connected to the second metal layer 1620. In this way, metal can be accurately deposited in a specific area (for example, an area where a conductive sheet is formed), ensuring adhesion between the conductive layer 141 and the second metal layer 1620, while reducing unnecessary metal waste and forming a precise conductive path.

[0176] It should be noted that the metal used for electroplating can be any one of copper, nickel and gold.

[0177] Step A8, removing the photoresist on the RDL layer 1640.

[0178] Step A9, etching the first metal layer 1610 and the second metal layer 1620 around the RDL layer 1640 until the etching reaches the polyimide layer 1422 and then stopping the etching, thereby completing the manufacturing of the conductive layer 141 .

[0179] In the disclosed embodiment, the first metal layer 1610 and the second metal layer 1620 around the RDL layer 1640 are etched to accurately remove the excess metal layer until the polyimide layer 1422 is etched to complete the graphic definition of the conductive layer 141. The principle is based on the process of selective etching. For example, the conductive layer 141 includes a plurality of conductive sheets of different shapes, and the conductive sheet may include one or more of an L-shaped conductive sheet 1411, a straight conductive sheet 1412, a ㄇ-shaped conductive sheet 1413, and a 『-shaped conductive sheet 1414. Among them, a plurality of position marks 1416 are provided on the conductive sheet, and the width of the conductive sheet at the position mark 1416 is greater than the width of the conductive sheet at other positions, which can reduce the risk of warping of the conductive sheet, facilitate reducing the width of the conductive sheet, and reduce the metal coverage, thereby reducing production costs. The conductive layer 141 may also include a plurality of balancing sheets 1415.

[0180] In one embodiment, an etching technique is used to remove the metal layer through chemical reaction or physical action. The depth and range of etching are precisely adjusted by controlling the etching time and the selection of chemical agents. In order to ensure that etching only acts on the metal layer without damaging the polyimide layer 1422 below, the embodiment of the present disclosure adopts relatively mild etching conditions or a phased etching process. The polyimide layer 1422, as a high temperature resistant and chemically resistant insulating material layer, is designed as an etching stop layer, that is, once the etching reaches the polyimide layer 1422, the etching process will stop to protect the underlying structure (such as the silicon substrate 1431) from damage. By etching in this way, the shape and size of the conductive layer 141 can be precisely controlled, providing the necessary circuit patterns and connection structures for subsequent process steps (such as interconnection, packaging, etc.), thereby completing the production of the conductive layer 141 and ensuring its electrical performance and structural stability.

[0181] The connection plate 140 manufactured by the above-mentioned manufacturing method in the embodiment of the present disclosure has good electrical performance and structural stability.

[0182] In the application embodiments, the terms "first", "second", and "third" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance; the term "plurality" refers to two or more, unless otherwise expressly defined. The terms "installed", "connected", "connected", "fixed", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; "connected" can be a direct connection or an indirect connection through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the application embodiments can be understood according to the specific circumstances.

[0183] In the description of the application embodiments, it should be understood that the directions or positional relationships indicated by the terms "up", "down", "left", "right", "front", "back", etc. are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the application embodiments and simplifying the description, rather than indicating or implying that the device or unit referred to must have a specific direction, be constructed and operated in a specific orientation, and therefore, should not be understood as a limitation on the application embodiments.

[0184] In the description of this specification, the description of the terms "one embodiment", "some embodiments", "specific embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the application embodiment. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0185] The above are only preferred embodiments of the application embodiments and are not intended to limit the application embodiments. For those skilled in the art, the application embodiments may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application embodiments shall be included in the protection scope of the application embodiments.

Claims

1. A connection board for a flash memory chip, characterized in that: include: An insulating layer (142) having a first surface and a second surface opposite to each other; A semiconductor substrate (143) is disposed on a first surface of the insulating layer (142); A conductive layer (141) is disposed on the second surface of the insulating layer (142), and the conductive layer (141) includes a plurality of conductive sheets of different shapes, and the conductive sheets are distributed at different positions on the second surface of the insulating layer (142), so that the pads (120) of the flash memory chip (110) are coupled to the external pins (206) through the conductive sheets, so as to reduce the proportion of the bonding wires crossing the flash memory chip (110).

2. The connection board of the flash memory chip according to claim 1, characterized in that: The insulating layer (142) comprises a first insulating layer, which is a polymer material layer or an oxide layer.

3. The connection board of the flash memory chip according to claim 1, characterized in that: The insulating layer (142) comprises: A first insulating layer having a first surface and a second surface opposite to each other, wherein the second surface of the first insulating layer is the second surface of the insulating layer (142); A second insulating layer, disposed on a first surface of the first insulating layer; Wherein, the first insulating layer is a polymer material layer, and the second insulating layer is an oxide layer.

4. The connection board of the flash memory chip according to claim 2 or 3, characterized in that: The connecting plate (140) further comprises: A third insulating layer (144) is disposed on the conductive layer (141), wherein the third insulating layer (144) is a polymer material layer.

5. The connection board of the flash memory chip according to claim 1, characterized in that: A plurality of position marks (1416) are provided on the conductive sheet, and the position marks (1416) are used to locate the wiring position so that the conductive sheet is coupled to the pad (120) of the flash memory chip (110) or the external pin (206) at the position marks (1416).

6. The connection board of the flash memory chip according to claim 5, characterized in that: The width of the conductive sheet at the position mark (1416) is greater than the width of the conductive sheet at a position where the position mark (1416) is not marked.

7. The connection board of the flash memory chip according to claim 1, characterized in that: The conductive sheet includes one or more of an L-shaped conductive sheet (1411), a straight-line conductive sheet (1412), a U-shaped conductive sheet (1413) and a '-shaped conductive sheet (1414).

8. The connection board of the flash memory chip according to claim 1, characterized in that: The conductive sheet comprises an L-shaped conductive sheet (1411), a straight-line conductive sheet (1412), a U-shaped conductive sheet (1413) and a "-shaped conductive sheet (1414); a plurality of the L-shaped conductive sheets (1411) and a plurality of the straight-line conductive sheets (1412) are located inside the "-shaped conductive sheet (1413); a plurality of balancing sheets (1415) distributed at intervals are provided at the opening of the "-shaped conductive sheet (1413).

9. The connection board of the flash memory chip according to claim 1, characterized in that: The semiconductor substrate (143) is a bare silicon wafer or a bare wafer, and the bare silicon wafer is a P-type silicon wafer or an N-type silicon wafer.

10. A flash memory chip, characterized in that: It comprises a chip body and a connecting board of a flash memory chip as described in any one of claims 1 to 9, wherein the connecting board (140) has a first surface and a second surface opposite to each other, the chip body is arranged on the first surface of the connecting board (140), the connecting board (140) is coupled to the chip body, and the overall size of the connecting board (140) is smaller than the overall size of the chip body.

11. The flash memory chip according to claim 10, characterized in that: The connecting plate (140) is located at the center of the chip body.

12. The flash memory chip according to claim 10, characterized in that: The connecting plate (140) further comprises: a first connection point group (201) and a second connection point group (202), wherein the first connection point group (201) and the second connection point group (202) are arranged on the second surface of the connecting plate (140) and distributed on both sides of the second surface of the connecting plate (140), and the first connection point group (201) and the second connection point group (202) each comprise a plurality of connection points (203), and the connection points (203) are coupled to the conductive layer (141) of the connecting plate (140); The chip body comprises a plurality of solder pads (120), the plurality of solder pads (120) being arranged on a surface side of the chip body close to a first surface of the connecting board (140); a distance between the plurality of solder pads (120) and the first connection point group (201) is smaller than a distance between the plurality of solder pads (120) and the second connection point group (202); M solder pads (120) in the plurality of solder pads (120) are coupled to a connection point (203) in the first connection point group (201); and a connection point (203) in the first connection point group (201) is coupled to a connection point (203) in the second connection point group (202) through the conductive layer (141); The flash memory chip (110) further comprises: a first pin group (204) and a second pin group (205), wherein the first pin group (204) and the second pin group (205) are distributed on two opposite sides of the chip body, the first pin group (204) and the second pin group (205) both comprise a plurality of external pins (206), the distance between the first pin group (204) and the plurality of solder pads (120) is smaller than the distance between the second pin group (205) and the plurality of solder pads (120), K solder pads (120) among the plurality of solder pads (120) are coupled to the external pins (206) in the first pin group (204), and the connection points (203) in the second connection point group (202) are coupled to the external pins (206) in the second pin group (205); Wherein, M and K are both integers greater than or equal to 1, and the sum of M and K is less than or equal to the total number of the plurality of pads (120).

13. The flash memory chip according to claim 12, characterized in that: The multiple external pins (206) in the first pin group (204) and the multiple solder pads (120) are evenly distributed in a straight line, and two solder pads (120) located on the outside of the multiple solder pads (120) are respectively coupled to the two external pins (206) located on the outside of the first pin group (204), the multiple external pins (206) in the first pin group (204) and K solder pads (120) in the multiple solder pads (120) correspond one by one along the length direction of the chip body, and the solder wires coupled between each group of corresponding solder pads (120) and the external pins (206) are parallel to the length direction of the chip body.

14. The flash memory chip according to claim 10, characterized in that: The connecting plate (140) further comprises: a plurality of connecting points (203), the plurality of connecting points (203) being arranged on the second surface of the connecting plate (140) and distributed on the outer edge of the connecting plate (140), the connecting points (203) being coupled to the conductive layer (141) of the connecting plate (140); The flash memory chip (110) further comprises: a first pin group (204) and a second pin group (205), wherein the first pin group (204) and the second pin group (205) are distributed on two opposite sides of the chip body, and the first pin group (204) and the second pin group (205) each comprise a plurality of external pins (206); The chip body comprises a plurality of solder pads (120), the plurality of solder pads (120) being arranged on a surface side of the chip body close to a first surface of the connecting board (140), the plurality of solder pads (120) being located between the first pin group (204) and the second pin group (205), T solder pads (120) of the plurality of solder pads (120) being coupled to a portion of external pins (206) of the first pin group (204), E solder pads (120) of the plurality of solder pads (120) being coupled to a portion of external pins (206) of the second pin group (205), and Q solder pads (120) of the plurality of solder pads (120) being coupled to the connecting point (203); Wherein, T, E and Q are all integers greater than or equal to 1, and the sum of T, E and Q is less than or equal to the total number of the plurality of pads (120).

15. A method for preparing a connecting plate, characterized in that: include: Providing a semiconductor substrate (143); coating an insulating layer solution on the semiconductor substrate (143), and performing a curing treatment to form an insulating layer (142); A photoresist is coated on the insulating layer (142), and exposure, development, electroplating, removal of the photoresist, and etching are performed through a mask to form a conductive layer (141).

16. The method for preparing a connecting plate according to claim 15, characterized in that: After the insulating layer solution is coated on the semiconductor substrate (143) and cured to form the insulating layer (142), the method for preparing the connecting plate further comprises: forming a connection layer between the insulating layer (142) and the conductive layer (141); The connection layer comprises a first metal layer (1610) and a second metal layer (1620), the first metal layer (1610) is made of titanium, and the second metal layer (1620) is made of copper.

17. The method for preparing a connecting plate according to claim 15, characterized in that: The conductive layer (141) comprises a plurality of conductive sheets of different shapes, wherein the conductive sheets comprise one or more of an L-shaped conductive sheet (1411), a straight-line conductive sheet (1412), a U-shaped conductive sheet (1413) and a U-shaped conductive sheet (1414), and the conductive sheets are copper sheets.

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