Semiconductor package

Abstract

A semiconductor package is disclosed. The semiconductor package may include a first semiconductor chip and a second semiconductor chip under the first semiconductor chip. The first semiconductor chip may include a first device layer, a first interconnect layer on a bottom surface of the first device layer, a first via penetrating the first device layer and electrically connected to the first interconnect layer, and a first pad on a bottom surface of the first interconnect layer. The second semiconductor chip may include a second device layer, a second via penetrating the second device layer, and a second pad on a top surface of the second device layer and electrically connected to the second via. When viewed in a plan view, the first via and the second via may be offset from each other in a horizontal direction, and the first via may be horizontally spaced apart from the first pad.

Description

[0001] This patent application claims the priority of Korean Patent Application No. 10-2023-0141230 filed in the Korean Intellectual Property Office on October 20, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a semiconductor package, and in particular, to a stacked semiconductor package. Background Art

[0003] In the semiconductor industry, in response to the increasing demand for large-capacity, thin and small semiconductor packages and / or electronic products therewith, various packaging technologies have been developed. For example, a packaging technology for vertically stacking semiconductor chips has been proposed to achieve a high-density chip stacking structure. Compared with a typical package provided in the form of a single semiconductor chip, this technology makes it possible to integrate semiconductor chips with various functions on a small area.

[0004] A semiconductor package includes a semiconductor chip that is configured to be easily used as a part of an electronic product. Typically, a semiconductor package includes a printed circuit board (PCB) and a semiconductor chip that is mounted on the PCB and electrically connected to the PCB using bonding wiring or bumps. With the development of the electronics industry, various studies are being conducted to improve the reliability and durability of semiconductor packages. Summary of the invention

[0005] Example embodiments of the inventive concepts provide a semiconductor package having improved structural stability.

[0006] Example embodiments of the inventive concepts provide a semiconductor package having improved electrical characteristics.

[0007] According to an example embodiment of the inventive concept, a semiconductor package includes a first semiconductor chip and a second semiconductor chip below the first semiconductor chip. The first semiconductor chip includes a first semiconductor substrate, a first semiconductor device on the bottom surface of the first semiconductor substrate, a first interconnection layer on the bottom surface of the first semiconductor substrate, a first via vertically penetrating the first semiconductor substrate and electrically connected to the first interconnection layer, and a first pad on the bottom surface of the first interconnection layer. The second semiconductor chip includes a second semiconductor substrate, a second via vertically penetrating the second semiconductor substrate, and a second pad on the top surface of the second semiconductor substrate and electrically connected to the second via. The first semiconductor chip and the second semiconductor chip are in direct contact with each other, and the first pad and the second pad include the same material and constitute a single complete object. The first via and the second via are offset from each other in a direction parallel to the bottom surface of the first semiconductor substrate, and when viewed in a plan view, the first via is horizontally spaced apart from the first pad, and the first via is electrically connected to the second pad through the first interconnection layer.

[0008] According to an example embodiment of the inventive concept, a semiconductor package includes a first semiconductor chip and a second semiconductor chip on the first semiconductor chip. The first semiconductor chip includes a first semiconductor substrate, a first semiconductor device on the bottom surface of the first semiconductor substrate, a first interconnection layer on the bottom surface of the first semiconductor substrate, a first via vertically penetrating the first semiconductor substrate and electrically connected to the first interconnection layer, a redistribution layer on the top surface of the first semiconductor substrate, and a first pad on the top surface of the redistribution layer. The second semiconductor chip includes a second semiconductor substrate, a second semiconductor device on the bottom surface of the second semiconductor substrate, a second interconnection layer on the bottom surface of the second semiconductor substrate, a second via vertically penetrating the second semiconductor substrate and electrically connected to the second interconnection layer, and a second pad on the bottom surface of the second interconnection layer. The first via and the second via are vertically aligned with each other, and the first pad and the second pad are vertically aligned with each other. Each group of the first via and the second via is offset from each group of the first pad and the second pad in a direction parallel to the top surface of the first semiconductor substrate by a distance that is 0.5 to 5 times the sum of the width of the first via and the width of the first pad or 0.5 to 5 times the sum of the width of the second via and the width of the second pad.

[0009] According to an example embodiment of the inventive concept, a semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip below the first semiconductor chip, and a mold layer on the substrate and encapsulating the first semiconductor chip and the second semiconductor chip. The first semiconductor chip includes a first semiconductor substrate, a first semiconductor device on the bottom surface of the first semiconductor substrate, a first interconnection layer on the bottom surface of the first semiconductor substrate, a first via hole vertically penetrating the first semiconductor substrate and electrically connected to the first interconnection layer, and a first pad on the bottom surface of the first interconnection layer. The second semiconductor chip includes a second semiconductor substrate, a second via hole vertically penetrating the second semiconductor substrate, and a second pad on the top surface of the second semiconductor substrate. The first semiconductor chip and the second semiconductor chip are in direct contact with each other, and each of the first pads and a corresponding one of the second pads include the same material and constitute a single complete object. When viewed in a plan view, the first via hole is in a lattice shape, and the first pad is in a lattice shape. Each of the first pads is between four adjacent via holes in the first via hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concept.

[0011] Figures 2 to 5 is a plan view illustrating an arrangement of pads and vias in a semiconductor package according to example embodiments of the inventive concepts.

[0012] Figures 6 to 8 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concept.

[0013] Fig. 9 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concept.

[0014] Figures 10 to 13 is a cross-sectional view showing the structure of semiconductor chips bonded to each other.

[0015] Fig.14 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concept.

[0016] Figures 15 to 17 is a cross-sectional view showing the structure of semiconductor chips bonded to each other. DETAILED DESCRIPTION

[0017] Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which some example embodiments are shown.

[0018] Although the terms "same," "equal," or "identical" are used in the description of example embodiments, it should be understood that some imprecision may exist. Therefore, when one element is referred to as being the same as another element, it should be understood that the element is the same as the other element within a desired manufacturing or operating tolerance range (e.g., ±10%).

[0019] When the term "about" or "substantially" is used in conjunction with a numerical value in this specification, it is intended that the relevant numerical value includes a manufacturing or operating tolerance (e.g., ±10%) around the stated numerical value. In addition, when the word "about" or "substantially" is used in conjunction with a geometric shape, it is intended that the accuracy of the geometric shape is not required, but the margin of the shape is within the disclosed range. In addition, regardless of whether a numerical value or shape is modified to "about" or "substantially", it will be understood that these values ​​and shapes should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) around the stated numerical value or shape.

[0020] As used herein, expressions such as "at least one of" when preceding a list of elements modify the entire list of elements and do not modify the individual elements in the list. Thus, for example, "at least one of A, B, or C" and "at least one of A, B, and C" both mean A, B, C, or any combination thereof. Likewise, A and / or B means A, B, or A and B.

[0021] Figure 1 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concept. Figures 2 to 5 is a plan view illustrating an arrangement of pads and vias in a semiconductor package according to example embodiments of the inventive concepts.

[0022] Reference Figure 1 , the semiconductor package may include a lower structure (or referred to as a “second semiconductor chip”) 10 and an upper structure (or referred to as a “first semiconductor chip”) 30 stacked thereon.

[0023] The lower structure 10 may include a first device layer 12 , a first insulating layer 14 , and a first pad 20 .

[0024] The first device layer 12 may include a semiconductor device. For example, the first device layer 12 may include a first semiconductor substrate and a first circuit layer thereon.

[0025] The first semiconductor substrate may be a semiconductor substrate (e.g., a semiconductor wafer). The first semiconductor substrate may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial thin film formed by selective epitaxial growth (SEG). The first semiconductor substrate may be formed of, for example, at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), and aluminum gallium arsenide (AlGaAs) or include, for example, at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), and aluminum gallium arsenide (AlGaAs). In some example embodiments, the first semiconductor substrate may be an insulating substrate.

[0026] The first circuit layer may be disposed on the first semiconductor substrate. The first circuit layer may include a first circuit pattern disposed on the top surface of the first semiconductor substrate and an insulating layer covering the first circuit pattern. The first circuit pattern may be a memory circuit, a logic circuit, or a combination thereof including one or more transistors. In some example embodiments, the first circuit pattern may include a passive device (such as a resistor or a capacitor). In example embodiments, the first circuit pattern may include an interconnect pattern electrically connected to the transistor or the passive device.

[0027] The first pad 20 may be disposed on the first device layer 12. The first pad 20 may have a damascene structure. For example, the first pad 20 may further include a seed layer or a barrier layer disposed to cover its side surface and bottom surface. The first pad 20 may have a plate shape or a tapered shape in which its width decreases as the distance to the first device layer 12 decreases. For example, when viewed in a cross-sectional view, the first pad 20 may have a quadrilateral shape, a rectangular shape, or a parallelogram shape. Unlike the structure shown, the first pad 20 may include a via portion and a pad portion stacked in sequence and connected to each other to form a single object, and may have a "T" shaped cross section. When viewed in a plan view, the first pad 20 may have a circular shape. In some example embodiments, when viewed in a plan view, the first pad 20 may have a quadrilateral shape or a rectangular shape. However, the inventive concept is not limited to this example, and if necessary, the planar shape of the first pad 20 may be changed in various ways. The first pad 20 may include at least one of the metal materials. As an example, the first pad 20 may be formed of copper (Cu) or include copper (Cu).

[0028] The first pad 20 may be electrically connected to the first circuit pattern of the first device layer 12. For example, Figure 1As shown in , the first interconnect line 16 may be disposed in the first device layer 12. The first interconnect line 16 may be a through via disposed to vertically penetrate an insulating layer in the first device layer 12. The first interconnect line 16 may be a columnar pattern placed in the first device layer 12 and extending in a vertical direction. In the first device layer 12, the first interconnect line 16 may extend vertically and may extend to the first pad 20. The first interconnect line 16 may electrically connect the first circuit pattern to the first pad 20. The planar area of ​​the first pad 20 may be greater than the planar area of ​​the first interconnect line 16. For example, the width of the first pad 20 may be greater than the width of the first interconnect line 16. The first interconnect line 16 may include a metal material (e.g., tungsten (W)). Although Figure 1 Although not shown in the figure, various conductive patterns constituting the interconnection structure may be disposed between the first circuit pattern and the first interconnection line 16 .

[0029] The first insulating layer 14 may be disposed on the first device layer 12. The first insulating layer 14 on the first device layer 12 may encapsulate the first pad 20. The top surface of the first pad 20 may be exposed to the outside of the first insulating layer 14. The top surface of the first insulating layer 14 may be coplanar with the top surface of the first pad 20. The first insulating layer 14 may be formed of or include at least one of an oxide, nitride, and oxynitride material containing an element constituting the first device layer 12. The first insulating layer 14 may be formed of or include at least one of an insulating material (e.g., silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiCN)).

[0030] The upper structure 30 may include a second device layer 32 , a second insulating layer 34 , and a second pad 40 .

[0031] The second device layer 32 may include a semiconductor device. For example, the second device layer 32 may include a second semiconductor substrate and a second circuit layer thereon.

[0032] The second semiconductor substrate may be a semiconductor substrate (e.g., a semiconductor wafer). The second semiconductor substrate may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial thin film formed by selective epitaxial growth (SEG). The second semiconductor substrate may be formed of, for example, at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), and aluminum gallium arsenide (AlGaAs) or include, for example, at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), and aluminum gallium arsenide (AlGaAs). In some example embodiments, the second semiconductor substrate may be an insulating substrate.

[0033] The second circuit layer may be disposed on the second semiconductor substrate. The second circuit layer may include a second circuit pattern disposed on the bottom surface of the second semiconductor substrate and an insulating layer covering the second circuit pattern. The second circuit pattern may be a memory circuit, a logic circuit, or a combination thereof including one or more transistors. In some example embodiments, the second circuit pattern may include a passive device (such as a resistor or a capacitor). In an embodiment, the second circuit pattern may include an interconnect pattern electrically connected to a transistor or a passive device.

[0034] The second interconnect line 36 may be disposed in the second device layer 32. For example, Figure 1 As shown in , the second interconnection line 36 may be a through-hole arranged to vertically penetrate the insulating layer in the second device layer 32. The second interconnection line 36 may be a columnar pattern placed in the second device layer 32 and extending in the vertical direction. The second interconnection line 36 may be electrically connected to the second circuit pattern. The second interconnection line 36 may include a metal material (e.g., tungsten (W)). Although Figure 1 Although not shown in the figure, various conductive patterns constituting the interconnection structure may be disposed between the second circuit pattern and the second interconnection line 36 .

[0035] The second pad 40 may be disposed on the second device layer 32. The second pad 40 may have a damascene structure. For example, the second pad 40 may further include a seed layer or a barrier layer disposed to cover its side surface and bottom surface. The second pad 40 may have a plate shape or a tapered shape whose width decreases as the distance to the second device layer 32 decreases. In an example embodiment, when viewed in a cross-sectional view, the second pad 40 may have a triangular shape or a parallelogram shape. Unlike the structure shown, the second pad 40 may include a via portion and a pad portion stacked in sequence and connected to each other to form a single object, and may have a "T" shaped cross section. When viewed in a plan view, the second pad 40 may have a circular shape. In an example embodiment, when viewed in a plan view, the second pad 40 may have a quadrilateral shape. However, the inventive concept is not limited to this example, and the planar shape of the second pad 40 may be changed in various ways if necessary. The planar area of ​​the second pad 40 may be greater than the planar area of ​​the second interconnect line 36. For example, the width of the second pad 40 may be greater than the width of the second interconnect line 36. The second pad 40 may be vertically spaced apart from the bottom surface of the second device layer 32. The second pad 40 may include at least one of metal materials. As an example, the second pad 40 may be formed of or include copper (Cu).

[0036] The second pad 40 may be horizontally offset from the second interconnect 36. The following description will be given based on the second pad 40 and the second interconnect 36 that are paired and electrically connected to each other. For example, the second pad 40 may not be vertically overlapped with the second interconnect 36. As an example, when viewed in a plan view, the side surface of the second pad 40 may be spaced apart from the side surface of the second interconnect 36. For example, the offset distance SD1 between the second pad 40 and the second interconnect 36 may be greater than half of the sum of the first width W1 of the second pad 40 and the second width W2 of the second interconnect 36. In this specification, the offset distance between the second pad 40 and the second interconnect 36 may mean the distance between the vertical center axis of the second pad 40 and the vertical center axis of the second interconnect 36 in the horizontal direction. Here, the offset direction between the second pad 40 and the second interconnect 36 may be parallel to the top surface of the lower structure 10 or the bottom surface of the upper structure 30, or may be a horizontal direction.

[0037] The arrangement of the second pad 40 and the second interconnection line 36 will be described in more detail below. The following description will be given based on the second pad 40 and the second interconnection line 36 which are paired and electrically connected to each other.

[0038] Reference Figure 2, the second pads 40 may be arranged in a lattice shape. For example, the second pads 40 may be arranged in the first direction D1 and the second direction D2. The second interconnects 36 may be arranged in a lattice shape. For example, the second interconnects 36 may be arranged in the first direction D1 and the second direction D2. The second pads 40 may be aligned with the second interconnects 36 in the first direction D1. As an example, each of the second pads 40 may be placed at a position spaced apart from a corresponding one of the second interconnects 36 along the first direction D1. Each of the second pads 40 may be placed between two second interconnects 36 adjacent to each other in the first direction D1 among the second interconnects 36. For the second pads 40 and the second interconnects 36 that are paired and electrically connected to each other, the second pads 40 may be disposed adjacent to the second interconnects 36 paired therewith, and may be disposed away from another second interconnect 36 adjacent thereto in the first direction D1. For example, each of the second pads 40 may be placed between the second interconnects 36, and may be adjacent to one of the second interconnects 36 that is electrically connected to the second pad 40.

[0039] In an example embodiment, if Figure 3 As shown in , each of the second pads 40 may be placed between the second interconnection lines 36 in the first direction D1. Here, each of the second pads 40 may be disposed to be spaced apart from a pair of second interconnection lines 36 by the same distance in the first direction D1. For example, the second pads 40 and the second interconnection lines 36 may be alternately arranged to be spaced apart from each other by the same distance in the first direction D1.

[0040] In an example embodiment, if Figure 4 As shown in , the second pads 40 may be arranged in a lattice shape. The second interconnects 36 may also be arranged in a lattice shape. Here, each of the second pads 40 may be placed between four second interconnects 36 adjacent to each other. For example, the second pads 40 and the second interconnects 36 may be alternately arranged in a third direction D3 and a fourth direction D4 that are not parallel to the first direction D1 and the second direction D2 and are orthogonal to each other. Here, the distance between the second pads 40 and the second interconnects 36 may be substantially uniform. In example embodiments, although not shown, each of the second pads 40 may be disposed adjacent to one of the second interconnects 36 that is electrically connected to the second pad 40, and may be disposed away from other second interconnects 36 in the second interconnects 36 that are around the second pad 40.

[0041] In an example embodiment, if Figure 5As shown in , the second pad 40 may be arranged in the third direction D3 and the fourth direction D4. The second interconnect lines 36 may also be arranged in the third direction D3 and the fourth direction D4. Here, each of the second pads 40 may be placed between four second interconnect lines 36 adjacent to each other. For example, the second pads 40 and the second interconnect lines 36 may be alternately arranged in the first direction D1 and the second direction D2. Here, the distance between the second pad 40 and the second interconnect lines 36 may be substantially uniform. In example embodiments, although not shown, each of the second pads 40 may be disposed adjacent to one of the second interconnect lines 36 electrically connected to the second pad 40, and may be disposed away from the other second interconnect lines 36 of the second interconnect lines 36 around the second pad 40.

[0042] However, the arrangement of the second pad 40 and the second interconnection line 36 is not limited to the above-described example, and various changes may be made if necessary.

[0043] Return to reference Figure 1 , the second insulating layer 34 may be disposed on the second device layer 32. The second insulating layer 34 on the second device layer 32 may encapsulate the second pad 40. The bottom surface of the second pad 40 may be exposed to the outside of the second insulating layer 34. The bottom surface of the second insulating layer 34 may be coplanar with the bottom surface of the second pad 40. The second insulating layer 34 may be in contact with the bottom surface of the second device layer 32. The thickness of the second insulating layer 34 may be thicker than the thickness of the second pad 40. In other words, the second pad 40 may be placed in the lower part of the second insulating layer 34. The second insulating layer 34 may be formed of or include at least one of an oxide, a nitride, and an oxynitride material containing an element constituting the second device layer 32. The second insulating layer 34 may be formed of or include at least one of insulating materials (e.g., silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiCN)).

[0044] The first interconnection pattern 38 may be disposed in the second insulating layer 34. When viewed in a cross-sectional view, the first interconnection pattern 38 may be placed between the second pad 40 and the second device layer 32. The first interconnection pattern 38 may electrically connect the second pad 40 to the second interconnection line 36. The first interconnection pattern 38 may include a horizontal interconnection pattern and a vertical interconnection pattern. The vertical interconnection pattern may connect the horizontal interconnection patterns to each other, connect the horizontal interconnection pattern to the second interconnection line 36, and connect the horizontal interconnection pattern to the second pad 40. The second pad 40 and the second interconnection line 36, which are horizontally spaced apart from each other, may be electrically connected to each other through the first interconnection pattern 38. In example embodiments, a portion of the second insulating layer 34 located between the second pad 40 and the second device layer 32 and the first interconnection pattern 38 may correspond to an interconnection layer connecting the second interconnection line 36 to the second pad 40.

[0045] The upper structure 30 may be disposed on the lower structure 10. The first pad 20 of the lower structure 10 may be vertically aligned with the second pad 40 of the upper structure 30. The first interconnect line 16 may be horizontally offset from the second interconnect line 36. The offset distance SD2 between the first interconnect line 16 and the second interconnect line 36 may be greater than half of the sum of the first width W1 of the second pad 40 and the second width W2 of the second interconnect line 36. In addition, the first interconnect line 16, the first pad 20, and the second pad 40 may be vertically aligned with each other. The lower structure 10 and the upper structure 30 may contact each other so that the first pad 20 is connected to the second pad 40.

[0046] At the interface between the lower structure 10 and the upper structure 30, the first insulating layer 14 of the lower structure 10 may be bonded to the second insulating layer 34 of the upper structure 30. Here, the first insulating layer 14 and the second insulating layer 34 may form a hybrid bonding structure of oxide, nitride or oxynitride. In this specification, the hybrid bonding structure may mean a bonding structure formed by two materials, which are of the same kind and fused at the interface between them. For example, the first insulating layer 14 and the second insulating layer 34 bonded to each other may have a continuous structure, and there may be no visible interface between the first insulating layer 14 and the second insulating layer 34. For example, the first insulating layer 14 and the second insulating layer 34 may be formed of the same material, and there may be no interface between the first insulating layer 14 and the second insulating layer 34. That is, the first insulating layer 14 and the second insulating layer 34 may be provided as a single object (e.g., a whole). For example, the first insulating layer 14 and the second insulating layer 34 may be bonded to each other to form a single object. However, the inventive concept is not limited to this example. The first insulating layer 14 and the second insulating layer 34 may be formed of different materials. Although not shown, the first insulating layer 14 and the second insulating layer 34 may not have a continuous structure, and there may be a visible or visible interface between the first insulating layer 14 and the second insulating layer 34. The first insulating layer 14 and the second insulating layer 34 may not be bonded to each other, and each of the first insulating layer 14 and the second insulating layer 34 may be provided as a separate element. Figure 1 The inventive concept is further described by way of example embodiments of the present invention.

[0047] The upper structure 30 may be connected to the lower structure 10. For example, the lower structure 10 and the upper structure 30 may contact each other. At the interface between the lower structure 10 and the upper structure 30, the first pad 20 of the lower structure 10 may be bonded to the second pad 40 of the upper structure 30. Here, the first pad 20 and the second pad 40 may form a metal-to-metal hybrid bonding structure. For example, the first pad 20 and the second pad 40 bonded to each other may have a continuous structure, and there may be no visible interface between the first pad 20 and the second pad 40. When the first pad 20 and the second pad 40 are formed of the same material, there may be no interface between the first pad 20 and the second pad 40. That is, the first pad 20 and the second pad 40 may be provided as a single object. For example, the first pad 20 and the second pad 40 may be combined with each other to form a single object.

[0048] The first interconnection line 16 may be formed of a material different from the first semiconductor substrate and the first circuit layer constituting the first device layer 12 or include a material different from the first circuit layer and the first semiconductor substrate constituting the first device layer 12. Therefore, the vertical stress in the lower structure 10 may be concentrated on the first interconnection line 16. For example, the thermal stress on the first interconnection line 16 may increase due to the heat generated during the process of manufacturing or operating the semiconductor package. This is because the first interconnection line 16 is formed of a material having a different thermal expansion coefficient from the first semiconductor substrate and the first circuit layer.

[0049] The second interconnection line 36 may be formed of a material different from the second semiconductor substrate and the second circuit layer constituting the second device layer 32 or include a material different from the second circuit layer and the second semiconductor substrate constituting the second device layer 32. Therefore, the vertical stress in the upper structure 30 may be concentrated on the second interconnection line 36. For example, the thermal stress on the second interconnection line 36 may increase due to the heat generated during the process of manufacturing or operating the semiconductor package. This is because the second interconnection line 36 is formed of a material having a different thermal expansion coefficient from the second semiconductor substrate and the second circuit layer.

[0050] According to an example embodiment of the inventive concept, the first interconnection line 16 vertically penetrating the lower structure 10 may be arranged to be horizontally offset from the second interconnection line 36 vertically penetrating the upper structure 30. Therefore, the stresses applied to the first interconnection line 16 and the second interconnection line 36 in the vertical direction may not overlap each other. In this case, the stress applied to the first interconnection line 16 may be dispersed into the first insulating layer 14 in the region above the first interconnection line 16, or may be transferred to the second insulating layer 34 through the second pad 40 and the first pad 20 and dispersed into the second insulating layer 34. The stress applied to the second interconnection line 36 may be dispersed into the second insulating layer 34 in the region below the second interconnection line 36. Therefore, the structural characteristics of the semiconductor package can be improved. In addition, the delamination problem between the first interconnection line 16 and the first pad 20 and between the second interconnection line 36 and the second pad 40 caused by stress can be alleviated or prevented, thereby improving the electrical connection characteristics between the first interconnection line 16 and the first pad 20 and between the second interconnection line 36 and the second pad 40. That is, a semiconductor package with improved electrical characteristics can be provided.

[0051] In the description of the exemplary embodiments to be explained below, for the sake of brevity, the previous reference Figures 1 to 5 Described elements may be identified by the same reference numerals without repeating their repeated descriptions.

[0052] Figure 6 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concept.

[0053] Reference Figure 6, the first pad 20 may be disposed on the first device layer 12. The first pad 20 may be vertically spaced apart from a top surface of the first device layer 12. The first pad 20 may be vertically aligned with the first interconnection line 16.

[0054] The first insulating layer 14 may be disposed on the first device layer 12. The first insulating layer 14 on the first device layer 12 may encapsulate the first pad 20. A top surface of the first pad 20 may be exposed to the outside of the first insulating layer 14. A top surface of the first insulating layer 14 may be coplanar with a top surface of the first pad 20. The first insulating layer 14 may contact with a top surface of the first device layer 12. The thickness of the first insulating layer 14 may be greater than the thickness of the first pad 20. That is, the first pad 20 may be placed in an upper portion of the first insulating layer 14.

[0055] The second interconnection pattern 18 may be disposed in the first insulating layer 14. When viewed in a vertical cross-sectional view, the second interconnection pattern 18 may be placed between the first pad 20 and the first device layer 12. The second interconnection pattern 18 may electrically connect the first pad 20 to the first interconnection line 16. The second interconnection pattern 18 may include a horizontal interconnection pattern and a vertical interconnection pattern. The vertical interconnection pattern may be provided to connect the horizontal interconnection patterns to each other, to connect the horizontal interconnection pattern to the first interconnection line 16, and to connect the horizontal interconnection pattern to the first pad 20. The first pad 20 and the first interconnection line 16, which are horizontally spaced apart from each other, may be electrically connected to each other through the second interconnection pattern 18. In example embodiments, a portion of the first insulating layer 14 located between the first pad 20 and the first device layer 12 and the second interconnection pattern 18 may correspond to an interconnection layer connecting the first interconnection line 16 to the first pad 20.

[0056] Figure 7 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concept.

[0057] Figure 6 An example is shown in which the first pad 20 is vertically aligned with the first interconnection line 16 , but the inventive concept is not limited to this example.

[0058] Reference Figure 7, the first pad 20 may be horizontally offset from the first interconnection line 16. The following description will be given based on the first pad 20 and the first interconnection line 16 that are paired and electrically connected to each other. For example, the first pad 20 may not be vertically overlapped with the first interconnection line 16. When viewed in a plan view, the side surface of the first pad 20 may be spaced apart from the side surface of the first interconnection line 16. For example, the offset distance between the first pad 20 and the first interconnection line 16 may be greater than half of the sum of the width of the first pad 20 and the width of the first interconnection line 16. In the present specification, the offset distance between the first pad 20 and the first interconnection line 16 may mean the distance between the vertical center axis of the first pad 20 and the vertical center axis of the first interconnection line 16 in the horizontal direction. Here, the offset direction between the first pad 20 and the first interconnection line 16 may be parallel to the top surface of the lower structure 10 or the bottom surface of the upper structure 30, or may be a horizontal direction.

[0059] The arrangement of the first pad 20 and the first interconnection line 16 in a plan view may be similar to that in reference Figures 2 to 5 The described arrangements of the second pad 40 and the second interconnection line 36 are the same or similar.

[0060] The lower structure 10 and the upper structure 30 may contact each other. At the interface between the lower structure 10 and the upper structure 30, the first pad 20 of the lower structure 10 may be bonded to the second pad 40 of the upper structure 30. The first pad 20 may be vertically aligned with the second pad 40. The first pad 20 and the second pad 40 may be horizontally spaced apart from the first interconnect line 16, and may be horizontally spaced apart from the second interconnect line 36. Here, when viewed in a plan view, the first pad 20 and the second pad 40 paired with each other may be placed between the first interconnect line 16 and the second interconnect line 36 connected thereto.

[0061] According to an example embodiment of the inventive concept, the first interconnection line 16 and the second interconnection line 36 may be disposed to be horizontally offset from each other, and the first pad 20 may be disposed to be offset from the first interconnection line 16 and the second pad 40 may be disposed to be offset from the second interconnection line 36. Therefore, the stresses applied to the first interconnection line 16 and the second interconnection line 36 in the vertical direction may not overlap each other. In this case, the stress applied to the first interconnection line 16 may be dispersed into the first insulating layer 14 in the region above the first interconnection line 16. The stress applied to the second interconnection line 36 may be dispersed into the second insulating layer 34 in the region below the second interconnection line 36. In addition, the stress caused by the first interconnection line 16 and the second interconnection line 36 may not be transferred to the first pad 20 and the second pad 40. That is, a semiconductor package with improved structural characteristics may be provided.

[0062] Figure 8 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concept.

[0063] Figure 7 An example is shown in which the first pad 20 and the second pad 40 are placed between the first interconnection line 16 and the second interconnection line 36 in a plan view, but the inventive concept is not limited to this example.

[0064] Reference Figure 8 , the first interconnection line 16 may be vertically aligned with the second interconnection line 36 .

[0065] The first pad 20 may be horizontally offset from the first interconnection line 16. For the first pad 20 and the first interconnection line 16 that are paired and electrically connected to each other, the first pad 20 may not vertically overlap the first interconnection line 16. The offset distance between the first pad 20 and the first interconnection line 16 may be greater than half of the sum of the width of the first pad 20 and the width of the first interconnection line 16.

[0066] The second pad 40 may be horizontally offset from the second interconnection line 36. For the second pad 40 and the second interconnection line 36 that are paired and electrically connected to each other, the second pad 40 may not vertically overlap the second interconnection line 36. The offset distance between the second pad 40 and the second interconnection line 36 may be greater than half of the sum of the width of the second pad 40 and the width of the second interconnection line 36.

[0067] The first pad 20 may be vertically aligned with the second pad 40. Therefore, the offset direction of the first pad 20 from the first interconnection line 16 may be the same as the offset direction of the second pad 40 from the second interconnection line 36.

[0068] According to an example embodiment of the inventive concept, although the first interconnect 16 is vertically aligned with the second interconnect 36, the first pad 20 and the second pad 40 may be disposed to be horizontally offset from the first interconnect 16 and the second interconnect 36, respectively. Therefore, the stresses applied to the first interconnect 16 and the second interconnect 36 in the vertical direction may not overlap each other. In this case, the stress applied to the first interconnect 16 may be dispersed into the first insulating layer 14 in the region above the first interconnect 16. The stress applied to the second interconnect 36 may be dispersed into the second insulating layer 34 in the region below the second interconnect 36. In addition, the stress caused by the first interconnect 16 and the second interconnect 36 may not be transferred to the first pad 20 and the second pad 40. That is, a semiconductor package with improved structural characteristics may be provided.

[0069] Fig. 9 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concept. Fig.10 is a cross-sectional view showing the structure of semiconductor chips bonded to each other.

[0070] Reference Fig. 9, a base substrate 100 may be provided. The base substrate 100 may include an integrated circuit provided therein. For example, the base substrate 100 may be a first semiconductor chip including an electronic device (eg, a transistor). For example, the base substrate 100 may be a wafer-level bare chip formed of a semiconductor material (eg, silicon (Si)). Although Fig. 9 An example in which the base substrate 100 is a first semiconductor chip is shown, but the inventive concept is not limited to this example. In an example embodiment, the base substrate 100 may be a substrate (e.g., a printed circuit board (PCB)) in which electronic components (e.g., transistors) are not provided. The silicon wafer may be thinner than the printed circuit board (PCB). Hereinafter, the base substrate 100 may be referred to as the first semiconductor chip 100.

[0071] The first semiconductor chip 100 may include a first semiconductor substrate 110 , a first via 130 , a first upper pad 140 , a first upper protective layer 150 , a first lower pad 160 , and a first lower protective layer 170 .

[0072] A first semiconductor substrate 110 may be provided. The first semiconductor substrate 110 may include a semiconductor material. For example, the first semiconductor substrate 110 may be a single crystal silicon substrate.

[0073] Although not shown, the first circuit layer may be disposed on the bottom surface of the first semiconductor substrate 110. The first circuit layer may include the integrated circuit described above. For example, the first circuit layer may be a memory circuit, a logic circuit, or a combination thereof. The bottom surface of the first semiconductor chip 100 on which the first circuit layer is disposed may be an active surface. However, in an example embodiment, the first circuit layer may not be disposed. In this case, a base substrate in which an electronic device (e.g., a transistor) is not included (or not formed) may be disposed instead of the first semiconductor chip 100.

[0074] The first via 130 may be provided to vertically penetrate the first semiconductor substrate 110. For example, the first via 130 may connect the top surface of the first semiconductor substrate 110 to the first circuit layer. The first via 130 and the first circuit layer may be electrically connected to each other. In an example embodiment, a plurality of first vias 130 may be provided. If necessary, an insulating layer (not shown) may be provided to encapsulate the first via 130. For example, the insulating layer may be formed of or include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and a low-k dielectric material.

[0075] The first upper pad 140 may be disposed on the top surface of the first semiconductor substrate 110. The first upper pad 140 may be coupled to the first via 130. In example embodiments, a plurality of first upper pads 140 may be provided. In this case, the first upper pads 140 may be coupled to the plurality of first vias 130, respectively, and the arrangement of the first upper pads 140 may be substantially the same as the arrangement of the first vias 130. The first upper pad 140 may be coupled to the first circuit layer through the first via 130. The first upper pad 140 may be formed of or include at least one of a metal material (e.g., copper (Cu), aluminum (Al), and nickel (Ni)).

[0076] The first upper protective layer 150 may be disposed on the top surface of the first semiconductor substrate 110 to encapsulate the first upper pad 140. The first upper protective layer 150 may be disposed to expose the top surface of the first upper pad 140. The top surface of the first upper protective layer 150 may be coplanar with the top surface of the first upper pad 140. The first semiconductor substrate 110 may be protected by the first upper protective layer 150. The first upper pad 140 may be connected to the first via 130. The first upper protective layer 150 may be formed of or include at least one of high density plasma (HDP) oxide, undoped silicate glass (USG), tetraethyl orthosilicate (TEOS), silicon nitride (SiN), silicon oxide (SiO), silicon oxycarbide (SiOC), silicon oxynitride (SiON), and silicon carbonitride (SiCN).

[0077] The first lower pad 160 may be disposed on the bottom surface of the first semiconductor substrate 110. For example, the first lower pad 160 may be disposed on the bottom surface of the first semiconductor substrate 110 or the bottom surface of the first circuit layer. The first lower pad 160 may be electrically connected to the first circuit layer. In example embodiments, a plurality of first lower pads 160 may be provided. The first lower pad 160 may be formed of or include at least one of a metal material (e.g., copper (Cu), aluminum (Al), and nickel (Ni)).

[0078] The first semiconductor chip 100 may further include a first lower protective layer 170. The first lower protective layer 170 may be disposed on the bottom surface of the first semiconductor substrate 110 to cover the first semiconductor substrate 110. The first lower protective layer 170 may be disposed to expose the first lower pad 160 through the bottom surface of the first lower pad 160. The first circuit layer may be protected by the first lower protective layer 170. The first lower protective layer 170 may be an insulating coating including epoxy resin.

[0079] The external terminal 105 may be disposed on the bottom surface of the first semiconductor chip 100. The external terminal 105 may be disposed on the first lower pad 160. The external terminal 105 may be electrically connected to the first semiconductor substrate 110 and the first via 130. In an example embodiment, the external terminal 105 may be disposed below the first via 130. In this case, the first via 130 may be exposed to the outside of the first semiconductor substrate 110 through the bottom surface of the first semiconductor substrate 110, and the external terminal 105 may be directly coupled to the first via 130. In an example embodiment, a plurality of external terminals 105 may be provided. In this case, the external terminals 105 may be coupled to the first lower pad 160, respectively. The external terminal 105 may be formed of or include an alloy containing at least one of tin (Sn), silver (Ag), copper (Cu), nickel (Ni), bismuth (Bi), indium (In), antimony (Sb), and cerium (Ce).

[0080] The chip stack CS may be disposed on the first semiconductor chip 100. The chip stack CS may include a plurality of second semiconductor chips 200 stacked vertically. The second semiconductor chips 200 may be of the same type. For example, the second semiconductor chips 200 may be memory chips. The second semiconductor chips 200 may be sequentially stacked on the first semiconductor chip 100. The present example embodiment relates to an example in which four second semiconductor chips 200 are disposed on the first semiconductor chip 100, but the inventive concept is not limited to this example. In an example embodiment, although not shown, two, three, five or more second semiconductor chips 200 may be disposed on the first semiconductor chip 100.

[0081] In the following, reference will be made to Fig. 9 and Fig.10 The second semiconductor chips 200, 200a and 200b are described in more detail. Fig.10 In the embodiment, for the purpose of distinction, the lower semiconductor chip and the upper semiconductor chip in the second semiconductor chip are identified by two different reference numerals 200a and 200b, but Fig.10 Each of the second semiconductor chips 200 a and 200 b may correspond to Fig. 9 The second semiconductor chip 200 is provided.

[0082] Reference Fig. 9 and Fig.10 Each of the second semiconductor chips 200 , 200 a and 200 b may include a second semiconductor substrate 210 , a second circuit layer 220 , a second via 230 , a second upper pad 240 , a second upper protective layer 250 , a second lower pad 260 and a second lower protective layer 270 .

[0083] A second semiconductor substrate 210 may be provided. The second semiconductor substrate 210 may include a semiconductor material. For example, the second semiconductor substrate 210 may be a single crystal silicon substrate. The second semiconductor substrate 210 may have a bottom surface and a top surface opposite to each other. The bottom surface of the second semiconductor substrate 210 may be the front surface of the second semiconductor substrate 210, and the top surface of the second semiconductor substrate 210 may be the rear surface of the second semiconductor substrate 210. Here, the front surface of the second semiconductor substrate 210 may be defined as a surface on which a semiconductor device, interconnection line or pad of the second semiconductor substrate 210 is formed or mounted, and the rear surface of the second semiconductor substrate 210 may be defined as a surface opposite to the front surface. The front surface of the second semiconductor substrate 210 may face the first semiconductor chip 100. In other words, the bottom surface of the second semiconductor substrate 210 may be an active surface.

[0084] Each of the second semiconductor chips 200, 200a, and 200b may have a second circuit layer 220 facing the first semiconductor chip 100. The second circuit layer 220 may include a semiconductor device 222, a first interconnection 226, and a second interconnection 224.

[0085] The semiconductor device 222 may include a transistor TR disposed on the bottom surface of the second semiconductor substrate 210. The transistor TR may include a source region and a drain region formed in a lower portion of the second semiconductor substrate 210, a gate electrode disposed on the bottom surface of the second semiconductor substrate 210, and a gate insulating layer interposed between the second semiconductor substrate 210 and the gate electrode. Fig.10 An example of setting one transistor TR is shown, but the inventive concept is not limited to this example. The semiconductor device 222 may include a plurality of transistors TR. The semiconductor device 222 may include a memory circuit. Although not shown, the semiconductor device 222 may include a logic unit or a memory unit formed on the bottom surface of the second semiconductor substrate 210, and may include a shallow device isolation pattern. In some example embodiments, the semiconductor device 222 may include a passive device (such as a capacitor).

[0086] The bottom surface of the second semiconductor substrate 210 may be covered with a device interlayer insulating layer 228. The device interlayer insulating layer 228 may be disposed on the bottom surface of the second semiconductor substrate 210 to bury the semiconductor device 222. Here, the device interlayer insulating layer 228 may be disposed to cover the semiconductor device 222. That is, the semiconductor device 222 may not be exposed to the outside through the device interlayer insulating layer 228. The device interlayer insulating layer 228 may be formed of or include at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON). In some example embodiments, the device interlayer insulating layer 228 may be formed of or include a low-k dielectric material. The device interlayer insulating layer 228 may have a single-layer or multi-layer structure. In the case where the device interlayer insulating layer 228 has a multi-layer structure, the interconnection layers to be described below may be respectively disposed in the insulating layers and the etching stop layer may be placed between the insulating layers. For example, the etch stop layer may be disposed on the bottom surface of at least one insulating layer. The etch stop layer may be formed of, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiCN) or include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiCN).

[0087] The first interconnect 226 may be disposed on the bottom surface of the device interlayer insulating layer 228. The first interconnect 226 may be disposed in the lower portion of the device interlayer insulating layer 228 and may be exposed to the outside through the bottom surface of the device interlayer insulating layer 228. The first interconnect 226 may include a horizontal interconnect pattern that serves as a portion of a horizontal interconnect structure or pad. At least a portion of the first interconnect 226 (hereinafter, a first portion of the first interconnect 226) may be connected to the bottom surface of the second via 230. Another portion of the first interconnect 226 (hereinafter, a second portion of the first interconnect 226) may be disposed adjacent to the semiconductor device 222.

[0088] A second interconnect 224 connected to the transistor TR may be disposed in the device interlayer insulating layer 228. The second interconnect 224 may be placed between the top surface and the bottom surface of the device interlayer insulating layer 228. The second interconnect 224 may connect a second portion of the first interconnect 226 to the semiconductor device 222. The second interconnect 224 may include a horizontal interconnect pattern for horizontal interconnection and a vertical contact for vertical interconnection.

[0089] The first interconnect 226 and the second interconnect 224 may be formed of or include, for example, copper (Cu) or tungsten (W).

[0090] The semiconductor device 222 (including the transistor TR), the device interlayer insulating layer 228 , and the first and second interconnections 226 and 224 may constitute a second circuit layer 220 .

[0091] The second via 230 may be provided to vertically penetrate the second semiconductor substrate 210. The second via 230 may be a pattern for vertical interconnection. The second via 230 may be provided to vertically penetrate the second semiconductor substrate 210 and the device interlayer insulating layer 228, and may be coupled to the top surface of the first portion of the first interconnect 226. The second via 230 may be provided to vertically penetrate the device interlayer insulating layer 228 and the second semiconductor substrate 210, and may be exposed to the outside through the top surface of the second semiconductor substrate 210. The second via 230 may be formed of, for example, tungsten (W) or include, for example, tungsten (W).

[0092] The second lower pad 260 may be disposed on the device interlayer insulating layer 228. The second lower pad 260 may be disposed on the bottom surface of the device interlayer insulating layer 228. The second lower pad 260 may have a damask structure. For example, the second lower pad 260 may also include a seed layer or a barrier layer that is disposed to cover its side surface and bottom surface. The planar area of ​​the second lower pad 260 may be greater than the planar area of ​​the second via 230. For example, the width of the second lower pad 260 may be greater than the width of the second via 230. The second lower pad 260 may be vertically spaced apart from the bottom surface of the second circuit layer 220. The second lower pad 260 may include at least one of the metal materials. As an example, the second lower pad 260 may be formed of copper (Cu) or include copper (Cu).

[0093] The second lower protective layer 270 may be disposed on the second circuit layer 220. For example, the second lower protective layer 270 may be disposed on the bottom surface of the second circuit layer 220 to cover the first interconnect 226. The second lower protective layer 270 on the bottom surface of the second circuit layer 220 may encapsulate the second lower pad 260. The second lower pad 260 may be exposed to the outside of the second lower protective layer 270. For example, when viewed in a plan view, the second lower protective layer 270 may encapsulate the second lower pad 260, but may not cover the second lower pad 260. The bottom surface of the second lower protective layer 270 may be coplanar with the bottom surface of the second lower pad 260. The second lower protective layer 270 may contact the bottom surface of the second circuit layer 220. The thickness of the second lower protective layer 270 may be greater than the thickness of the second lower pad 260. In other words, the second lower pad 260 may be placed in the lower portion of the second lower protective layer 270. The second lower protective layer 270 may be formed of or include at least one of silicon nitride (SiN), silicon oxide (SiO), silicon oxycarbide (SiOC), silicon oxynitride (SiON) and silicon carbonitride (SiCN).

[0094] The second lower pad 260 may be horizontally offset from the second via 230. The following description will be given based on the second lower pad 260 and the second via 230 that are paired and electrically connected to each other. For example, the second lower pad 260 may not be vertically overlapped with the second via 230. As an example, when viewed in a plan view, the side surface of the second lower pad 260 may be spaced apart from the side surface of the second via 230. For example, the offset distance between the second lower pad 260 and the second via 230 may be greater than half of the sum of the width of the second lower pad 260 and the width of the second via 230. In this specification, the offset distance between the second lower pad 260 and the second via 230 may mean the distance between the vertical center axis of the second lower pad 260 and the vertical center axis of the second via 230 in the horizontal direction. Here, the offset direction between the second lower pad 260 and the second via 230 may be a horizontal direction.

[0095] The first interconnection pattern 262 may be disposed in the second lower protective layer 270. When viewed in a vertical cross-sectional view, the first interconnection pattern 262 may be placed between the second lower pad 260 and the second circuit layer 220. The first interconnection pattern 262 may electrically connect the second lower pad 260 to the first interconnection 226. The first interconnection pattern 262 may include a horizontal interconnection pattern and a vertical interconnection pattern. The vertical interconnection pattern may connect the horizontal interconnection patterns to each other, connect the horizontal interconnection pattern to the first interconnection 226, and connect the horizontal interconnection pattern to the second lower pad 260. The second lower pad 260 and the first interconnection 226, which are horizontally spaced apart from each other, may be electrically connected to each other through the first interconnection pattern 262. In example embodiments, a portion of the second lower protective layer 270 placed between the second lower pad 260 and the second circuit layer 220 and the first interconnection pattern 262 may correspond to an interconnection layer connecting the first interconnection 226 to the second lower pad 260.

[0096] The second upper pad 240 may be disposed on the top surface of the second semiconductor substrate 210. The second upper pad 240 may be connected to the second via 230. For example, the second via 230 may be disposed to vertically penetrate the second semiconductor substrate 210 and may be coupled to the bottom surface of the second upper pad 240. In other words, the second upper pad 240 may be vertically aligned with the second via 230. The planar area of ​​the second upper pad 240 may be greater than the planar area of ​​the second via 230. For example, the width of the second upper pad 240 may be greater than the width of the second via 230. The second upper pad 240 may include a metal material. As an example, the second upper pad 240 may be formed of copper (Cu) or include copper (Cu).

[0097] The second upper protective layer 250 may be disposed on the top surface of the second semiconductor substrate 210. The second upper protective layer 250 on the top surface of the second semiconductor substrate 210 may encapsulate the second upper pad 240. The second upper pad 240 may be exposed by the second upper protective layer 250. For example, when viewed in a plan view, the second upper protective layer 250 may encapsulate the second upper pad 240, but may not cover the second upper pad 240. The top surface of the second upper protective layer 250 may be coplanar with the top surface of the second upper pad 240. The second upper protective layer 250 may be formed of or include at least one of high density plasma (HDP) oxide, undoped silicate glass (USG), tetraethyl orthosilicate (TEOS), silicon nitride (SiN), silicon oxide (SiO), silicon oxycarbide (SiOC), silicon oxynitride (SiON), and silicon carbonitride (SiCN). The second upper protective layer 250 may have a single layer or multi-layer structure.

[0098] The second semiconductor chips 200, 200a, and 200b may have substantially the same structure. However, the uppermost second semiconductor chip 200 among the second semiconductor chips 200 of the chip stack CS may have a structure different from that of the other second semiconductor chips 200. For example, the uppermost second semiconductor chip 200 among the second semiconductor chips 200 may include a second semiconductor substrate 210, a second circuit layer 220, a second lower pad 260, and a second lower protective layer 270. The uppermost second semiconductor chip 200 may not have the second via 230, the second upper pad 240, the second upper protective layer 250, and the redistribution layer 280 (see Fig.11 ). However, the inventive concept is not limited to this example. In example embodiments, although not shown, the uppermost second semiconductor chip 200 among the second semiconductor chips 200 may include at least one of the second via 230, the second upper pad 240, the second upper protective layer 250, and the redistribution layer 280. The uppermost second semiconductor chip 200 among the second semiconductor chips 200 may be thicker than the other second semiconductor chips 200 among the second semiconductor chips 200.

[0099] The second semiconductor chips 200 may be sequentially mounted on top of each other. The mounting of the second semiconductor chips 200 of the chip stack CS may be performed by the same method. Hereinafter, the mounting of the second semiconductor chips 200 of the chip stack CS will be described with reference to an example in which one second semiconductor chip (hereinafter, upper chip 200b) is mounted on another second semiconductor chip (hereinafter, lower chip 200a) below it.

[0100] The upper chip 200b may be disposed on the lower chip 200a. The second upper pad 240 of the lower chip 200a may face the upper chip 200b. The second upper pad 240 of the lower chip 200a may be vertically aligned with the second lower pad 260 of the upper chip 200b. The lower chip 200a and the upper chip 200b may contact each other. The second via 230 of the lower chip 200a may be horizontally offset from the second via 230 of the upper chip 200b. The offset distance between the second via 230 of the lower chip 200a and the second via 230 of the upper chip 200b may be greater than half of the sum of the width of the second lower pad 260 and the width of the second via 230. In addition, the second via 230 of the lower chip 200a, the second upper pad 240 of the lower chip 200a, and the second lower pad 260 of the upper chip 200b may be vertically aligned with each other.

[0101] At the interface between the lower chip 200a and the upper chip 200b, the second upper protective layer 250 of the lower chip 200a may be bonded to the second lower protective layer 270 of the upper chip 200b. Here, the second upper protective layer 250 and the second lower protective layer 270 may form a mixed bonding structure of oxide, nitride or oxynitride. For example, the second upper protective layer 250 and the second lower protective layer 270 bonded to each other may have a continuous structure, and there may be no visible interface between the second upper protective layer 250 and the second lower protective layer 270. In other words, the second upper protective layer 250 and the second lower protective layer 270 may be set as a single object. However, the inventive concept is not limited to this example. The second upper protective layer 250 and the second lower protective layer 270 may be formed of or include materials different from each other. The second upper protective layer 250 and the second lower protective layer 270 may not have a continuous structure, and there may be a visible interface between the second upper protective layer 250 and the second lower protective layer 270.

[0102] The lower chip 200a can be bonded to the upper chip 200b. For example, the lower chip 200a and the upper chip 200b can contact each other. At the interface between the lower chip 200a and the upper chip 200b, the second upper pad 240 of the lower chip 200a can be bonded to the second lower pad 260 of the upper chip 200b. For example, the second upper pad 240 and the second lower pad 260 can form a metal-to-metal hybrid bonding structure. For example, the second upper pad 240 and the second lower pad 260 bonded to each other can have a continuous structure, and there can be no visible interface between the second upper pad 240 and the second lower pad 260. In other words, the second upper pad 240 and the second lower pad 260 can be set as a single object.

[0103] According to an example embodiment of the inventive concept, the second vias 230 respectively included in at least two or all of the second semiconductor chips 200 may be horizontally offset from each other. In this case, the stresses applied to the second vias 230 in the vertical direction may not overlap each other. Therefore, the stress applied to the second vias 230 may be dispersed into the second upper protective layer 250 or the second lower protective layer 270. Therefore, the structural characteristics of the semiconductor package can be improved. In addition, the delamination problem between the second via 230, the second upper pad 240 and the second lower pad 260 caused by stress can be alleviated or prevented, thereby enhancing the electrical connection characteristics between the second via 230, the second upper pad 240 and the second lower pad 260. That is, a semiconductor package with improved electrical characteristics can be provided.

[0104] Further references Fig. 9, the chip stack CS may be mounted on the first semiconductor chip 100. The chip stack CS may be disposed on the first semiconductor chip 100. The first upper pad 140 of the first semiconductor chip 100 may be vertically aligned with the second lower pad 260 of the lowermost one of the second semiconductor chips 200. The bonding structure between the lowermost one of the second semiconductor chips 200 and the first semiconductor chip 100 may be the same as or similar to the bonding structure between the second semiconductor chips 200. For example, the first semiconductor chip 100 may contact the lowermost one of the second semiconductor chips 200, and at the interface between the first semiconductor chip 100 and the lowermost one of the second semiconductor chips 200, the first upper pad 140 of the first semiconductor chip 100 may be bonded to the second lower pad 260 of the lowermost one of the second semiconductor chips 200. In some example embodiments, the lowermost one of the second semiconductor chips 200 may be mounted on the first semiconductor chip 100 in a flip chip manner. For example, a connection terminal (e.g., a solder ball) may be provided for electrical connection between the first upper pad 140 of the first semiconductor chip 100 and the second lower pad 260 of the lowermost one of the second semiconductor chips 200. In this case, an underfill material may be provided in the space between the chip stack CS and the first semiconductor chip 100, and the underfill material may encapsulate the connection terminal.

[0105] The molding layer 300 may be disposed on the first semiconductor chip 100. The molding layer 300 may cover the top surface of the first semiconductor chip 100. The molding layer 300 may encapsulate the chip stack CS. For example, the molding layer 300 may cover the side surface of the second semiconductor chip 200. The molding layer 300 may protect the chip stack CS. The molding layer 300 may include an insulating material. For example, the molding layer 300 may be formed of or include an epoxy molding compound (EMC). Different from the structure shown, the molding layer 300 may be formed to cover the chip stack CS. In other words, the molding layer 300 may cover the rear surface of the uppermost second semiconductor chip 200 in the second semiconductor chip 200.

[0106] In the description of the exemplary embodiments to be explained below, for the sake of brevity, the previous reference Fig. 9 and Fig.10 Described elements may be identified by the same reference numerals without repeating their repeated descriptions.

[0107] Fig.11 is a cross-sectional view showing the structure of semiconductor chips bonded to each other.

[0108] Reference Fig.11 The redistribution layer 280 may be disposed between the second semiconductor substrate 210 of the lower chip 200a and the second upper protective layer 250. The redistribution layer 280 may include a redistribution insulating layer and a redistribution pattern 282 in the redistribution insulating layer.

[0109] The redistribution insulating layer may cover the top surface of the second semiconductor substrate 210. The second upper protective layer 250 and the second upper pad 240 may be disposed on the redistribution insulating layer. That is, the second upper protective layer 250 and the second upper pad 240 may be vertically spaced apart from the second semiconductor substrate 210 and the second via 230 by the redistribution insulating layer. The redistribution insulating layer may be formed of or include at least one of silicon nitride (SiN), silicon oxide (SiO), and silicon oxynitride (SiON).

[0110] The redistribution pattern 282 may be disposed in the redistribution insulating layer. The redistribution pattern 282 may electrically connect the second via 230 to the second upper pad 240. The redistribution pattern 282 may include interconnection patterns of various shapes (eg, referring to Figure 6 The second interconnection pattern 18 described above may include, for example, a redistribution pattern 282 that may include a horizontal interconnection pattern for horizontal connection and a vertical interconnection pattern for vertical connection.

[0111] Fig.11 An example is shown where the redistribution layer 280 is disposed only in the lower chip 200a, but the inventive concept is not limited to this example. In example embodiments, the redistribution layer 280 may be disposed between the second semiconductor substrate 210 of the upper chip 200b and the second upper protective layer 250, and all second semiconductor chips 200 (e.g., see Fig. 9 ) may have a redistribution layer 280 .

[0112] Fig.12 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concept.

[0113] Fig.11 An example is shown in which the second upper pad 240 of the lower chip 200 a is vertically aligned with the second via hole 230 of the lower chip 200 a , but the inventive concept is not limited to this example.

[0114] Reference Fig.12, the second via 230 of the lower chip 200a may be horizontally offset from the second upper pad 240 of the lower chip 200a. The following description will be given based on the second upper pad 240 and the second via 230 that are paired and electrically connected to each other. For example, the second upper pad 240 may not be vertically overlapped with the second via 230. For example, the offset distance between the second upper pad 240 and the second via 230 may be greater than half of the sum of the width of the second upper pad 240 and the width of the second via 230. Here, the offset direction between the second upper pad 240 and the second via 230 may be a horizontal direction.

[0115] The lower chip 200a and the upper chip 200b may contact each other. At the interface between the lower chip 200a and the upper chip 200b, the second upper pad 240 of the lower chip 200a may be bonded to the second lower pad 260 of the upper chip 200b. The second upper pad 240 may be vertically aligned with the second lower pad 260. The second upper pad 240 and the second lower pad 260 may be horizontally spaced apart from the second via 230 of the lower chip 200a and the second via 230 of the upper chip 200b. Here, when viewed in a plan view, the second upper pad 240 and the second lower pad 260, which are paired with each other, may be placed between the second via 230 of the lower chip 200a and the second via 230 of the upper chip 200b connected to them.

[0116] Fig.13 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concept.

[0117] Fig.12 An example is shown in which the second upper pad 240 and the second lower pad 260 are placed between the second via hole 230 of the lower chip 200 a and the second via hole 230 of the upper chip 200 b when viewed in a plan view, but the inventive concept is not limited to this example.

[0118] Reference Fig.13 , the second via hole 230 of the lower chip 200 a may be vertically aligned with the second via hole 230 of the upper chip 200 b .

[0119] The second upper pad 240 of the lower chip 200a may be horizontally offset from the second via 230. For the second upper pad 240 and the second via 230 that are paired and electrically connected to each other, the second upper pad 240 may not vertically overlap with the second via 230. The offset distance between the second upper pad 240 and the second via 230 may be greater than half of the sum of the width of the second upper pad 240 and the width of the second via 230.

[0120] The second lower pad 260 of the upper chip 200b may be horizontally offset from the second via 230. For the second lower pad 260 and the second via 230 that are bonded and electrically connected to each other, the second lower pad 260 may not vertically overlap the second via 230. The offset distance between the second lower pad 260 and the second via 230 may be greater than half of the sum of the width of the second lower pad 260 and the width of the second via 230.

[0121] The second upper pad 240 of the lower chip 200a may be vertically aligned with the second lower pad 260 of the upper chip 200b. Therefore, the offset direction of the second upper pad 240 of the lower chip 200a from the second via 230 may be the same as the offset direction of the second lower pad 260 of the upper chip 200b from the second via 230.

[0122] Reference Fig.13 , the second vias 230 of the lower chip 200a and the second vias 230 of the upper chip 200b are vertically aligned with each other, and the second upper pad 240 of the lower chip 200a and the second lower pad 260 of the upper chip 200b are vertically aligned with each other. The respective groups of the second vias 230 of the lower chip 200a and the second vias 230 of the upper chip 200b are offset from the respective groups of the second upper pad 240 of the lower chip 200a and the second lower pad 260 of the upper chip 200b in a direction parallel to the top surface of the lower chip 200a or the upper chip 200b by a distance that is 0.5 to 5 times the sum of the width of the second lower pad 260 and the width of the second via 230, or 0.5 to 5 times the sum of the width of the second upper pad 240 and the width of the second via 230.

[0123] Fig.14 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concept. Fig.15 is a cross-sectional view showing the structure of semiconductor chips bonded to each other.

[0124] Fig. 9 An example is shown in which active surfaces of all the second semiconductor chips 200 face the first semiconductor chip 100 , but the inventive concept is not limited to this example.

[0125] Reference Fig.14 , the second semiconductor chip 200 may be stacked on the first semiconductor chip 100. In an example embodiment, a pair of second semiconductor chips 200 adjacent to each other in the vertical direction may be arranged to have active surfaces facing each other. For example, the second semiconductor chips 200 may be bonded to each other in a face-to-face manner. In some example embodiments, a pair of second semiconductor chips 200 adjacent to each other in the vertical direction may be arranged to have inactive surfaces facing each other. That is, the second semiconductor chips 200 may be bonded to each other in a back-to-back manner.

[0126] In the following, reference will be made to Fig.14 and Fig.15 The second semiconductor chips 200, 200a and 200b are described in more detail. Fig.15 In the embodiment, for the purpose of distinction, the lower second semiconductor chip (hereinafter, the lower chip) and the upper second semiconductor chip (hereinafter, the upper chip) in the second semiconductor chips are identified by two different reference numerals 200a and 200b, but Fig.15 Each of the second semiconductor chips 200 a and 200 b may correspond to Fig.14 The second semiconductor chip 200 is provided.

[0127] The upper chip 200b may be disposed on the lower chip 200a. The active surface of the lower chip 200a may face the active surface of the upper chip 200b. For example, the lower chip 200a and the upper chip 200b may be disposed in a face-to-face manner. The second lower pad 260 of the lower chip 200a may face the upper chip 200b. The second lower pad 260 of the lower chip 200a may be vertically aligned with the second lower pad 260 of the upper chip 200b. In other words, Fig.15 The lower chip 200a can be connected with Fig.10 The inverted structure of the lower chip 200a is substantially the same. The lower chip 200a and the upper chip 200b may contact each other. The second via 230 of the lower chip 200a may be horizontally offset from the second via 230 of the upper chip 200b. The offset distance between the second via 230 of the lower chip 200a and the second via 230 of the upper chip 200b may be greater than half of the sum of the width of the second lower pad 260 and the width of the second via 230. In addition, the second via 230 of the lower chip 200a, the second lower pad 260 of the lower chip 200a, and the second lower pad 260 of the upper chip 200b may be vertically aligned with each other.

[0128] Fig.16 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concept.

[0129] Fig.15 An example is shown in which the second lower pad 260 of the lower chip 200 a is vertically aligned with the second via hole 230 of the lower chip 200 a , but the inventive concept is not limited to this example.

[0130] Reference Fig.16, the second via 230 of the lower chip 200a can be horizontally offset from the second lower pad 260 of the lower chip 200a. The second via 230 and the second lower pad 260 can be electrically connected to each other through the first interconnect pattern 262 therebetween. The following description will be given based on the second lower pad 260 and the second via 230 that are paired and electrically connected to each other. For example, the second lower pad 260 and the second via 230 may not be vertically overlapped with each other. For example, the offset distance between the second lower pad 260 and the second via 230 may be greater than half of the sum of the width of the second lower pad 260 and the width of the second via 230. Here, the offset direction between the second lower pad 260 and the second via 230 may be a horizontal direction.

[0131] The lower chip 200a and the upper chip 200b may contact each other. At the interface between the lower chip 200a and the upper chip 200b, the second lower pad 260 of the lower chip 200a may be bonded to the second lower pad 260 of the upper chip 200b. The second lower pad 260 of the lower chip 200a and the second lower pad 260 of the upper chip 200b may be vertically aligned with each other. The second lower pad 260 of the lower chip 200a and the second lower pad 260 of the upper chip 200b may be horizontally spaced apart from the second via 230 of the lower chip 200a and the second via 230 of the upper chip 200b. Here, the second lower pad 260 of the lower chip 200a and the second lower pad 260 of the upper chip 200b, which are paired with each other, may be connected to the second via 230 of the lower chip 200a and the second via 230 of the upper chip 200b, respectively, and may be placed between the second vias 230 of the lower chip 200a and the upper chip 200b connected to them.

[0132] Fig.17 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concept.

[0133] Fig.16 An example is shown in which the second lower pad 260 is placed between the second via hole 230 of the lower chip 200 a and the second via hole 230 of the upper chip 200 b when viewed in a plan view, but the inventive concept is not limited to this example.

[0134] Reference Fig.17 , the second via hole 230 of the lower chip 200 a may be vertically aligned with the second via hole 230 of the upper chip 200 b .

[0135] The second lower pad 260 of the lower chip 200a may be horizontally offset from the second via 230. For the second lower pad 260 and the second via 230 that are paired and electrically connected to each other, the second lower pad 260 may not vertically overlap with the second via 230. The offset distance between the second lower pad 260 and the second via 230 may be greater than half of the sum of the width of the second lower pad 260 and the width of the second via 230.

[0136] The second lower pad 260 of the upper chip 200b may be horizontally offset from the second via 230. For the second lower pad 260 and the second via 230 that are paired and electrically connected to each other, the second lower pad 260 may not vertically overlap the second via 230. The offset distance between the second lower pad 260 and the second via 230 may be greater than half of the sum of the width of the second lower pad 260 and the width of the second via 230.

[0137] The second lower pad 260 of the lower chip 200a and the second lower pad 260 of the upper chip 200b may be vertically aligned with each other. Therefore, the offset direction of the second lower pad 260 of the lower chip 200a from the second via hole 230 may be the same as the offset direction of the second lower pad 260 of the upper chip 200b from the second via hole 230.

[0138] In a semiconductor package according to some example embodiments of the inventive concept, a first interconnection line (e.g., a lower via) vertically penetrating a lower structure may be horizontally offset from a second interconnection line (e.g., an upper via) vertically penetrating an upper structure. In this case, the vertical stresses applied to the first interconnection line and the second interconnection line may not overlap each other. For example, the stress applied to the first interconnection line may be dispersed into the first insulating layer in the region above the first interconnection line, or may be transferred to the second insulating layer through the second pad and the first pad and dispersed into the second insulating layer. The stress applied to the second interconnection line may be dispersed into the second insulating layer in the region below the second interconnection line. In other words, a semiconductor package with improved structural characteristics may be provided. In addition, the delamination problem caused by the stress between the first and second interconnections and the first and second pads may be alleviated or prevented, thereby improving the electrical connection characteristics between the first and second interconnections and the first and second pads. In other words, the electrical characteristics of the semiconductor package may be further improved.

[0139] While some example embodiments of the inventive concept have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: a first semiconductor chip; as well as a second semiconductor chip, below the first semiconductor chip, The first semiconductor chip includes a first device layer, a first interconnection layer on a bottom surface of the first device layer, a first via hole vertically penetrating the first device layer and electrically connected to the first interconnection layer, and a first pad on a bottom surface of the first interconnection layer. The second semiconductor chip includes a second device layer, a second via hole vertically penetrating the second device layer, and a second pad on a top surface of the second device layer and electrically connected to the second via hole, and wherein the first semiconductor chip and the second semiconductor chip are in direct contact with each other, The first pad and the second pad comprise the same material and constitute a single integral object, The first via and the second via are offset from each other in a direction parallel to a bottom surface of the first device layer, and The first via is horizontally spaced apart from the first pad when viewed in a plan view, and the first via is electrically connected to the second pad through the first interconnection layer.

2. The semiconductor package according to claim 1, wherein: The first pad, the second pad, and the second via are vertically aligned with each other.

3. The semiconductor package according to claim 1, wherein: The first pad and the second pad are vertically aligned with each other, and When viewed in a plan view, the first pad and the second pad are spaced apart from the first via hole and the second via hole.

4. The semiconductor package according to claim 2 or 3, wherein: The second semiconductor chip further includes a redistribution layer on a top surface of the second device layer and electrically connecting the second pad to the second via.

5. The semiconductor package according to claim 1, wherein: The offset distance between the first via and the second via is greater than half of a sum of a first width of the first via and a second width of the first pad.

6. The semiconductor package according to claim 1, wherein: The second device layer also includes: a second semiconductor substrate, the second pad being disposed on a top surface of the second semiconductor substrate; and a second circuit layer, on the bottom surface of the second semiconductor substrate, and including a second semiconductor device disposed on the bottom surface of the second semiconductor substrate, The second via connects the second circuit layer to the second pad.

7. The semiconductor package according to claim 1, wherein: The second device layer also includes: a second semiconductor substrate, the second pad being disposed on a bottom surface of the second semiconductor substrate; and a second circuit layer, on the top surface of the second semiconductor substrate, The second via connects the second circuit layer to the second pad.

8. The semiconductor package according to claim 1, wherein: The first via hole, the second via hole, the first pad and the second pad are respectively provided in plural numbers, Each of the first vias is electrically connected to one of the second vias through the first pad and the second pad, and Each of the first pads is placed between two adjacent ones of the first via holes.

9. The semiconductor package according to claim 8, wherein: Each of the first pads is between side surfaces of the two adjacent ones of the first via holes when viewed in a plan view.

10. The semiconductor package according to claim 8, wherein: When viewed in a plan view, the first via holes are arranged in a lattice shape, and Each of the first pads is between four adjacent first via holes among the first via holes.

11. A semiconductor package, comprising: a first semiconductor chip; as well as a second semiconductor chip, on the first semiconductor chip, The first semiconductor chip includes a first semiconductor substrate, a first circuit layer on a bottom surface of the first semiconductor substrate, a first interconnection layer on a bottom surface of the first circuit layer, a first via vertically penetrating the first semiconductor substrate and the first circuit layer and electrically connected to the first interconnection layer, a redistribution layer on a top surface of the first semiconductor substrate, and a first pad on a top surface of the redistribution layer. The second semiconductor chip includes a second semiconductor substrate, a second circuit layer on a bottom surface of the second semiconductor substrate, a second interconnection layer on a bottom surface of the second circuit layer, a second via hole vertically penetrating the second semiconductor substrate and the second circuit layer and electrically connected to the second interconnection layer, and a second pad on a bottom surface of the second interconnection layer, and wherein the first via hole and the second via hole are vertically aligned with each other, The first pad and the second pad are vertically aligned with each other, and The respective groups of the first vias and the second vias are offset from the respective groups of the first pads and the second pads in a direction parallel to the top surface of the first semiconductor substrate by a distance that is 0.5 to 5 times the sum of the width of the first vias and the width of the first pad, or 0.5 to 5 times the sum of the width of the second vias and the width of the second pad.

12. The semiconductor package according to claim 11, wherein The first semiconductor chip and the second semiconductor chip are in direct contact with each other, and The first pad and the second pad include the same material and constitute a single integral object.

13. The semiconductor package according to claim 11, wherein: The first via is horizontally spaced apart from the first pad when viewed in plan view, and the first via is electrically connected to the first pad through the redistribution layer, and The second via is horizontally spaced apart from the second pad when viewed in a plan view, and the second via is electrically connected to the second pad through the second interconnection layer.

14. The semiconductor package according to claim 11, wherein The first via hole, the second via hole, the first pad and the second pad are respectively provided in plural numbers, Each of the first vias is electrically connected to one of the second vias through the first pad and the second pad, and Each of the first pads is between two adjacent first via holes among the first via holes.

15. The semiconductor package according to claim 14, wherein: Each of the first pads is between side surfaces of the two adjacent ones of the first via holes when viewed in a plan view.

16. The semiconductor package according to claim 14, wherein: When viewed in a plan view, the first vias are in a lattice shape, and Each of the first pads is placed between four adjacent ones of the first via holes.

17. A semiconductor package, comprising: substrate; a first semiconductor chip on a substrate; a second semiconductor chip, below the first semiconductor chip; as well as a molding layer on the substrate and encapsulating the first semiconductor chip and the second semiconductor chip, The first semiconductor chip includes a first semiconductor substrate, a first circuit layer on a bottom surface of the first semiconductor substrate, a first interconnection layer on a bottom surface of the first circuit layer, a first via hole vertically penetrating the first semiconductor substrate and the first circuit layer and electrically connected to the first interconnection layer, and a first pad on a bottom surface of the first interconnection layer. The second semiconductor chip includes a second semiconductor substrate, a second via hole vertically penetrating the second semiconductor substrate, and a second pad on the top surface of the second semiconductor substrate, and wherein the first semiconductor chip and the second semiconductor chip are in direct contact with each other, each of the first pads and a corresponding one of the second pads comprises the same material and constitutes a single integral object, When viewed in a plan view, the first via hole is in a lattice shape, and the first pad is in a lattice shape, and Each of the first pads is between four adjacent first via holes among the first via holes.

18. The semiconductor package according to claim 17, wherein: The first via hole and the second via hole are offset from each other in a direction parallel to a bottom surface of the first semiconductor substrate.

19. The semiconductor package according to claim 18, wherein: The first pad, the second pad, and the second via are vertically aligned with each other.

20. The semiconductor package according to claim 18, wherein The first pad and the second pad are vertically aligned with each other, and When viewed in a plan view, the first pad and the second pad are spaced apart from the first via hole and the second via hole.

Images