High-zero-depth phased-array antenna unit

Abstract

The invention relates to a high-zero-depth phased-array antenna unit. The high-zero-depth phased-array antenna unit comprises a first dielectric substrate, a second dielectric substrate, a third dielectric substrate, a fourth dielectric substrate, a DSPSL power divider network and a tuning radiation unit, the tuning radiation unit adopts a double-layer tuning radiation unit structure, the middle parts of the four side edges of each layer of tuning radiation unit are all provided with grooves, and a plurality of tuning feed columns are adopted in the grooves for feeding, so that the balance effect of a unit space field and a phase is realized, mutual superposition is weakened, and the radiation efficiency is improved. And the zero depth of the phased-array antenna unit is increased. The feed network adopts a DSPSL power divider network, so that 180-degree phase difference and amplitude difference of diagonal feed in an ultra-wideband range are ensured; butterfly-shaped, fan-shaped and other bilaterally-symmetrical gaps are adopted in the DSPSL power divider network, and impedance matching of a non-power-dividing end and the field vector direction in an antenna unit can be adjusted.

Description

Technical Field

[0001] The present application relates to the technical field of phased array antennas, and in particular to a high zero-depth phased array antenna unit. Background Art

[0002] With the technological advancement and continuous cost optimization of phased array antennas, there will be more and more use scenarios for phased array antennas in the future. High integration, broadband and low cost are the mainstream of future phased array antennas. In particular, for the positioning and tracking of moving objects, high zero-depth phased array radar antennas are required. The existing antenna unit forms, whether they are patch, dipole or Vivaldi unit structures, have low zero-depth values ​​when the array is formed, basically between 20 and 30 dB, which has low pointing accuracy for high-precision positioning application scenarios. Summary of the invention

[0003] In order to at least overcome the problem of low zero depth value of phased array antenna units in the related art to a certain extent, the present application provides a high zero depth phased array antenna unit.

[0004] The scheme of this application is as follows: A high zero-depth phased array antenna unit, comprising: A first dielectric substrate, a second dielectric substrate, a third dielectric substrate, a fourth dielectric substrate, a DSPSL (Double-Sided Parallel-Strip Line) power divider network and a tuned radiating unit; The first dielectric substrate, the second dielectric substrate, the third dielectric substrate and the fourth dielectric substrate are stacked in sequence from bottom to top; The DSPSL power divider network is arranged in the first dielectric substrate and the second dielectric substrate; The tuned radiation unit is arranged in the third dielectric substrate and the fourth dielectric substrate; The DSPSL power divider network has left-right symmetrical gaps inside; The tuned radiating unit comprises: a right-side tuned lumped component, a left-side tuned lumped component, a lower tuned radiating unit, an upper tuned radiating unit and a plurality of tuned feeding poles; The lower tuning radiation unit and the upper tuning radiation unit are square structures, and the middle parts of the four sides of the square structure are provided with grooves; Each of the tuning and feeding posts is arranged in a different groove; The right tuning lumped component and the left tuning lumped component are arranged in symmetrical grooves.

[0005] Preferably, there are two or four tuning feed posts.

[0006] Preferably, the tuning feed column includes a resistor, a capacitor or an inductor.

[0007] Preferably, the down-tuning radiation unit and the tuning feed column are arranged in the third dielectric substrate; The upper tuning radiation unit, the right tuning lumped components and the left tuning lumped components are arranged in the fourth dielectric substrate.

[0008] Preferably, the DSPSL power divider network comprises: DSPSL lower microstrip line, field resonance slot ground, first feed post of power divider, lower microstrip line end impedance adapter, field resonance slot fan-outer, DSPSL upper microstrip line, upper microstrip line end impedance adapter and second feed post of power divider; The DSPSL lower microstrip line, the first feeding column of the power divider, and the lower microstrip line end impedance adapter are arranged in the first dielectric substrate; The DSPSL upper microstrip line, the upper microstrip line end impedance adapter and the second feeding column of the power divider are arranged in the second dielectric substrate; The field resonance gap is arranged between the first dielectric substrate and the second dielectric substrate; The field resonance slot fan-shaped device is arranged inside the field resonance slot, and the field resonance slot fan-shaped device has left-right symmetrical slots.

[0009] The technical solution provided by this application may have the following beneficial effects: The high zero-depth phased array antenna unit in the present application includes: a first dielectric substrate, a second dielectric substrate, a third dielectric substrate, a fourth dielectric substrate, a DSPSL power divider network and a tuned radiation unit; the first dielectric substrate, the second dielectric substrate, the third dielectric substrate and the fourth dielectric substrate are stacked in sequence from bottom to top; the DSPSL power divider network is arranged in the first dielectric substrate and the second dielectric substrate; the tuned radiation unit is arranged in the third dielectric substrate and the fourth dielectric substrate; the DSPSL power divider network has left-right symmetrical gaps inside; the tuned radiation unit includes: right-side tuning lumped components, left-side tuning lumped components, a lower tuning radiation unit, an upper tuning radiation unit and a plurality of tuning feed pillars; the lower tuning radiation unit and the upper tuning radiation unit are square structures, and grooves are provided in the middle parts of the four sides of the square structure; each tuning feed pillar is arranged in a different groove; the right-side tuning lumped components and the left-side tuning lumped components are arranged in symmetrical grooves.

[0010] The tuned radiating unit in the present application adopts a double-layer tuned radiating unit structure, and grooves are opened in the middle part of the four sides of each layer of tuned radiating unit, and multiple tuning feeding posts are used for feeding at the groove position, so as to achieve the balance effect of the unit space field and phase, weaken the mutual superposition, and increase the zero depth of the phased array antenna unit. The feeding network adopts the DSPSL power divider network to ensure the 180° phase difference and amplitude difference of its diagonal feeding within the ultra-wideband range; the DSPSL power divider network adopts butterfly-shaped, fan-shaped and other left-right symmetrical gaps to adjust the impedance matching of the non-power dividing end and the field vector direction inside the antenna unit.

[0011] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0013] Figure 1 It is a structural schematic diagram of a high zero-depth phased array antenna unit provided by an embodiment of the present application; Figure 2 It is a schematic structural diagram of a tuned radiation unit in a high zero-depth phased array antenna unit provided by an embodiment of the present application; Figure 3 It is a structural schematic diagram of a DSPSL power divider network in a high zero-depth phased array antenna unit provided by an embodiment of the present application; Figure 4 is an exploded diagram of a high zero-depth phased array antenna unit provided by an embodiment of the present application; Figure 5 This is a top view of a high zero-depth phased array antenna unit provided by an embodiment of the present application.

[0014] Figure numerals: first dielectric substrate-1; second dielectric substrate-2; third dielectric substrate-3; fourth dielectric substrate-4; DSPSL power divider network-5; DSPSL lower microstrip line-501; field resonance slot ground-502; first feeding post of power divider-503; impedance adapter at the end of lower microstrip line-504; field resonance slot fan-shaped device-505; DSPSL upper microstrip line-506; impedance adapter at the end of upper microstrip line-507; second feeding post of power divider-508; tuned radiating unit-6; right tuned lumped component-601; left tuned lumped component-602; lower tuned radiating unit-603; upper tuned radiating unit-604; first tuned feeding post-605; second tuned feeding post-606. DETAILED DESCRIPTION

[0015] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0016] Figure 1 is a schematic diagram of a high zero-depth phased array antenna unit provided by an embodiment of the present application, referring to Figure 1 , a high zero-depth phased array antenna unit, comprising: A first dielectric substrate 1, a second dielectric substrate 2, a third dielectric substrate 3, a fourth dielectric substrate 4, a DSPSL power divider network 5 and a tuned radiation unit 6; The first dielectric substrate 1, the second dielectric substrate 2, the third dielectric substrate 3 and the fourth dielectric substrate 4 are stacked in sequence from bottom to top; The DSPSL power divider network 5 is arranged in the first dielectric substrate 1 and the second dielectric substrate 2; The tuned radiation unit 6 is arranged in the third dielectric substrate 3 and the fourth dielectric substrate 4; The DSPSL power divider network 5 has left-right symmetrical gaps inside; The tuned radiation unit 6 includes: a right-side tuned lumped component 601, a left-side tuned lumped component 602, a lower tuned radiation unit 603, an upper tuned radiation unit 604 and a plurality of tuned feeding posts; The lower tuning radiation unit 603 and the upper tuning radiation unit 604 are square structures, and the middle parts of the four sides of the square structure are provided with grooves; Each tuning feed column is arranged in a different groove; The right tuning lumped component 601 and the left tuning lumped component 602 are arranged in symmetrical grooves.

[0017] It should be noted that the first dielectric substrate 1 , the second dielectric substrate 2 , the third dielectric substrate 3 , and the fourth dielectric substrate 4 may be dielectric substrates commonly used in the prior art, such as PCB dielectric substrates.

[0018] It should be noted that there are two or four tuning feed poles to realize a double-feed or quad-feed feeding structure. Figure 2 is a schematic structural diagram of a tuned radiation unit 6 in a high zero-depth phased array antenna unit provided by an embodiment of the present application, Figure 4 FIG. 1 is an exploded diagram of a high zero-depth phased array antenna unit provided by an embodiment of the present application, such as Figure 2 or Figure 4As shown, the tuning feed pillars include a first tuning feed pillar 605 and a second tuning feed pillar 606 , and the first tuning feed pillar 605 and the second tuning feed pillar 606 are disposed in adjacent side grooves.

[0019] In specific practice, the tuned feed post includes lumped elements such as resistors, capacitors or inductors.

[0020] It should be noted that the lower tuning radiation unit 603 and the tuning feeding column are arranged in the third dielectric substrate 3; The upper tuning radiation unit 604 , the right tuning lumped component 601 and the left tuning lumped component 602 are arranged in the fourth dielectric substrate 4 .

[0021] Figure 3 is a structural diagram of a DSPSL power divider network 5 in a high zero-depth phased array antenna unit provided by an embodiment of the present application, Figure 4 is an exploded diagram of a high zero-depth phased array antenna unit provided by an embodiment of the present application, referring to Figure 3-Figure 4 , the DSPSL power divider network 5 comprises: DSPSL lower microstrip line 501, field resonance slot ground 502, power divider first feeding post 503, lower microstrip line end impedance adapter 504, field resonance slot fan-outer 505, DSPSL upper microstrip line 506, upper microstrip line end impedance adapter 507 and power divider second feeding post 508; The DSPSL lower microstrip line 501, the power divider first feeding column 503, and the lower microstrip line end impedance adapter 504 are arranged in the first dielectric substrate 1; The DSPSL upper microstrip line 506, the upper microstrip line end impedance adapter 507 and the power divider second feeding column 508 are arranged in the second dielectric substrate 2; The field resonance gap 502 is arranged between the first dielectric substrate 1 and the second dielectric substrate 2; The field resonance slot sector 505 is disposed inside the field resonance slot 502, and the field resonance slot sector 505 has left-right symmetrical slots.

[0022] The top view of the high zero-depth phased array antenna unit is as follows Figure 5 As shown. Figure 5 It can be seen that the slot of the field resonance slot sector 505 is a bilaterally symmetrical structure. In specific practice, the slot of the field resonance slot sector 505 can be a bilaterally symmetrical structure such as a fan-shaped structure, a butterfly structure or a star-shaped structure.

[0023] Experimental data proves that the zero-depth radiation patterns of the four-element array antenna and the sixteen-element array antenna composed of the tuned radiation unit 6 can continue to change in a positive direction as the number of elements increases, that is, the increase in the zero depth of the phased array antenna unit is achieved.

[0024] The tuned radiation unit 6 in the technical solution adopts the structure of a double-layer tuned radiation unit 6, and the middle part of the four sides of each layer of the tuned radiation unit 6 is provided with grooves, and multiple tuning feeding posts are used for feeding at the groove position, so as to achieve the balance effect of the unit space field and phase, weaken the mutual superposition, and increase the zero depth of the phased array antenna unit. The feeding network adopts the DSPSL power divider network 5 to ensure the 180° phase difference and amplitude difference of its diagonal feeding within the ultra-wideband range; the DSPSL power divider network 5 adopts butterfly-shaped, fan-shaped and other left-right symmetrical gaps inside, which can adjust the impedance matching of the non-power dividing end and the field vector direction inside the antenna unit.

[0025] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.

[0026] It should be noted that, in the description of this application, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, the meaning of "plurality" refers to at least two.

[0027] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0028] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0029] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A high zero-depth phased array antenna unit, characterized in that: include: A first dielectric substrate, a second dielectric substrate, a third dielectric substrate, a fourth dielectric substrate, a DSPSL power divider network and a tuned radiation unit; The first dielectric substrate, the second dielectric substrate, the third dielectric substrate and the fourth dielectric substrate are stacked in sequence from bottom to top; The DSPSL power divider network is arranged in the first dielectric substrate and the second dielectric substrate; The tuned radiation unit is arranged in the third dielectric substrate and the fourth dielectric substrate; The DSPSL power divider network has left-right symmetrical gaps inside; The tuned radiating unit comprises: a right-side tuned lumped component, a left-side tuned lumped component, a lower tuned radiating unit, an upper tuned radiating unit and a plurality of tuned feeding poles; The lower tuning radiation unit and the upper tuning radiation unit are square structures, and the middle parts of the four sides of the square structure are provided with grooves; Each of the tuning and feeding posts is arranged in a different groove; The right tuning lumped component and the left tuning lumped component are arranged in symmetrical grooves.

2. The high zero-depth phased array antenna unit according to claim 1, characterized in that: The number of the tuning and feeding posts is two or four.

3. The high zero-depth phased array antenna unit according to claim 1, characterized in that: The tuning feed column includes a resistor, a capacitor or an inductor.

4. The high zero-depth phased array antenna unit according to claim 1, characterized in that: The lower tuning radiation unit and the tuning feed column are arranged in the third dielectric substrate; The upper tuning radiation unit, the right tuning lumped components and the left tuning lumped components are arranged in the fourth dielectric substrate.

5. The high zero-depth phased array antenna unit according to claim 1, characterized in that: The DSPSL power divider network includes: DSPSL lower microstrip line, field resonance slot ground, first feed post of power divider, lower microstrip line end impedance adapter, field resonance slot fan-outer, DSPSL upper microstrip line, upper microstrip line end impedance adapter and second feed post of power divider; The DSPSL lower microstrip line, the first feeding column of the power divider, and the lower microstrip line end impedance adapter are arranged in the first dielectric substrate; The DSPSL upper microstrip line, the upper microstrip line end impedance adapter and the second feeding column of the power divider are arranged in the second dielectric substrate; The field resonance gap is arranged between the first dielectric substrate and the second dielectric substrate; The field resonance slot fan-shaped device is arranged inside the field resonance slot, and the field resonance slot fan-shaped device has left-right symmetrical slots.

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