Fault protection circuit and system of CAN bus

Abstract

The invention discloses a fault protection circuit and system of a CAN bus, and belongs to the technical field of CAN bus transceivers, the fault protection circuit comprises a PMOS transistor, an NMOS transistor and a Zener diode, the drain electrode of the PMOS transistor serves as an output port and is used for outputting signals, the base electrode and the source electrode of the PMOS transistor are jointly connected to the drain electrode of the NMOS transistor, the grid electrode of the PMOS transistor is connected with a grounding end, and the Zener diode is used for outputting the signals. The cathode of the Zener diode is connected with the source electrode of the PMOS tube, the anode of the Zener diode is connected with the grid electrode of the PMOS tube, and the base electrode and the source electrode of the NMOS tube are jointly connected to serve as an input port and used for being connected with a protected circuit. A fault protection circuit is formed by connecting a PMOS tube and an NMOS tube, so that the voltage of a protected circuit is ensured, and the protected circuit is prevented from being damaged when a CAN bus pin is connected to a positive direct-current high voltage or a negative direct-current high voltage.

Description

Technical Field

[0001] The present invention relates to the technical field of CAN bus transceivers, and in particular to a fault protection circuit and system for a CAN bus. Background Art

[0002] The Controller Area Network (CAN) bus is widely used in the automotive and industrial control fields with complex working environments. However, faults may occur during its operation, causing the bus to be short-circuited to power supplies such as ±12V, ±24V or even higher. To avoid damage to the CAN bus transceiver, a bus fault protection circuit is often connected in series between the data line pins and the driver of the CAN bus to ensure that the CAN bus transceiver can still work normally after the DC fault voltage disappears.

[0003] exist Figure 1 In the bus driving circuit structure of the CAN bus transceiver shown, CANH10 (high data line) and CANL20 (low data line) are respectively connected to the CAN bus, the power supply of the protected circuit, i.e., the driving circuit part, is generally 5V or 3.3V, and the bus fault protection voltage is generally ±16V, ±40V, ±58V or ±70V. A first bus fault protection circuit 11 and a second bus fault protection circuit 21 are respectively connected in series between the CANH driver 12 and CANH10 and the CANL driver 22 and CANL20 to protect the driving circuit when a fault occurs.

[0004] For example Figure 2 The bus fault protection circuit implementation scheme in the conventional technology is implemented by connecting the first high-voltage diode D1 and the second high-voltage diode D2 in series between the CANH driver 12 and CANH10 and the CANL driver 22 and CANL20 respectively to protect the driving circuit. Although the first high-voltage diode D1 can effectively block the positive DC fault high voltage of the CANH10 pin, it cannot effectively block the negative DC fault high voltage of the CANH10 pin; relatively, the second high-voltage diode D2 can effectively block the negative DC fault high voltage of the CANL20 pin, but cannot effectively block the positive DC fault high voltage of the CANL20 pin.

[0005] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention

[0006] The object of the present invention is to provide a fault protection circuit and system for a CAN bus, so as to solve the problem in the prior art that the fault protection circuit can only block a single-direction fault high voltage.

[0007] In order to solve the above technical problems, the present invention provides a fault protection circuit, comprising a PMOS tube, an NMOS tube and a Zener diode, wherein the drain of the PMOS tube is used as an output port for receiving a signal, the base and source of the PMOS tube are commonly connected to the drain of the NMOS tube, the gate of the PMOS tube is connected to a ground terminal, the cathode of the Zener diode is connected to the source of the PMOS tube, the anode of the Zener diode is connected to the gate of the PMOS tube, and the base and source of the NMOS tube are commonly connected as an input port for connecting a protected circuit:

[0008] When negative DC high voltage appears, the PMOS tube is turned on, the Zener diode is reversely conducted to protect the PMOS tube, and the gate of the NMOS tube is connected to the power supply voltage to reduce the voltage at the input port;

[0009] When a positive DC high voltage appears, the PMOS tube is turned on and then turned off, while the NMOS tube is always turned on to ensure the voltage at the input port;

[0010] The direction of the voltage drop from the input port to the output port is recorded as a negative direction, and the opposite direction is recorded as a positive direction.

[0011] Preferably, the gate of the PMOS tube is also connected to the ground terminal through a resistor.

[0012] Preferably, the NMOS tube is an N-type LDMOS tube.

[0013] Preferably, the PMOS tube is a P-type LDMOS tube.

[0014] A fault protection circuit for a CAN bus, comprising a CAN bus pin, a protected circuit and a fault protection circuit, wherein an input port and an output port of the fault protection circuit are respectively connected to the protected circuit and the CAN bus pin, the fault protection circuit comprises a PMOS tube, an NMOS tube and a Zener diode, the drain of the PMOS tube serves as the output port for connecting to the CAN bus pin, the base and source of the PMOS tube are commonly connected to the drain of the NMOS tube, the cathode of the Zener diode is connected to the source of the PMOS tube, the anode of the Zener diode is connected to the gate of the PMOS tube, the base and source of the NMOS tube are commonly connected as the input port for connecting to the protected circuit, and the gate of the PMOS tube is also connected to a ground terminal through a resistor, wherein:

[0015] When negative DC high voltage appears, the PMOS tube is turned on, the Zener diode is reversely conducted to protect the PMOS tube, and the gate of the NMOS tube is connected to the power supply voltage to reduce the voltage at the input port;

[0016] When a positive DC high voltage appears, the PMOS tube is turned on and then turned off, and the NMOS tube is always turned on to ensure the voltage at the input port;

[0017] The direction of the voltage drop from the input port to the output port is recorded as negative, and the opposite direction is recorded as positive.

[0018] Preferably, the NMOS tube is an N-type LDMOS tube.

[0019] Preferably, the PMOS tube is a P-type LDMOS tube.

[0020] Preferably, the CAN bus pin is a CANH pin, and the protected circuit is a CANH driver.

[0021] Preferably, the CAN bus pin is a CANL pin, and the protected circuit is a CANL driver.

[0022] A CAN bus system includes the above-mentioned CAN bus fault protection circuit.

[0023] In the fault protection circuit and the fault protection circuit of the CAN bus provided by the present invention, the power supply voltage is connected through the NMOS tube to ensure the voltage at the input port under positive DC high voltage. Under negative DC high voltage, the PMOS tube is turned on and then cut off, and the protected circuit connected to the input port is protected by the NMOS tube being turned on, thereby effectively blocking the positive and negative DC high voltages.

[0024] The CAN bus system provided by the present invention and the fault protection circuit and the fault protection circuit of the CAN bus provided by the present invention belong to the same inventive concept. Therefore, the CAN bus system provided by the present invention has at least all the advantages of the fault protection circuit and the fault protection circuit of the CAN bus provided by the present invention, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a circuit diagram of a bus driving circuit of an existing CAN bus transceiver;

[0026] Figure 2 It is a circuit diagram of a fault protection circuit of a CAN bus in conventional technology;

[0027] Figure 3 It is a circuit diagram of a fault protection circuit of a CAN bus provided by an embodiment of the present invention;

[0028] Figure 4 It is a schematic diagram of a parasitic diode formed on a PMOS tube provided by an embodiment of the present invention.

[0029] Figure 1-Figure 2 middle:

[0030] 10. CANH; 11. First bus fault protection circuit; 12. CANH driver; 20. CANL; 21. Second bus fault protection circuit; 22. CANL driver.

[0031] Figure 3-Figure 4 middle:

[0032] 100, CAN bus pin; 200, fault protection circuit; 201, output port; 202, intermediate node; 203, input port; 300, protected circuit. DETAILED DESCRIPTION

[0033] The fault protection circuit and system of the CAN bus proposed by the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be understood that the drawings in the specification do not necessarily show the specific structure of the present invention in proportion, and the illustrative features used to illustrate certain principles of the present invention in the drawings in the specification will also adopt a slightly simplified drawing method. The specific design features of the present invention disclosed herein include, for example, specific dimensions, directions, positions and shapes, which will be determined in part by the specific environment to be applied and used. And, in the embodiments described below, sometimes the same figure mark is used in common between different drawings to represent the same part or a part with the same function, and its repeated description is omitted. In this specification, similar numbers and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0034] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0035] The inventors have found that there are certain limitations to using only high-voltage diodes to protect the drive circuit. The high-voltage diode can only block the DC high voltage in a single direction, but it is difficult to block the DC high voltage from the other direction. In actual use, the high data line (CANH) pin and the low data line (CANL) pin of the CAN bus can easily be shorted to the power supply voltage of ±12V, ±24V or even higher, thereby causing DC fault high voltage.

[0036] Based on this, the core idea of ​​the present invention is to form a fault protection circuit by connecting PMOS tubes and NMOS tubes to ensure the voltage of the protected circuit and avoid damage to the protected circuit when the CAN bus pin is connected to positive DC high voltage or negative DC high voltage.

[0037] Specifically, Figure 3 As shown, a fault protection circuit includes a PMOS tube P1, an NMOS tube N1 and a Zener diode D3, wherein the drain of the PMOS tube P1 is used as an output port 201 for receiving a signal, the base and source of the PMOS tube P1 are commonly connected to the drain of the NMOS tube N1, the gate of the PMOS tube P1 is connected to a ground terminal GND, the cathode of the Zener diode D3 is connected to the source of the PMOS tube P1, the anode of the Zener diode D3 is connected to the gate of the PMOS tube P1, and the base and source of the NMOS tube N1 are commonly connected as an input port 203 for connecting to a protected circuit 300:

[0038] When negative DC high voltage appears, the PMOS transistor P1 is turned on, the Zener diode D3 is reversely turned on to protect the PMOS transistor P1, and the gate of the NMOS transistor N1 is connected to the power supply voltage VDD to reduce the voltage at the input port 203;

[0039] When a positive DC high voltage appears, the PMOS transistor P1 is turned on and then turned off, while the NMOS transistor N1 is always turned on to ensure the voltage at the input port 203;

[0040] The direction of the voltage drop from the input port 203 to the output port 201 is recorded as a negative direction, and the opposite direction is recorded as a positive direction.

[0041] In normal operation, since the gate of the NMOS tube N1 is connected to the power supply voltage VDD, the NMOS tube N1 is turned on; the PMOS tube P1 is turned on, and its gate is connected to the ground terminal GND, so the current output by the protected circuit 300 can be output through the NMOS tube N1 and the PMOS tube P1. The voltage at the input port 203 under positive DC high voltage is guaranteed by connecting the NMOS tube N1 to the power supply voltage VDD. Under negative DC high voltage, the PMOS tube P1 is turned on and then turned off. The protected circuit 300 connected to the input port 203 is protected by the NMOS tube N1 being turned on, thereby effectively blocking the positive and negative DC high voltages.

[0042] When a forward DC high voltage appears at the output port 201, the parasitic diode between the drain and the base of the PMOS tube P1 may be turned on. Figure 4 As shown, the intermediate node 202 will also have a positive DC high voltage, and the drain of the NMOS tube, that is, the intermediate node 202, can withstand a higher positive DC high voltage without being damaged. Since the gate of the NMOS tube N1 is connected to the power supply voltage VDD, the voltage of its source, that is, the input port 203, is not higher than the power supply voltage VDD, so the voltage at the input port 203 is reduced, and the protected circuit 300 can be effectively protected.

[0043] When negative DC high voltage appears at the output port 201, after the PMOS tube P1 is turned on for a period of time, when the voltage at the intermediate node 202 gradually decreases to close to 0V, the PMOS tube P1 is turned off, thereby preventing the voltage at the intermediate node 202 from further decreasing. Therefore, the voltage at the intermediate node 202 will not decrease below 0V, the NMOS tube N1 is always turned on, and the voltage at the input port 203 cannot decrease below 0V, thereby effectively protecting the protected circuit 300 connected to the input port 203.

[0044] In addition, the breakdown voltage between the gate and the source of the PMOS tube P1 is relatively low, generally not exceeding 6V. The gate and the source of the PMOS tube P1 cannot withstand high voltage, so a Zener diode D3 is connected in series between the two. If the Zener diode D3 is not provided, when a forward DC high voltage such as +70V voltage appears at the intermediate node 202, the voltage difference between the source and the gate of the PMOS tube P1 will be equal to 70V, which is much higher than the breakdown voltage between the source and the gate, thereby causing the gate oxide of the PMOS tube P1 to be broken down, causing irreversible damage to the PMOS tube P1; the negative electrode, i.e., the N electrode, of the Zener diode D3 is connected to the intermediate node 202, and the positive electrode, i.e., the P electrode, is connected to the gate of the PMOS tube P1. When a forward DC high voltage appears at the intermediate node 202, the Zener diode D3 will be reversely conducted. When the Zener diode D3 is reversely conducted, the voltage across the two ends thereof is lower than the breakdown voltage between the gate and the source of the PMOS tube P1, thereby avoiding irreversible breakdown damage to the gate oxide of the PMOS tube P1.

[0045] Figure 3 The input port 203 and the output port 201 of the fault protection circuit 200, the input port 203 is often used to connect the protected circuit 300, when protecting the CAN bus driving circuit, the protected circuit 300 is a CANH driver or a CANL driver, and correspondingly, the output port 201 is connected to the CANH or CANL pin of the bus.

[0046] It can be understood that the protected circuit 300 often has a fixed supply voltage. Here, the positive DC high voltage often refers to the positive voltage connected to the CAN bus pin 100 that exceeds the supply voltage of the protected circuit 300, and the negative DC high voltage refers to the negative voltage connected to the CAN bus pin 100 that is lower than the supply voltage of the protected circuit 300.

[0047] Specifically, the gate of the PMOS tube P1 is also connected to the ground terminal GND through the resistor R1.

[0048] Based on the above analysis, it can be known that the NMOS transistor N1 is a high-voltage-resistant N-type MOS transistor, for example, the NMOS transistor N1 is an N-type LDMOS transistor, and the PMOS transistor P1 is a high-voltage-resistant P-type MOS transistor, for example, the PMOS transistor P1 is a P-type LDMOS transistor.

[0049] The present invention also provides a fault protection circuit for a CAN bus based on the same concept, comprising a CAN bus pin 100, a protected circuit 300 and a fault protection circuit 200, wherein an input port 203 and an output port 201 of the fault protection circuit 200 are respectively connected to the protected circuit 300 and the CAN bus pin 100, the fault protection circuit 200 comprises a PMOS tube P1, an NMOS tube N1 and a Zener diode D3, the drain of the PMOS tube P1 serves as the output port 201 for connecting to the CAN bus pin 100, the base and source of the PMOS tube P1 are commonly connected to the drain of the NMOS tube N1, the cathode of the Zener diode D3 is commonly connected to the source of the PMOS tube P1, the anode of the Zener diode D3 is commonly connected to the gate of the PMOS tube P1, the base and source of the NMOS tube N1 are commonly connected as the input port 203 for connecting to the protected circuit 300, and the gate of the PMOS tube P1 is also commonly connected to the ground terminal GND through a resistor R1, wherein:

[0050] When negative DC high voltage appears, the PMOS transistor P1 is turned on, the Zener diode D3 is reversely turned on to protect the PMOS transistor P1, and the gate of the NMOS transistor N1 is connected to the power supply voltage VDD to reduce the voltage at the input port 203;

[0051] When a positive DC high voltage appears, the PMOS transistor P1 is turned on and then turned off, and the NMOS transistor N1 is always turned on to ensure the voltage at the input port 203;

[0052] The direction of the voltage drop from the input port 203 to the output port 201 is marked as negative, and the opposite direction is marked as positive.

[0053] The base and source of the NMOS tube N1 are connected to the input port 203, the drain is connected to the intermediate node 202, and the gate is connected to the power supply voltage VDD, which is generally 5V or 3.3V. The base and source of the PMOS tube P1 are connected to the intermediate node 202, the drain is connected to the output port 201 to the CAN bus pin 100, and the gate is grounded through the resistor R1. The cathode of the Zener diode D3 is connected to the intermediate node 202, and the anode is connected to the gate of the PMOS tube P1.

[0054] In normal operation, since the gate of the NMOS tube N1 is connected to the power supply voltage VDD, the NMOS tube N1 is turned on; the PMOS tube P1 is turned on, and its gate is connected to the ground terminal GND, so the current output by the protected circuit 300 can be output through the NMOS tube N1 and the PMOS tube P1. The voltage at the input port 203 under positive DC high voltage is guaranteed by connecting the NMOS tube N1 to the power supply voltage VDD. Under negative DC high voltage, the PMOS tube P1 is turned on and then turned off. The protected circuit 300 connected to the input port 203 is protected by the NMOS tube N1 being turned on, thereby effectively blocking the positive and negative DC high voltages.

[0055] When a forward DC high voltage appears at the output port 201, the parasitic diode between the drain and the base of the PMOS tube may be turned on, such as Figure 4 As shown, the intermediate node 202 will also have a positive DC high voltage, and the drain of the NMOS tube, that is, the intermediate node 202, can withstand a higher positive DC high voltage without being damaged. Since the gate of the NMOS tube is connected to the power supply voltage VDD, the voltage of its source end, that is, the input port 203, is not higher than the power supply voltage VDD, so the voltage at the input port 203 is reduced, and the protected circuit 300 can be effectively protected.

[0056] When negative DC high voltage appears at the output port 201, after the PMOS tube P1 is turned on for a period of time, when the voltage at the intermediate node 202 gradually decreases to close to 0V, the PMOS tube P1 is turned off, thereby preventing the voltage at the intermediate node 202 from further decreasing. Therefore, the voltage at the intermediate node 202 will not decrease below 0V, the NMOS tube N1 is always turned on, and the voltage at the input port 203 cannot decrease below 0V, thereby effectively protecting the protected circuit 300 connected to the input port 203.

[0057] In addition, the breakdown voltage between the gate and the source of the PMOS tube P1 is relatively low, generally not exceeding 6V. The gate and the source of the PMOS tube P1 cannot withstand high voltage, so a Zener diode D3 is connected in series between the two. If the Zener diode D3 is not provided, when a forward DC high voltage such as +70V voltage appears at the intermediate node 202, the voltage difference between the source and the gate of the PMOS tube P1 will be equal to 70V, which is much higher than the breakdown voltage between the source and the gate, thereby causing the gate oxide of the PMOS tube P1 to be broken down, causing irreversible damage to the PMOS tube P1; the negative electrode, i.e., the N electrode, of the Zener diode D3 is connected to the intermediate node 202, and the positive electrode, i.e., the P electrode, is connected to the gate of the PMOS tube P1. When a forward DC high voltage appears at the intermediate node 202, the Zener diode D3 will be reversely conducted. When the Zener diode D3 is reversely conducted, the voltage across the two ends thereof is lower than the breakdown voltage between the gate and the source of the PMOS tube P1, thereby avoiding irreversible breakdown damage to the gate oxide of the PMOS tube P1.

[0058] Based on the above analysis, it can be known that the NMOS transistor N1 is a high-voltage-resistant N-type MOS transistor, for example, the NMOS transistor N1 is an N-type LDMOS transistor, and the PMOS transistor P1 is a high-voltage-resistant P-type MOS transistor, for example, the PMOS transistor P1 is a P-type LDMOS transistor.

[0059] In one implementation, the CAN bus pin 100 is a CANH pin, and the protected circuit 300 is a CANH driver. Alternatively, the CAN bus pin 100 is a CANL pin, and the protected circuit 300 is a CANL driver. A fault protection circuit 200 may be connected to both the CANH pin and the CANL pin to block positive and negative DC high voltages, thereby effectively preventing damage to the protected circuit 300.

[0060] The present invention also provides a CAN bus system, including the above-mentioned CAN bus fault protection circuit. The CAN bus fault protection circuit of one or more of the above-mentioned embodiments is applied to the bus system of the automotive electrical network, such as the bus system of four-wheel drive or two-wheel drive vehicles driven by gasoline engines and / or diesel engines, natural gas-driven vehicles (such as natural gas trucks), pure electric vehicles, hybrid vehicles, etc.

[0061] In summary, in the fault protection circuit and system of the CAN bus provided in the embodiment of the present invention, the power supply voltage VDD is connected to the NMOS tube N1 to ensure the voltage at the input port 203 under positive DC high voltage, and under negative DC high voltage, the PMOS tube P1 is turned on and then cut off, and the protected circuit 300 connected to the input port 203 is protected by the NMOS tube N1 being turned on, thereby solving the problem in the prior art that the fault protection circuit can only block the fault high voltage in a single direction.

[0062] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A fault protection circuit, characterized in that: It includes a PMOS tube, an NMOS tube and a Zener diode, the drain of the PMOS tube is used as an output port for receiving a signal, the base and source of the PMOS tube are connected to the drain of the NMOS tube, the gate of the PMOS tube is connected to the ground terminal, the cathode of the Zener diode is connected to the source of the PMOS tube, the anode of the Zener diode is connected to the gate of the PMOS tube, and the base and source of the NMOS tube are connected as an input port for connecting to a protected circuit: When negative DC high voltage appears, the PMOS tube is turned on, the Zener diode is reversely conducted to protect the PMOS tube, and the gate of the NMOS tube is connected to the power supply voltage to reduce the voltage at the input port; When a positive DC high voltage appears, the PMOS tube is turned on and then turned off, while the NMOS tube is always turned on to ensure the voltage at the input port; The direction of the voltage drop from the input port to the output port is recorded as a negative direction, and the opposite direction is recorded as a positive direction.

2. The fault protection circuit according to claim 1, characterized in that: The gate of the PMOS tube is also connected to the ground terminal through a resistor.

3. The fault protection circuit according to claim 1, characterized in that: The NMOS tube is an N-type LDMOS tube.

4. The fault protection circuit according to claim 1, characterized in that: The PMOS tube is a P-type LDMOS tube.

5. A fault protection circuit for a CAN bus, characterized in that: It includes a CAN bus pin, a protected circuit and a fault protection circuit, wherein the input port and the output port of the fault protection circuit are respectively connected to the protected circuit and the CAN bus pin, the fault protection circuit includes a PMOS tube, an NMOS tube and a Zener diode, the drain of the PMOS tube serves as the output port for connecting to the CAN bus pin, the base and source of the PMOS tube are connected to the drain of the NMOS tube, the cathode of the Zener diode is connected to the source of the PMOS tube, the anode of the Zener diode is connected to the gate of the PMOS tube, the base and source of the NMOS tube are connected as the input port for connecting to the protected circuit, and the gate of the PMOS tube is also connected to the ground terminal through a resistor, wherein: When negative DC high voltage appears, the PMOS tube is turned on, the Zener diode is reversely conducted to protect the PMOS tube, and the gate of the NMOS tube is connected to the power supply voltage to reduce the voltage at the input port; When a positive DC high voltage appears, the PMOS tube is turned on and then turned off, and the NMOS tube is always turned on to ensure the voltage at the input port; The direction of the voltage drop from the input port to the output port is recorded as negative, and the opposite direction is recorded as positive.

6. The fault protection circuit of the CAN bus as claimed in claim 5, characterized in that: The NMOS tube is an N-type LDMOS tube.

7. The fault protection circuit of the CAN bus as claimed in claim 5, characterized in that: The PMOS tube is a P-type LDMOS tube.

8. The fault protection circuit of the CAN bus as claimed in claim 5, characterized in that: The CAN bus pin is a CANH pin, and the protected circuit is a CANH driver.

9. The fault protection circuit of the CAN bus as claimed in claim 5, characterized in that: The CAN bus pin is a CANL pin, and the protected circuit is a CANL driver.

10. A CAN bus system, characterized in that: A fault protection circuit for a CAN bus comprising the method described in any one of claims 5 to 9.

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