Single-sensor digital control method of three-level flying capacitor buck converter

Abstract

The invention discloses a single-sensor digital control method for a three-level flying capacitor buck converter. The method comprises the following steps: analyzing the circuit working mechanism of the three-level flying capacitor buck converter, wherein the circuit working mechanism comprises the on-off logic of each switching device, four static working modes and two dynamic working switching modes when the circuit is in normal operation; taking one static working mode point (1, 0) as an example to analyze the influence of flying capacitor voltage balance on the normal operation of the circuit; the invention provides a single-sensor digital control strategy for solving the problem of voltage balance at two ends of a flying capacitor of a three-level flying capacitor buck converter circuit. An improved digital control strategy is provided; carrying out stability analysis on the algorithm; for a digital control algorithm with subharmonic oscillation, a solution strategy is provided, a digital slope compensation technology is introduced, and the problem of subharmonic oscillation existing in the algorithm is eliminated; based on derivation of a digital valley voltage control technology, the digital peak voltage control technology is summarized and expanded.

Description

Technical Field

[0001] The invention belongs to the technical field of power electronics, and in particular relates to a single-sensor digital control method for a three-level flying capacitor buck converter. Background Art

[0002] Compared with the traditional two-level buck circuit, the three-level flying capacitor buck converter has the direct advantages of halving the stress on the switching device, halving the voltage swing of the filter inductor, doubling the output voltage frequency, and reducing the volume of the magnetic components. The flying capacitor voltage imbalance problem is a major challenge in the topology design of the three-level flying capacitor buck converter. Most of the existing research on this problem focuses on relying on multi-sensor control or using analog control methods. However, the large number of sensors is not conducive to the miniaturization design of the equipment. Moreover, analog control has poor stability and limited flexibility. Summary of the invention

[0003] In view of the problem that the existing flying capacitor voltage balancing requires too many sensors, the present invention provides a single-sensor digital control method for a three-level flying capacitor buck converter, which provides a more convenient solution to the flying capacitor voltage balancing problem in a three-level flying capacitor buck circuit.

[0004] The technical solution of the present invention is as follows:

[0005] A single sensor digital control method for a three-level flying capacitor buck converter comprises the following steps:

[0006] The working mechanism of the three-level flying capacitor buck converter circuit is analyzed, including the on-off logic of each switch device during normal operation of the circuit, four static working modes, and two dynamic working switching modes. The on-off logic of each switch device during normal operation includes: the first switch device Q1 and the fourth switch device Q4 are complementary turned on, the second switch device Q2 and the third switch device Q3 are complementary turned on, and the first switch device Q1 and the second switch device Q2 present a staggered conduction characteristic with a phase difference of 180°; the four static working modes include: based on the coordinate sequence (Q1, Q2) composed of the first switch device and the second switch device, they are described as state I, state II, state III, and state IV respectively, and the coordinate sequence (Q1, Q2) corresponds to (1, 0), (0, 0), (0, 1), and (1, 1) respectively; the two dynamic working switching modes include: the circuit working dynamic switching process is divided into two working modes according to the range of the voltage conversion ratio G, and the voltage conversion ratio G is the output voltage V o With input voltage V g The ratio is: mode 1, i.e., when G<0.5, the circuit static working modes are switched in the order of Ⅰ→Ⅱ→Ⅲ→Ⅱ; mode 2, i.e., when G>0.5, the circuit static working modes are switched in the order of Ⅳ→Ⅰ→Ⅳ→Ⅲ;

[0007] Taking one of the static operating mode points (1,0) as an example, the influence of flying capacitor voltage balance on the normal operation of the circuit is analyzed;

[0008] Aiming at the voltage balance problem of the flying capacitor in the three-level flying capacitor buck converter circuit, a single sensor digital control strategy is proposed, namely, a single sensor digital voltage dual-loop feedback V 2 Control technology, including digital valley voltage control and digital peak voltage control;

[0009] And overcome the delay of one output change cycle, and propose an improved digital control strategy; then conduct stability analysis on the algorithm;

[0010] For digital control algorithms with subharmonic oscillation, a solution strategy is proposed, which introduces digital slope compensation technology to eliminate the subharmonic oscillation problem in the algorithm;

[0011] Then, based on the derivation of digital valley voltage control technology, the summary is extended to digital peak voltage control technology;

[0012] Further analysis is conducted to determine whether the digital valley value and digital peak value have the self-balancing characteristics of the flying capacitor after the subharmonic oscillation is eliminated.

[0013] In a possible implementation manner, the three-level flying capacitor buck converter includes a DC input voltage source V g 、Flying capacitor C fly , bridge arm composed of switching devices, filter inductor L o , output capacitor C o As well as the DC output terminal, the DC input voltage source V g Connected in parallel with the bridge arm consisting of four switching devices (Q1, Q2, Q3, Q4) in series, the flying capacitor C fly Connected in parallel at both ends of the series branch composed of Q2 and Q3, the filter inductor L o and output capacitor C o The series branch composed of Q3 and Q4 is connected in parallel with the series branch composed of Q3 and Q4. The output capacitor C o Connect in parallel with the DC output terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 The basic circuit architecture of a three-level flying capacitor buck converter;

[0015] Figure 2 The four static operating modes of the three-level flying capacitor buck converter and the corresponding equivalent circuit diagram;

[0016] Figure 3Output waveforms of the three-level flying capacitor buck converter under two dynamic working switching modes;

[0017] Figure 4 The digital control system architecture of the three-level flying capacitor buck converter of the present invention;

[0018] Figure 5 It is the digital valley voltage control waveform diagram under the leading edge modulation mode when G<0.5;

[0019] Figure 6 It is the digital valley voltage control waveform diagram under the trailing edge modulation mode when G<0.5;

[0020] Figure 7 It is the digital valley voltage control waveform diagram under the triangle leading edge modulation mode when G<0.5;

[0021] Figure 8 It is the digital valley voltage control waveform diagram under the triangle trailing edge modulation mode when G<0.5;

[0022] Fig. 9 It is a timing diagram of the leading edge modulation digital circuit;

[0023] Fig.10 It is the improved digital valley voltage control waveform diagram under the leading edge modulation mode when G<0.5;

[0024] Fig.11 It is the waveform diagram of the improved digital valley voltage control under the trailing edge modulation mode when G<0.5;

[0025] Fig.12 This is the waveform diagram of the improved digital valley voltage control under the leading edge modulation mode after slope compensation when G<0.5;

[0026] Fig.13 This is the output waveform of the improved digital valley voltage control under the leading edge modulation mode after slope compensation when G<0.5 and there is a small disturbance in the flying capacitor voltage. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] A single sensor digital control method for a three-level flying capacitor buck converter according to an embodiment of the present invention comprises the following steps:

[0029] The working mechanism of the three-level flying capacitor buck converter circuit is analyzed, including the on-off logic of each switch device during normal operation of the circuit, four static working modes, and two dynamic working switching modes: the on-off logic of each switch device during normal operation is characterized in that the first switch device Q1 and the fourth switch device Q4 are complementary turned on, the second switch device Q2 and the third switch device Q3 are complementary turned on, and the first switch device Q1 and the second switch device Q2 present a staggered conduction characteristic with a phase difference of 180°; four static working modes are characterized in that they are described based on the coordinate sequence (Q1, Q2) formed by the first switch device and the second switch device, and are recorded as state I, state II, state III, and state IV respectively, and the coordinate sequence (Q1, Q2) corresponds to (1,0), (0,0), (0,1), and (1,1) respectively; two dynamic working switching modes are characterized in that the circuit working dynamic switching process is divided into two working modes according to the range of the voltage conversion ratio G, and the voltage conversion ratio G is the output voltage V o With input voltage V g The ratio is: mode 1, i.e., when G<0.5, the circuit static working modes are switched in the order of Ⅰ→Ⅱ→Ⅲ→Ⅱ; mode 2, i.e., when G>0.5, the circuit static working modes are switched in the order of Ⅳ→Ⅰ→Ⅳ→Ⅲ;

[0030] Taking one of the static operating mode points (1,0) as an example, the impact of the flying capacitor voltage balance on the normal operation of the circuit is analyzed. If the voltage across the flying capacitor cannot reach the steady-state value, the voltage imbalance problem of the series devices will be highlighted.

[0031] Aiming at the voltage balance problem of the flying capacitor in the three-level flying capacitor buck converter circuit, a single sensor digital control strategy is proposed, namely, a single sensor digital voltage dual-loop feedback V 2 Control technology, including digital valley voltage control technology and digital peak voltage control technology;

[0032] And overcome the delay of one output change cycle, and propose an improved digital control strategy; then conduct stability analysis on the algorithm;

[0033] For digital control algorithms with subharmonic oscillation, a solution strategy is proposed, which introduces digital slope compensation technology to eliminate the subharmonic oscillation problem in the algorithm;

[0034] Then, based on the derivation of digital valley voltage control technology, a table summary is given to extend it to digital peak voltage control technology;

[0035] Further analysis is conducted to determine whether the digital valley value and digital peak value have the self-balancing characteristics of the flying capacitor after the subharmonic oscillation is eliminated.

[0036] In a specific embodiment of the present invention, Figure 1As shown in the figure, the basic circuit structure of the three-level flying capacitor buck converter is proposed. The circuit mainly includes a DC input voltage source V g 、Flying capacitor C fly , bridge arm composed of switching devices, filter inductor L o , output capacitor C o And DC output terminal. DC input voltage source V g It is connected in parallel with the bridge arm consisting of four switching devices (Q1, Q2, Q3, Q4) connected in series. fly Connected in parallel at both ends of the series branch consisting of Q2 and Q3. Filter inductor L o and output capacitor C o The series branch formed by Q3 and Q4 is connected in parallel with the series branch formed by Q3 and Q4. o In the exemplary embodiment of the present invention, the DC output terminal is connected in parallel with a pure resistive load R as an example, and the voltage across the pure resistive load R is recorded as the output voltage v o To facilitate the subsequent description, Figure 1 The key measurement points are marked in the figure: The voltage across the series branch composed of switch devices Q3 and Q4 is defined as the switch node voltage V sw , and set the flying capacitor C fly and filter inductor L o The reference current direction is Figure 1 As shown, it helps explain the operating principle and dynamic behavior of the circuit.

[0037] In a specific application example, for the above-mentioned three-level flying capacitor buck converter circuit, the analysis of its working mechanism includes the conduction logic of each switch device when the circuit is operating normally; the four static working modes; and the two dynamic working switching modes. Among them, the analysis of the conduction logic of each switch device when the three-level flying capacitor buck converter circuit is operating normally specifically includes that the first switch device Q1 and the fourth switch device Q4 are complementary turned on, and the second switch device Q2 and the third switch device Q3 are complementary turned on, and the complementary conduction means that when one device in a pair is turned on, the other is in the off state, and vice versa; in addition, when the three-level flying capacitor buck converter circuit reaches a steady state, the first switch device Q1 and the second switch device Q2 present a staggered conduction characteristic with a phase difference of 180°.

[0038] Further, the analysis Figure 1The four static working modes of the three-level flying capacitor buck converter circuit shown in the figure specifically include: due to the complementary conduction characteristics of the switch devices in the three-level flying capacitor buck converter, the on and off of the four switch devices are controlled, and there are two degrees of freedom. For example, when the on and off states of the first switch device Q1 and the second switch device Q2 are determined, the on and off states of the third switch device Q3 and the fourth switch device Q4 are also determined. If a switch device is turned on, it is recorded as Q n =1 (where n=1,2,3,4); if a switch is turned off, it is recorded as Q n =0 (where n=1, 2, 3, 4). In the examples of the present invention, the first switching device Q1 and the second switching device Q2 are taken as examples for explanation, but the embodiments of the present invention are not limited to this. Q1 has two on-off states, namely Q1=1 or Q1=0, and Q2 has two on-off states, namely Q2=1 or Q2=0. If the conduction state of the first switching device Q1 is used as the horizontal coordinate, and the conduction state of the second switching device Q2 is used as the vertical coordinate to form a coordinate sequence (Q1, Q2), and the circuit is described based on this coordinate sequence, there are 4 static working modes, which are respectively recorded as state I, state II, state III, and state IV. The coordinate sequence (Q1, Q2) corresponds to (1, 0), (0, 0), (0, 1), and (1, 1), respectively. The equivalent circuit diagrams corresponding to the 4 static working modes are shown as follows. Figure 2 shown.

[0039] Further, the analysis Figure 1 The three-level flying capacitor buck converter circuit shown in the figure has two dynamic working switching modes, specifically including: defining the output voltage V o With input voltage V g The ratio is the voltage conversion ratio G, that is, Ideally, G is equal to the on-duty ratios D1 and D2 of Q1 and Q2. Due to the staggered conduction characteristics of the switching devices in the three-level flying capacitor buck converter, the circuit will be affected by the voltage conversion ratio G in a switching cycle (T s ) and presents two different dynamic working switching modes. Figure 3 As shown, the two dynamic working switching modes are: Mode 1: When G<0.5, Figure 2 The static working modes of the circuit are switched in the order of Ⅰ→Ⅱ→Ⅲ→Ⅱ; Mode 2: When G>0.5, Figure 2 The circuit static working modes are switched in the order of IV → I → IV → III. In both working modes, the output voltage will be s ) changes twice, and the output voltage change cycle is recorded as T sw .

[0040] In a specific application example, taking one of the static working mode points (1,0) as an example to analyze the influence of the flying capacitor voltage balance on the normal operation of the circuit, specifically includes taking the circuit working mode of (Q1,Q2)=(1,0) as an example to start a detailed description, but the embodiment of the present invention is not limited to this. Figure 1 The three-level flying capacitor step-down converter circuit, the input voltage V g With the first switch device Q1, the flying capacitor C fly The fourth switch device Q4 forms a first switch loop; at the same time, the flying capacitor C fly Together with the second switch device Q2 and the third switch device Q3, a second switch loop is formed. Figure 2 In the static working state at the coordinate point (1,0), that is, when the first switch device Q1 is turned on and the second switch device Q2 is turned off, the fourth switch device Q4 is turned off and the third switch device Q3 is turned on. The equivalent circuit is as follows: Figure 2 In the first switch loop, the voltage relationship is as follows, where the flying capacitor C fly The voltage across the two ends is v fly , the voltage across the fourth switch device Q4 is

[0041]

[0042] In the second switch loop, the voltage relationship exists in the following equation, and the voltage across the second switch device Q2 is

[0043]

[0044] From equations (1) and (2), we can see that if the flying capacitor C fly Voltage across the terminals v fly can reach a steady-state value, i.e. Then the voltage drops of the second switch device Q2 and the fourth switch device Q4 are equal and are only the input voltage V g On the contrary, if the flying capacitor C fly Voltage across the terminals v fly Unable to reach the steady-state value, that is, or situations will lead to and If the voltage imbalance problem of the series devices exists for a long time, it will not only aggravate the voltage instability of the flying capacitor, cause charging and discharging imbalance, but also eventually lead to the imbalance of the three-level flying capacitor buck converter system and lose its circuit function. Figure 1 The three-level flying capacitor step-down converter circuit shown in FIG. controls the flying capacitor C fly Voltage across the terminals v flyAchieving balance is particularly important for the normal operation of the circuit and for leveraging the key advantages of this topology.

[0045] In a specific application example, for Figure 1 the voltage balance problem across the flying capacitors of the three-level flying capacitor buck converter circuit shown, a digital control strategy based on a single sensor is proposed, namely, a digital voltage dual-loop feedback V 2 control technology, including digital valley voltage control technology and digital peak voltage control technology, specifically including the control system architecture, control principle, control process, and control algorithm.

[0046] Furthermore, the present invention proposes a digital control system architecture for a three-level flying capacitor buck converter, which is characterized in that as Figure 4 shown, it is composed of a three-level flying capacitor buck converter circuit and a digital controller. The digital controller integrates an analog-to-digital converter (ADC), a discrete proportional-integral-derivative (D-PID) compensator, and a digital pulse width modulator (DPWM). Specifically, the output voltage port of the three-level flying capacitor buck converter circuit and the drive signal port for controlling the states of four switching devices are respectively connected to the digital controller.

[0047] Furthermore, the control principle of the present invention is based on Figure 4 the analysis shown in the figure, which is an extension of the basic circuit of the three-level flying capacitor buck converter shown in Figure 1 . Specifically, when the equivalent series resistance R o on the output capacitor C e branch is significantly smaller than the load resistance R, i.e., R e <<R, then the high-frequency varying inductor current ripple Δi L on the inductor completely flows through the output capacitor C o , and discharges the output capacitor C e through the series resistance R o , thereby generating a voltage drop Δi e R L on R e that is the same as the slope of the inductor current. When the capacitance of C o is very large, its voltage V cap can be considered constant, then the output voltage is composed of a constant quantity and a ripple quantity, i.e., V o =V cap +Di L R e , and the ripple change trend of the output voltage V o will change with the change of the inductor current ripple Δi L . The digital controller senses the output voltage V oThe ripple changes, and responds accordingly in combination with the algorithm proposed in the present invention, generates corresponding drive signals, controls the on and off of the switching devices in the circuit, and thus achieves the target output.

[0048] Furthermore, the control process of the present invention specifically includes the following steps: an analog-to-digital conversion (ADC) module in a digital controller converts the output voltage V o Sampling is performed to obtain a digital sampling value v o The system has a preset reference voltage V stored in digital form. ref The reference voltage is equal to the sampled output voltage v o The error signal is then fed into the discrete proportional integral derivative (D-PID) control module to generate the corresponding voltage control signal v pi Then, the digital pulse width modulation (DPWM) module generates a voltage sample according to the current output voltage v o and the voltage control signal v generated by the D-PID module pi , combined with the specific algorithm proposed by the present invention, the switch duty cycle required by the circuit is calculated. Based on this calculation result, the DPWM module outputs high and low level drive signals at different time intervals to accurately control the on and off states of the four switch devices, thereby achieving effective regulation of the output voltage.

[0049] Furthermore, the present invention specifically describes the control algorithm, including the implementation of the digital valley voltage control algorithm under leading edge, trailing edge, triangular leading edge, and triangular trailing edge modulation, and the three-level flying capacitor buck converter operates in mode 1, i.e., G<0.5, as an example, but the embodiments of the present invention are not limited to this.

[0050] like Figure 5 The figure shows the control waveform of the three-level flying capacitor buck converter under the leading edge modulation mode with digital valley voltage control when the inductor current works in the continuous conduction mode (the inductor current never reaches 0 in one switching cycle) under the condition of G<0.5, where m1 and m2 are the output voltage ripple v detected by the digital controller. o According to the working principle of the three-level flying capacitor buck converter, within the range of G<0.5, m1 and m2 are:

[0051]

[0052] d n-1 d n are the corresponding switch device conduction duty ratios when two adjacent output voltages change, V ois the average value of the output voltage in steady state, the solid line is the steady state waveform, and the dotted line is the change trend of the output voltage after the disturbance occurs. At the beginning of each output voltage change cycle, the output voltage is sampled once to obtain the sampled value v o , define the values ​​of two consecutive samples as v o (n-1), v o (n). The digital controller generates a valley voltage control signal v through its built-in discrete proportional integral derivative (D-PID) controller. pi Since the natural frequency of the system is much lower than the switching frequency, it can be considered that the valley voltage control signal v pi No significant changes occurred, that is, v pi (n) = v pi (n-1). Voltage disturbance at the beginning of cycle n-1 Reflected in v o (n-1), if no other disturbance occurs in the current period, there is DPWM according to v o (n-1), v pi , duty cycle d n-1 , the circuit parameters pre-stored in the digital controller, and the duty cycle d calculated by different modulation methods n , so that in the nth cycle, the valley value of the output voltage ripple is detected and v pi Equal. According to Figure 5 , G<0.5, the digital valley voltage control principle under the leading edge modulation mode, at the beginning of the nth switching cycle, Q1 and Q2 are turned off, v o Decline, after time (0.5-d n-1 )T s After that, Q1 is turned on, v o Rising, conduction d n-1 T s After the time, Q1 turns off again and keeps the current switching cycle (T s ) ends, Q1 and Q2 are staggered The ripple voltage valley value of the nth switching cycle is v ovy (n), by Figure 5 have to:

[0053] v pi =v ovy (n) = v o (n-1)-m2d' n-1 T s +m1d n-1 T s -m2d' n T s (4)

[0054] Among them, d' n =0.5-d n ,d' n-1 =0.5-d n-1 From equation (4), it can be further obtained that the duty cycle algorithm of the digital valley control three-level flying capacitor buck converter under the leading edge modulation mode when the voltage conversion ratio G<0.5 is:

[0055]

[0056] Similarly, refer to Figure 6 , gives the digital valley voltage control waveform under the trailing edge modulation mode when G<0.5. In the trailing edge modulation, the sampling point of each output change cycle appears at the valley position of the ripple. Figure 6 We can get:

[0057] v pi =v ovy (n) = v o (n-1)+m1d n-1 T s -m2d' n-1 T s +m1d n T s -m2d' n T s (6)

[0058] It can be further obtained from formula (6) that the duty cycle algorithm of the digital valley control three-level flying capacitor buck converter under the trailing edge modulation mode when the voltage conversion ratio G<0.5 is:

[0059]

[0060] Similarly, refer to Figure 7 , given the triangle leading edge modulation digital valley voltage control when G<0.5, at the beginning of the nth cycle, Q1 and Q2 are turned off, v o Decline, elapsed time Q1 is turned on, v o Rise, through d n-1 T s time, Q1 turns off again until the end of the current cycle, and Q2 is out of phase with Q1 In triangular leading edge modulation, the sampling point of each switching cycle appears in the middle of the output voltage ripple falling stage; the switch tubes Q2 and Q1 are turned on in each output voltage change cycle (T sw ) has the same off time at the beginning and end of the segment. Figure 7 We can get:

[0061]

[0062] From equation (8), we can further obtain the duty cycle algorithm of the three-level flying capacitor buck converter under the digital valley control triangular leading edge modulation mode when G<0.5:

[0063]

[0064] Similarly, refer to Figure 8 , given the triangle trailing edge modulation digital valley voltage control when G<0.5, Figure 8 We can get:

[0065]

[0066] It can be further obtained from formula (10) that the duty cycle algorithm of the digital valley control three-level flying capacitor buck converter under the triangular trailing edge modulation mode when G<0.5 is:

[0067]

[0068] In a specific application example, the above are all derived within the range of G<0.5. The present invention extends the applicable scope of digital control to the range of G>0.5, characterized in that, from the above analysis, it can be seen that formulas (5), (7), (9), and (11) respectively give the duty cycle algorithms of the digital valley control three-level flying capacitor buck converter under leading edge, trailing edge, symmetrical triangular leading edge, and symmetrical triangular trailing edge modulation when G<0.5. When G>0.5, the above algorithm is still applicable, the difference is that the rising and falling slopes of the output voltage ripple are different in the two working modes. Formula (12) gives the expressions of m1 and m2 when G>0.5:

[0069]

[0070] Observe the duty cycles of equations (5), (7), (9), and (11). The duty cycles obtained by the above algorithms are all calculated based on the quantities in the previous output change cycle. There is a delay of one output change cycle. If the delay of one output change cycle can be overcome, the duty cycle required for the current switch can be calculated based on the state quantity of the current output change cycle.

[0071] In a specific application example, the present invention overcomes the delay of an output change cycle and proposes an improved digital control strategy, which specifically includes that for a digital control circuit, there are usually the following time intervals: sampling time and circuit delay interval t s , the algorithm calculates the time interval t c (including D-PID and DPWM time), duty cycle update time t r For the digital valley voltage controlled three-level flying capacitor buck converter of the present invention, The key to overcoming the switching cycle delay is to maximize t r , so that there is sufficient time to update the duty cycle, and t s It is usually determined by the circuit hardware structure and remains basically unchanged, so try to minimize t c This makes it more feasible to overcome the switching cycle delay. Taking the leading edge modulation digital circuit timing diagram as an example, Fig. 9 , if the timing t can be met r >dT s , we can realize the improved leading edge modulation digital valley control algorithm. Fig.10 As shown in the figure, the control waveform of the improved digital valley control three-level flying capacitor buck converter under the leading edge modulation mode is given. Fig.10 , we can get:

[0072] v pi =v ovy (n-1) = v o (n-1)-m2(0.5-d n-1 )T s (13)

[0073] It can be further obtained from formula (13) that the duty cycle algorithm of the improved digital valley control three-level flying capacitor buck converter under the leading edge modulation mode is:

[0074]

[0075] Depend on Fig.10 It can be seen that after the disturbance occurs at the beginning of the n-1th cycle, the valley value of the output voltage ripple can reach the control target v in the n-1th cycle. pi .

[0076] Similarly, equations (15), (16), and (17) respectively give the duty cycle calculation algorithms of the improved digital valley voltage controlled three-level flying capacitor buck converter under trailing edge modulation, triangular leading edge modulation, and triangular trailing edge modulation:

[0077]

[0078] In a specific application example, the present invention performs stability analysis on the algorithm, specifically including that the improved digital control algorithm overcomes the delay of one output change cycle in the traditional digital control algorithm, and the two have the same stability. Taking the improved digital control algorithm as an example for stability analysis, the ratio Conduct research. Fig.10 , the improved digital valley voltage control waveform under the leading edge modulation mode, from the geometric relationship between the triangle and parallelogram in the figure, we can get:

[0079]

[0080] The stable region needs to satisfy |K| < 1. Substitute m1 and m2 when G < 0.5 and G > 0.5 respectively to obtain the stable region of the improved digital valley voltage control three-level flying capacitor buck converter under the leading-edge modulation method:

[0081]

[0082] Similarly, from the control waveforms of the improved digital valley voltage control three-level flying capacitor buck converter under the trailing-edge modulation method shown in Fig.11 it can be seen that the output voltage disturbance that appears at the beginning of the previous output voltage change cycle disappears at the end of the next output voltage change cycle. Therefore, the trailing-edge modulation eliminates the possible subharmonic oscillation problem in the improved digital valley voltage control three-level flying capacitor buck converter from the modulation principle. Therefore, the stable region of the improved digital valley voltage control three-level flying capacitor buck converter under the trailing-edge modulation method is 0 < G < 1; in addition, similar to the principle of deriving the stable region of the leading-edge modulation, it can be obtained that the improved digital valley voltage control three-level flying capacitor buck converter under the triangular leading-edge modulation method will generate subharmonic oscillations in the full range of the voltage conversion ratio, that is, 0 < G < 1; the stable range of the improved digital valley voltage control three-level flying capacitor buck converter under the triangular trailing-edge modulation method is the same as that of the trailing-edge modulation, which is 0 < G < 1.

[0083] In a specific application example, for the digital control algorithm with subharmonic oscillations, a solution strategy is proposed, and the digital ramp compensation technology is introduced to eliminate the subharmonic oscillation problem existing in the algorithm. It is characterized in that the control waveforms of the leading-edge modulation improved digital valley control three-level flying capacitor buck converter using the digital ramp compensation technology are as shown in Fig.12 where k comp is the slope of the digital ramp compensation. It can be obtained that:

[0084]

[0085] Substitute m1 and m2 when G < 0.5 and G > 1 respectively to obtain:

[0086]

[0087] Therefore, the minimum ramp slope required for the algorithm of the leading-edge modulation improved digital valley control three-level flying capacitor buck converter using the digital ramp compensation technology is Similarly, the minimum ramp slope required for the algorithm of the triangular leading-edge modulation improved digital valley control three-level flying capacitor buck converter using the digital ramp compensation technology is

[0088] Furthermore, for the single-sensor digital voltage dual-loop feedback control technology proposed in the present invention, the above are all derivations based on the digital valley voltage control technology, and the digital peak voltage control technology also has a similar derivation process and conclusion. Specifically, Table 1 summarizes the duty cycle calculation method based on the single-sensor digital voltage dual-loop feedback control technology under different modulation modes, including leading edge modulation, trailing edge modulation, triangular leading edge modulation and triangular trailing edge modulation, which are applicable to digital valley voltage control technology and digital peak voltage control technology. In addition, the present invention also proposes an improved digital valley voltage control technology and an improved digital peak voltage control technology, and lists the duty cycle algorithm expressions corresponding to these two improved technologies in Table 1.

[0089]

[0090] At the same time, since the improved digital control algorithm has the same stability as the traditional digital control algorithm, Table 2 lists in detail the stable areas of the single-sensor digital voltage dual-loop feedback control technology under different modulation modes, which is applicable to the (improved) digital valley voltage control technology and the (improved) digital peak voltage control technology. Among them, the digital valley voltage control technology is stable in the full range under the trailing edge modulation and triangular trailing edge modulation modes, unstable in the full range under the triangular leading edge modulation mode, and stable in part of the range under the leading edge modulation mode; the digital peak voltage control technology has a similar conclusion. In addition, in the case of generating subharmonic oscillations, in the original control voltage signal (v pi ) is superimposed on the basis of slope compensation. The minimum slope of the compensable slope varies according to the single-edge modulation (leading edge modulation, trailing edge modulation) and double-edge modulation (triangular leading edge modulation, triangular trailing edge modulation). The compensation of positive slope or negative slope also varies depending on valley control or peak control.

[0091]

[0092] Furthermore, after using digital slope compensation technology to eliminate the subharmonic oscillation of the output voltage, the impact on the voltage stability of the flying capacitor is analyzed, including: Fig.13 , taking the three-level flying capacitor buck converter controlled by digital valley value under leading edge modulation mode and operated in the mode of G<0.5 as an example, assuming that there is a disturbance V fly , that is, the flying capacitor voltage Due to the disturbance V fly The existence of will definitely affect the unbalanced charging and discharging of the flying capacitor, and at the same time lead to different duty cycles of the two switching devices, which are set as D1 and D2 respectively. According to the geometric relationship of the waveform, we can get:

[0093]

[0094] The average current flowing through the flying capacitor is:

[0095]

[0096] Among them, A pos and A neg are the positive and negative areas of the flying capacitor current curve, respectively. By solving the geometric relationship and substituting equations (24) and (25) into equation (26), we can obtain the average current formula of the flying capacitor in the range of G < 0.5:

[0097]

[0098] From formula (27), we can see that in the range of G < 0.5, when the compensation slope satisfies This will make the average current I fly The positive and negative voltage disturbance V fly The positive and negative signs are opposite. Therefore, it can be concluded that the digital valley control method of the three-level flying capacitor buck converter under the leading edge modulation mode will inherently stabilize the flying capacitor voltage and eventually reach a balanced state once the subharmonic oscillation of the converter output voltage is suppressed. Similarly, the digital valley control method under the triangular leading edge modulation mode can also reach a similar conclusion. Therefore, the digital valley control has the characteristic of self-balancing the flying capacitor voltage after the subharmonic oscillation is eliminated.

[0099] Differently, digital peak control does not have the characteristic of self-balancing the flying capacitor voltage after the subharmonic oscillation is eliminated. The flying capacitor voltage will only be stable when the peak-to-peak ripple is large enough.

[0100] It should be understood that the exemplary embodiments described herein are illustrative rather than restrictive. Although one or more embodiments of the present invention are described in conjunction with the accompanying drawings, it should be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present invention as defined by the appended claims.

Claims

1. A single sensor digital control method for a three-level flying capacitor buck converter, characterized in that: The following steps are involved: The working mechanism of the three-level flying capacitor buck converter circuit is analyzed, including the on-off logic of each switch device during normal operation of the circuit, four static working modes, and two dynamic working switching modes. The on-off logic of each switch device during normal operation includes: the first switch device Q1 and the fourth switch device Q4 are complementary turned on, the second switch device Q2 and the third switch device Q3 are complementary turned on, and the first switch device Q1 and the second switch device Q2 present a staggered conduction characteristic with a phase difference of 180°; the four static working modes include: based on the coordinate sequence (Q1, Q2) composed of the first switch device and the second switch device, they are described as state I, state II, state III, and state IV respectively, and the coordinate sequence (Q1, Q2) corresponds to (1, 0), (0, 0), (0, 1), and (1, 1) respectively; the two dynamic working switching modes include: the circuit working dynamic switching process is divided into two working modes according to the range of the voltage conversion ratio G, and the voltage conversion ratio G is the output voltage V o With input voltage V g The ratio is: mode 1, i.e., when G<0.5, the circuit static working modes are switched in the order of Ⅰ→Ⅱ→Ⅲ→Ⅱ; mode 2, i.e., when G>0.5, the circuit static working modes are switched in the order of Ⅳ→Ⅰ→Ⅳ→Ⅲ; Taking one of the static operating mode points (1,0) as an example, the influence of flying capacitor voltage balance on the normal operation of the circuit is analyzed; Aiming at the voltage balance problem of the flying capacitor in the three-level flying capacitor buck converter circuit, a single sensor digital control strategy is proposed, namely, a single sensor digital voltage dual-loop feedback V 2 Control technology, including digital valley voltage control and digital peak voltage control; And overcome the delay of one output change cycle, and propose an improved digital control strategy; then conduct stability analysis on the algorithm; For digital control algorithms with subharmonic oscillation, a solution strategy is proposed, which introduces digital slope compensation technology to eliminate the subharmonic oscillation problem in the algorithm; Then, based on the derivation of digital valley voltage control technology, the summary is extended to digital peak voltage control technology; Further analysis is conducted to determine whether the digital valley value and digital peak value have the self-balancing characteristics of the flying capacitor after the subharmonic oscillation is eliminated.

2. The single sensor digital control method for a three-level flying capacitor buck converter according to claim 1, characterized in that: The three-level flying capacitor buck converter comprises a DC input voltage source V g 、Flying capacitor C fly , bridge arm composed of switching devices, filter inductor L o , output capacitor C o As well as the DC output terminal, the DC input voltage source V g Connected in parallel with the bridge arm consisting of four switching devices (Q1, Q2, Q3, Q4) in series, the flying capacitor C fly Connected in parallel at both ends of the series branch composed of Q2 and Q3, the filter inductor L o and output capacitor C o The series branch composed of Q3 and Q4 is connected in parallel with the series branch composed of Q3 and Q4. The output capacitor C o Connect in parallel with the DC output terminal.

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