Voltage regulator circuit, corresponding driver circuit, apparatus and method of operation

Abstract

The invention relates to a voltage regulator circuit, a corresponding driver circuit, a device and an operation method. A voltage regulator circuit is provided that includes an input node for receiving an input supply voltage, an output node for generating a regulated output voltage, and a switchable pass element disposed between the input node and the output node. A comparator circuit compares the regulated output voltage to a dynamic threshold to generate a control signal to control the switchable pass element. The asserted control signal causes the switchable through element to be turned on, and vice versa. The threshold selection and shaping circuit shapes the regulated output voltage or the dynamic threshold such that (i) in response to assertion of the control signal, the difference between the dynamic threshold and the regulated output voltage suddenly increases and then gradually decreases toward a target static value, and (ii) in response to de-assertion of the control signal, the difference between the dynamic threshold and the regulated output voltage suddenly decreases and then gradually decreases toward a target static value. The difference suddenly increases and then gradually decreases toward a target static value.

Description

Technical Field

[0001] The present description relates to switching (ie, on / off) voltage regulators and control circuits thereof.

[0002] For example, a switching voltage regulator can be implemented in a driver circuit of a half-bridge switching circuit with a high-side bootstrap architecture. High voltage (HV) half-bridge switching circuits can be used in various applications, such as motor drive (motor control) devices, electronic ballasts for fluorescent lamps, power supply devices, power converters, etc. Background Art

[0003] In order to improve the overall efficiency of the switching circuit, gallium nitride (GaN) power transistors are increasingly used in half-bridge switching circuits to replace traditional power transistors (such as traditional silicon MOS field effect transistors or insulated gate bipolar transistors, IGBTs). For example, GaN power transistors can provide lower gate capacitance and higher switching speed.

[0004] A driver circuit for such a GaN half-bridge circuit is known, for example, from document US11476845B2, which is hereby incorporated by reference in its entirety. In brief, the document discloses a half-bridge driver including a high-side bootstrap path, as annexed hereto. Figure 1 As illustrated in FIG. The half-bridge driver HBD has a pair of input terminals (eg, a positive power supply terminal 100a and a reference power supply terminal 100b or ground) configured to receive a power supply voltage from an external power supply PS between them. In the present application, the power supply voltage is a sensor power supply voltage V CC , but more generally the supply voltage may be referred to as V supply The half-bridge driver HBD is also configured to receive a low voltage control signal IN for controlling the high-side and low-side switches HS, LS of the half-bridge. HS , IN LS The half-bridge driver HBD includes a high-side gate driver circuit 12a and a low-side gate driver circuit 12b. The low-side gate driver circuit 12b receives a low-side low voltage control signal IN LS , and generates a corresponding low-side gate control signal LVG for the low-side switch LS of the half-bridge circuit between a pair of output terminals 120b, 102b. The output terminal 102b (internally coupled to the driver HBD) is coupled to the ground terminal 100b. Alternatively, the integrated circuit HBD may have a single ground pin. The high-side gate driver circuit 12a receives the high-side low voltage control signal IN via the level shifter circuit 14. HS , and a corresponding high-side (shifted) gate control signal HVG for the high-side switch HS of the half-bridge circuit is generated between a pair of output terminals 120a, 102a. The output terminal 102a is a switching node of the half-bridge circuit, where an output voltage VOUT The low-side gate driver circuit 12b is powered by the sensor supply voltage V CC biased, and the high-side gate driver circuit 12a is biased by the bootstrap voltage V in the floating section FS of the half-bridge driver circuit BO Specifically, the bias voltage V BO is provided between the switching node 102a of the half-bridge circuit (acting as a floating ground) and a floating power supply node 104 (ie, a floating positive power supply voltage above the floating ground). The floating power supply node 104 is connected to the floating power supply node 104 via a bootstrap capacitor C B A floating power supply node 104 is connected to the switching node 102a of the half-bridge circuit (e.g., external to the integrated circuit of the half-bridge driver circuit HBD). In addition, the floating power supply node 104 is coupled to the positive terminal 100a (internally coupled to the integrated circuit of the half-bridge driver circuit HBD) via a bootstrap path including two transistors Q3 and Q1′. Specifically, the first transistor Q3 (e.g., an n-channel MOS transistor) operating as an active diode has its conductive channel connected between the positive terminal 100a and the intermediate power supply node 106 (or "decoupling node"), while the second transistor Q1′ (e.g., a p-channel MOS transistor) operating as a current limiter has its conductive channel connected between the decoupling node 106 and the floating power supply node 104. The transistors Q3 and Q1′ are arranged to have "back-to-back" body diodes (D3 and D1′, respectively) in the bootstrap path from the node 100a to the node 104. The active diode Q3 and the current limiter Q1′ are controlled by control circuits 60 and 62, respectively. The control circuit 60 of the active diode Q3 is implemented in the low voltage part of the half-bridge driver HBD, and the control circuit 62 of the current limiter Q1′ is implemented in the floating part FS of the half-bridge driver HBD. The high-side gate driver circuit 12a is provided between nodes 104 and 102a (voltage V BO ), and the level shifter circuit 14 has a first part (sensor power supply voltage V CC ) and the second portion (intermediate supply voltage V S ).

[0005] exist Figure 1 In the structure of , the switching operation of the half-bridge circuit results in a bootstrap recharging phase (during which the high-side switch HS is turned off and the low-side switch LS is turned on) and a bootstrap supply phase (during which the high-side switch HS is turned on and the low-side switch LS is turned off). During the bootstrap recharging phase, the switch node 102a of the half-bridge is coupled to ground, and the bootstrap capacitor CB is charged by a (controlled) current flowing from the positive power supply terminal 100a to the floating power supply node 104 through the active diode Q3 and the current limiter Q1′. Specifically, during the bootstrap recharging phase, the active diode Q3 realizes the voltage V SThe on / off regulation is performed to reduce (eg, minimize) the voltage drop between the terminal 100a and the node 106 (ie, to maintain the voltage V S Approach voltage V CC ), and the current limiter Q1′ realizes the voltage V BO The on / off regulation is used to adjust the voltage V BO The voltage is kept within the desired voltage range (for example, set to 5.4V), thereby operating as a non-dissipative clamp circuit. In the bootstrap supply phase, the switch node 102a of the half-bridge is coupled to the positive bus voltage V BUS positive bus pin 108 and stored in the bootstrap capacitor C B The charge in the bootstrap capacitor is supplied to the high-side gate driver circuit 12a. In the subsequent switching cycle, during another bootstrap recharging phase, the charge in the bootstrap capacitor is restored.

[0006] In the known solutions discussed above, the decoupling node 106 is capacitively coupled to the control (eg, gate) terminal of transistor Q3 (eg, via gate-drain parasitic capacitance C gd_Q3 ), the control (eg, gate) terminal of transistor Q1′ (eg, via gate-source parasitic capacitance C gd_Q1′ ), and ground (e.g., via other parasitic capacitance C VS0 During the bootstrap recharge phase, the bootstrap path operates to maintain voltage regulation at the decoupling node 106 and at the floating supply node 104. B (ie, between the floating power supply node 104 and the switching node 102a, V BO =V BOOT -V OUT ) of the bootstrap voltage V BO When the voltage at the decoupling node 106 is increased to the required voltage (eg, 5.4V), the voltage at the decoupling node 106 is regulated to the proximity sensor supply voltage V CC During the bootstrap recharge phase, the regulation of the bootstrap voltage is essentially unaffected by clock feedthrough (or gate feedthrough, i.e., the result of the coupling between the control signal on the analog switch and the analog signal through the switch), as long as the bootstrap capacitor C B The parasitic capacitance C is usually large compared to the parasitic capacitance at the decoupling node 106. However, in each regulation, the parasitic capacitance C gd_Q3 and C gd_Q1′ is not negligible and is related to the parasitic capacitance C VS0 For example, the capacitance is C gd_Q3 / (C VS0 +C gd_Q3 ) may be approximately 0.5. Therefore, the voltage V at the intermediate power supply node 106 S The regulation may be prone to clock feedthrough.

[0007] The above application represents a switching regulator that may be affected by clock feedthrough (ie, providing a voltage V at node 106 via switch Q3). S Other applications may be affected by similar problems. Therefore, there is a need in the art to provide an improved control circuit for a switching voltage regulator that helps to combat clock feedthrough. Such a control circuit can be applied, for example, to control an active diode switch in a half-bridge driver. Summary of the invention

[0008] It is an object of one or more embodiments to help provide such an improved switching voltage regulator that can be used to implement an active diode switch of a gate drive circuit.

[0009] According to one or more embodiments, this object is achieved by a voltage regulator circuit having the features set out in the appended claims.

[0010] One or more embodiments may relate to a corresponding half-bridge driver circuit.

[0011] One or more embodiments may be directed to corresponding electronic devices (eg, an active clamp flyback converter or a resonant LLC converter).

[0012] One or more embodiments may be directed to corresponding methods of operation.

[0013] The claims are an integral part of the technical teaching provided here regarding the embodiments.

[0014] According to one aspect of the present invention, a voltage regulator circuit includes: an input node configured to receive an input supply voltage; an output node configured to generate a regulated output voltage; a switchable transfer element having a selective conductive channel arranged between the input node and the output node; and a comparator circuit configured to compare the regulated output voltage with a dynamic threshold to generate a control signal to control the switching of the switchable transfer element. The asserted control signal causes the switchable transfer element to be turned on, and the de-asserted control signal causes the switchable transfer element to be turned off. The voltage regulator circuit further includes a threshold selection and shaping circuit, which is configured to shape the regulated output voltage and / or the dynamic threshold so that:

[0015] In response to assertion of the control signal, the difference between the dynamic threshold and the regulated output voltage increases abruptly and then decreases gradually toward a target static value; and

[0016] In response to de-assertion of the control signal, the difference between the regulated output voltage and the dynamic threshold value increases abruptly and then gradually decreases toward the target static value.

[0017] Thus, one or more embodiments may provide a switching voltage regulator that applies a “dynamic hysteresis” method to the control of a transfer element such that the hysteresis width is expanded as needed to include noise peaks of the regulated signal, and “excessive” negative feedback that may result in uncontrolled on / off oscillation conditions may be suppressed.

[0018] According to another aspect of the present specification, the half-bridge driver circuit includes: a positive power supply pin and a ground pin, configured to receive a power supply voltage between them; a first control pin, configured to receive a low-voltage high-side control signal for controlling a high-side switch of the half-bridge circuit; and a second control pin, configured to receive a low-voltage low-side control signal for controlling a low-side switch of the half-bridge circuit. The half-bridge driver circuit also includes a high-side gate driver circuit and a low-side gate driver circuit, the high-side gate driver circuit is configured to receive the low-voltage high-side control signal via a level shifter circuit and generate a corresponding high-side gate control signal (HVG), and the low-side gate driver circuit is configured to receive the low-voltage low-side control signal and generate a corresponding low-side gate control signal. The high-side gate driver circuit is biased between a floating power supply pin and a switch pin of the half-bridge driver circuit, and the floating power supply pin is coupled to the positive power supply pin via a bootstrap path. The bootstrap path includes a voltage regulator circuit according to one aspect of the present specification, the voltage regulator circuit having an input node connected to a positive power supply pin and an output node connected to a decoupling node inside a half-bridge driver circuit, and a current limiter circuit arranged between the decoupling node and the floating power supply pin.

[0019] According to another aspect of the present specification, an electronic device includes a half-bridge driver circuit according to one aspect of the present specification, a high-side switch coupled between a positive bus pin and a switch pin of the half-bridge driver circuit, a low-side switch coupled between the switch pin and a ground pin of the half-bridge driver circuit, and a bootstrap capacitor coupled between a floating power supply pin and the switch pin of the half-bridge driver circuit.

[0020] According to another aspect of this specification, a method of operating a voltage regulator circuit according to an aspect of this specification includes:

[0021] receiving an input supply voltage at the input node;

[0022] generating a regulated output voltage at the output node;

[0023] comparing the regulated output voltage to a dynamic threshold at the comparator circuit to generate a control signal to control switching of the switchable pass element, switching the switchable pass element on in response to the control signal being asserted, and switching the switchable pass element off in response to the control signal being de-asserted; and

[0024] The regulated output voltage and / or the dynamic threshold are shaped at the threshold selection and shaping circuit, causing the difference between the dynamic threshold and the regulated output voltage to suddenly increase and then gradually decrease toward a target static value in response to assertion of the control signal, and causing the difference between the regulated output voltage and the dynamic threshold to suddenly increase and then gradually decrease toward a target static value in response to de-assertion of the control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] One or more embodiments will now be described by way of example with reference to the accompanying drawings, in which:

[0026] Figure 1 is an exemplary circuit block diagram of a half-bridge switching circuit and an associated half-bridge driver including a high-side bootstrap architecture as discussed above;

[0027] Figure 2 is an exemplary circuit block diagram of a bootstrap path of a half-bridge driver, showing a possible implementation of a control circuit for an active diode of the bootstrap path;

[0028] Figure 3 Yes Figure 2 A diagram of possible waveforms of signals in a circuit of , showing an undesirable oscillatory condition due to clock feedthrough;

[0029] Figure 4 Yes Figure 2 A diagram of possible waveforms of signals in a circuit of wherein voltage regulation is subject to freezing of counter clock feedthrough;

[0030] Figure 5 Yes Figure 2 A diagram of possible waveforms of signals in a circuit of where the hysteresis width is magnified to count clock feedthrough;

[0031] Figure 6 Yes Figure 2 A diagram of possible waveforms of signals in a circuit of , showing an undesirable oscillatory condition due to clock feedthrough;

[0032] Figure 7 is a diagram of possible waveforms of signals included in one or more embodiments of the present specification, illustrating the use of dynamic hysteresis for regulating outputs to suppress oscillatory conditions due to clock feedthrough;

[0033] Figure 8 According to one or more embodiments of the present specification, according to Figure 7 A schematic (e.g., conceptual) circuit diagram of a control circuit configured to control a switching element of a switching regulator having dynamic hysteresis and operating in accordance with a waveform of the present invention;

[0034] Fig. 9 According to one or more embodiments of this specification, based on Figure 7 and 8 An exemplary circuit diagram of a control circuit configured to control a switching element of a switching regulator having dynamic hysteresis;

[0035] Fig.10 Yes Fig. 9 A diagram of possible waveforms of signals in a circuit, illustrating the use of dynamic hysteresis;

[0036] Fig.11 is an exemplary circuit diagram of a control circuit configured to control an active diode driver with a bootstrap path having dynamic hysteresis according to one or more embodiments of the present specification;

[0037] Fig.12 yes Fig.11 An exemplary circuit diagram of the small signal operation of the circuit;

[0038] Fig.13 and Fig.14 It is shown Fig.12 A diagram of possible time modulations of the resistance of certain resistors in a circuit;

[0039] Fig.15 Yes Figure 2 A diagram of possible waveforms of signals in a circuit of FIG. 1 in which an unwanted oscillatory state is suppressed by implementing dynamic hysteresis control according to one or more embodiments of the present description; and

[0040] Fig.16 is a circuit block diagram of an exemplary switching voltage regulator with hysteresis, to which dynamic hysteresis control according to one or more embodiments of the present specification is applicable. DETAILED DESCRIPTION

[0041] In the following description, one or more specific details are shown for the purpose of providing a deeper understanding of the examples of the embodiments of the present description. The embodiments may be obtained without one or more specific details, or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail so as not to obscure certain aspects of the embodiments.

[0042] References to "one embodiment" or "an embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or characteristic described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in an embodiment" that may appear in one or more points of this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular configurations, structures, or characteristics may be combined in any appropriate manner.

[0043] The headings / reference signs used herein are provided for convenience only and do not limit the scope of protection or the scope of the embodiments.

[0044] In the drawings attached hereto, unless the context otherwise indicates, the same parts or elements are denoted by the same reference numerals / numbers, and the corresponding description will not be repeated for the sake of brevity.

[0045] By way of introduction to the detailed description of the exemplary embodiments, reference may be made to the following discussion of Figures 2 to 5 .

[0046] Figure 2 As reference Figure 1 The exemplary circuit block diagram of the bootstrap path in the discussed half-bridge driver additionally shows a possible implementation of a control circuit 60 for the active diode Q3 (circuit 60 is also referred to as “active diode driver” in this application). Figure 2 The active diode driver 60 is implemented for regulating the intermediate power supply voltage V S Specifically, the driver 60 includes a voltage sensor 20, which includes a switchable voltage reference V T The comparator 22 has a voltage V coupled to the node 106 to sense the voltage V S , and may alternatively be coupled to a first (eg, higher) static threshold voltage V via switch 24. T，H_S or coupled to a second (eg, lower) static threshold voltage V T，L_S In this application, the threshold voltage V T，H_S and V T，L_S The sensor supply voltage V CC for reference, but more generally, the threshold voltage can be referenced to the voltage V ref Therefore, by alternately selecting the reference voltage V of the comparator 22 T (V T，H_S or V T，L_S ), using static hysteresis to achieve an intermediate supply voltage V for regulation purposes S The comparator 22 generates an activation signal ACT_D_ON for the active diode Q3. T，H_S and V T，L_S and the selection (e.g., size) of their gaps is a requirement for noise filtering (which is preferably V T，H_S and V T，L_S The larger gap between) and the adjustment accuracy (it is preferred that V T，H_S and V T，L_SThe active diode driver 60 further includes a NAND gate 26 configured to apply NAND logic processing to the signal ACT_D_ON and the low-side gate control signal LVG. The output signal generated by the NAND gate 26 is passed to the inverter 28, and the output terminal of the inverter 28 is coupled to the pump capacitor C OV The first terminal of the pump capacitor C OV The second terminal of is coupled to the control (eg, gate) terminal of the active diode transistor Q3. In addition, the diode 29 has a configuration to receive the sensor supply voltage V CC The anode terminal of the active diode transistor Q3 and the cathode terminal of the active diode transistor Q3 are coupled to the control (eg, gate) terminal of the active diode transistor Q3. Therefore, the control signal G_ACT_D for the active diode transistor Q3 is generated at the control (eg, gate) terminal of the transistor Q3.

[0047] Figure 3 Yes Figure 2 A diagram of possible waveforms of the signals in the circuit, specifically: sensor supply voltage V CC (dashed line), static threshold voltage V T，H_S and V T，L_S (dashed line), the intermediate power supply voltage V at node 106 S (solid line), the floating supply voltage V at node 104 BOOT (solid line), the output voltage V at the switch node 102a OUT (solid line), low-side gate control signal LVG (solid line) and active diode control signal G_ACT_D (solid line). Figure 3 The waveform shows the use of voltage sensor 20 with static hysteresis to regulate the voltage V at node 106 S In some cases this may result in uncontrolled on / off oscillations. In fact, due to the capacitive coupling C gd_Q3 Each on / off commutation of the active diode Q3 may occur at the intermediate supply voltage V S The overshoot / undershoot that can exceed the hysteresis window (i.e., the voltage V S Increase to V T，H_S Above or the voltage V S Reduce to V T，L_S ), thereby triggering an uncontrolled on / off oscillation state of transistor Q3. The oscillation frequency may depend on the regulation response delay and may be relatively high (e.g., about 50 MHz). Specifically, when the desired bootstrap voltage V is reached, BO (e.g., 5.4V) (e.g., see Figure 3 At time t1), the current limiter Q1′ is disconnected and the node 106 is connected from the bootstrap capacitor C BThe coupling coefficient between node 106 and the gate terminal of transistor Q3 is large enough to trigger clock feedthrough and eventually lead to an undesirable on / off oscillation state. The on / off oscillation mode may last for most of the operating cycle of the device, resulting in high current consumption (e.g., about 10 mA) from the external power supply and / or high frequency noise on the power supply. The oscillation state can be stopped by the occurrence of at least one of the following events: (i) the current limiter Q1′ is turned on, with a voltage V BOOT Node 106 is connected to node 104, thereby connecting the bootstrap capacitor C B or (ii) signal LVG (at node 120b) switches to a de-asserted state (eg, logic low), thereby forcing active diode Q3 (whose activation signal ACT_D_ON is gated by signal LVG at gate 26) to turn off.

[0048] Certain methods can be used to counteract the clock feedthrough phenomenon. For example, in a first method, a so-called charge extractor circuit is used to compensate the gate coupled noise by an opposite noise. The charge extractor is appropriately coupled with respect to the gate signal (in this case, complementary to the signal G_ACT_D). However, due to the sensitive nature of node 106, this solution may be critical and may imply a large area occupation.

[0049] A second approach to the clock feedthrough problem is to freeze the regulation state for a certain time interval (i.e., to prevent signal G_ACT_D from switching too quickly) after the gate control signal (in this example, signal G_ACT_D) has switched from one value to another, such as Figure 4 As shown in the figure, Figure 4 In this case, the signal V CC , V T，H_S , V T，L_S , V S , V BOOT , V OUT , waveforms of LVG and G_ACT_D. After the first commutation of the signal G_ACT_D, the freezing phase introduced in the regulation holds the value of the signal G_ACT_D for an appropriate time, preventing the start of the on / off oscillation state. However, this approach may trigger the bootstrap capacitor C B The “backwash 1” current toward the positive power supply terminal 100a (assuming the following conditions: the bootstrap voltage V BO Below the target value, e.g. 5.4V for the entire phase, the current limiter Q1′ is turned on; the recirculation is “deep” and decreases suddenly after the low-side switch LS has been turned on). Therefore, this second method may lead to a degradation in the efficiency of the bootstrap charging phase, thereby preventing the bootstrap voltage V BOto reach the desired voltage level.

[0050] A third approach to the clock feedthrough problem is to select a larger hysteresis width for comparator 22 (i.e., V T，H_S With V T，L_S ) to include any possible noise peaks within the hysteresis window, such as Figure 5 As shown in the figure, Figure 5 In this case, the signal V CC , V T，H_S , V T，L_S , V S , V BOOT , V OUT , possible waveforms of LVG and G_ACT_D. Here, the hysteresis width (V T，H_S -V T，L_S ) is large enough to include the voltage V caused by the coupled noise S This helps avoid the onset of undesirable on / off oscillation modes. However, this approach can have disadvantages under some operating conditions. First, the accuracy of regulation can deteriorate in cases where the peak-to-peak amplitude of the coupled noise can be in the range of 1V or more; the use of active diodes themselves is questionable relative to conventional passive diodes. Second, if the high voltage threshold V T，H_S Higher than the sensor supply voltage V CC , then the backwash current as described above can be triggered and can last for a long time.

[0051] However, it has been noted that the onset of the on / off oscillation state is acceptable if its impact on noise and current consumption is acceptable (limited), i.e. if the oscillation frequency is controlled. This is especially true if the switch is controlled by an overvoltage driver, as in reference Figure 1 and 2 In the example discussed, some on / off oscillation rate may even be useful, helping to recharge the gate terminal when it is in a "bootstrapped" state. Moreover, a small and controlled amount of backwash current is acceptable if the effect of the backwash current on the charging efficiency is also acceptable. Therefore, one or more embodiments are directed to circuits that implement functions that control the above-mentioned disadvantages. This function is called "dynamic hysteresis" and relies on time shaping (i.e., changing it over time) of the hysteresis threshold. In particular, the threshold is shaped to temporarily widen the hysteresis width and gradually re-enter the "normal" (or "static") hysteresis width, taking into account the following considerations:

[0052] Required by commutation of the regulation state (e.g., commutation of the logic value ACT_D_ON output by the voltage sensor 20) D_ON);

[0053] Alternatively setting one or more amplifications of the hysteresis width by increasing the upper threshold or by decreasing the lower threshold in order to filter (or "tolerate") noise peaks coming from the commutation itself; and

[0054] Re-enter the phase to track the damped phase of the noise.

[0055] It should be noted that one or more embodiments may be applied to any type of switching voltage regulator in which a switching element (e.g., a pass element) controls the flow of current between an input voltage node and an output regulation node based on a comparison of an output voltage with a threshold. Therefore, although the present description will primarily concern the intermediate supply voltage V at node 106 of the bootstrap path of the half-bridge driver circuit, S regulation, but it should be understood that one or more embodiments may involve any kind of switching voltage regulator.

[0056] By comparison Figure 6 and Figure 7 The concept of dynamic hysteresis can be better understood by looking at the waveforms shown in Figure 6 and Figure 7 shows the signal V S (or more generally, the voltage regulated by the regulator Vreg), V T (propagated to the selected threshold of the comparator – thick line), V T，H_S and V T，L_S (static threshold), V CC (or more generally, the sensor reference voltage V ref ) and G_ACT_D (or more generally, the control signal Reg_sw of the transfer element of the voltage regulator). Figure 6 As illustrated in FIG. 1 and discussed previously, when using conventional fixed hysteresis, an on / off regulation with narrow hysteresis can trigger an uncontrolled oscillation state whose period is determined by the detected signal V S The sum of the delays occurring between crossing one of the thresholds and commutation of transistor Q3 gives (for example, in Figure 6 In the voltage V S drops below V T，L_S The subsequent assertion of the determination signal G_ACT_D from low to high, and the voltage V S rises above V T，H_S The subsequent de-assertion of the determination signal G_ACT_D from high to low). Figure 7 As illustrated in FIG. , dynamic hysteresis can be used to perform on / off regulation, where the dynamic threshold voltage V T，H_D and V T，L_D separated by a "base" gap, the magnitude of which may be the same as the magnitude of the static hysteresis (e.g. Figure 6 V T，H_S -V T，L_S), but can be modulated over time (as further disclosed below) to control the oscillation mechanism, thereby reducing noise and power consumption.

[0057] In detail, Figure 8 is a schematic circuit diagram of a control circuit 80 configured to generate a control signal Reg_sw for a switching element (eg, a transfer element) of a switching voltage regulator, thereby implementing dynamic hysteresis. The control circuit 80 receives a reference voltage V ref (exist Figure 1 and Figure 2 In the application example, the sensor supply voltage V CC ), and the regulation voltage Vreg generated by the voltage regulator (at Figure 1 and Figure 2 The application example is an intermediate supply voltage V S As discussed further below, the threshold selection / shaping circuit 82 is used to select the reference voltage V ref Start to generate dynamic threshold voltage V T . Dynamic threshold V T The regulated voltage Vreg is fed to a comparator circuit 84 which generates a control signal Reg_sw. For example, the dynamic threshold V T is fed to the positive terminal of the comparator 84, and the regulated voltage Vreg is fed to the negative terminal of the comparator 84, so that if V reg <V T , then the control signal Reg_sw is asserted (e.g., high), and if V reg >V T , then the control signal Reg_sw is de-asserted (eg, low).

[0058] Specifically, in the selection / shaping circuit 82, the input node 820 receives the reference voltage V ref . About high dynamic threshold V T，H_D The voltage generator 822 coupled to the node 820 adds the fixed voltage to the reference voltage V ref To generate a high static threshold V at node 824 T，H_S The voltage generator 826 coupled to the node 824 adds another fixed voltage to the high static threshold V T，H_S To generate a high maximum threshold V at node 828 T，H_MAX Node 828 can be selectively coupled to generate a high dynamic threshold V via switch 830 T，H_D A discharge path (eg, an RC circuit) is coupled between nodes 824 and 832 and can be selectively activated via switch 830 to discharge the high dynamic voltage V at node 832. T，H_D Towards the high quiescent voltage V at node 824 T，H_STherefore, switch 830 can couple node 832 to node 828 to discharge voltage V T，H_D Bring to maximum value V T，H_MAX , or alternatively decouple node 832 from node 828 and activate the discharge path to cause voltage V T，H_D Towards static value V T，H_S Specifically, the discharge path may include a capacitor C coupled between nodes 824 and 832. H , and a resistor R which can be selectively coupled between nodes 824 and 832 via switch 830 H . About the low dynamic threshold V T，L_D The voltage generator 842 coupled to the node 820 is shaped from the reference voltage V ref Subtract a fixed voltage to produce a low static threshold V at node 844 T，L_S The voltage generator 846 coupled to the node 844 is connected to the low static threshold V T，L_S Another fixed voltage is subtracted to produce a low minimum threshold V at node 848 T，L_MIN Node 848 can be selectively coupled via switch 850 to generate a low dynamic threshold V T，L_D A charging path (eg, an RC circuit) is coupled between nodes 844 and 852 and can be selectively activated via switch 850 to charge the low dynamic voltage V at node 852. T，L_D Towards the low quiescent voltage V at node 844 T，L_S Therefore, switch 850 can couple node 852 to node 848 to increase the voltage V T，L_D Bring to minimum value V T，L_MIN , or alternatively decouple node 852 from node 848 and activate the charging path to make voltage V T，L_D Towards static value V T，L_S Specifically, the charging path may include a capacitor C coupled between nodes 844 and 852. L , and a resistor R which can be selectively coupled between nodes 844 and 852 via switch 850 L The selection / shaping circuit 82 further includes a switch 860 that selectively couples the positive terminal of the comparator 84 to the node 832 to use the high dynamic threshold V T，H_D As the threshold signal V T , or coupled to node 852 to use a low dynamic threshold V T，L_D As the threshold signal V T .

[0059] Therefore, in Figure 8 In the circuit, the threshold value V is selected according to the output of the comparator 84. Tto implement hysteresis and, before selection, has been added to the static value (V T，H_S or V T，L_S ) and the threshold value (V T，H_D or V T，L_D ) is precharged to the maximum or minimum value (V T，H_MAX or V T，L_MIN ). The additional contribution is dynamic (or "transient") and decays (eg, exponentially) according to an appropriate decay time (set by an RC circuit in this example), so that the dynamic threshold asymptotically reaches the corresponding static value.

[0060] See again Figure 7 , switches 830, 850 and 860 may be controlled according to the following timing scheme, assuming that comparator 84 is initially configured to receive a low threshold V T，L_D (ie, switch 860 is initially set to propagate voltage V T，L_D , that is, V T =V T，L_D =V T，L_S ). When the regulated voltage V reg Down to V T At the following time (time t1), the control signal Reg_sw switches to the asserted state, and the switch 860 is set to couple the comparator 84 to the node 832 to receive the previously precharged maximum value V T，H_MAX The voltage V T，H_D (i.e., V T =V T，H_D ). Therefore, the voltage V T Reaching the maximum value V T，H_MAX At the same time, switch 830 is set to couple node 832 to resistor R H , so that the voltage V T，H_D Start towards voltage V T，H_S At the same time, on the other side, switch 850 is set to couple node 852 to node 848, so that voltage V T，L_D is brought to a minimum value V T，L_MIN . Maintaining this configuration (i.e., V T =V T，H_D , V T，H_D Towards V T，H_S decay, and V T，L_D =V T，L_MIN ) until the regulated voltage V reg Crossing the V T (i.e., it exceeds V T，H_D , time t2). At this time, the control signal Reg_sw switches to the deasserted state, and the switch 860 is set to couple the comparator 84 to the node 852 to receive the node 852 which has been precharged to the minimum value V T，L_MINThe voltage V T，L_D (i.e., V T =V T，L_D ). Therefore, the voltage V T Reach the minimum value V T，L_MIN At the same time, switch 850 is set to couple node 852 to resistor R L , so that the voltage V T，L_D Start towards voltage V T，L_S At the same time, on the other side, switch 830 is set to couple node 832 to node 828, so that voltage V T，H_D Reaching the maximum value V T，H_MAX . Maintaining this configuration (i.e., V T =V T，L_D , V T，L_D Towards V T，L_S decay, and V T，H_D =V T，H_MAX ) until the regulated voltage V reg Crossing the V again T (i.e., it drops to V T，L_D Hereinafter, time t3). At this time, a new cycle starts from time t1.

[0061] Fig. 9 is an exemplary circuit diagram of a possible circuit implementation operating according to the principles of the control circuit 80 and the threshold selection / shaping circuit 82. In this implementation, the circuit 82 includes a circuit configured at a power supply voltage V Supply and ground GND. The current flow line includes the following components of the series device: coupled to the power supply voltage V Supply and node 932 to provide a bias current I bias The current generator 902 includes a resistor Rtsh disposed between nodes 932 and 924, a resistor Rtdh disposed between nodes 924 and 820, a resistor Rtsl disposed between nodes 820 and 944, a resistor Rtdl disposed between nodes 944 and 952, and a resistor coupled between node 952 and ground to absorb the bias current I biasThe current generator 904 is provided. In addition, a bypass transistor 906 (e.g., an n-channel MOS transistor) having an adjustable conductivity is provided in parallel with the resistor Rtsh and is controlled by the modulation signal DYHY_H, and a bypass transistor 908 (e.g., an n-channel MOS transistor) having an adjustable conductivity is provided in parallel with the resistor Rtd1 and is controlled by the modulation signal DYHY_L. The first shaping circuit 92 is coupled to the output of the comparator 84 and is configured to generate the signal DYHY_H, so that in response to the assertion (e.g., a rising edge) of the signal Reg_sw, the modulation signal DYHY_H is suddenly transferred from the asserted state to the de-asserted state to turn off the transistor 906, and then gradually (e.g., smoothly) is transferred from the de-asserted state to the asserted state again to gradually increase the conductivity of the transistor 906. Therefore, when the signal Reg_sw switches to the asserted state, the transistor 906 is suddenly turned off and then gradually turned on, so that the resistance Rtsh′ between the nodes 924 and 932 suddenly passes from a negligible value (approximately zero) to Rtsh and then gradually decays toward zero again. Therefore, the high dynamic threshold V at the node 932 is T，H_D Typically equal to the high static threshold V T，H_S (V T，H_S =V ref +I bias *Rtdh), in response to the signal Reg_sw (V T，H_MAX =V ref +I bias *(Rtdh+Rtsh)) is asserted and suddenly set to the maximum value V T，H_MAX , and then again towards V T，H_S Similarly, the second shaping circuit 94 is coupled to the output of the comparator 84 and is configured to generate the signal DYHY_L so that in response to the de-assertion (e.g., falling edge) of the signal Reg_sw, the modulation signal DYHY_L is suddenly transferred from the asserted state to the de-asserted state to turn off the transistor 908, and then gradually (e.g., smoothly) is transferred from the de-asserted state to the asserted state again to gradually increase the conductivity of the transistor 908. Therefore, when the signal Reg_sw switches to the de-asserted state, the transistor 908 is suddenly turned off and then gradually turned on, so that the resistance Rtd1′ between the nodes 944 and 952 is suddenly transferred from a negligible value (approximately zero) to Rtd1 and then gradually decays toward zero again. Therefore, the low dynamic threshold V at the node 952 is T，L_D Typically equal to the low quiescent threshold V T，L_S (V T，L_S =V ref -I bias *Rts1), in response to the deassertion of signal Reg_sw (V T，L_MIN =V ref -I bias*(Rts1+Rtd1)) and suddenly set to the minimum value V T，L_MIN , and then again towards V T，L_S attenuation.

[0062] Therefore, in general, Fig. 9 architecture, by transferring voltage to / from the reference voltage V ref Add / subtract fixed R*I contribution (Rtdh*I bias and Rtsl*I bias ) to generate the static threshold (V T，H_S and V T，L_S ). Dynamic Threshold (V T，H_D and V T，L_D ) is generated by adding / subtracting the temporary R*I contribution given by the time-varying resistor. On both sides, the maximum / minimum values ​​(V, respectively) are generated by smoothing the gate voltage drive (i.e., signals DYHY_H and DYHY_L) with respective transistors (e.g., n-channel MOS transistors) bypassing. T，H_MAX and V T，L_MIN ) to obtain resistance modulation, the conductance of the transistors being modulated from zero (completely off) to a maximum value that effectively bypasses the respective resistors (i.e., where the resistance of the bypass transistor is negligible compared to the resistance of the bypass resistor). Figure 8 The maximum and minimum values ​​of V T，H_MAX and V T，L_MIN Here it is created in "real time" (eg within a few nanoseconds) when the corresponding threshold is selected. As soon as a relevant change in the sensor output is detected (eg a commutation of the signal Reg_sw), the modulated signals DYHY_H and DYHY_L are generated. Figure 8 The signal waveform in the circuit structure is Fig.10 As shown in the figure, Figure 7 The difference between the two figures is that the dynamic threshold V T，H_D and V T，L_D shape.

[0063] Note that in some embodiments, by modulating the two input signals of comparator 84, rather than modulating two different threshold signals, a similar Figure 8 and Fig. 9 The dynamic hysteresis operation of the circuit. For example, Fig.11 is a circuit diagram of one or more exemplary embodiments in which the dynamic hysteresis operating principle is applied to a half-bridge driver (similar to Figure 2 The active diode driver 60 of the bootstrap path of the half-bridge driver) applies modulation to the voltage V CC (It is used to replace the reference voltage V ref) to produce a low dynamic threshold and applied to the voltage V S (which corresponds to the regulated voltage V reg ) to simulate high dynamic threshold effects.

[0064] In particular, Fig.11 The active diode adjustment sensor 20 includes a diode arranged at a power supply terminal 100a (to receive a voltage V CC ) and ground GND. The first current flow line includes the following components arranged in series: a set of series-connected diodes DL (e.g., two diodes) arranged to conduct from node 100a to node 150, a decoupling transistor NL (e.g., an n-channel MOS high-voltage transistor) having a conducting channel arranged between node 150 and node 152 and coupled to the sensor supply voltage V CC A control (e.g., gate) terminal of the transistor 150 is provided, a resistor R1 (e.g., 2 kΩ) disposed between nodes 152 and 154, a resistor R2 (e.g., 24 kΩ) disposed between nodes 154 and 156, a resistor R3 (e.g., 4 kΩ) disposed between nodes 156 and 158, and a resistor R4 (e.g., 4 kΩ) coupled between node 158 and ground GND to sink a bias current I bias (e.g., 23 μA) current generator 160. In addition, a bypass transistor 162 (e.g., an n-channel MOS transistor) with adjustable conductivity is provided in parallel with the resistor R2 and is controlled by the modulation signal DYHY_L, and a bypass transistor 164 (e.g., an n-channel MOS transistor) operating as an on / off switch is provided in parallel with the resistor R3 and is controlled by the activation signal ACT_D_ON. Therefore, a voltage V is generated at the node 158. CC_I .

[0065] Fig.11 The active diode regulation sensor 20 includes a diode disposed at an intermediate power supply node 106 (to receive a voltage V S ) and ground GND. The second current flow line includes the following components arranged in series: a set of series-connected diodes DH (e.g., two diodes) arranged to conduct from node 106 to node 170, a decoupling transistor NH (e.g., an n-channel MOS high-voltage transistor) having a conducting channel arranged between node 170 and node 172 and coupled to the sensor supply voltage V CC A control (eg, gate) terminal of , a resistor R4 (eg, 8 kΩ) is arranged between nodes 172 and 178, and a current generator 180 is coupled between node 178 and ground GND to sink a bias current I bias(For example, 23 μA). In addition, a bypass transistor 182 (for example, an n-channel MOS transistor) with adjustable conductivity is provided in parallel with the resistor R4 and is controlled by the modulation signal DYHY_H. Therefore, a voltage V is generated at the node 178. S _ I .

[0066] like Fig.11 As shown, current generators 160 and 180 may be implemented as current mirrors. Thus, sensor 20 may include: a diode-connected transistor 190 (e.g., an n-channel MOS transistor) having a conductive channel disposed between bias source BIAS and ground GND; a transistor 160 (e.g., an n-channel MOS transistor) having a conductive channel disposed between node 158 and ground GND; and a transistor 180 (e.g., an n-channel MOS transistor) having a conductive channel disposed between node 178 and ground GND, wherein control (e.g., gate) terminals of transistors 160 and 180 are coupled to a control (e.g., gate) terminal of transistor 190. In addition, pull-down transistor 192 may have a conductive path disposed between control terminals of transistors 160, 180 and ground, and may be controlled by a disable signal DIS. If the low-side switch LS of the half-bridge is turned off, the disable signal DIS may be asserted (e.g., high), and if the low-side switch LS of the half-bridge is turned on, the disable signal DIS may be de-asserted (e.g., low), so that the sensor circuit 20 functions (only) when the low-side switch LS is turned on. Thus, the signal DIS may substantially correspond to the complement of the low-side gate control signal LVG.

[0067] like Fig.11 As shown, comparator 84 (or 22) has a first (eg, positive) terminal coupled to node 158 and a second (eg, negative) terminal coupled to node 178 to compare signal V CC_I and V S_I The activation signal ACT is selected by the enable signal EN at the AND logic gate 194 to generate the activation signal ACT_D_ON for the active diode Q3 when the low-side switch LS is turned on (only). Therefore, the signal EN can basically correspond to the low-side gate control signal LVG (and the complement of the signal DIS). The shaping circuits 92 and 94 are basically as described in reference Fig. 9 and Fig.10The operation is as discussed, that is, in response to the assertion (e.g., rising edge) of the signal ACT_D_ON (or equivalently, in response to the de-assertion of the complement ACT_D_OFF of the signal ACT_D_ON), ​​the signal DYHY_H is generated to gradually pass from the de-asserted state to the asserted state, and in response to the de-assertion (e.g., falling edge) of the signal ACT_D_ON, the signal DYHY_L is generated to gradually pass from the de-asserted state to the asserted state. For example, the smooth transition of the signal DYHY_H may last for about 2 μs and the smooth transition of the signal DYHY_L may last for about 50 ns.

[0068] It should be noted that active diode adjustment sensor 20 is drain driven (i.e., the input signals are taken at nodes 150 and 170 which are the drain terminals of transistors NL and NH), and as long as one of the input signals (specifically, V S ) can be biased at a high voltage and MOS technology allows decoupling the low voltage from the high voltage (only) via the drain. The decoupling transistors NL, NH are "pseudo-cascode" high voltage n-channel MOS transistors that can separate the internal nodes from the input nodes when the input nodes (particularly node 106) are at a high voltage phase.

[0069] Fig.12 yes Fig.11 1 is an exemplary circuit diagram of the small signal operation of the voltage sensor 20. In the first current flow line, the diode DL provides about 2*V BE The fixed voltage drop of transistor NL provides a resistor R NL =k*(V CC -V CC_S -V Th ), where V CC_S is the voltage at node 152, resistor R2 with transistor 162 provides a variable resistance R2 mod (e.g., variable between about 24 kΩ and about 0.2 kΩ), and resistor R3 with transistor 164 provides a bypassable fixed resistance. In the second current flow line, diode DH provides about 2*V BE The fixed voltage drop of transistor NH provides resistance RNH = k*(V S -V S_S -V Th ), where V S_S is the voltage at node 172, resistor R4 with transistor 182 provides a variable resistance R4 mod (For example, variable between about 8 kΩ and about 0.2 kΩ).

[0070] Fig.13 is the resistor R2 modA timing diagram of possible changes in response to the falling edge of the signal ACT_D_ON, Fig.14 is the resistor R4 mod A timing diagram of possible changes in response to a rising edge of the signal ACT_D_ON.

[0071] Therefore, the second current flow line (“bootstrap side” or “high side”) acts as a voltage shifter, where once the input voltage V S Close to the trigger point, the high voltage decoupler NH operates in linear mode. The linear mode operation is set by the series diode DH, which reduces the drain voltage of transistor NH enough to exit the saturation mode. The voltage shift is determined by the bias current I bias (generated, for example, by a saturated n-channel MOS transistor 180) operates via a series resistor that can be bypassed or time modulated. A similar voltage shifter is provided by the first current low line (the "reference side"), whose input voltage is the sensor supply voltage V CC Static and Dynamic Hysteresis The static and dynamic hysteresis are obtained by separate modulation of the total resistance encountered by the current in the shifter.

[0072] exist Fig.11 and Fig.12 In the example, as referenced Figure 2 As discussed, the values ​​of the static and dynamic thresholds may be set according to certain design rules discussed below.

[0073] In particular, the static high threshold V T，H_S Can be set to V CC To maximize the benefits of using active diode Q3, it is possible to set it slightly below the voltage V CC The first reason is that, although the drain-source on-resistance of the active diode Q3 may be very low (e.g., several ohms), the voltage V S In fact, the sensor supply voltage V will never be reached. CC The second reason is that if the value of V T，H_S =V CC , then due to the mismatch of certain parameters of the components of the two voltage shifters in the voltage sensor 20 or the comparator 84, the static high threshold V T，H_S may be accidentally set at the sensor supply voltage V CC In some applications, this can result in a small but potentially harmful “backwash current” that affects the bootstrap voltage V BO Such a potential mismatch can therefore be compensated by introducing an opposite mismatch, resulting in a static high threshold V T，H_S Slightly lower than the voltage VCC For example, in a specific example, the static high threshold V T，H_S Can be set equal to V CC The value of -46mV is because the hysteresis resistors R2, R3 and R4 are bypassed (providing a low resistance of about 100Ω to the current) and the operating resistor R1 has a resistance of about 2kΩ, making the V CC and V S The voltage mismatch (i.e., V CC_I V S_I ) is equal to 23μA*2kΩ-46mV. On the other hand, the static low threshold V T，L_S can be a threshold selected when the sensor is enabled, and its value can be set by the "Operation Resistor Configuration", that is: V T，L_S =V CC -(2+4)kΩ*23μA=V CC -138mV. Therefore, the static hysteresis width (i.e., V T，H_S -V T，L_S ) can be about 90 mV, which is sufficient to filter noise (e.g., thermal, flicker, RTS noise) in typical semiconductor devices.

[0074] Regarding the dynamic threshold, the maximum value of the dynamic high threshold V T，H_MAX Can be set to V CC +138mV, while the decay time can be set to about 2μs. This setting can directly affect the trade-off between the desire to limit the occurrence of on / off oscillation states and the desire to limit the backwash current. In practice, the dynamic high threshold (defined by V CC +(8-2)kΩ*23μA gives the maximum value V T，H_MAX can be set at the turn-on transition of active diode Q3 (e.g., from about V CC To about 2*V CC ) and the resulting signal V S above any estimated overshoot (e.g., within 6-sigma statistics) of CC <V S <V T，H and the current limiter Q1' is switched on). The decay time can be set to represent a compromise between the two parameters of the contrast requirement mentioned previously, namely the current consumption due to the controlled on / off mechanism and the bootstrap voltage V due to the temporary backwash current. BO For example, in a typical case, the current I associated with a controlled on / off oscillation cc It can be about 80μA. The bootstrap voltage V BOThe drop in can be evaluated in a worse case (as discussed in more detail below), taking into account the bootstrap capacitor C B This can result in an acceptable value (e.g., about 140 mV) for a capacitance of about 100 nF. On the other hand, the minimum value of the dynamic low threshold V T，L_MIN Can be set to V by “Working Resistor Configuration” CC -690mV (V T，L_MIN =V CC -(2+4+24)kΩ*23μA=V CC -690mV), and the decay time can be set to about 50ns.

[0075] Fig.15 Yes Figure 1 and Figure 2 A diagram of possible waveforms of signals in an architecture of which the Fig.11 The active diode regulation sensor 20 illustrated in FIG. 2 , specifically: the sensor power supply voltage V CC (dashed line), threshold voltage V T，H_D and V T，L_D (dashed line), the intermediate power supply voltage V at node 106 S (solid line), the floating supply voltage V at node 104 BOOT (solid line), the output voltage V at the switch node 102a OUT (solid line), low-side gate control signal LVG (solid line) and diode control signal G_ACT_D (solid line). Fig.15 The waveform shows the use of voltage sensor 20 with dynamic hysteresis to regulate the voltage V at node 106 S The backwash current can be effectively limited to an acceptable amount, thereby setting up dynamic control of this undesirable event. For example, when the current limiter Q1' is turned on, the voltage V S The waveform is slightly lower than the high threshold V T，H The theoretically possible worst case waveform of the active diode Q3 can be assumed to have an on-resistance (Rds) of about 10Ω and a signal V T，H and V S The decay of is linear to estimate the wasted charge. Under these assumptions, at V BOOT >V S >V CC The charge wasted during the phase can therefore be estimated as:

[0076] (V T，H_MAX -V CC )*T decay / (2*Rds)=138mV*2μs / 20Ω~14nC

[0077] The bootstrap capacitor C B In the case of a capacitance of about 100nF, this wasted charge may cause the bootstrap voltage V BO The drop is about 140mV.

[0078] As previously discussed, one or more embodiments are applicable not only to half-bridge drivers with high-side bootstrap architecture, but generally to any switching (on / off) voltage regulator with hysteresis that may be affected by gate feedthrough issues. Fig.16 is a circuit block diagram of an exemplary switching regulator 300, which includes a circuit for receiving an input power supply voltage V Supply The input node 302 is used to generate the regulation voltage V reg an output node 304, a transfer element 306 (on / off switch) provided between nodes 302 and 304 (eg, a MOS transistor) and controlled by a signal Gate_sw (wherein the transfer element 306 has a parasitic capacitance coupling C between the output terminal and the control terminal); gs ), a filter capacitor C is provided between the output node 304 and the ground GND. F , set between the output node 304 and the voltage reference node 308 at a voltage V L Load Z L The comparator 310 is configured to convert the hysteresis voltage V reg With the reference voltage V ref The dynamic threshold V T A comparison is made, and the gate driver 312 is configured to generate a signal Gate_sw as a function of the result of the comparison operated by the comparator 310 .

[0079] exist Fig.16 In the general example, the filter capacitor C F and parasitic capacitance coupling C gs The ratio between is critical in the occurrence of the same problem discussed previously with reference to the bootstrap path circuit of the half-bridge driver, namely the possible occurrence of undesirable high frequency on / off oscillation mode or undesirable backwash current. For example, the on / off oscillation state can be triggered when the following conditions are met: DV Gate *C gs / (C F +C gs )>DV Threshold , where DV Gate is the dynamic characteristic of the signal Gate_sw, DV Threshold is the width of the hysteresis of the comparator 310. Therefore, when sufficient (eg, large enough) filter capacitors cannot be implemented, dynamic hysteresis may be a solution.

[0080] Thus, one or more embodiments may provide for temporal modulation of the voltage threshold in an on / off regulation with hysteresis. The purpose is to temporarily enlarge the hysteresis width to include noise peaks of the regulation signal within the hysteresis range, for example to suppress excessive negative feedback that may lead to an uncontrolled on / off oscillation state. When such a threshold is selected, the threshold may be temporally modulated by adding a voltage contribution to each (or only one) baseline threshold level (also referred to as a static threshold). The additional voltage contribution may then decay to zero, for example due to an RC discharge or any equivalent circuit within a dedicated threshold control circuit, so that the dynamic threshold asymptotically approaches the static level.

[0081] Thus, one or more embodiments as illustrated herein may be implemented in a manner that varies the width of the static hysteresis (ie, the static or baseline threshold V T，H_S With V T，L_S A satisfactory compromise is achieved between the requirements of providing regulation accuracy while the difference between the voltage and the frequency is fairly limited and the requirements of providing noise and power consumption while the coupled noise is absorbed and the ripple of the regulated voltage is controlled as both voltage and frequency.

[0082] Without prejudice to the essential principles, the details and embodiments may vary even significantly with respect to what has been described by way of example, without departing from the scope of protection.

[0083] The scope of protection is determined by the appended claims.

[0084] A voltage regulator circuit (300) can be summarized as comprising: an input node (302; 100a) configured to receive an input supply voltage (V Supply ; V CC ); the output node (304; 106) is configured to generate a regulated output voltage (V reg ; V S ); a switchable transfer element (306; Q3) having a selective conductive path disposed between the input node (302) and the output node (304); and a comparator circuit (310; 84) configured to convert the regulated output voltage (V reg ) and dynamic threshold (V T ) is compared to generate a control signal (Reg_sw; act) to control the switching of the switchable transfer element (306), wherein the control signal is asserted to cause the switchable transfer element (306) to be turned on, and the control signal is de-asserted to cause the switchable transfer element (306) to be turned off; wherein the voltage regulator circuit (300) further includes a threshold selection and shaping circuit (82; 20) configured to shape the regulated output voltage and / or the dynamic threshold so that: in response to the assertion of the control signal (Reg_sw), the dynamic threshold (V T) and the regulated output voltage (V reg ) suddenly increases and then gradually decreases toward the target static value; and in response to the de-assertion of the control signal (Reg_sw), the regulated output voltage (V reg ) and the dynamic threshold (V T ) suddenly increases and then gradually decreases towards the target static value.

[0085] The threshold selection and shaping circuit (82) may include: a reference node (820) configured to receive a reference voltage (V ref ); a first circuit device configured to add a first fixed voltage to the reference voltage (V ref ) to generate the upper static threshold (V T，H_S ); a second circuit device configured to add a first variable voltage to the upper static threshold (V T，H_S ) to generate the upper dynamic threshold (V T，H_D ); a third circuit device, configured to obtain a reference voltage (V ref ) minus a second fixed voltage to produce the lower static threshold (V T，L_S ); a fourth circuit device, configured to be from the lower static threshold (V T，L_S ) minus the second variable voltage to generate the lower dynamic threshold (V T，L_D ); wherein the first variable voltage can be gradually decreased in response to the assertion of the control signal (Reg_sw), and the second variable voltage can be gradually decreased in response to the de-assertion of the control signal (Reg_sw); and wherein the threshold selection and shaping circuit (82) can also include a switch (860) configured to propagate the upper dynamic threshold (V T，H_D ) and propagates the lower dynamic threshold (V T，L_D ) to generate the dynamic threshold (V T ).

[0086] The first circuit device may include a first voltage generator (822) coupled between the reference node (820) and a first static node (824) to generate the upper static threshold (V T，H_S ); the second circuit device may include a second voltage generator (826) coupled in parallel between the first static node (824) and the first dynamic node (832) and a first selectively activatable RC discharge circuit (R H , C H), wherein the first dynamic node (832) is coupled to the second voltage generator (826) in response to the control signal (Reg_sw) being de-asserted, and is coupled to the first RC discharge circuit (R H , C H ) to generate the upper dynamic threshold (V T，H_D ); the third circuit device may include a third voltage generator (842) coupled between the reference node (820) and a second static node (844) to generate the lower static threshold (V T，L_S ); the fourth circuit device may include a fourth voltage generator (846) coupled in parallel between the second static node (844) and the second dynamic node (852) and a second selectively activatable RC discharge circuit (R L , C L ), wherein the second dynamic node (852) is coupled to the fourth voltage generator (846) in response to the control signal (Reg_sw) being asserted, and is coupled to the second RC discharge circuit (R L , C L ) to generate the lower dynamic threshold (V T，L_D ).

[0087] The threshold selection and shaping circuit (82) may include a voltage at the supply voltage (V Supply ) and ground (GND), and wherein: the first circuit device may include a first resistor (Rtdh) arranged in the current flow line between the reference node (820) and a first static node (924) to generate the upper static threshold (V T，H_S ); the second circuit device may include a second resistor (Rtsh) and a first bypass transistor (906) arranged in parallel in the current flow line between the first static node (924) and the first dynamic node (932), wherein the conductivity of the first bypass transistor (906) may gradually increase in response to the assertion of the control signal (Reg_sw) to generate the upper dynamic threshold (V T，H_D ); the third circuit device may include a third resistor (Rtsl) arranged in the current flow line between the reference node (820) and the second static node (944) to generate the lower static threshold (V T，L_S); the fourth circuit device may include a fourth resistor (Rtd1) and a second bypass transistor (908) arranged in parallel in the current flow line between the second static node (944) and the second dynamic node (952), wherein the conductivity of the second bypass transistor (908) may gradually increase in response to the de-assertion of the control signal (Reg_sw) to generate the lower dynamic threshold (V T，L_D ).

[0088] In a stable state, the conductivity of the first bypass transistor (906) and the second bypass transistor (908) may be high.

[0089] The threshold selection and shaping circuit (20) may include: a first circuit device configured to select and reshape the input power supply voltage (V CC ) to generate a static threshold (V CC_S ); a second circuit device, the second circuit device is configured to be from the static threshold (V CC_S ) to generate a dynamic threshold (V CC_I ); a third circuit device configured to output the regulated output voltage (V S ) to generate a static comparison signal (V S_S ); a fourth circuit device, configured to obtain a static comparison signal (V S_S ) to generate a dynamic comparison signal (V S_I ); wherein the first variable voltage can be gradually reduced in response to the de-assertion of the control signal (ACT), and the second variable voltage can be gradually reduced in response to the assertion of the control signal (ACT); wherein the comparator circuit (84) can be configured to set the dynamic threshold (V CC_I ) and the dynamic comparison signal (V S_I ) are compared to generate the control signal (ACT).

[0090] The first circuit arrangement may include a first diode set (DL) coupled in series to a first decoupling transistor (NL) between the input node and a first quiescent node (152, 154) to generate the quiescent threshold (V CC_S); the second circuit device may include a first resistor (R2) and a first modulation transistor (162) coupled in parallel between the first static node (152, 154) and the first dynamic node (156, 158), wherein the conductivity of the first modulation transistor (162) may gradually increase in response to a falling edge of the control signal (ACT) to generate the dynamic threshold (V CC_I ); the third circuit device may include a second diode set (DH) coupled in series with a second decoupling transistor (NH) between the output node (106) and a second static node (172) to generate the static comparison signal (V S_S ); the fourth circuit device may include a second resistor (R4) and a second modulation transistor (182) coupled in parallel between the second static node (172) and the second dynamic node (178), wherein the conductivity of the second modulation transistor (182) may gradually increase in response to a rising edge of the control signal (ACT) to generate the comparison signal (V S_I ).

[0091] The threshold selection and shaping circuit (20) may further include a third resistor (R3) and a bypass transistor (164) coupled in parallel between the first dynamic node (156) and the input of the comparator circuit (84), wherein the bypass transistor (164) may be fully turned on in response to the control signal (ACT) being asserted, and may be fully turned off in response to the control signal (ACT) being de-asserted.

[0092] A half-bridge driver circuit (HBD) can be summarized as comprising: a positive power supply pin (100a) and a ground pin (100b, 102b) configured to receive a power supply voltage (V CC ); A first control pin configured to receive a low voltage high side control signal (IN) for controlling a high side switch (HS) of a half bridge circuit HS ); a second control pin configured to receive a low-voltage low-side control signal (IN) for controlling a low-side switch (LS) of the half-bridge circuit. LS ); a high-side gate driver circuit (12a) configured to receive the low voltage high-side control signal (IN) via a level shifter circuit (14) HS ) and generates a corresponding high-side gate control signal (HVG); a low-side gate driver circuit (12b) is configured to receive the low-voltage low-side control signal (IN LS) and generates a corresponding low-side gate control signal (LVG); wherein the high-side gate driver circuit (12a) is biased between a floating power supply pin (104) and a switch pin (102a) of the half-bridge driver circuit (HBD), and wherein the floating power supply pin (104) is coupled to the positive power supply pin (100a) via a bootstrap path, the bootstrap path comprising: a voltage regulator circuit (300) which may include an input node (302; 100a) configured to receive an input power supply voltage (V Supply ; V CC ); the output node (304; 106) is configured to generate a regulated output voltage (V reg ; V S ); a switchable transfer element (306; Q3) having a selective conductive path arranged between the input node (302) and the output node (304); and a comparator circuit (310; 84) configured to convert the regulated output voltage (V reg ) and dynamic threshold (V T ) is compared to generate a control signal (Reg_sw; act) to control the switching of the switchable transfer element (306), wherein the control signal is asserted to cause the switchable transfer element (306) to be turned on, and the control signal is de-asserted to cause the switchable transfer element (306) to be turned off; wherein the voltage regulator circuit (300) further includes a threshold selection and shaping circuit (82; 20) configured to shape the regulated output voltage and / or the dynamic threshold, so that: in response to the assertion of the control signal (Reg_sw), the dynamic threshold (V T ) and the regulated output voltage (V reg ) suddenly increases and then gradually decreases toward a target static value; and in response to the de-assertion of the control signal (Reg_sw), the regulated output voltage (V reg ) and the dynamic threshold (V T ) suddenly increases and then gradually decreases toward a target static value, the input node of the voltage regulator circuit (300) is connected to the positive power supply pin (100a) and the output node thereof is connected to a decoupling node (106) inside the half-bridge driver circuit (HBD); and a current limiter circuit (Q1′) is arranged between the decoupling node (106) and the floating power supply pin (104).

[0093] An electronic device, generally comprising: a half-bridge driver circuit (HBD), which may include a positive power supply pin (100a) and a ground pin (100b, 102b), wherein the positive power supply pin (100a) and the ground pin (100b, 102b) are configured to receive a power supply voltage (VCC ); A first control pin configured to receive a low voltage high side control signal (IN) for controlling a high side switch (HS) of a half bridge circuit HS ); a second control pin configured to receive a low-voltage low-side control signal (IN) for controlling a low-side switch (LS) of the half-bridge circuit. LS ); a high-side gate driver circuit (12a) configured to receive the low voltage high-side control signal (IN) via a level shifter circuit (14) HS ) and generates a corresponding high-side gate control signal (HVG); a low-side gate driver circuit (12b) is configured to receive the low-voltage low-side control signal (IN LS ) and generates a corresponding low-side gate control signal (LVG); wherein the high-side gate driver circuit (12a) is biased between a floating power supply pin (104) and a switch pin (102a) of the half-bridge driver circuit (HBD), and wherein the floating power supply pin (104) is coupled to the positive power supply pin (100a) via a bootstrap path, the bootstrap path comprising: a voltage regulator circuit (300), the input node of the voltage regulator circuit (300) being connected to the positive power supply pin (100a), and the output node of the voltage regulator circuit (300) being connected to the half-bridge a decoupling node (106) inside the driver circuit (HBD); and a current limiter circuit (Q1′) disposed between the decoupling node (106) and the floating power supply pin (104); a high-side switch (HS) coupled between the positive bus pin (108) of the half-bridge driver circuit (HBD) and the switch pin (102a); a low-side switch (LS) coupled between the switch pin (102a) and the ground pin (100b, 102b) of the half-bridge driver circuit (HBD); and a bootstrap capacitor (C B ), coupled between the floating power supply pin (104) and the switch pin (102a) of a half-bridge driver circuit (HBD).

[0094] A method of operating a voltage regulator circuit (300) can be summarized as comprising: receiving an input supply voltage (V Supply ; V CC ); generating a regulated output voltage (V reg ; V S ); the regulated output voltage (V reg ) and dynamic threshold (V T) are compared to generate a control signal (Reg_sw; ACT) to control the switching of the switchable transfer element (306), turning on the switchable transfer element (306) in response to the control signal being asserted, and turning off the switchable transfer element (306) in response to the control signal being de-asserted; shaping the output regulation voltage and / or the dynamic threshold at the threshold selection and shaping circuit (82; 20), suddenly increasing and then gradually decreasing the difference between the dynamic threshold (VT) and the output regulation voltage (Vreg) towards a target static value in response to the assertion of the control signal (Reg_sw), and suddenly increasing and then gradually decreasing the difference between the output regulation voltage (Vrek) and the dynamic threshold (VTs) towards the target static value in response to the control signal (Reg_sw) being de-asserted.

[0095] The various embodiments described above can be combined to provide additional embodiments. These and other changes can be made to the embodiments according to the above detailed description. Generally, in the following claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full range of equivalents to which these claims are authorized. Therefore, the claims are not limited by this disclosure.

Claims

1. A voltage regulator circuit, comprising: an input node configured to receive an input supply voltage; an output node configured to output a regulated output voltage; a switchable transfer element having a selectively conductive path disposed between the input node and the output node; a comparator circuit configured to compare the regulated output voltage to a dynamic threshold to generate a control signal to control switching of the switchable pass element, wherein assertion of the control signal causes the switchable pass element to be turned on and de-assertion of the control signal causes the switchable pass element to be turned off; as well as A threshold selection and shaping circuit configured to shape the regulated output voltage or the dynamic threshold such that: In response to assertion of the control signal, the difference between the dynamic threshold and the regulated output voltage is increased and then gradually decreased toward a target static value; as well as In response to de-assertion of the control signal, the difference between the regulated output voltage and the dynamic threshold is increased and then gradually decreased toward the target static value.

2. The voltage regulator circuit of claim 1 , wherein the threshold selection and shaping circuit comprises: a reference node configured to receive a reference voltage; a first circuit device configured to add a first fixed voltage to the reference voltage to generate an upper static threshold; a second circuit device configured to add a first variable voltage to the upper static threshold to produce an upper dynamic threshold; a third circuit device configured to subtract a second fixed voltage from the reference voltage to generate a lower static threshold; a fourth circuit device configured to subtract a second variable voltage from the lower static threshold to produce a lower dynamic threshold, wherein the first variable voltage is gradually decreased in response to assertion of the control signal, and the second variable voltage is gradually decreased in response to de-assertion of the control signal; and A switch is configured to generate the dynamic threshold received at the comparator circuit by propagating the upper dynamic threshold in response to assertion of the control signal and propagating the lower dynamic threshold in response to de-assertion of the control signal.

3. The voltage regulator circuit according to claim 2, wherein: The first circuit arrangement includes a first voltage generator coupled between the reference node and a first static node to generate the upper static threshold at the first static node, the second circuit arrangement comprising a second voltage generator and a first selectively activatable RC discharge circuit coupled in parallel between the first static node and a first dynamic node, wherein the first dynamic node is coupled to the second voltage generator in response to the control signal being de-asserted and is coupled to the first RC discharge circuit in response to the control signal being asserted to produce the upper dynamic threshold at the first dynamic node, The third circuit arrangement includes a third voltage generator coupled between the reference node and a second quiescent node to generate the lower quiescent threshold at the second quiescent node, and The fourth circuit device includes a fourth voltage generator and a second selectively activatable RC discharge circuit, which are coupled in parallel between the second static node and a second dynamic node, wherein the second dynamic node is coupled to the fourth voltage generator in response to the control signal being asserted and is coupled to the second RC discharge circuit in response to the control signal being de-asserted to produce the lower dynamic threshold at the second dynamic node.

4. The voltage regulator circuit of claim 2, wherein the threshold selection and shaping circuit comprises a current flow line between the input supply voltage and ground, and wherein: the first circuit arrangement comprising a first resistor arranged in the current flow line between the reference node and a first quiescent node in order to produce the upper quiescent threshold at the first quiescent node, the second circuit arrangement comprising a second resistor and a first bypass transistor arranged in parallel in the current flow line between the first static node and a first dynamic node, wherein a conductivity of the first bypass transistor is gradually increased in response to assertion of the control signal to produce the upper dynamic threshold at the first dynamic node, The third circuit arrangement comprises a third resistor arranged in the current flow line between the reference node and a second quiescent node so as to produce the lower quiescent threshold at the second quiescent node, and The fourth circuit device includes a fourth resistor and a second bypass transistor, the fourth resistor and the second bypass transistor are arranged in parallel in the current flow path between the second static node and a second dynamic node, wherein the conductivity of the second bypass transistor is gradually increased in response to de-assertion of the control signal to produce the lower dynamic threshold at the second dynamic node. 5 . The voltage regulator circuit of claim 4 , wherein in a steady state, the conductivity of the first bypass transistor and the conductivity of the second bypass transistor are high.

6. The voltage regulator circuit of claim 1 , wherein the threshold selection and shaping circuit comprises: a first circuit device configured to subtract a first fixed voltage from the input supply voltage to generate a static threshold; a second circuit device configured to subtract a first variable voltage from the static threshold to generate the dynamic threshold; a third circuit device configured to subtract a second fixed voltage from the regulated output voltage to generate a static comparison signal; as well as a fourth circuit device configured to subtract a second variable voltage from the static comparison signal to generate a dynamic comparison signal, wherein the first variable voltage is gradually decreased in response to de-assertion of the control signal, and the second variable voltage is gradually decreased in response to assertion of the control signal, and The comparator circuit is configured to compare the dynamic threshold with the dynamic comparison signal to generate the control signal.

7. The voltage regulator circuit according to claim 6, wherein: The first circuit arrangement includes a first diode set coupled in series to a first decoupling transistor between the input node and a first quiescent node to produce the quiescent threshold at the first quiescent node, the second circuit device comprising a first resistor and a first modulation transistor, the first resistor and the first modulation transistor being coupled in parallel between the first static node and a first dynamic node, wherein the conductivity of the first modulation transistor is gradually increased in response to a falling edge of the control signal to generate the dynamic threshold at the first dynamic node, The third circuit device includes a second diode set coupled in series to a second decoupling transistor between the output node and a second static node to generate the static comparison signal at the second static node, and The fourth circuit device includes a second resistor and a second modulation transistor, which are coupled in parallel between the second static node and a second dynamic node, wherein the conductivity of the second modulation transistor is gradually increased in response to a rising edge of the control signal to generate the comparison signal at the second dynamic node.

8. The voltage regulator circuit of claim 7 , wherein the threshold selection and shaping circuit further comprises a third resistor and a bypass transistor coupled in parallel between the first dynamic node and the input of the comparator circuit, wherein the bypass transistor is fully turned on in response to the control signal being asserted and is fully turned off in response to the control signal being de-asserted.

9. A half-bridge driver circuit, comprising: Positive power supply pin; Decoupling nodes; as well as A floating power supply pin, coupled to the positive power supply pin via a bootstrap path, comprises: A voltage regulator circuit comprising: an input node coupled to the positive supply pin and configured to receive an input supply voltage; an output node coupled to the decoupling node and configured to output a regulated output voltage; a switchable transfer element having a selectively conductive path disposed between the input node and the output node; a comparator circuit configured to compare the regulated output voltage to a dynamic threshold to generate a control signal to control switching of the switchable transfer element, wherein assertion of the control signal causes the switchable transfer element to switch on and de-assertion of the control signal causes the switchable transfer element to switch off; and A threshold selection and shaping circuit configured to shape the regulated output voltage or the dynamic threshold such that: In response to assertion of the control signal, the difference between the dynamic threshold and the regulated output voltage is increased and then gradually decreased toward a target static value; and In response to de-assertion of the control signal, the difference between the regulated output voltage and the dynamic threshold is increased and then gradually decreased toward the target static value; and A current limiter circuit is disposed between the decoupling node and the floating power supply pin.

10. The half-bridge driver circuit according to claim 9, comprising: Ground pin; a first control pin configured to receive a low voltage high side control signal for controlling a high side switch of a half bridge circuit; a second control pin configured to receive a low-voltage low-side control signal for controlling a low-side switch of the half-bridge circuit; a high-side gate driver circuit configured to receive the low voltage high-side control signal via a level shifter circuit and generate a corresponding high-side gate control signal; as well as a low-side gate driver circuit configured to receive the low-voltage low-side control signal and generate a corresponding low-side gate control signal; Wherein the high-side gate driver circuit is biased between the floating supply pin and a switch pin of the half-bridge driver circuit.

11. The half-bridge driver circuit of claim 9, wherein the threshold selection and shaping circuit comprises: a reference node configured to receive a reference voltage; a first circuit device configured to add a first fixed voltage to the reference voltage to generate an upper static threshold; a second circuit device configured to add a first variable voltage to the upper static threshold to produce an upper dynamic threshold; a third circuit device configured to subtract a second fixed voltage from the reference voltage to generate a lower static threshold; a fourth circuit device configured to subtract a second variable voltage from the lower static threshold to produce a lower dynamic threshold, wherein the first variable voltage is gradually decreased in response to assertion of the control signal, and the second variable voltage is gradually decreased in response to de-assertion of the control signal; and A switch is configured to generate the dynamic threshold received at the comparator circuit by propagating the upper dynamic threshold in response to assertion of the control signal and propagating the lower dynamic threshold in response to de-assertion of the control signal.

12. The half-bridge driver circuit according to claim 11, wherein: The first circuit arrangement includes a first voltage generator coupled between the reference node and a first static node to generate the upper static threshold at the first static node, the second circuit arrangement comprising a second voltage generator and a first selectively activatable RC discharge circuit coupled in parallel between the first static node and a first dynamic node, wherein the first dynamic node is coupled to the second voltage generator in response to the control signal being de-asserted and is coupled to the first RC discharge circuit in response to the control signal being asserted to produce the upper dynamic threshold at the first dynamic node, The third circuit arrangement includes a third voltage generator coupled between the reference node and a second quiescent node to generate the lower quiescent threshold at the second quiescent node, and The fourth circuit device includes a fourth voltage generator and a second selectively activatable RC discharge circuit, which are coupled in parallel between the second static node and a second dynamic node, wherein the second dynamic node is coupled to the fourth voltage generator in response to the control signal being asserted, and is coupled to the second RC discharge circuit in response to the control signal being de-asserted to produce the lower dynamic threshold at the second dynamic node.

13. The half-bridge driver circuit of claim 11 , wherein the threshold selection and shaping circuit comprises a current flow line between the input supply voltage and ground, and wherein: the first circuit arrangement comprising a first resistor arranged in the current flow line between the reference node and a first quiescent node in order to produce the upper quiescent threshold at the first quiescent node, the second circuit arrangement comprising a second resistor and a first bypass transistor arranged in parallel in the current flow line between the first static node and a first dynamic node, wherein a conductivity of the first bypass transistor is gradually increased in response to assertion of the control signal to produce the upper dynamic threshold at the first dynamic node, The third circuit arrangement comprises a third resistor arranged in the current flow line between the reference node and a second quiescent node so as to produce the lower quiescent threshold at the second quiescent node, and The fourth circuit device includes a fourth resistor and a second bypass transistor, which are arranged in parallel in the current flow line between the second static node and a second dynamic node, wherein the conductivity of the second bypass transistor is gradually increased in response to de-assertion of the control signal to produce the lower dynamic threshold at the second dynamic node. 14 . The half-bridge driver circuit of claim 13 , wherein in a stable state, the conductivity of the first bypass transistor and the second bypass transistor is high.

15. The half-bridge driver circuit of claim 9, wherein the threshold selection and shaping circuit comprises: a first circuit device configured to subtract a first fixed voltage from the input supply voltage to generate a static threshold; a second circuit device configured to subtract a first variable voltage from the static threshold to produce a dynamic threshold; a third circuit device configured to subtract a second fixed voltage from the regulated output voltage to generate a static comparison signal; as well as a fourth circuit device configured to subtract a second variable voltage from the static comparison signal to generate a dynamic comparison signal, wherein the first variable voltage is gradually decreased in response to de-assertion of the control signal, and the second variable voltage is gradually decreased in response to assertion of the control signal, and The comparator circuit is configured to compare the dynamic threshold with the dynamic comparison signal to generate the control signal.

16. An electronic device comprising: The half-bridge driver circuit according to claim 10; a high-side switch coupled between the positive bus pin and a switch pin of the half-bridge driver circuit; a low-side switch coupled between the switch pin and the ground pin of the half-bridge driver circuit; as well as A bootstrap capacitor is coupled between the floating power supply pin and the switch pin of the half-bridge driver circuit.

17. A method of operating a voltage regulator circuit, comprising: receiving an input supply voltage at an input node; generating a regulated output voltage at an output node; comparing the regulated output voltage to a dynamic threshold by a comparator circuit to generate a control signal that controls switching of a switchable pass element by switching the switchable pass element on in response to the control signal being asserted and switching the switchable pass element off in response to the control signal being de-asserted; as well as The threshold selection and shaping circuit shapes the regulated output voltage or the dynamic threshold by increasing and then gradually decreasing the difference between the dynamic threshold and the regulated output voltage toward a target static value in response to assertion of the control signal, and increasing and then gradually decreasing the difference between the regulated output voltage and the dynamic threshold toward the target static value in response to de-assertion of the control signal.

18. The method according to claim 17, comprising: receiving a reference voltage; adding a first fixed voltage to the reference voltage to generate an upper static threshold; adding a first variable voltage to the upper static threshold to produce an upper dynamic threshold; subtracting a second fixed voltage from the reference voltage to produce a lower static threshold; subtracting a second variable voltage from the lower static threshold to produce a lower dynamic threshold; decreasing the first variable voltage in response to assertion of the control signal or decreasing the second variable voltage in response to de-assertion of the control signal; as well as The dynamic threshold is generated by propagating the upper dynamic threshold in response to assertion of the control signal or propagating the lower dynamic threshold in response to de-assertion of the control signal.

19. The method according to claim 17, comprising: subtracting a first fixed voltage from the input supply voltage to produce a static threshold; subtracting a first variable voltage from the static threshold to produce a dynamic threshold; subtracting a second fixed voltage from the regulated output voltage to generate a static comparison signal; subtracting a second variable voltage from the static comparison signal to generate a dynamic comparison signal; gradually decreasing the first variable voltage in response to de-assertion of the control signal, or gradually decreasing the second variable voltage in response to assertion of the control signal; and The dynamic threshold is compared with the dynamic comparison signal to generate the control signal.

20. The method of claim 17, wherein the switchable transfer element has a selectively conductive channel disposed between the input node and the output node.

Images