Four-phase clock circuit
By using oscillator circuits, current mirror arrays and thermometer encoding modules in the four-phase clock circuit, the high power consumption problem caused by D flip-flops in high-frequency application scenarios is solved, and a four-phase quadrature clock signal output with low power consumption and low noise is achieved.
Patent Information
- Application Number
- CN202411933219.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-26
- Publication Date
- 2025-04-22
AI Technical Summary
In high-frequency application scenarios, when the frequency divider cascade circuit composed of D flip-flops is used in the prior art to generate orthogonal clock signals, it will lead to higher power consumption and affect the energy efficiency ratio of the system.
Using a four-phase clock circuit including an oscillator circuit, a current mirror array and a thermometer encoding module, the binary code is converted into a thermometer encoding through the thermometer encoding module, the number of openings of the current mirror array is controlled, and the total output current is adjusted to control the oscillation frequency of the oscillator circuit, thereby outputting a four-phase quadrature clock signal.
Reduces design complexity, reduces layout area, avoids noise introduced by the additional circuit and consumes additional power, and achieves a low-power, low-noise multi-channel mutually orthogonal clock output.
Smart Images
Figure CN119865129A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a four-phase clock circuit. Background Art
[0002] In the field of high-speed digital communications and integrated circuits, the generation technology of orthogonal clock signals is crucial. Orthogonal clock signals refer to clocks with four phases and are widely used in many application scenarios such as Ethernet switches / routers, broadcast video / audio timing, processor and FPGA clocks, arbitrary frequency clock conversion, fiber channel, and telecommunication line cards.
[0003] In the prior art, there are two main methods for generating orthogonal clock signals: one is to combine an oscillator and an active multiphase filter, and any differential clock signal can be processed by an active multiphase filter to generate the required 90° phase shift, thereby outputting an orthogonal clock signal. The advantage of this method is its wide applicability, which does not limit the type of oscillator and can be used with a variety of oscillators; the other is to combine an oscillator and a frequency divider. This method uses a high-frequency clock input and a frequency divider cascade circuit composed of a D flip-flop to generate a four-phase clock signal of 0°, 90°, 180°, and 270°. The advantage of this method is that it is simple in design and easy to implement, and is particularly suitable for high-frequency applications. However, in high-frequency application scenarios, the D flip-flop needs to be switched frequently, which will result in higher power consumption, which may affect the energy efficiency ratio of the system. Summary of the invention
[0004] The invention provides a four-phase clock circuit to realize output of low-power, low-noise, multi-channel mutually orthogonal clocks.
[0005] According to one aspect of the present invention, there is provided a four-phase clock circuit, comprising an oscillator circuit, a current mirror array and a thermometer encoding module;
[0006] The thermometer encoding module is connected to the current mirror array, and the thermometer encoding module is used to convert the binary code into the thermometer code;
[0007] The current mirror array is used to control the number of current mirrors turned on according to the thermometer code, and adjust the total output current to control the oscillation frequency of the oscillator circuit;
[0008] The oscillator circuit is used for outputting a clock signal.
[0009] Optionally, the oscillator circuit includes two delay units, the two delay units are connected via a differential connection, control ends of the two delay units are connected together, and are jointly controlled by the current mirror array.
[0010] Optionally, the first delay unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;
[0011] The first electrode of the first transistor is connected to the output current of the current mirror array, the second electrode of the first transistor is connected to the second electrode of the third transistor, the gate of the first transistor and the gate of the third transistor are connected to the first negative input terminal of the oscillator circuit, and the first electrode of the third transistor is grounded; the first electrode of the second transistor is connected to the output current of the current mirror array, the second electrode of the second transistor is connected to the second electrode of the fourth transistor, the gate of the second transistor and the gate of the fourth transistor are connected to the first positive input terminal of the oscillator circuit, and the first electrode of the fourth transistor is grounded;
[0012] The first electrode of the fifth transistor is connected to the output current of the current mirror array, the gate of the fifth transistor is connected to the second electrode of the second transistor, the second electrode of the fourth transistor, the second electrode of the sixth transistor and the first negative output terminal of the oscillator circuit, and the second electrode of the fifth transistor is connected to the first positive output terminal of the oscillator circuit; the first electrode of the sixth transistor is connected to the output current of the current mirror array, the gate of the sixth transistor is connected to the second electrode of the first transistor, the second electrode of the third transistor, the second electrode of the fifth transistor and the first positive output terminal of the oscillator circuit, and the second electrode of the sixth transistor is connected to the first negative output terminal of the oscillator circuit.
[0013] Optionally, the second delay unit includes: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor;
[0014] The first electrode of the seventh transistor is connected to the output current of the current mirror array, the second electrode of the seventh transistor is connected to the second electrode of the ninth transistor, the gate of the seventh transistor and the gate of the ninth transistor are connected to the second negative input terminal of the oscillator circuit, and the first electrode of the ninth transistor is grounded; the first electrode of the eighth transistor is connected to the output current of the current mirror array, the second electrode of the eighth transistor is connected to the second electrode of the tenth transistor, the gate of the eighth transistor and the gate of the tenth transistor are connected to the second positive input terminal of the oscillator circuit, and the first electrode of the tenth transistor is grounded;
[0015] The first electrode of the eleventh transistor is connected to the output current of the current mirror array, the gate of the eleventh transistor is connected to the second electrode of the eighth transistor, the second electrode of the tenth transistor, the second electrode of the twelfth transistor and the second negative output terminal of the oscillator circuit, and the second electrode of the eleventh transistor is connected to the second positive output terminal of the oscillator circuit; the first electrode of the twelfth transistor is connected to the output current of the current mirror array, the gate of the twelfth transistor is connected to the second electrode of the seventh transistor, the second electrode of the ninth transistor, the second electrode of the eleventh transistor and the second positive output terminal of the oscillator circuit, and the second electrode of the twelfth transistor is connected to the second negative output terminal of the oscillator circuit.
[0016] Optionally, the fifth transistor, the sixth transistor, the eleventh transistor and the twelfth transistor have consistent characteristics; the first transistor, the second transistor, the seventh transistor and the eighth transistor have consistent characteristics; the third transistor, the fourth transistor, the ninth transistor and the tenth transistor have consistent characteristics.
[0017] Optionally, the fifth transistor, the first transistor and the third transistor satisfy a positive feedback condition:
[0018] g ml (r o1 / / r o2 )≥1;
[0019] Among them, g ml is the transconductance of the fifth transistor, r o1 , r o2 is the on-resistance of the first transistor and the third transistor.
[0020] Optionally, the thermometer encoding module includes logic units arranged in multiple rows and columns, and the logic units include AND gates and NOR gates; the first input end of the AND gate inputs the current row number of the row and column code, the second input end of the AND gate inputs the current column number of the row and column code, the output end of the AND gate inputs the first input end of the NOR gate, the second input end of the NOR gate inputs the next row of the current row number of the row and column code, and the output of the NOR gate controls the conduction or disconnection of the switch of the current mirror array.
[0021] Optionally, the thermometer encoding logic is:
[0022]
[0023] Among them, Row is the current row number of the row and column code, Col is the current column number of the row and column code, Row_next is the next row of the current row number of the row and column code, and Thermal_code is the output thermometer code.
[0024] Optionally, the thermometer encoding module is used to use SPI to convert the serial input binary code into a row and column code, and to open the current mirror in the current mirror array by row and column selection; when the row and column code converted by the binary input signal changes by one bit, one and only one logic unit in the current mirror array is selected.
[0025] Optionally, the current mirror array includes multiple current sources and multiple switches corresponding to the current sources, and the current mirror array is used to control the number of current mirrors turned on according to the thermometer code, adjust the total output current, and control the oscillation frequency of the oscillator circuit.
[0026] The technical solution of the embodiment of the present invention uses an oscillator circuit, a current mirror array and a thermometer encoding module, and uses a thermometer encoding module to convert binary code into thermometer code to control the switch of the current mirror array. Each turned-on current mirror will output the same current. When the number of turned-on current mirrors changes, the total output current will also change accordingly. The total output current is input into the oscillator circuit, and the total current passing through the oscillator can be adjusted to achieve control of the oscillation frequency, thereby outputting a four-phase orthogonal clock signal. The technical solution of the present invention reduces the design complexity, reduces the layout area, and avoids the noise introduced by the additional circuit and the consumption of additional power consumption.
[0027] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0029] Figure 1 is a schematic structural diagram of a four-phase clock circuit provided according to an embodiment of the present invention;
[0030] Figure 2 is a circuit schematic diagram of a first delay unit provided according to an embodiment of the present invention;
[0031] Figure 3 is a circuit schematic diagram of a second delay unit provided according to an embodiment of the present invention;
[0032] Figure 4 is a schematic diagram of the structure of a thermometer encoding module provided according to an embodiment of the present invention;
[0033] Figure 5 is a schematic diagram of a thermometer encoding logic truth table provided according to an embodiment of the present invention;
[0034] Figure 6 is a schematic structural diagram of a current mirror array provided according to an embodiment of the present invention;
[0035] Figure 7 4 is a circuit schematic diagram of a four-phase clock circuit provided according to an embodiment of the present invention. DETAILED DESCRIPTION
[0036] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.
[0037] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0038] Figure 1 The present invention provides a schematic diagram of the structure of a four-phase clock circuit. This embodiment can be applied to low-power application scenarios such as passive Internet of Things and low-power Bluetooth, and the frequency mixing, modulation, and demodulation of signals. The circuit can be configured in industrial control systems and integrated circuits. Figure 1 As shown, the circuit includes: an oscillator circuit 101, a current mirror array 102 and a thermometer encoding module 103;
[0039] The thermometer encoding module 103 is connected to the current mirror array 102, and the thermometer encoding module 103 is used to convert the binary code into the thermometer code; the current mirror array 102 is used to control the number of current mirrors turned on according to the thermometer code, and adjust the total output current to control the oscillation frequency of the oscillator circuit 101; the oscillator circuit 101 is used to output a clock signal.
[0040] Among them, the oscillator circuit 101 is a circuit that can generate a stable and continuous periodic signal, and can realize the self-excitation of the signal through positive feedback, so that it can continuously change at a certain frequency. The oscillator circuit 101 can be a two-stage ring oscillator, which can directly output an orthogonal four-phase clock, which not only reduces the design complexity and reduces the layout area, but also avoids the noise introduced by the additional circuit and consumes additional power. At the same time, a buffer stage can be set after the ring oscillator, and the buffer stage can enhance the oscillator driving ability. The ring oscillator structure of the ring oscillator can output a larger swing, which can avoid the swing being too small to cause the subsequent buffer stage (buffer) to work in the intermediate state and cannot be detected, and can simplify the design of the subsequent buffer. The current mirror array 102 can be used to copy or mirror a reference current to one or more output terminals. The current mirror array 102 may include multiple current mirrors and multiple switches, and the current source is usually composed of a current mirror. The current mirror can copy the reference current through a transistor, such as a PMOS transistor. If the transistors have the same size, the same gate-source voltage, and all work in the saturation region, they will conduct the same current, thereby realizing the "mirror" of the current. The thermometer encoding module 103 is an encoding method used in a digital-to-analog converter, which can convert a digital signal into an analog signal. The thermometer encoding module 103 is a linear encoding, and the thermometer encoding module 103 can convert binary into thermometer encoding. Since there are many current mirrors in the current mirror array 102, if the switch of each current mirror is led out separately, it will cause too many ports. The thermometer encoding module 103 converts the binary code into the thermometer code to control the number of current mirrors in the current mirror array 102 to be turned on. The number of transistors turned on can refer to the number of transistors turned on in the current mirror array 102. When the number of current mirrors turned on changes, each turned-on current mirror will output the same current, and the total current is the sum of the output currents of all turned-on current mirrors. Therefore, the total current output will also change accordingly. After the total current output by the current mirror array 102 is input to the oscillator circuit 101, the oscillation frequency of the oscillator circuit 101 can be adjusted by changing the current in the circuit. The total current passing through the oscillator circuit 101 can be adjusted to control the oscillation frequency, thereby outputting a four-phase orthogonal clock signal.
[0041] The technical solution of the embodiment of the present invention uses an oscillator circuit, a current mirror array and a thermometer encoding module, and uses a thermometer encoding module to convert binary code into thermometer code to control the switch of the current mirror array. Each turned-on current mirror will output the same current. When the number of turned-on current mirrors changes, the total output current will also change accordingly. The total output current is input into the oscillator circuit, and the total current passing through the oscillator can be adjusted to achieve control of the oscillation frequency, thereby outputting a four-phase orthogonal clock signal. The technical solution of the present invention reduces the design complexity, reduces the layout area, and avoids the noise introduced by the additional circuit and the consumption of additional power consumption.
[0042] In some optional embodiments of the present invention, the oscillator circuit may include two delay units, the two delay units are connected via a differential connection, and the control ends of the two delay units are connected together and are controlled together via a current mirror array.
[0043] Among them, the delay unit can generate an output signal after a certain time delay after the arrival of the input signal, and provide a certain signal gain to ensure that the two-stage structure forms positive feedback to complete the oscillation, which is manifested as a certain delay from the input signal to the output signal in the time domain, and this delay time is 1 / 4 of the waveform period. Differential connection means that the output signals of the two delay units exist in differential form. The differential connection of the delay unit can improve the circuit's anti-noise ability, and by controlling the delay, the phase noise of the circuit can be reduced. The control ends of the two delay units are connected together, and the two delay units are subject to the same control signal. The control signal can be from a current mirror array, or it can be the output current of the current mirror array.
[0044] Figure 2 is a schematic diagram of the structure of a first delay unit provided according to an embodiment of the present invention. In some optional embodiments of the present invention, Figure 2 As shown, the first delay unit includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6;
[0045] The first electrode of the first transistor M1 is connected to the output current of the current mirror array, the second electrode of the first transistor M1 is connected to the second electrode of the third transistor M3, the gate of the first transistor M1 and the gate of the third transistor M3 are connected to the first negative input terminal Vin1 of the oscillator circuit, and the first electrode of the third transistor M3 is grounded; the first electrode of the second transistor M2 is connected to the output current of the current mirror array, the second electrode of the second transistor M2 is connected to the second electrode of the fourth transistor M4, the gate of the second transistor M2 and the gate of the fourth transistor M4 are connected to the first positive input terminal Vip1 of the oscillator circuit, and the first electrode of the fourth transistor M4 is grounded;
[0046] A first electrode of the fifth transistor M5 is connected to the output current of the current mirror array, a gate of the fifth transistor M5 is connected to the second electrode of the second transistor M2, the second electrode of the fourth transistor M4, the second electrode of the sixth transistor M6 and the first negative output terminal Von1 of the oscillator circuit, and a second electrode of the fifth transistor M5 is connected to the first positive output terminal Vop1 of the oscillator circuit; a first electrode of the sixth transistor M6 is connected to the output current of the current mirror array, a gate of the sixth transistor M6 is connected to the second electrode of the first transistor M1, the second electrode of the third transistor M3, the second electrode of the fifth transistor M5 and the first positive output terminal Vop1 of the oscillator circuit, and a second electrode of the sixth transistor M6 is connected to the first negative output terminal Von1 of the oscillator circuit.
[0047] Among them, the first electrode of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 can be a source electrode, and the second electrode can be a drain electrode. The first transistor M1, the second transistor M2, the fifth transistor M5, and the sixth transistor M6 can be PMOS tubes, the third transistor M3 and the fourth transistor M4 can be NMOS tubes, and the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are PMOS and NMOS input transconductance stages. The PMOS and NMOS input transconductance stages refer to the input of the oscillator circuit constructed using PMOS and NMOS transistors in the analog integrated circuit design, which can provide high gain and effectively suppress common-mode signal interference. The fifth transistor M5 and the sixth transistor M6 cross each other to form a PMOS cross-coupled load, the gate of the fifth transistor M5 is connected to the drain of the second transistor M2, the drain of the fourth transistor M4, and the drain of the sixth transistor M6, and the gate of the sixth transistor M6 is connected to the drain of the first transistor M1, the drain of the third transistor M3, and the drain of the fifth transistor M5, forming a differential structure. Two delay units of the same structure and size are connected differentially to form a positive feedback loop. The cross-coupling structure enables the oscillator to have anti-interference performance and high gain characteristics. The differential design can reduce the noise injected by the power supply. In addition, the source electrodes of the first transistor M1, the second transistor M2, the fifth transistor M5, and the sixth transistor M6 are all connected to the output current of the current mirror array. Since the current mirror of the current mirror array includes transistors, its drain-source voltage is relatively stable, which can suppress the noise from the power supply to a certain extent.
[0048] Figure 3 is a schematic diagram of the structure of a second delay unit provided according to an embodiment of the present invention. In some optional embodiments of the present invention, Figure 3 The second delay unit shown includes: a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12;
[0049] The first electrode of the seventh transistor M7 is connected to the output current of the current mirror array, the second electrode of the seventh transistor M7 is connected to the second electrode of the ninth transistor M9, the gate of the seventh transistor M7 and the gate of the ninth transistor M9 are connected to the second negative input terminal Vin2 of the oscillator circuit, and the first electrode of the ninth transistor M9 is grounded; the first electrode of the eighth transistor M8 is connected to the output current of the current mirror array, the second electrode of the eighth transistor M8 is connected to the second electrode of the tenth transistor M10, the gate of the eighth transistor M8 and the gate of the tenth transistor M10 are connected to the second positive input terminal Vip2 of the oscillator circuit, and the first electrode of the tenth transistor M10 is grounded;
[0050] The first electrode of the eleventh transistor M11 is connected to the output current of the current mirror array, the gate of the eleventh transistor M11 is connected to the second electrode of the eighth transistor M8, the second electrode of the tenth transistor M10, the second electrode of the twelfth transistor M12 and the second negative output terminal Von2 of the oscillator circuit, and the second electrode of the eleventh transistor M11 is connected to the second positive output terminal Vop2 of the oscillator circuit; the first electrode of the twelfth transistor M12 is connected to the output current of the current mirror array, the gate of the twelfth transistor M12 is connected to the second electrode of the seventh transistor M7, the second electrode of the ninth transistor M9, the second electrode of the eleventh transistor M11 and the second positive output terminal Vop2 of the oscillator circuit, and the second electrode of the twelfth transistor M12 is connected to the second negative output terminal Von2 of the oscillator circuit.
[0051] Among them, the first electrode of the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11 and the twelfth transistor M12 can be a source electrode, and the second electrode can be a drain electrode. The seventh transistor M7, the eighth transistor M8, the eleventh transistor M11 and the twelfth transistor M12 can be PMOS transistors, the ninth transistor M9 and the tenth transistor M10 can be NMOS transistors, and the seventh transistor M7, the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10 are PMOS and NMOS input transconductance stages. The eleventh transistor M11 and the twelfth transistor M12 cross each other to form a PMOS cross-coupled load, the gate of the eleventh transistor M11 is connected to the drain of the eighth transistor M8, the drain of the tenth transistor M10 and the drain of the twelfth transistor M12, and the gate of the twelfth transistor M12 is connected to the drain of the seventh transistor M7, the drain of the ninth transistor M9 and the drain of the eleventh transistor M11, forming a differential structure. Two delay units of the same structure and size form a positive feedback loop through differential connection. The cross-coupling structure enables the oscillator to have anti-interference performance and high gain characteristics. The differential design can reduce the noise injected by the power supply. In addition, the sources of the seventh transistor M7, the eighth transistor M8, the eleventh transistor M11 and the twelfth transistor M12 are all connected to the output current of the current mirror array. Since the current mirror of the current mirror array includes transistors, its drain-source voltage is relatively stable, which can suppress the noise from the power supply to a certain extent. The oscillator circuit consists of two delay units, adopting an even-numbered structure, and when connected, one side is connected to the same phase end and the other end is connected to the reverse end.
[0052] In some optional embodiments of the present invention, reference Figure 2 and Figure 3 The fifth transistor M5, the sixth transistor M6, the eleventh transistor M11 and the twelfth transistor M12 have consistent characteristics; the first transistor M1, the second transistor M2, the seventh transistor M7 and the eighth transistor M8 have consistent characteristics; the third transistor M3, the fourth transistor M4, the ninth transistor M9 and the tenth transistor M10 have consistent characteristics.
[0053] Among them, the consistency of transistor characteristics means that their electrical parameters have small deviations, including threshold voltage, maximum leakage current, transconductance, carrier mobility and other parameters.
[0054] In some optional embodiments of the present invention, reference Figure 2 and Figure 3 , the fifth transistor M5, the first transistor M1 and the third transistor M3 meet the positive feedback condition:
[0055] g ml (r o1 / / r o2 )≥1;
[0056] Among them, g ml is the transconductance of the fifth transistor M5, r o1 , r o2 is the on-resistance of the first transistor M1 and the third transistor M3.
[0057] Specifically, the fifth transistor M5 meets the positive feedback condition with the first transistor M1 and the third transistor M3. The fifth transistor M5, the sixth transistor M6, the eleventh transistor M11 and the twelfth transistor M12 have the same characteristics; the first transistor M1, the second transistor M2, the seventh transistor M7 and the eighth transistor M8 have the same characteristics; the third transistor M3, the fourth transistor M4, the ninth transistor M9 and the tenth transistor M10 have the same characteristics. Then the transistors with the same corresponding characteristics also meet the positive feedback condition. It can ensure that the oscillator can start.
[0058] Figure 4 is a schematic diagram of the structure of a thermometer encoding module provided according to an embodiment of the present invention. In some optional embodiments of the present invention, for example Figure 4 As shown, the thermometer encoding module includes logic units arranged in multiple rows and columns, and the logic units include an AND gate AND1 and a NOR gate NAND1; the first input end of the AND gate AND1 inputs the current row number Row of the row and column code, the second input end of the AND gate inputs the current column number Col of the row and column code, the output end of the AND gate inputs the first input end of the NOR gate, the second input end of the NOR gate inputs the next row Row_next of the current row number of the row and column code, and the output of the NOR gate controls the conduction or disconnection of the switch of the current mirror array.
[0059] Among them, the thermometer code is a linear code. As the control word increases, the control amount changes the same each time. The thermometer code can control the current mirror switch. The thermometer code is 1, the current mirror is turned on, and OTW is in binary code form, where 01 represents binary 1 and 10 represents binary 2. The high two bits of binary Hig 2Bits: 01 are converted into rows of row and column codes, and the low two bits of binary Low 2Bits: 10 are converted into columns of row and column codes. The row and column codes are converted into thermometer codes according to the encoding logic of the thermometer encoding module.
[0060] Figure 5 is a schematic diagram of a thermometer encoding logic truth table provided according to an embodiment of the present invention. In some optional embodiments of the present invention, the thermometer encoding logic is:
[0061]
[0062] Among them, Row is the current row number of the row and column code, Col is the current column number of the row and column code, Row_next is the next row of the current row number of the row and column code, and Thermal_code is the output thermometer code.
[0063] Specifically, the thermometer encoding module can output the corresponding thermometer code according to the thermometer encoding logic truth table, such as Figure 5 As shown, when the current row number Row of the row and column code is 0 and the current column number Col of the row and column code is 0, if the next row Row_next of the current row number of the row and column code is 0, the output thermometer code Thermal_code is 1; if the next row Row_next of the current row number of the row and column code is 1, the output thermometer code Thermal_code does not exist. When the current row number Row of the row and column code is 0 and the current column number Col of the row and column code is 1, if the next row Row_next of the current row number of the row and column code is 0, the output thermometer code Thermal_code is 1; if the next row Row_next of the current row number of the row and column code is 1, the output thermometer code Thermal_code does not exist. When the current row number Row of the row and column code is 1 and the current column number Col of the row and column code is 0, if the next row Row_next of the current row number of the row and column code is 0, the output thermometer code Thermal_code is 1; if the next row Row_next of the current row number of the row and column code is 1, the output thermometer code Thermal_code is 0. When the current row number Row of the row and column code is 1 and the current column number Col of the row and column code is 1, if the next row Row_next of the current row number of the row and column code is 0, the output thermometer code Thermal_code is 0; if the next row Row_next of the current row number of the row and column code is 1, the output thermometer code Thermal_code is 0.
[0064] In some optional embodiments of the present invention, the thermometer encoding module is used to use SPI to convert the serial input binary code into a row and column code, and turn on the current mirror in the current mirror array by row and column selection; when the row and column code converted by the binary input signal changes by one bit, one and only one logic unit in the current mirror array is selected.
[0065] Among them, the thermometer encoding module represents the digital signal in thermometer code, in which the change of each digital bit only affects the state of one bit. In thermometer coding, the increase or decrease of each bit will only cause the change of one bit. Serial input binary code means that the data is input in a serial manner, that is, the data is transmitted one by one in sequence bit by bit. Binary code means that the data is represented in binary form. SPI is a serial communication protocol used for short-distance communication between microcontrollers and other digital devices. Row and column code is a parallel data representation method in which data is organized into rows and columns. The thermometer encoding module is used to receive serial binary data through the SPI interface and convert it into row and column code, and then further convert the row and column code into thermometer code. The current mirror of each row can be controlled by selecting a specific row signal to control whether it is turned on, thereby realizing the control of current. In the current mirror array of thermometer coding, when the input signal changes by one bit, only one corresponding current mirror will be activated to output current. Each change of the thermometer code only affects the state of one logic unit, and one and only one unit in the current mirror array is selected.
[0066] Figure 6 is a schematic diagram of the structure of a current mirror array provided according to an embodiment of the present invention. In some optional embodiments of the present invention, Figure 6 As shown, the current mirror array includes multiple current sources I1 and multiple switches S1 corresponding to the current sources. The current mirror array is used to control the number of current mirrors turned on according to the thermometer code, adjust the total output current, and control the oscillation frequency of the oscillator circuit.
[0067] Among them, in the current mirror array, the current source I1 is usually composed of a current mirror, and the current mirror can copy the reference current through a transistor. It can be a PMOS current mirror. The PMOS current mirror passes through multiple PMOS transistors of equal size. When they have the same gate-source voltage, their leakage current is also the same, thereby realizing the "mirror" of the current. The current mirror array includes multiple current sources I1 and multiple switches S1 corresponding to the current sources. Each current mirror array is placed together with its corresponding decoding circuit and the switch controlling the current mirror unit to ensure that the delay time from the digital control signal to each current mirror is the same. The switch S1 of the current source I1 can be controlled according to the thermometer code, and the corresponding current source I1 is turned on according to the conduction of the switch S1, and the total output current Ip is adjusted to control the oscillation frequency of the oscillator circuit. Iconstant represents the current when the oscillator operates at the lowest oscillation frequency, ensuring that when the thermometer code is 0, the oscillator still operates at the lowest frequency required by the system.
[0068] Figure 7 1 is a circuit schematic diagram of a four-phase clock circuit provided according to an embodiment of the present invention. Figure 7As shown, the working principle of the four-phase clock circuit is as follows: the input binary code is converted into a thermometer code through the thermometer encoding module 201, the number of current mirrors turned on in the current mirror array 202 is controlled according to the thermometer code, the switch S1 of the current source I1 is controlled, the corresponding current source I1 is turned on according to the conduction of the switch S1, the total current Ip output is adjusted, and the total current Ip is input to the oscillator circuit 203, the oscillator circuit 203 is a two-stage ring oscillator, each oscillator is composed of a delay unit, and the delay unit adopts a differential cross-coupling structure. The total current passing through the oscillator can be adjusted to achieve control of the oscillation frequency, thereby outputting a four-phase orthogonal clock signal. Among them, Coarse represents the unit current of the coarse adjustment control array. Medium represents the unit current of the medium adjustment control array. Fine represents the unit current of the fine adjustment control array. Iconstant represents the current when the oscillator works at the lowest oscillation frequency. It is ensured that when the control code is 0, the oscillator still works at the lowest frequency required by the system. Vip1 represents the first positive input terminal of the oscillator circuit, Vin1 represents the first negative input terminal of the oscillator circuit 203, Vop1 represents the first positive output terminal of the oscillator circuit 203, Von1 represents the first negative output terminal of the oscillator circuit 203, Vip2 represents the second positive input terminal of the oscillator circuit 203, Vin2 represents the second negative input terminal of the oscillator circuit 203, Vop2 represents the second positive output terminal of the oscillator circuit 203, and Von2 represents the second negative output terminal of the oscillator circuit 203.
[0069] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.
[0070] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims
1. A four-phase clock circuit, characterized in that: including an oscillator circuit, a current mirror array, and a thermometer encoding module; The thermometer encoding module is connected to the current mirror array, and the thermometer encoding module is used to convert the binary code into the thermometer code; The current mirror array is used to control the number of current mirrors turned on according to the thermometer code, and adjust the total output current to control the oscillation frequency of the oscillator circuit; The oscillator circuit is used for outputting a clock signal.
2. The circuit according to claim 1, characterized in that The oscillator circuit includes two delay units, the two delay units are connected via a differential connection, the control ends of the two delay units are connected together, and are controlled together through the current mirror array.
3. The circuit according to claim 2, characterized in that The first delay unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; The first electrode of the first transistor is connected to the output current of the current mirror array, the second electrode of the first transistor is connected to the second electrode of the third transistor, the gate of the first transistor and the gate of the third transistor are connected to the first negative input terminal of the oscillator circuit, and the first electrode of the third transistor is grounded; the first electrode of the second transistor is connected to the output current of the current mirror array, the second electrode of the second transistor is connected to the second electrode of the fourth transistor, the gate of the second transistor and the gate of the fourth transistor are connected to the first positive input terminal of the oscillator circuit, and the first electrode of the fourth transistor is grounded; The first electrode of the fifth transistor is connected to the output current of the current mirror array, the gate of the fifth transistor is connected to the second electrode of the second transistor, the second electrode of the fourth transistor, the second electrode of the sixth transistor and the first negative output terminal of the oscillator circuit, and the second electrode of the fifth transistor is connected to the first positive output terminal of the oscillator circuit; the first electrode of the sixth transistor is connected to the output current of the current mirror array, the gate of the sixth transistor is connected to the second electrode of the first transistor, the second electrode of the third transistor, the second electrode of the fifth transistor and the first positive output terminal of the oscillator circuit, and the second electrode of the sixth transistor is connected to the first negative output terminal of the oscillator circuit.
4. The circuit according to claim 3, characterized in that The second delay unit includes: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; The first electrode of the seventh transistor is connected to the output current of the current mirror array, the second electrode of the seventh transistor is connected to the second electrode of the ninth transistor, the gate of the seventh transistor and the gate of the ninth transistor are connected to the second negative input terminal of the oscillator circuit, and the first electrode of the ninth transistor is grounded; the first electrode of the eighth transistor is connected to the output current of the current mirror array, the second electrode of the eighth transistor is connected to the second electrode of the tenth transistor, the gate of the eighth transistor and the gate of the tenth transistor are connected to the second positive input terminal of the oscillator circuit, and the first electrode of the tenth transistor is grounded; The first electrode of the eleventh transistor is connected to the output current of the current mirror array, the gate of the eleventh transistor is connected to the second electrode of the eighth transistor, the second electrode of the tenth transistor, the second electrode of the twelfth transistor and the second negative output terminal of the oscillator circuit, and the second electrode of the eleventh transistor is connected to the second positive output terminal of the oscillator circuit; the first electrode of the twelfth transistor is connected to the output current of the current mirror array, the gate of the twelfth transistor is connected to the second electrode of the seventh transistor, the second electrode of the ninth transistor, the second electrode of the eleventh transistor and the second positive output terminal of the oscillator circuit, and the second electrode of the twelfth transistor is connected to the second negative output terminal of the oscillator circuit.
5. The circuit according to any one of claims 3 to 4, characterized in that: The fifth transistor, the sixth transistor, the eleventh transistor and the twelfth transistor have consistent characteristics; the first transistor, the second transistor, the seventh transistor and the eighth transistor have consistent characteristics; the third transistor, the fourth transistor, the ninth transistor and the tenth transistor have consistent characteristics.
6. The circuit according to claim 5, characterized in that The fifth transistor, the first transistor and the third transistor satisfy a positive feedback condition: g ml (r o1 / / r o2 )≥1； Among them, g ml is the transconductance of the fifth transistor, r o1 , r o2 is the on-resistance of the first transistor and the third transistor.
7. The circuit according to claim 1, characterized in that The thermometer encoding module includes logic units arranged in multiple rows and columns, and the logic units include AND gates and NOR gates; the first input end of the AND gate inputs the current row number of the row and column code, the second input end of the AND gate inputs the current column number of the row and column code, the output end of the AND gate inputs the first input end of the NOR gate, the second input end of the NOR gate inputs the next row of the current row number of the row and column code, and the output of the NOR gate controls the conduction or disconnection of the switch of the current mirror array.
8. The circuit according to claim 7, characterized in that Thermometer coding logic is: Among them, Row is the current row number of the row and column code, Col is the current column number of the row and column code, Row_next is the next row of the current row number of the row and column code, and Thermal_code is the output thermometer code.
9. The circuit according to any one of claims 1 to 8, characterized in that: The thermometer encoding module is used to convert the serial input binary code into row and column codes using SPI, and turn on the current mirrors in the current mirror array by row and column selection; when the row and column codes converted by the binary input signal change by one bit, one and only one logic unit in the current mirror array is selected.
10. The circuit according to any one of claims 1 to 8, characterized in that: The current mirror array includes a plurality of current sources and a plurality of switches corresponding to the current sources. The current mirror array is used to control the number of current mirrors turned on according to the thermometer code, and adjust the total output current to control the oscillation frequency of the oscillator circuit.