Clock generation circuit based on receiver signal

Abstract

The invention relates to the technical field of electronic circuits, and discloses a clock generation circuit based on receiver signals. The circuit comprises an edge detection circuit, a latch, a time-delay circuit, an output logic and a state controller, the edge detection circuit is used for detecting edge jump of a marking signal in a receiver output signal and generating a pulse signal, the latch responds to the pulse signal to carry out state overturning and keeping, the time-delay circuit carries out time-delay processing on a latch signal, and the output logic is connected with the state controller. The output logic generates a reference clock with a fixed duty ratio according to the latch signal and the delay signal, and the state controller is responsible for managing the working state and the reset time sequence of the circuit. The clock is recovered by detecting the mark signal in the data stream, a traditional high-frequency phase discriminator does not need to be used, the method has the advantages of being low in power consumption and low in jitter, and the duty ratio of the clock can be flexibly adjusted according to actual requirements.

Description

Technical Field

[0001] The present application relates to the field of electronic circuit technology, and in particular to a clock recovery circuit technology based on data signal characteristics. Background Art

[0002] In modern electronic systems, the receiver circuit needs to recover the clock signal from the received data signal to achieve correct data sampling and synchronous processing. At present, the mainstream clock recovery scheme generally adopts the phase-locked loop structure, and its core component is the high-frequency phase detector. Although this scheme is widely used, there are some technical problems that need to be solved urgently.

[0003] First, the traditional clock recovery circuit relies on a high-frequency phase detector to detect the phase difference and make corrections, which requires the devices in the circuit to operate at a higher frequency. The use of high-speed devices not only pushes up the overall power consumption of the circuit, but also increases the difficulty of design and manufacturing. Especially in some power-sensitive portable devices and low-power application scenarios, this high power consumption characteristic becomes a serious limiting factor.

[0004] Secondly, in the actual data transmission process, the received data signal often contains a large number of jumps. Traditional clock recovery circuits will continuously respond to and adjust these jumps. This frequent phase correction easily introduces additional clock jitter. Excessive clock jitter not only affects the accuracy of data sampling, but may also cause system performance degradation, which is particularly prominent in high-speed data transmission applications.

[0005] Third, existing clock recovery circuits generally lack flexible configuration capabilities. In different application scenarios, the system may require clock signals with different duty cycles, but traditional circuits are difficult to achieve such flexible adjustments. At the same time, due to the complex circuit structure, modifying or optimizing clock characteristics often requires major design changes, which limits the practicality and adaptability of the circuit.

[0006] In addition, during the transmission of continuous data frames, the existing clock recovery circuit lacks an effective state management mechanism, which makes it difficult for the circuit to accurately identify the start and end times of data transmission, and cannot perform state switching and reset in time, affecting the reliability and stability of the circuit in practical applications.

[0007] Therefore, it is urgent to develop a new clock recovery solution that can reduce circuit power consumption, ensure the quality of the clock signal, and have flexible configuration capabilities and reliable state management mechanisms. This is of great significance to improving the overall performance of electronic systems. Summary of the invention

[0008] The purpose of the present application is to provide a clock generation circuit based on a receiver signal to solve the problems raised in the above background technology.

[0009] The present application discloses a clock generation circuit based on a receiver signal, comprising an edge detection circuit, a latch, a delay circuit, an output logic circuit and a state controller, wherein:

[0010] The edge detection circuit is used to receive and detect the edge jump of the marker signal in the receiver output signal, and generate a pulse signal indicating the edge jump;

[0011] The input end of the latch is connected to the output end of the edge detection circuit, and is used to respond to the pulse signal to flip and maintain the state, thereby generating a latch signal;

[0012] The input end of the delay circuit is connected to the output end of the latch, and is used to output a delayed latch signal after delaying the latch signal for a preset time;

[0013] The first input terminal of the output logic circuit is connected to the output terminal of the latch, and the second input terminal is connected to the output terminal of the delay circuit, and is used to generate a reference clock signal with a fixed duty cycle according to the rising edge of the latch signal and the rising edge of the delayed latch signal;

[0014] The state controller is used to generate a reset signal when the delayed latch signal is at a high level and the data transmission indication signal is at a low level. The output end of the reset signal is respectively connected to the latch and the delay circuit, and is used to control the latch and the delay circuit to reset.

[0015] In a preferred example, the edge detection circuit includes a first delay unit, an XOR gate and an AND gate, wherein: the input end of the first delay unit and the first input end of the XOR gate are both used to receive the receiver output signal, and the output end of the first delay unit is connected to the second input end of the XOR gate; the first input end of the AND gate is connected to the output end of the XOR gate, the second input end is used to receive the receiver output signal, and the output end is used to output the pulse signal.

[0016] In a preferred example, the latch includes a trigger end, a reset end and an output end, wherein: the trigger end is connected to the output end of the edge detection circuit for receiving the pulse signal; the reset end is connected to the output end of the state controller for receiving the reset signal; the output end is used to output the latch signal, and the latch only responds to the edge transition of the flag signal once during each frame of data transmission.

[0017] In a preferred example, the delay circuit includes: a first trigger and a second trigger, the data input end of the first trigger is connected to the output end of the latch, the data input end of the second trigger is connected to the output end of the first trigger, and the output end of the second trigger is used to output the delayed latch signal; wherein the clock input ends of the first trigger and the second trigger are both used to receive the system clock signal, and the reset ends are both used to receive the reset signal.

[0018] In a preferred example, the frequency of the system clock signal is higher than the frequency of the reference clock signal.

[0019] In a preferred example, another implementation of the delay circuit includes: a resistor and capacitor delay unit, including a resistor and a capacitor connected in series, whose input end is connected to the output end of the latch; a first inverter and a second inverter connected in series, the input end of the first inverter is connected to the output end of the resistor and capacitor delay unit, and the output end of the second inverter is used to output the delayed latch signal.

[0020] In a preferred example, the output logic circuit includes:

[0021] A first NAND gate, used to make the reference clock signal generate a rising edge when the latch signal has a rising edge, wherein the first input end is used to receive the latch signal, and the second input end is connected to the inverting output end of the reference clock signal;

[0022] A second NAND gate is used to make the reference clock signal produce a falling edge when the delayed latch signal has a rising edge, wherein the first input end is connected to the output end of the first NAND gate, the second input end is used to receive the delayed latch signal, and the output end is connected to the in-phase output end of the reference clock signal.

[0023] In a preferred example, the state controller includes: an AND gate circuit, a first input end of which is connected to the delayed latch signal, a second input end is used to receive an inverted signal of the data transmission indication signal, and an output end is used to output the reset signal.

[0024] The clock generation circuit solution provided by this application can achieve the following technical effects:

[0025] First, the present application recovers the clock by detecting the edge transition of the marker signal in the receiver output data. Compared with the traditional high-frequency phase detector structure, this solution uses a relatively simple edge detection and latch circuit, does not require the use of high-speed devices, has a simple overall circuit structure, and greatly reduces system power consumption.

[0026] Second, the latch of the present application adopts a single response mechanism, which only responds to the jump of the first flag signal during each frame of data transmission and ignores the subsequent data jumps. This design ensures the stability of the clock signal, effectively suppresses the interference that may be caused by data jumps, and makes the recovered clock signal have lower jitter characteristics.

[0027] Third, the present application provides a variety of delay circuit implementation schemes: one is a trigger cascade structure based on the system clock, and the other is a delay circuit based on an adjustable RC time constant. This flexible and configurable design allows the duty cycle of the clock signal to be easily adjusted according to actual application requirements, greatly improving the applicability and practical value of the circuit.

[0028] Fourth, the application uses a state controller to intelligently manage the working state of the circuit, which can accurately grasp the start and end timing of data transmission and realize automatic reset and state switching of the circuit. This design significantly improves the reliability and stability of the clock recovery circuit, enabling it to cope with continuous data frame transmission scenarios.

[0029] In summary, the present application innovatively solves the technical problems of high power consumption and complex structure of traditional clock recovery circuits, and provides a low-power, low-jitter, multi-mode configurable clock recovery solution, demonstrating significant technical advantages and broad application prospects.

[0030] A large number of technical features are recorded in the specification of this application, which are distributed in various technical solutions. If all possible combinations of technical features of this application (i.e., technical solutions) are to be listed, the specification will be too long. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of this application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions are all deemed to have been recorded in this specification), unless the combination of such technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed, and features C and D are equivalent technical means that play the same role. Technically, only one can be used, and it is impossible to use them at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be deemed to have been recorded because it is technically infeasible, and the solution of A+B+C+E should be deemed to have been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of the overall architecture of a clock generating circuit based on a receiver signal according to the first embodiment of the present application.

[0032] Figure 2It is a flow chart of the working state of the clock generating circuit based on the receiver signal according to the first embodiment of the present application.

[0033] Figure 3 It is a structural diagram of an edge detection circuit of a clock generating circuit based on a receiver signal according to the first embodiment of the present application.

[0034] Figure 4 4 is a latch circuit diagram of a clock generating circuit based on a receiver signal according to the first embodiment of the present application.

[0035] Figure 5 It is a circuit structure diagram of the remaining modules of the clock generation circuit based on the receiver signal according to the first embodiment of the present application.

[0036] Figure 6 4 is a timing diagram of a clock generating circuit based on a receiver signal according to the first embodiment of the present application. DETAILED DESCRIPTION

[0037] In the following description, many technical details are provided to help readers better understand the present application. However, those skilled in the art can understand that the technical solution claimed in the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0038] Description of some concepts:

[0039] Receiver: refers to the device used to receive signals in a communication system. Its function is to convert the signals transmitted in the channel into original information data.

[0040] Clock recovery circuit: refers to the circuit unit in the receiver used to extract the synchronous clock signal from the received data and provide the synchronous timing signal for data recovery.

[0041] Flag signal: refers to a specific bit sequence in a data frame used to indicate the beginning or end of data. It usually has a fixed pattern and appears periodically in the data.

[0042] Edge transition: refers to the process in which a signal changes rapidly from one state to another in time. It is divided into two types: rising edge (from low to high) and falling edge (from high to low).

[0043] Pulse signal: refers to a signal whose amplitude changes rapidly between two fixed values, usually used to trigger or synchronize other circuit units.

[0044] Latch: A basic logic storage unit that can store one bit of binary data under the control of a clock signal. Often used to temporarily store and synchronize digital signals.

[0045] Delay circuit: A circuit unit that causes the input signal to produce a preset time delay, commonly used in signal synchronization, pulse width control, etc.

[0046] System clock: A reference clock signal used in a digital system to control the working rhythm and synchronization of various components, usually generated by an oscillator.

[0047] Flip-flop: A digital logic circuit with memory function that can store one bit of state information under the control of a clock signal. Often used to build sequential logic circuits.

[0048] Duty cycle: refers to the ratio of the time that the signal is at a high level in one cycle to the entire cycle time, reflecting the ratio of the duration of the high and low levels of the signal.

[0049] State controller: refers to the control unit that controls and coordinates the working status of each part of the system, and realizes the system's workflow by receiving feedback information and issuing control instructions.

[0050] Data transmission indication signal: refers to the control signal generated by the transmitter to indicate the start and end time of data transmission. The receiver can judge and control the reception process of the data frame based on this signal.

[0051] Jitter: refers to the deviation of the actual time of a signal from the ideal time, reflecting the phase instability of the signal. Excessive jitter will affect system performance and reliability.

[0052] The following is a brief description of some of the innovative features of this application:

[0053] First, this application proposes to use the inherent periodic flags in the data signal for clock extraction, which completely breaks through the shackles of the traditional clock recovery scheme's reliance on high-speed phase detectors. This application cleverly recovers the clock signal by detecting the flag signal jump in the received data, and uses a simple and efficient edge detection and latch circuit to replace the complex analog phase detector structure, which not only fundamentally reduces the circuit power consumption, but also greatly simplifies the complexity of circuit design, and has significant technical advantages and application value.

[0054] Secondly, the present application designs a unique latch single trigger mechanism, which effectively solves the problem of interference of digital data jumps on clock recovery. Different from the traditional solution, the latch circuit of the present application only responds to the first flag signal jump in each data frame and remains "immune" to subsequent data jumps. The introduction of this mechanism has qualitatively improved the stability of the clock signal, clearing the technical obstacles for achieving high-speed and high-precision data sampling and transmission.

[0055] Again, this application proposes a novel solution of a multi-mode configurable delay circuit, which realizes flexible and precise adjustment of clock parameters. Different from the prior art, this application provides two delay implementation methods based on trigger cascade and adjustable RC network, and dynamically adjusts the clock duty cycle by accurately controlling the delay parameters. This flexible and configurable design gives this application a strong environmental adaptability, enabling it to optimize the working mode in real time according to actual application requirements, thereby effectively being compatible with different communication protocol standards and data transmission rates.

[0056] Furthermore, this application introduces an innovative design of an intelligent state control mechanism to achieve adaptive adjustment of the working state of the clock recovery circuit. The state controller accurately controls the timing of sending and receiving data frames by detecting the data transmission indication signal in real time, so that the circuit can achieve seamless switching between different states such as data communication and idle. This intelligent control strategy is particularly suitable for burst communication scenarios in emerging technology fields such as the Internet of Things. It can achieve efficient use of energy while ensuring communication quality. It can be said that it is well versed in the development trend of communication systems and has a forward-looking technical vision.

[0057] The various innovative points of this application form a unique synergistic efficiency mechanism, and together build a highly optimized clock recovery system with excellent performance: the edge detection circuit provides accurate trigger signals for clock recovery; the latch circuit ensures robust capture of the clock signal; the delay circuit realizes fine regulation of the clock waveform; and the state controller optimizes the system state in real time through intelligent management strategies. Thanks to this systematic innovative design from top-level architecture to bottom-level implementation, this application can always maintain a stable and reliable working state in complex and changeable actual application environments, and can be regarded as an ideal clock solution for the new generation of green, efficient and intelligent communication systems.

[0058] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0059] The first embodiment of the present application relates to a clock generation circuit based on a receiver signal, and its structure is as follows: Figures 1 to 5 As shown, including:

[0060] Edge detection circuit, latch, delay circuit, output logic circuit and state controller, wherein:

[0061] The edge detection circuit is used to receive and detect the edge jump of the marker signal in the receiver output signal, and generate a pulse signal indicating the edge jump;

[0062] The input end of the latch is connected to the output end of the edge detection circuit, and is used to respond to the pulse signal to flip and maintain the state, thereby generating a latch signal;

[0063] The input end of the delay circuit is connected to the output end of the latch, and is used to output a delayed latch signal after delaying the latch signal for a preset time;

[0064] The first input terminal of the output logic circuit is connected to the output terminal of the latch, and the second input terminal is connected to the output terminal of the delay circuit, and is used to generate a reference clock signal with a fixed duty cycle according to the rising edge of the latch signal and the rising edge of the delayed latch signal;

[0065] The state controller is used to generate a reset signal when the delayed latch signal is at a high level and the data transmission indication signal is at a low level. The output end of the reset signal is respectively connected to the latch and the delay circuit, and is used to control the latch and the delay circuit to reset.

[0066] Optionally, the edge detection circuit includes a first delay unit, an XOR gate and an AND gate, wherein: the input end of the first delay unit and the first input end of the XOR gate are both used to receive the receiver output signal, and the output end of the first delay unit is connected to the second input end of the XOR gate; the first input end of the AND gate is connected to the output end of the XOR gate, the second input end is used to receive the receiver output signal, and the output end is used to output the pulse signal.

[0067] Optionally, the latch includes a trigger end, a reset end and an output end, wherein: the trigger end is connected to the output end of the edge detection circuit for receiving the pulse signal; the reset end is connected to the output end of the state controller for receiving the reset signal; the output end is used to output the latch signal, and the latch only responds to the edge transition of the flag signal once during each frame of data transmission.

[0068] Optionally, the delay circuit includes: a first trigger and a second trigger, the data input terminal of the first trigger is connected to the output terminal of the latch, the data input terminal of the second trigger is connected to the output terminal of the first trigger, and the output terminal of the second trigger is used to output the delayed latch signal; wherein, the clock input terminals of the first trigger and the second trigger are both used to receive the system clock signal, and the reset terminals are both used to receive the reset signal.

[0069] Optionally, the frequency of the system clock signal is higher than the frequency of the reference clock signal.

[0070] Optionally, another implementation of the delay circuit includes: a resistor and capacitor delay unit, including a resistor and a capacitor connected in series, and an input end of which is connected to the output end of the latch; a first inverter and a second inverter connected in series, the input end of the first inverter is connected to the output end of the resistor and capacitor delay unit, and the output end of the second inverter is used to output the delayed latch signal.

[0071] Optionally, the output logic circuit includes:

[0072] A first NAND gate, used to make the reference clock signal generate a rising edge when the latch signal has a rising edge, wherein the first input end is used to receive the latch signal, and the second input end is connected to the inverting output end of the reference clock signal;

[0073] A second NAND gate is used to make the reference clock signal produce a falling edge when the delayed latch signal has a rising edge, wherein the first input end is connected to the output end of the first NAND gate, the second input end is used to receive the delayed latch signal, and the output end is connected to the in-phase output end of the reference clock signal.

[0074] Optionally, the state controller includes: an AND gate circuit, a first input end of which is connected to the delayed latch signal, a second input end is used to receive an inverted signal of the data transmission indication signal, and an output end is used to output the reset signal.

[0075] Working principle:

[0076] The above embodiment proposes a low-power, low-jitter clock generation circuit based on a receiver signal. The core principle is to use the periodic characteristics of the marker signal in the received data frame to extract a reference clock synchronized with the data without using a traditional high-speed phase detector structure.

[0077] The complete working process of the circuit is as follows:

[0078] Initial waiting stage: Before data transmission starts, the circuit is in a waiting state and each module remains in the initial state.

[0079] Edge detection stage: When a data frame is received, the edge detection circuit detects the jump of the flag signal in the receiver output signal through the combination structure of the delay unit and the logic gate. In specific implementation, the input signal after the delay unit is compared with the original signal in the XOR gate to detect the signal jump, and then the pulse signal corresponding to the rising edge is obtained through the AND gate.

[0080] Signal latching stage: After receiving the pulse signal output by the edge detection circuit, the latch flips and maintains its state. In particular, the latch adopts a single response mechanism, that is, during each frame of data transmission, it only responds to the jump of the first flag signal and ignores the subsequent data jumps. This design ensures the stability of the clock signal.

[0081] Delay processing stage: The output signal of the latch is processed in two ways - one is directly used as the input of the output logic, and the other is generated through the delay circuit to generate a delayed latch signal. The delay circuit provides two implementation schemes: one is to use the trigger cascade structure driven by the system clock, and the other is to use an RC delay circuit with an adjustable RC time constant so that the delay amount can be flexibly configured.

[0082] Clock generation stage: The output logic circuit adopts a NAND gate combination structure, and cleverly uses the timing relationship between the latch signal and the delayed latch signal to generate a reference clock. The rising edge of the latch signal triggers the rising edge of the reference clock, and the rising edge of the delayed latch signal triggers the falling edge of the reference clock, thereby generating a clock signal with a fixed duty cycle. The clock period is determined by the period of the flag signal, and the duty cycle is controlled by the delay amount of the delay circuit.

[0083] State reset stage: At the end of each frame of data transmission, the state controller generates a reset signal at an appropriate time by monitoring the level status of the delayed latch signal and the data transmission indication signal, so that the latch and delay circuit return to the initial state and prepare for the clock extraction of the next frame of data.

[0084] Compared with the traditional clock data recovery circuit using a high-speed phase detector, the innovation of the above embodiment is reflected in: the inherent characteristics of the data frame are cleverly used to extract the reference clock, and stable clock recovery can be achieved through a simple edge detection and delay processing circuit. This design not only reduces the power consumption and complexity of the circuit, but also provides an adjustable clock duty cycle, which has significant technical advantages in practical applications.

[0085] It should be pointed out that, first of all, the above embodiments deeply analyze the actual needs of low-power wireless communication systems, and innovatively propose an efficient and energy-saving clock recovery solution for its stringent power consumption constraints. Unlike the traditional high-speed phase detector solution, the above embodiments cleverly utilize the inherent periodic flags in the data signal, and realize clock extraction through simple and efficient edge detection and latching operations, which fundamentally solves the power consumption bottleneck. At the same time, the multi-mode configurable delay circuit gives the above embodiments extraordinary flexibility, which can not only accurately control the clock duty cycle, but also intelligently switch the working mode, minimizing energy consumption while ensuring performance.

[0086] Secondly, a unique synergistic efficiency-enhancing mechanism is formed between the technical links of the above embodiments. The edge detection circuit accurately captures the flag signal jump and provides a reliable trigger for clock recovery; the latch circuit cleverly introduces a single response mechanism to effectively suppress data jump interference and ensure clock stability; the delay circuit accurately adjusts the clock edge based on the latch state and strictly controls the signal quality; the state controller monitors the data transmission status in real time and intelligently schedules the circuit working mode. This interlocking and systematic technical architecture enables the above embodiments to always maintain reliable and stable system performance in complex and changeable communication scenarios.

[0087] Furthermore, the above embodiments show excellent versatility and scalability. Thanks to the flexible and configurable delay circuit and intelligent control mechanism, the above embodiments are widely compatible with a variety of data rates and encoding methods, whether it is the traditional LVDS interface or advanced SubLVDS, MIPI and other high-speed serial standards, they can provide perfect support. This excellent adaptability enables the above embodiments to be widely used in many fields such as smart phones, wearable devices, and Internet of Things terminals, greatly expanding its application boundaries.

[0088] More importantly, the above embodiments provide unique and effective solutions for practical application scenarios. Taking the field of Internet of Things as an example, terminal devices usually adopt a bursty intermittent communication mode. Thanks to the intelligent state management mechanism, the above embodiments can stably output high-quality clocks during data transmission, and automatically enter a low-power state during idle periods, achieving the best balance between system performance and energy efficiency. This intelligent working mode is the best clock recovery tool for the new generation of low-power communication systems.

[0089] In summary, the above embodiments have been designed with innovative systems from multiple dimensions such as power consumption, performance, and applicability to meet the actual needs of low-power wireless communications. The exquisite coordination between technical links, the wide compatibility in application fields, and the excellent performance in actual scenarios have jointly created the leading position of the above embodiments in the field of clock recovery technology. This groundbreaking innovation will surely provide strong technical support for the new generation of green, efficient, and intelligent communication systems.

[0090] In order to better understand the technical solution of the present application, a specific example is provided below for illustration. The details listed in the example are mainly for ease of understanding and are not intended to limit the scope of protection of the present application.

[0091] This example proposes a design scheme for a clock generation circuit, which detects the edge transition of the receiver output signal to recover the clock signal related to the data stream. Compared with the high-frequency phase detector in the traditional clock and data recovery circuit, this design has lower requirements on the device operating speed, consumes less power, and can recover a reference clock signal with lower jitter.

[0092] Figure 1 The overall architecture diagram of the clock generation circuit is shown. Since the time interval of each frame of data is the same and the flag signal is consistent, a more accurate low-frequency reference clock can be obtained by detecting the flag signal of each frame of data. First, the output signal RX_DATA of the receiver enters the edge detection circuit, identifies the edge jump of the flag signal, and outputs a pulse signal to the latch, so that the latch is reversed, indicating that the flag signal has been received. The latch output is connected to the delay circuit and output logic. After the delay, the latch output is processed by the output logic to obtain the reference clock signal CKREF_OUT. The state controller is used to configure the working state and timing of the circuit, and to open, close and reset the circuit.

[0093] Furthermore, in the present application, the edge detection circuit is used to accurately capture the transition moment of the flag signal and provide a reliable trigger signal for clock recovery. The latch circuit adopts an innovative single response mechanism, which only latches the transition of the first flag signal in each frame of data, effectively avoiding the interference of subsequent data transitions and ensuring the stability of the latched signal. The delay circuit accurately delays the edge transition of the clock signal according to the latch state, and flexibly adjusts the clock duty cycle through the configurable delay time to meet different application requirements. Finally, the output logic circuit integrates the latch signal and the delay signal to generate a reference clock output with an ideal waveform and duty cycle.

[0094] It is worth mentioning that the application also designs an intelligent state controller, which automatically detects the start and end time of the data frame by real-time monitoring of the data transmission indication signal, and dynamically controls the working mode switching and system reset of the clock recovery circuit according to the data transmission status. This adaptive state control mechanism ensures that the clock generation circuit can work stably and reliably in actual application scenarios, and is particularly suitable for emerging fields such as the Internet of Things with burst data transmission.

[0095] In short, the functional circuit links of this application work together and closely cooperate to form a highly optimized clock recovery system. This collaborative working mode gives full play to the technical advantages of each circuit, solves the problems of clock recovery such as power consumption and jitter from the source, and represents the development trend of future clock recovery technology. It is believed that this technical solution will provide strong technical support for the new generation of high-speed, efficient and low-power communication systems.

[0096] Figure 2The working state flow chart of the clock generation circuit is shown. In the idle state without data transmission, the circuit is in a waiting state, waiting for the edge jump in the flag signal when the data starts to be transmitted. When the data starts to be transmitted, the edge detection circuit detects the edge jump and generates a pulse signal to trigger the latch, causing it to flip and lock. At this time, the output logic also flips accordingly, outputs the corresponding edge jump of the reference clock, and then outputs another edge jump after a certain delay, thereby forming a reference clock signal with a fixed duty cycle. When the data transmission of this frame is completed, the data transmission indication signal of the system becomes a low level. After being processed by the state controller, the entire circuit will be reset and re-enter the waiting state, waiting for the arrival of the next frame of data.

[0097] To put it more concretely, first, before data transmission begins, the entire clock generation circuit is in a waiting state. At this time, the latch, delay circuit, and output logic all maintain their initial states. The state controller determines whether the current state is in an idle period by detecting whether the data transmission indication signal is at a low level.

[0098] Once the receiver starts receiving a new data frame, the edge transition of the flag signal will appear in the data signal. The edge detection circuit monitors the input data signal in real time, and once the transition of the flag signal is captured, a pulse trigger signal is generated and output to the latch.

[0099] After the latch circuit receives the trigger pulse from the edge detection circuit, it will immediately flip from the initial state to the locked state and maintain this state until it receives the reset signal. The change of the latch state also synchronously triggers the state change of the output logic circuit.

[0100] The output logic circuit combines the output state of the latch and the output of the delay circuit to generate a reference clock signal. When the latch output flips, it means that a new clock cycle begins, and the output of the reference clock signal will generate a rising edge.

[0101] Next, the delay circuit starts to work, and it outputs the latched signal after a specific delay time. When the delay ends and the delayed signal is output, the output logic circuit flips again, and the reference clock signal generates a falling edge. The time interval between the rising edge and the falling edge is determined by the delay time of the delay circuit, so that the duty cycle of the clock can be accurately controlled.

[0102] When the data frame transmission is completed, the state controller will detect that the data transmission indication signal has changed to a low level. At this time, the controller will issue a reset instruction to reset the latch and delay circuit to the initial state to prepare for receiving the next frame of data. The entire circuit re-enters the idle waiting state, completing a complete workflow.

[0103] In this working mode, the present application can generate a reference clock synchronized with data transmission in real time according to the rhythm of the input data stream. Thanks to the periodicity of the flag signal, the jitter of the recovered clock signal is very small. Moreover, the duty cycle can be flexibly configured through the delay time to adapt to different communication protocols. At the same time, due to the introduction of the state controller, the present circuit can adaptively handle continuous or burst data transmission and always maintain a stable and reliable working state.

[0104] In summary, the clock generation circuit of the present application cleverly utilizes the characteristics of the input signal, and through the perfect coordination of various functional links such as edge detection, state latching, and delay control, it flexibly and controllably generates a high-precision, low-jitter synchronous clock, which is suitable for various high-speed data transmission applications.

[0105] Figure 3 The structure diagram of the edge detection circuit is shown. Taking rising edge detection as an example, falling edge detection can add an inverter between the input RX_DATA signal and the output stage AND gate. The input signal RX_DATA is directly connected to the XOR gate and first connected to the XOR gate after a delay. When the input is reversed, the XOR gate outputs a positive pulse with the same pulse width as the delay, and then passes through the AND logic with the input signal to determine whether the input is a rising edge jump, and then generates a corresponding positive pulse (pos_out) at the output.

[0106] Furthermore, the edge detection circuit is an important component of the clock recovery system of the present application. Its core function is to monitor the input received data signal in real time, accurately capture the transition moment of the flag signal, and output a pulse trigger signal synchronized with the transition.

[0107] The key to this circuit is to use the combination of XOR gate and delay unit to cleverly realize the edge jump judgment. Specifically, the input signal RX_DATA is directly connected to one input end of the XOR gate, and the other input end of the XOR gate is connected after a certain time delay through the delay unit.

[0108] When the input signal changes (taking the rising edge as an example), due to the delay difference between the two inputs of the XOR gate, the two inputs must be different at this time, and the XOR gate output is high. The width of this high-level pulse is exactly equal to the delay time of the delay unit. Subsequently, when the delayed signal also changes, the two ends of the XOR gate return to the same state, and its output becomes low.

[0109] Next, the output pulse of the XOR gate and the original input signal RX_DATA are sent to the AND gate for logic judgment. Only when the XOR gate outputs a high-level pulse and RX_DATA is also high at the same time, the AND gate outputs a high level, indicating that a rising edge is detected. This "first XOR, then AND gate" design can accurately distinguish the rising edge jump of the input signal and effectively avoid false triggering of the falling edge or burrs.

[0110] Finally, the AND gate outputs a positive pulse signal pos_out that is strictly synchronized with the rising edge transition as the output of the edge detection circuit. This pulse signal can be directly used to trigger subsequent circuits such as latches.

[0111] It is worth mentioning that the edge detection circuit has a simple structure, is easy to implement, and has strong anti-interference ability. By properly selecting the delay time parameters of the delay unit, the optimal pulse width can be obtained, and the pulse duration can be shortened as much as possible while ensuring reliable triggering, thereby reducing the impact on the system timing. In addition, this circuit can also be easily expanded to dual-edge detection. As shown in the figure, only an inverter is added before the AND gate to realize the detection of the falling edge.

[0112] In summary, the edge detection circuit proposed in this application makes full use of the timing characteristics of simple logic gates, and uses the combination of XOR gates and AND gates to achieve accurate and reliable signal transition detection. This provides a solid trigger signal foundation for the clock recovery system, reflects the high degree of ingenuity in circuit design of this application, and has significant technical advantages.

[0113] Figure 4 The latch circuit diagram is shown. When the edge detection circuit generates a positive pulse output (pos_out), the latch output (latch_out) will flip from a low level to a high level, and then maintain this state. Subsequent positive pulses or negative pulses will not cause the latch output to change, that is, the latch output only flips once when the flag signal in each frame of data arrives, and subsequent data jumps will not change the latch state until the data transmission is completed. The state controller generates a reset signal (reset) to make the latch output return to a low level and wait for the arrival of the next frame of data.

[0114] Furthermore, the latch circuit plays a crucial role in the clock recovery system of the present application. It is responsible for capturing and temporarily storing the output pulse of the edge detection circuit and generating a stable latch signal, and is a bridge connecting the trigger signal and the clock recovery logic.

[0115] The biggest feature of this latch circuit is its unique single-shot trigger mechanism. Specifically, in each data frame, the latch is only sensitive to the first incoming edge pulse signal pos_out. Once the rising edge of the pulse is detected, its output latch_out will immediately jump from a low level to a high level. After this flip occurs, the latch will firmly lock the current high level state to maintain output stability.

[0116] This single-trigger latching method cleverly avoids the interference that may be caused by signal jumps during data transmission. Since the data signal is random and its jumps are frequent, it is likely to cause the edge detection circuit to output continuous pulses, which is extremely unfavorable for maintaining clock stability. However, the latch of the present application can effectively isolate subsequent edge triggering events. Once the locked state is reached, regardless of whether pos_out has subsequent pulse outputs, latch_out will stably maintain the existing state and will not change.

[0117] This state lock lasts until the current data frame transmission ends. When the data transmission ends, the system state controller will send a reset signal reset to pull the output of the latch back to a low level to prepare for the arrival of the next data frame. When a new frame of data arrives, the latch starts working again and captures the jump of the first flag signal again, repeating the cycle to complete the recovery of the clock signal synchronized with the data.

[0118] It can be seen that the single-shot trigger characteristic of the latch plays a crucial role. It effectively isolates the random interference of the data signal, extracts only the edge information synchronized with the frame, eliminates the jitter of the clock signal, and provides a reliable latch signal for the stable operation of the subsequent logic. At the same time, relying on the inter-frame reset function of the state controller, the latch can be dynamically refreshed between frames, adapting to different data rates and frame lengths, and ensuring the continuity and reliability of clock recovery.

[0119] In summary, the latch circuit of the present application represents a novel clock signal latching scheme. The innovative single-shot trigger mechanism and the ingenious inter-frame reset design effectively overcome the influence of data signal transition on clock recovery. At the same time, it has a simple structure and convenient control, and can be easily integrated into various high-speed data transmission systems.

[0120] Figure 5The circuit structure diagram of the remaining modules of the clock generation circuit is shown. The latch output latch_out generates the latch_out_d signal through the delay circuit. There are two ways to implement the delay circuit. One is to rely on the clock beat and use the system clock clk_hf with a higher frequency than the output reference clock CKREF_OUT to control the trigger. After two-stage trigger delay, the latch_out_d signal is generated. The other is to use a larger resistor and capacitor for delay, and then shape it through two stages of inverters to obtain a latch_out_d signal with a steep edge. Both delay circuits perform a fast reset when the reset signal (reset) is low. The output logic causes the output CKREF_OUT to jump to the rising edge when the latch_out rises, and causes the CKREF_OUT to jump to the falling edge when the latch_out_d rises. The width of the clock signal, or the duty cycle, is controlled by the delay size of the delay circuit. The state controller is used to generate a reset signal. When the delayed latch_out_d signal becomes a high level and the data transmission indication signal (en_data) of the system is a low level, a reset signal (reset) is generated.

[0121] Further, the working principle of the delay circuit, output logic and state controller is as follows:

[0122] First of all, the delay circuit plays a vital role in this application. It is responsible for accurately delaying the latch signal latch_out and generating a delayed signal latch_out_d, thereby controlling the duty cycle of the output clock. This application cleverly provides two optional delay circuit implementations to meet different application requirements.

[0123] The first delay method relies on the system clock clk_hf and two-stage triggers. clk_hf is a high-speed clock much higher than the target clock frequency CKREF_OUT, which is used to control the working rhythm of the trigger. The latch signal latch_out passes through two D flip-flops in succession, and completes the delay of two clock cycles under the drive of clk_hf. This clock-based delay control is very accurate, and the delay amount can be flexibly configured through the number of clock cycles of clk_hf, which is very suitable for occasions with strict requirements on the clock duty cycle.

[0124] The second delay method uses an RC circuit, which uses the charging and discharging process of resistors and capacitors to achieve signal delay. The latch signal latch_out first passes through an RC network to generate a slowly changing signal, and then is shaped by two stages of inverters to obtain a clean square wave signal latch_out_d. This analog delay circuit is simple to implement and low in cost. It can be continuously adjusted over a wide range by adjusting the RC parameters. For applications where the duty cycle requirements are not strict, this method is more economical and efficient.

[0125] It is worth mentioning that no matter which delay circuit is used, the reset signal reset is essential. When the reset signal is low, the trigger or inverter in the delay circuit will be reset to the initial state immediately. This ensures that the delay circuit, latch, and output logic can be reset synchronously at the beginning of each data frame, ensuring the independence between different frames and avoiding the accumulation of erroneous delay signals.

[0126] Secondly, the output logic circuit is like a clever signal "conductor", cleverly coordinating the latch signal latch_out and the delay signal latch_out_d to accurately synthesize the target clock CKREF_OUT. Through a very clever logical relationship, it synchronizes the rising edge of CKREF_OUT with the rising edge of latch_out, and the falling edge with the rising edge of latch_out_d. This sophisticated timing control makes the period and duty cycle of the output clock completely determined by the flipping moment of the latch signal and the delay time of the delay signal. In other words, as long as the delay of the delay circuit is appropriate, the ideal clock waveform can be configured. All this is due to the unique logic circuit design of the present application, which avoids other complex control mechanisms and realizes efficient and reliable clock synthesis.

[0127] Finally, the state controller is the "brain" of this application, which comprehensively monitors the system status and coordinates the smooth transition of each module between different data frames. In particular, the generation logic of the reset signal reset reflects the high attention paid by this application to system reliability. The controller comprehensively judges the delay signal latch_out_d and the data transmission indication signal en_data. Only when latch_out_d is high (indicating that the current clock cycle has been generated) and en_data is low (indicating that the current data frame has ended), the reset is triggered to prepare the clock recovery circuit for the next frame. This judgment logic ensures the accuracy of the reset timing, eliminates the "preemptive run" or "late arrival" of the reset signal and the effective clock, and fundamentally guarantees the stability and reliability of the system in the processing of continuous data frames.

[0128] In short, the delay circuit, output logic and state controller constitute the core control unit of the clock recovery system of this application. They have clear division of labor and cooperate with each other to achieve precise control of the clock signal. The diversified delay control methods, ingenious and efficient clock synthesis logic, and rigorous and reliable state management mechanism are integrated to build a powerful and complete clock control system of this application. This advanced control architecture will surely become the "benchmark" for synchronous clock recovery of high-speed data transmission systems, and will have a profound impact on improving the performance and reliability of communication systems.

[0129] Figure 6 The timing diagram of the clock generation circuit is shown. The length and content of each frame of data are different, so the number and position of the positive pulse (pos_out) output by the edge detection circuit are also different, but each frame signal will have a same indication signal, so at the beginning of data transmission, the spacing between the first positive pulses in each frame is equal, which is a period of T, and the corresponding latch output latch_out and delay circuit output latch_out_d are obtained. After the output logic, the clock CKREF_OUT with a period of T is finally obtained. The system's data indication signal en_data generally has an uncertain delay relative to the data envelope and cannot be used directly as a clock, but it can be used to determine whether the data transmission has ended, and then generate a reset signal (reset) according to the conditions. When the data is too short, or even only an indication signal is present, the reset signal needs to wait until the delay signal latch_out_d flips before being pulled down to a low level to ensure a constant CKREF_OUT pulse width. After latch_out_d is reset to a low level, the reset signal (reset) becomes a high level again after a short logic delay, so that the latch can be flipped again by a positive pulse.

[0130] More specifically, the above timing relationship is as follows:

[0131] The clock recovery circuit of the present application makes full use of the characteristics of the input data signal and cleverly extracts a stable synchronous clock from data frames of varying lengths. Although the length and content of each frame of data are inconsistent, resulting in the pulse signal (pos_out) output by the edge detection circuit being uncertain in quantity and position, since there is a fixed indication signal at the beginning of each frame, the first pulse pos_out generated is periodic in time, and the period is the period T of the target clock.

[0132] Taking advantage of this feature, the key point of this application is to lock the first pulse signal of each frame of data through a latch circuit, and generate a latch signal latch_out and a delay signal latch_out_d with a well-designed delay circuit, and then through a clever combination of output logic, finally synthesize a synchronous clock CKREF_OUT with a stable period and constant pulse width. The timing design of the entire circuit is rigorous and ingenious, which fully reflects the precise grasp and flexible use of the characteristics of the input signal in this application.

[0133] It is worth mentioning that although the data transmission indication signal en_data cannot be used directly as a clock (because it has an uncertain delay relative to the data), it still plays an important role in this application. en_data is used to determine the end time of each frame of data, and then together with the delay signal latch_out_d, it provides a reliable basis for the generation of the reset signal reset. In particular, for extremely short frames or even only the indication signal, the reset signal will deliberately wait for latch_out_d to complete a complete flip before performing a reset, thereby ensuring that the pulse width of the clock signal CKREF_OUT remains constant. At the same time, after a short delay after the reset, the reset signal will quickly recover, allowing the latch circuit to be ready to capture the next frame of data in time. These details all demonstrate the precision and rigor of the reset timing control of this application.

[0134] In summary, this application cleverly utilizes the inherent characteristics of the input signal, and through careful timing design and rigorous logic control, stably extracts the synchronous clock from the variable-length data stream, and outputs a clock signal with a constant period and a stable duty cycle. Regardless of how the data frame length and content change, this application can work reliably, embodying extremely strong adaptability and robustness, and well meeting the needs of actual high-speed data transmission systems.

[0135] It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements. In the application documents of this patent, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, which includes two situations: performing the action only according to the element, and performing the action according to the element and other elements. Expressions such as multiple, multiple, and multiple include 2, 2 times, 2 kinds, and more than 2, more than 2 times, and more than 2 kinds.

[0136] All documents mentioned in this application are considered to be included in the disclosure of this application as a whole, so that they can be used as the basis for modification when necessary. In addition, it should be understood that after reading the above disclosure of this application, those skilled in the art can make various changes or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A clock generating circuit based on a receiver signal, characterized in that: It includes edge detection circuit, latch, delay circuit, output logic circuit and state controller, wherein: The edge detection circuit is used to receive and detect the edge jump of the marker signal in the receiver output signal, and generate a pulse signal indicating the edge jump; The input end of the latch is connected to the output end of the edge detection circuit, and is used to respond to the pulse signal to flip and maintain the state, thereby generating a latch signal; The input end of the delay circuit is connected to the output end of the latch, and is used to output a delayed latch signal after delaying the latch signal for a preset time; The first input terminal of the output logic circuit is connected to the output terminal of the latch, and the second input terminal is connected to the output terminal of the delay circuit, and is used to generate a reference clock signal with a fixed duty cycle according to the rising edge of the latch signal and the rising edge of the delayed latch signal; The state controller is used to generate a reset signal when the delayed latch signal is at a high level and the data transmission indication signal is at a low level. The output end of the reset signal is respectively connected to the latch and the delay circuit, and is used to control the latch and the delay circuit to reset.

2. The clock generating circuit based on the receiver signal as claimed in claim 1, characterized in that: The edge detection circuit includes a first delay unit, an XOR gate and an AND gate, wherein: the input end of the first delay unit and the first input end of the XOR gate are both used to receive the receiver output signal, and the output end of the first delay unit is connected to the second input end of the XOR gate; the first input end of the AND gate is connected to the output end of the XOR gate, the second input end is used to receive the receiver output signal, and the output end is used to output the pulse signal.

3. The clock generating circuit based on the receiver signal as claimed in claim 1, characterized in that: The latch includes a trigger end, a reset end and an output end, wherein: the trigger end is connected to the output end of the edge detection circuit for receiving the pulse signal; the reset end is connected to the output end of the state controller for receiving the reset signal; the output end is used to output the latch signal, and the latch only responds to the edge transition of the flag signal once during each frame of data transmission.

4. The clock generating circuit based on the receiver signal as claimed in claim 1, characterized in that: The delay circuit includes: a first trigger and a second trigger, the data input end of the first trigger is connected to the output end of the latch, the data input end of the second trigger is connected to the output end of the first trigger, and the output end of the second trigger is used to output the delayed latch signal; wherein, the clock input ends of the first trigger and the second trigger are both used to receive the system clock signal, and the reset ends are both used to receive the reset signal.

5. The clock generating circuit based on the receiver signal as claimed in claim 4, characterized in that: The frequency of the system clock signal is higher than the frequency of the reference clock signal.

6. The clock generating circuit based on the receiver signal as claimed in claim 1, characterized in that: Another implementation of the delay circuit includes: a resistor and a capacitor connected in series, whose input end is connected to the output end of the latch; a first inverter and a second inverter connected in series, the input end of the first inverter is connected to the output end of the resistor and capacitor delay unit, and the output end of the second inverter is used to output the delayed latch signal.

7. The clock generating circuit based on the receiver signal as claimed in claim 1, characterized in that: The output logic circuit comprises: A first NAND gate, used to make the reference clock signal generate a rising edge when the latch signal has a rising edge, wherein the first input end is used to receive the latch signal, and the second input end is connected to the inverting output end of the reference clock signal; A second NAND gate is used to make the reference clock signal produce a falling edge when the delayed latch signal has a rising edge, wherein the first input end is connected to the output end of the first NAND gate, the second input end is used to receive the delayed latch signal, and the output end is connected to the in-phase output end of the reference clock signal.

8. The clock generating circuit based on the receiver signal as claimed in claim 1, characterized in that: The state controller comprises: an AND gate circuit, a first input end of which is connected to the delayed latch signal, a second input end of which is used to receive the inverted signal of the data transmission indication signal, and an output end of which is used to output the reset signal.

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