Polymorphic SAR ADC optimization method and system based on automatic calibration

Abstract

The invention provides a polymorphic SAR ADC optimization method and system based on automatic calibration, and the method comprises the steps: collecting the amplitude and frequency of an input signal in real time, and monitoring the key performance indexes of an ADC; designing an optimization objective function; the N value is optimized through a dynamic search algorithm, and the optimal N value suitable for the current signal condition is selected; calculating a target function value corresponding to each optimal N value, and selecting the N value which maximizes the optimization target function; adjusting the state number of the multi-state comparator according to the optimal N value; the result of each acquisition period is fed back in real time, and the selection of the N value is adjusted in real time by storing and comparing the performance calculation result of each state. A dynamic calibration mechanism is introduced, and the state number of a comparator is optimized in real time, so that the system can efficiently operate under different PVT conditions, the signal-to-noise ratio (SNR) is remarkably improved, the fluctuation of effective digits (ENOB) is reduced, and the multi-scene requirements of high-speed communication, precise measurement and portable equipment are met.

Description

Technical Field

[0001] The present invention relates to the technical field of analog-to-digital circuits, and in particular to a polymorphic SAR ADC optimization method and system based on automatic calibration. Background Art

[0002] The successive approximation analog-to-digital converter (SAR ADC) is an analog-to-digital conversion architecture based on bit-by-bit decision making. Its core working principle is to gradually approximate the final digital output by comparing the input analog signal with a gradually adjusted digital quantization signal. This architecture has attracted widespread attention for its high energy efficiency and relatively simple circuit implementation, especially in areas such as portable devices, communication systems, and sensors that require high low power consumption.

[0003] Traditional SAR ADC mainly uses binary comparators to make decisions, and each comparison outputs two states (0 or 1), corresponding to one bit of the digital quantity. Through bit-by-bit comparison, a typical N-bit SAR ADC requires N comparison cycles to complete a conversion. Although this architecture has significant low power advantages, its conversion speed is usually limited by the comparator decision time and bit-by-bit search time, especially in high sampling rate and high resolution application scenarios.

[0004] To overcome the speed limitations of traditional SAR ADCs, researchers have begun to explore the use of polymorphic comparators. In this architecture, more information can be output for each comparison by expanding the number of comparator output states (e.g., three-state, five-state, or more). This approach significantly reduces the number of comparison cycles required to complete a data conversion, thereby increasing data acquisition speed.

[0005] For example, a three-state comparator can output three states: "+1", "0" and "-1"; a five-state comparator is further subdivided into "-2", "-1", "0", "+1" and "+2". In these structures, the metastability of the comparator is used to define additional states. This design concept has successfully demonstrated its advantages in certain low- and medium-resolution applications, such as high-speed communication or data link systems. However, although the multi-state architecture can improve speed and resolution, its implementation faces several technical challenges:

[0006] 1) Existing three-state or five-state comparator architectures usually use a fixed number of states, which is difficult to adapt to different operating conditions, and the input voltage range corresponding to each state needs to be precisely designed to avoid data errors caused by state misjudgment. For example, when the input signal amplitude is small, a comparator with a high state number may introduce additional noise and misjudgment; while under high input signal amplitude, a comparator with a low state number may not be able to fully utilize its resolution potential. 2) Polymorphic logic requires more complex circuit implementation and will result in higher power consumption. 3) As the number of states increases, the circuit's sensitivity to process, supply voltage and temperature (PVT) changes increases significantly, resulting in performance instability. 4) Lack of automated adjustment mechanism. The calibration of polymorphic comparators mostly relies on offline static adjustment, and lacks a dynamic optimization mechanism, which makes it difficult to maintain optimal performance in actual operation. Summary of the invention

[0007] In view of the deficiencies in the prior art, the present invention provides a polymorphic SAR ADC optimization method and system based on automatic calibration. The present invention selects the optimal number of comparator states (N value) in real time through dynamic detection and adjustment to adapt to different working conditions and maximize system performance.

[0008] The technical solution of the present invention is: a polymorphic SAR ADC optimization method based on automatic calibration, comprising the following steps:

[0009] S1) collect the amplitude and frequency of the input signal in real time and monitor the key performance indicators of the ADC;

[0010] S2), design optimization objective function F(N):

[0011] F(N)=w1·SNR(N)+w2·ENOB(N)-w3·power consumption(N)-w4·false positive rate(N)

[0012] Wherein, w1, w2, w3, and w4 are all adjustable weights; SNR(N) is a function of the signal-to-noise ratio SNR; ENOB(N) is a function of the effective number of bits ENOB; N represents the number of polymorphic states of the comparator;

[0013] S3), optimizing the N value by a dynamic search algorithm, selecting the best N value suitable for the current signal condition; calculating the objective function value corresponding to each best N value, and selecting the best N value that maximizes the optimization objective function as the best N value;

[0014] S4), adjusting the number of states of the polymorphic comparator according to the optimal N value;

[0015] S5) Provide real-time feedback on the results of each acquisition cycle, store and compare the performance calculation results of each state, and adjust the selection of N value in real time.

[0016] Preferably, in step S1), the amplitude and frequency information of the analog signal is collected by an input signal processing circuit, and the key performance indicators of the monitoring ADC include signal-to-noise ratio SNR, total harmonic distortion THD, and effective number of bits ENOB.

[0017] Preferably, in step S3), the dynamic search algorithm is a heuristic search algorithm or a stepwise approximation method, and the heuristic search algorithm includes but is not limited to a genetic algorithm or a particle swarm optimization algorithm.

[0018] Preferably, in step S4), the polymorphic comparator adjusts the metastable resolution time and controls the resolution window to achieve output of different state numbers; and adjusts the working mode of the polymorphic comparator through a control signal to achieve dynamic switching of the N value.

[0019] Preferably, in step S4), the polymorphic comparator is based on a strong feedback comparator and is added with a polymorphic logic control unit. By controlling the polymorphic logic control unit, the adjustability of the number of states and the metastable window is achieved; the polymorphic comparator first receives an input signal and performs a preliminary comparison on the signal, and at the same time adjusts the metastable resolution time by controlling the clock signal of the input stage of the polymorphic comparator; the resolution window is precisely controlled by adjusting the clock signal; and then different state values ​​are output according to the amplitude of the input signal and given to the encoding circuit for encoding.

[0020] Preferably, the present invention further provides a multi-state SAR ADC optimization system based on automatic calibration, comprising:

[0021] An input signal processing circuit is used to collect amplitude and frequency information of the analog signal;

[0022] The automatic calibration module provides real-time feedback on the results of each acquisition cycle and stores and compares the performance calculation results of each state;

[0023] The automatic calibration module includes a performance monitoring module, a dynamic calibration algorithm module and an N value storage module; wherein,

[0024] The performance monitoring module is connected to the input signal processing circuit through the SPI bus to monitor the key performance indicators of the ADC, including the signal-to-noise ratio (SNR), total harmonic distortion (THD), and effective number of bits (ENOB); and outputs the calculation and simulation results to the dynamic calibration algorithm module;

[0025] Dynamic calibration algorithm module, used to calculate and select the optimal N value suitable for the current signal conditions;

[0026] An N value storage module, used to store the optimal N value calculated by the dynamic calibration algorithm module;

[0027] A polymorphic comparison control unit, used for adjusting the number of states of the polymorphic comparator according to the optimal N value;

[0028] The output and encoding circuit module is used to encode and output the quantization result of the state comparison control unit.

[0029] Preferably, the dynamic calibration algorithm module uses a dynamic search algorithm to optimize the N value, selects the optimal N value suitable for the current signal condition, and then calculates the N value that maximizes the optimization objective function of the optimal N value.

[0030] Preferably, the polymorphic comparator adjusts the metastable resolution time and controls the resolution window to achieve output of different state numbers; and adjusts the working mode of the polymorphic comparator through a control signal to achieve dynamic switching of the N value.

[0031] The beneficial effects of the present invention are:

[0032] 1. The present invention dynamically adjusts the number of comparator states so that the SAR ADC can maintain optimal performance under different input signals and PVT conditions. Compared with the fixed N value design, it can effectively improve the SNR and reduce the ENOB fluctuation;

[0033] 2. The present invention reduces overall power consumption by running small signal scenarios in low state number mode, and is particularly suitable for portable devices;

[0034] 3. The dynamic calibration mechanism of the present invention significantly improves the system's adaptability to process, temperature and voltage changes, ensuring reliability; and the present invention can dynamically adjust the number of states of the comparator according to the frequency and amplitude of the input signal to ensure high sampling rate and low latency;

[0035] 4. The present invention supports a variety of application scenarios such as high-speed communication (high sampling rate), high-precision instruments (high resolution) and portable devices (low power consumption);

[0036] 5. The hardware implementation of the dynamic adjustment algorithm of the present invention occupies less than 5% of the total chip area and does not significantly increase the design complexity and cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a flow chart of the method of the present invention;

[0038] Figure 2 It is a schematic diagram of the process flow of dynamic calibration of the present invention;

[0039] Figure 3 is a schematic diagram of a simulation structure in which polymorphic automatic calibration is not used in an embodiment of the present invention;

[0040] Figure 4 Schematic diagram of simulation results after state automatic calibration in an embodiment of the present invention. DETAILED DESCRIPTION

[0041] The specific implementation of the present invention will be further described below in conjunction with the accompanying drawings:

[0042] Example 1

[0043] like Figure 1 and 2 As shown, this embodiment provides a polymorphic SAR ADC optimization method based on automatic calibration, comprising the following steps:

[0044] S1) collect the amplitude and frequency of the input signal in real time and monitor the key performance indicators of the ADC;

[0045] In this embodiment, the amplitude and frequency information of the analog signal is collected through the input signal processing circuit. The key performance indicators of the monitoring ADC include signal-to-noise ratio SNR, total harmonic distortion THD, and effective number of bits ENOB.

[0046] S2), design optimization objective function F(N):

[0047] F(N)=w1·SNR(N)+w2·ENOB(N)-w3·power consumption(N)-w4·false positive rate(N)

[0048] Wherein, w1, w2, w3, and w4 are all adjustable weights; SNR(N) is a function of the signal-to-noise ratio (SNR); ENOB(N) is a function of the effective number of bits (ENOB); N represents the number of polymorphic states of the comparator; In this embodiment, different weights can be selected according to different scenario requirements, and the specific values ​​of the weights can be obtained through experimental calibration. For example, for communication scenarios with high signal-to-noise ratio (SNR) priority, w1 = 0.7, w2 = 0.2, w3 = 0.05, and w4 = 0.05. In low power consumption scenarios, w3 and w4 can be appropriately increased. For high-precision applications, w1 and w2 should account for more than 80% of the total weight.

[0049] S3), optimizing the N value through a dynamic search algorithm, selecting the optimal N value suitable for the current signal condition; and calculating the objective function value corresponding to each optimal N value, and selecting the N value that maximizes the optimization objective function;

[0050] In this embodiment, the dynamic search algorithm is a heuristic search algorithm or a stepwise approximation method, and the heuristic search algorithm includes but is not limited to a genetic algorithm or a particle swarm optimization algorithm.

[0051] In this embodiment, if the successive approximation method is used to optimize the N value, the following steps are specifically included:

[0052] S311), initialization:

[0053] 1. Input parameter settings;

[0054] Set the search N value range. In this embodiment, min To N max , corresponding to the possible range of states of the polymorphic comparator;

[0055] 2. Set the algorithm type, such as genetic algorithm, particle swarm optimization, simulated annealing;

[0056] 3. The initial search step size ΔN is used to control the search granularity;

[0057] 4. Define stopping conditions, such as the maximum number of iterations (T max ), objective function convergence threshold, etc.

[0058] 5. Initialize the search space and generate an initial candidate N value set N candidate = {N1, N2, ..., N k}, these N values ​​are all in [N min N max ] range.

[0059] S312), signal feature acquisition and preprocessing:

[0060] 1. Collect the amplitude and frequency information of the input signal in real time;

[0061] 2. Perform necessary preprocessing on the input signal data, including filtering, denoising, amplitude normalization, etc., to ensure data accuracy;

[0062] 3. Determine the parameters that need to be monitored for the key performance indicators of the ADC, including: signal-to-noise ratio (SNR), total harmonic distortion (THD), effective number of bits (ENOB), etc.

[0063] S313), search iteration process:

[0064] Step 1: From the current N value set N 候选 Choose one N i ;

[0065] Step 2: Obtain various performance indicators under the N value through signal feature collection and preprocessing;

[0066] Step 3: Substitute the above indicators into the objective function F(N) to obtain the objective function value (F(N)) of the current N value. i ));

[0067] Step 4: Update the search results and compare the current F(N i ) and the historical best objective function value F best ; If F(N i )>F best , then update F bestand the corresponding N best ; Otherwise, reduce the step size or change direction;

[0068] Step 5: Update the N value set according to the rules of the search algorithm;

[0069] Step 6: Determine the stopping condition. If the maximum number of iterations T is reached max , or the objective function converges to the threshold, stop searching; otherwise, continue iterating.

[0070] Confirm N best After the optimal N value under the current signal conditions is obtained, it is stored in N opt and N opt Output, for use in the subsequent step S4) to adjust the state number of the polymorphic comparator; at the same time, store the current signal condition and N opt The corresponding relationship provides a reference for subsequent real-time adjustment.

[0071] As a preferred embodiment of this embodiment, if this embodiment selects a genetic algorithm to optimize the N value, the following steps are specifically included:

[0072] 1. Population initialization:

[0073] An initial population is randomly generated, each individual represents a possible N value configuration (such as N1, N2, ..., N k );

[0074] Each individual is coded as a binary or real number;

[0075] Initialize the population size P and the maximum number of iterations T max ;

[0076] 2. Fitness evaluation:

[0077] For each individual N i Calculate its objective function value F(N i ), taking the objective function value as the fitness value;

[0078] 3. Select an action:

[0079] Use roulette wheel method or tournament selection method to select individuals with high fitness from the current population to enter the mating pool;

[0080] 4. Crossover operation:

[0081] Pair the individuals in the mating pool in pairs and perform a crossover operation to generate new individuals; for example, use the single-point crossover method to exchange some of the genes of two individuals at a random position;

[0082] 5. Mutation operation:

[0083] With a certain probability Pmutate Randomly change some gene values ​​of individuals to prevent them from falling into local optimality;

[0084] 6. Population update:

[0085] Add the newly generated individuals to the population, and select the top P best individuals according to the fitness value to form a new generation of population;

[0086] 7. Termination condition check:

[0087] If the maximum number of iterations T is reached max Or the objective function value converges, terminate the algorithm and output the optimal N value. Otherwise, return to step 2.

[0088] As a preferred embodiment of this embodiment, if this embodiment selects the particle swarm optimization algorithm to optimize the N value, it specifically includes the following steps:

[0089] 1. Particle initialization:

[0090] Initialize the particle swarm randomly, each particle represents an N value configuration. Initialize the position X of each particle i and speed V i ; Set the particle swarm size P and the maximum number of iterations T max .

[0091] 2. Fitness evaluation:

[0092] Calculate the objective function value F(X) of each particle's current N value i );

[0093] Update the individual optimal position Pi and the global optimal position G of the particle;

[0094] 3. Speed ​​update:

[0095] Update particle velocity according to the formula:

[0096] V i =w·V i +c1·r1·(P i -X i )+c2·r2·(GX i )

[0097] Among them: w is the inertia weight, which controls the movement trend of particles; c1, c2 are learning factors, which represent the weights of individual and global experience; r1, r2 are random numbers.

[0098] 4. Location Update:

[0099] Update the particle position according to the formula:

[0100] X i =X i+V i

[0101] 5. Fitness evaluation and update:

[0102] Calculate the new objective function value F(X i );Update individual optimal position P i and the global optimal position G.

[0103] 6. Termination condition check:

[0104] If the maximum number of iterations T is reached max Or the objective function value converges, terminate the algorithm and output the optimal N value. Otherwise, return to step 3.

[0105] S4), adjusting the number of states of the polymorphic comparator according to the optimal N value;

[0106] The polymorphic comparator adopts a strong feedback comparator and adds a polymorphic logic control unit. By controlling the polymorphic logic control unit, the adjustability of the state number and the metastable window is achieved; the polymorphic comparator first receives the input signal and performs a preliminary comparison on the signal, and at the same time adjusts the metastable resolution time by controlling the clock signal of the input stage of the polymorphic comparator; the resolution window is accurately controlled by adjusting the clock signal; and then different state values ​​are output according to the amplitude of the input signal and given to the encoding circuit for encoding.

[0107] In this embodiment, the polymorphic comparator adjusts the metastable resolution time and controls the resolution window to achieve output of different state numbers; achieves output of different state numbers (such as three states, five states or more states); and adjusts the working mode of the polymorphic comparator through a control signal to achieve dynamic switching of the N value.

[0108] In this embodiment, a lower N value (such as tri-state) may be selected under small signal amplitude to reduce power consumption; and when a large signal is input, the N value may be automatically increased to improve the resolution of data conversion.

[0109] In this embodiment, the number of states of the comparator is adjusted according to the optimal N value, specifically:

[0110] Adjust the metastable resolution time of the comparator:

[0111] Using the metastable characteristics of the comparator, different metastable resolution times correspond to different output resolutions; when determining the N value, it can be achieved by adjusting the metastable resolution time of the comparator:

[0112] Metastable resolution time T meta Determines the output state resolution of the comparator; shorter T meta The number of output states will be reduced, and a longer T metaThe input differential signal can be resolved more accurately, increasing the number of states.

[0113] By controlling the clock cycle or enable signal at the comparator input stage, the metastable resolution time can be extended or shortened; the clock frequency can be adjusted to accurately control the resolution window.

[0114] Adjust the comparator input sensitivity:

[0115] The input sensitivity of the comparator directly affects the number of states it can distinguish; when the sensitivity is higher, smaller input differential signals can be mapped into different states, thereby increasing the number of states.

[0116] Adjust the gain of the input transconductance amplifier (e.g., by changing the input current or resistor value); use a front-end amplifier with adjustable gain to dynamically adjust the sensitivity to match the target N value; that is, add a programmable gain control (PGA) at the input to enhance signal resolution capabilities.

[0117] Reconfigure the backend digital encoding logic:

[0118] After the comparator's state number N is adjusted, its corresponding digital encoding logic needs to be re-matched to ensure that the back-end digital circuit can correctly identify N discrete states; adjust the resolution of the digital sampling logic to divide the metastable output signal into N uniform intervals; recalibrate the comparator's output range to map the actual output to N states.

[0119] Dynamic calibration mechanism:

[0120] After adjusting the number of comparator states, it is necessary to ensure the accuracy of state division and optimize the state range through dynamic calibration. The metastable output characteristics of the comparator (such as signal amplitude or delay time) can be monitored. The input gain, resolution time or bias current can be dynamically adjusted according to the monitoring results to ensure the stability of the state number N.

[0121] S5) Provide real-time feedback on the results of each acquisition cycle, store and compare the performance calculation results of each state, and adjust the selection of N value in real time.

[0122] This embodiment updates the N value selection of the system after each performance evaluation to cope with changes in input signals and system environment, and ensures the stability and reliability of the system during long-term operation through continuous signal sampling, performance evaluation and application of optimization algorithms.

[0123] Example 2

[0124] This embodiment provides a multi-state SAR ADC optimization system based on automatic calibration, including:

[0125] An input signal processing circuit is used to collect amplitude and frequency information of the analog signal;

[0126] The automatic calibration module provides real-time feedback on the results of each acquisition cycle and stores and compares the performance calculation results of each state;

[0127] The automatic calibration module includes a performance monitoring module, a dynamic calibration algorithm module and an N value storage module; wherein,

[0128] The performance monitoring module is connected to the input signal processing circuit through the SPI bus to monitor the key performance indicators of the ADC, including the signal-to-noise ratio (SNR), total harmonic distortion (THD), and effective number of bits (ENOB); and outputs the calculation and simulation results to the dynamic calibration algorithm module;

[0129] Dynamic calibration algorithm module, used to calculate and select the optimal N value suitable for the current signal conditions;

[0130] An N value storage module, used to store the optimal N value calculated by the dynamic calibration algorithm module;

[0131] A polymorphic comparison control unit, used for adjusting the number of states of the polymorphic comparator according to the optimal N value;

[0132] The output and encoding circuit module is used to encode and output the quantization result of the state comparison control unit.

[0133] As a preferred embodiment of the present invention, the dynamic calibration algorithm module uses a dynamic search algorithm to optimize the N value, selects the optimal N value suitable for the current signal condition, and then calculates the N value that maximizes the optimization objective function of the optimal N value.

[0134] In this embodiment, the expression of the optimization objective function is:

[0135] F(N)=w1·SNR(N)+w2·ENOB(N)-w3·power consumption(N)-w4·false positive rate(N)

[0136] Wherein, w1, w2, w3, and w4 are all adjustable weights; SNR(N) is a function of the signal-to-noise ratio (SNR); ENOB(N) is a function of the effective number of bits (ENOB); and N represents the number of polymorphic states of the comparator.

[0137] In this embodiment, different weights can be selected according to different scenario requirements. The specific weight values ​​can be obtained through experimental calibration. For example, for communication scenarios with high signal-to-noise ratio (SNR) priority, w1 = 0.7, w2 = 0.2, w3 = 0.05, w4 = 0.05. In low power consumption scenarios, w3 and w4 can be appropriately increased. For high-precision applications, w1 and w2 should account for more than 80% of the total weight.

[0138] In this embodiment, the dynamic search algorithm adopts a heuristic search algorithm or a step-by-step approximation method, and the heuristic search algorithm includes but is not limited to a genetic algorithm or a particle swarm optimization algorithm.

[0139] As a preferred embodiment of the present invention, the polymorphic comparator adjusts the metastable resolution time and controls the resolution window to achieve output of different state numbers; and adjusts the working mode of the polymorphic comparator through a control signal to achieve dynamic switching of the N value.

[0140] In this embodiment, the polymorphic comparator is based on a strong feedback comparator and is added with a polymorphic logic control unit. By controlling the polymorphic logic control unit, the adjustability of the number of states and the metastable window is achieved; the polymorphic comparator first receives an input signal and performs a preliminary comparison on the signal, and at the same time adjusts the metastable resolution time by controlling the clock signal of the input stage of the polymorphic comparator; the resolution window is precisely controlled by adjusting the clock signal; and then different state values ​​are output according to the amplitude of the input signal and given to the encoding circuit for encoding.

[0141] Figure 3 , 4 The simulation results of the architecture are verified by simulation in this embodiment, wherein Figure 3 Because the polymorphic automatic calibration circuit is not used, it can be seen that the ENOB is only 6.75 bits. Figure 4 The simulation results after using the state automatic calibration circuit show that ENOB is improved to 8.01bit. It can be seen that this architecture can effectively improve SNR and reduce ENOB fluctuations.

[0142] The above embodiments and descriptions are only for illustrating the principles and best embodiments of the present invention. Without departing from the spirit and scope of the present invention, the present invention may be subject to various changes and improvements, all of which fall within the scope of the present invention to be protected.

Claims

1. A polymorphic SAR ADC optimization method based on automatic calibration, characterized in that: The steps include: S1) collect the amplitude and frequency of the input signal in real time and monitor the key performance indicators of the ADC; S2), design optimization objective function F(N): F(N)=w1·SNR(N)+w2·ENOB(N)-w3·power consumption(N)-w4·false positive rate(N) Wherein, w1, w2, w3, and w4 are all adjustable weights; SNR(N) is a function of the signal-to-noise ratio SNR; ENOB(N) is a function of the effective number of bits ENOB; N represents the number of polymorphic states of the comparator; S3), searching and optimizing the N value through a dynamic search algorithm, selecting the best N value suitable for the current signal condition; calculating the objective function value corresponding to each best N value, and selecting the best N value that maximizes the optimization objective function as the best N value; S4), adjusting the number of states of the polymorphic comparator according to the optimal N value; S5) Provide real-time feedback on the results of each acquisition cycle, store and compare the performance calculation results of each state, and adjust the selection of N value in real time.

2. The method for optimizing a polymorphic SAR ADC based on automatic calibration according to claim 1, characterized in that: In step S1), the amplitude and frequency information of the analog signal are collected through the input signal processing circuit, and the key performance indicators of the monitoring ADC include signal-to-noise ratio SNR, total harmonic distortion THD, and effective number of bits ENOB.

3. The method for optimizing a polymorphic SAR ADC based on automatic calibration according to claim 1, characterized in that: In step S3), the dynamic search algorithm is a heuristic search algorithm or a stepwise approximation method, and the heuristic search algorithm includes but is not limited to a genetic algorithm or a particle swarm optimization algorithm.

4. The method for optimizing a polymorphic SAR ADC based on automatic calibration according to claim 1, characterized in that: In step S4), the number of states of the comparator is adjusted according to the optimal N value, specifically: The polymorphic comparator adjusts the metastable analysis time and controls the analysis window to achieve output of different state numbers; and adjusts the working mode of the polymorphic comparator through a control signal to achieve dynamic switching of the N value.

5. The method for optimizing a polymorphic SAR ADC based on automatic calibration according to claim 4, characterized in that: In step S4), the polymorphic comparator is based on a strong feedback comparator and is added with a polymorphic logic control unit. By controlling the polymorphic logic control unit, the adjustability of the state number and the metastable window is achieved; the polymorphic comparator first receives an input signal and performs a preliminary comparison on the signal, and at the same time adjusts the metastable resolution time by controlling the clock signal of the input stage of the polymorphic comparator; By adjusting the clock signal, the parsing window is precisely controlled; then, different state values ​​are output according to the amplitude of the input signal and given to the encoding circuit for encoding.

6. A polymorphic SAR ADC optimization system based on automatic calibration, characterized in that: The system is optimized by using the method described in claims 1-5, and the system comprises: An input signal processing circuit is used to collect amplitude and frequency information of the analog signal; The automatic calibration module provides real-time feedback on the results of each acquisition cycle and stores and compares the performance calculation results of each state; The automatic calibration module includes a performance monitoring module, a dynamic calibration algorithm module and an N value storage module; wherein, The performance monitoring module is connected to the input signal processing circuit through the SPI bus to monitor the key performance indicators of the ADC, including the signal-to-noise ratio (SNR), total harmonic distortion (THD), and effective number of bits (ENOB); and outputs the calculation and simulation results to the dynamic calibration algorithm module; Dynamic calibration algorithm module, used to calculate and select the optimal N value suitable for the current signal conditions; An N value storage module, used to store the optimal N value calculated by the dynamic calibration algorithm module; A polymorphic comparison control unit, used for adjusting the number of states of the polymorphic comparator according to the optimal N value; The output and encoding circuit module is used to encode and output the quantization result of the state comparison control unit.

7. The multi-state SAR ADC optimization system based on automatic calibration according to claim 6, characterized in that: The dynamic calibration algorithm module uses a dynamic search algorithm to search and optimize the N value, selects the optimal N value suitable for the current signal condition, and then calculates the N value that maximizes the optimization objective function of the optimal N value.

8. The multi-state SAR ADC optimization system based on automatic calibration according to claim 7, characterized in that: The dynamic search algorithm is a heuristic search algorithm or a step-by-step approximation method, and the heuristic search algorithm includes but is not limited to a genetic algorithm or a particle swarm optimization algorithm.

9. The multi-state SAR ADC optimization system based on automatic calibration according to claim 7, characterized in that: The expression of the optimization objective function is: F(N)=w1·SNR(N)+w2·ENOB(N)-w3·power consumption(N)-w4·false positive rate(N)Wherein, w1, w2, w3, w4 are all adjustable weights; SNR(N) is a function of the signal-to-noise ratio SNR; ENOB(N) is a function of the effective number of bits, ENOB; N represents the number of polymorphic states of the comparator.

10. The multi-state SAR ADC optimization system based on automatic calibration according to claim 6, characterized in that: The polymorphic comparator is based on a strong feedback comparator and is added with a polymorphic logic control unit. By controlling the polymorphic logic control unit, the adjustability of the state number and the metastable window is achieved; the polymorphic comparator first receives an input signal and performs a preliminary comparison on the signal, and at the same time adjusts the metastable resolution time by controlling the clock signal of the polymorphic comparator input stage; By adjusting the clock signal, the analysis window is precisely controlled; then, different state values ​​are output according to the amplitude of the input signal and given to the output and encoding circuit module for encoding.

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