Video image real-time splicing method

Abstract

The invention relates to a video image real-time splicing method, and the method comprises the steps: carrying out the two-stage D trigger synchronization of received first video data and second video data, and obtaining the synchronized first video data and the synchronized second video data; writing the synchronized first video data into a first first-in first-out queue, and writing the synchronized second video data into a second first-in first-out queue; determining a first read effective signal and a second read effective signal according to the line synchronization signal and the data effective signal of the synchronized first video data; and according to the first read effective signal and the second read effective signal, reading data from the first first-in first-out queue and the second first-in first-out queue for splicing to obtain target video data. According to the video image real-time splicing method provided by the embodiment of the invention, real-time splicing of two paths of video data can be realized, the time sequence is stable, and image tearing is not easy to occur.

Description

Technical Field

[0001] The present application relates to the field of image processing technology, and in particular to a real-time video image stitching method. Background Art

[0002] Video image stitching technology is a technology that combines multiple video images into a continuous, wide-angle or large-size video image. It can integrate video images from different cameras to form a complete perspective. Video image stitching technology can expand the size of the image, for example, to increase the display dimension in the horizontal or vertical direction.

[0003] In some application scenarios (such as live broadcast), video image splicing is required to be performed in real time. In the related art, video image splicing adopts the method of alternating display of video images of left and right channels. That is, in the display process of a frame of video image, the left half screen image is displayed first, and then the right half screen image is displayed. When using FPGA (Field Programmable Gate Array) to implement the video image splicing technology, it is necessary to call the IP core (Intellectual Property core) provided by the FPGA manufacturer, which requires relevant configuration of the IP core. If the configuration is improper, the timing is prone to instability, resulting in image tearing. In addition, the versatility of this method is also poor. Therefore, a new real-time video image splicing method is urgently needed. Summary of the invention

[0004] In view of this, a real-time video image stitching method is proposed.

[0005] In a first aspect, an embodiment of the present application provides a method for real-time splicing of video images, the method comprising: performing two-level D flip-flop synchronization on the received first video data and the second video data to obtain synchronized first video data and synchronized second video data, the first video data being the video data of the left channel, the second video data being the video data of the right channel, and the resolution of the image corresponding to the first video data being the same as the resolution of the image corresponding to the second video data; writing the synchronized first video data into a first first-in-first-out queue, and writing the synchronized second video data into a second first-in-first-out queue, the bit width of each written data being a first preset bit width; determining a first read valid signal and a second read valid signal according to a row synchronization signal and a data valid signal of the synchronized first video data; reading data from the first first-in-first-out queue and the second first-in-first-out queue according to the first read valid signal and the second read valid signal for splicing to obtain target video data, the bit width of each read data being a second preset bit width, and the second preset bit width being twice the first preset bit width.

[0006] In some possible implementations, determining a first read valid signal and a second read valid signal based on a line synchronization signal and a data valid signal of the synchronized first video data includes: determining a first read valid signal based on the line synchronization signal and the data valid signal of the synchronized first video data when it is detected that the line synchronization signal of the synchronized first video data is valid; and determining a second read valid signal based on the first read valid signal.

[0007] In some possible implementations, determining the first read valid signal based on the line synchronization signal and the data valid signal of the synchronized first video data includes: setting the value of the first counter to 0 when it is detected that the line synchronization signal of the synchronized first video data is valid; detecting whether the data valid signal of the synchronized first video data is 1 in each clock cycle; adding 1 to the value of the first counter when it is detected that the data valid signal of the synchronized first video data is 1; and setting the first read valid signal to 1 when the value of the first counter is between N and 2N, where N is used to indicate half of the length of the data valid signal of the synchronized first video data, and N is a positive integer.

[0008] In some possible implementations, determining the first read valid signal according to the row synchronization signal and the data valid signal of the synchronized first video data includes: when the value of the first counter is greater than 2N, setting the first read valid signal to 0.

[0009] In some possible implementations, determining the second read valid signal based on the first read valid signal includes: when a falling edge of the first read valid signal is detected, setting the second read valid signal to 1 and setting the value of the second counter to 0; adding 1 to the value of the second counter, and determining whether the value of the second counter is less than N; when the value of the second counter is less than N, performing the following steps in the next clock cycle: adding 1 to the value of the second counter, and determining whether the value of the second counter is less than N.

[0010] In some possible implementations, determining the second read valid signal according to the first read valid signal includes: when the value of the second counter is greater than or equal to N, setting the second read valid signal to 0.

[0011] In some possible implementations, writing the synchronized first video data into the first first-in-first-out queue includes: at the rising edge of each clock cycle, when the data valid signal of the synchronized first video data is 1, writing data of a first preset bit width in the first video data into the first first-in-first-out queue, wherein the first preset bit width is 24 bits.

[0012] In some possible implementations, the target video data includes first target data from a left channel and second target data from a right channel, and the data is read from the first first-in-first-out queue and the second first-in-first-out queue according to the first read valid signal and the second read valid signal for splicing to obtain the target video data, including: when the first read valid signal is 1, at the rising edge of each clock cycle, data of a second preset bit width is read from the first first-in-first-out queue, and the read data is used as the first target data; when the second read valid signal is 1, at the rising edge of each clock cycle, data of a second preset bit width is read from the second first-in-first-out queue, and the read data is used as the second target data.

[0013] In some possible implementations, the received first video data and the second video data are synchronized by two levels of D triggers to obtain synchronized first video data and synchronized second video data, including: performing two levels of D trigger synchronization on the received first video data through a first trigger to obtain synchronized first video data; performing two levels of D trigger synchronization on the received second video data through a second trigger to obtain synchronized second video data.

[0014] The real-time splicing method of video images of the embodiment of the present application can perform two-level D flip-flop synchronization on the received first video data and the second video data to obtain the synchronized first video data and the synchronized second video data; then perform bit width conversion on the synchronized first video data through the first first-in-first-out queue, and perform bit width conversion on the synchronized second video data through the second first-in-first-out queue, and at the same time, determine the first read valid signal and the second read valid signal according to the line synchronization signal and the data valid signal of the synchronized first video data; then, read the data from the first first-in-first-out queue and the second first-in-first-out queue according to the first read valid signal and the second read valid signal for splicing to obtain the target video data.

[0015] In this way, the left and right video data (i.e., the video data of the left and right channels) with the same resolution can be spliced ​​into one video data in real time, and then the spliced ​​video image can be obtained. Each frame of the spliced ​​video image has only one field synchronization signal and a line synchronization signal, which is displayed as a complete image. The real-time splicing method of the video image of the embodiment of the present application can not only realize the real-time splicing of two video data, but also has stable timing, is not prone to image tearing, and has strong versatility.

[0016] These and other aspects of the present application will become more apparent from the following description of the embodiment(s). BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the present application and, together with the description, serve to explain the principles of the present application.

[0018] Figure 1 A flowchart showing a method for real-time splicing of video images according to an embodiment of the present application is shown;

[0019] Figure 2 A schematic diagram showing a method of determining a first read valid signal according to an embodiment of the present application is shown;

[0020] Figure 3 A schematic diagram showing a method of determining a second read valid signal according to an embodiment of the present application is shown;

[0021] Figure 4 A timing diagram of a first first-in-first-out queue according to an embodiment of the present application is shown;

[0022] Figure 5 A timing diagram of data splicing according to an embodiment of the present application is shown;

[0023] Figure 6 A schematic diagram showing a method for real-time stitching of video images according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0024] Various exemplary embodiments, features and aspects of the present application will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0025] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0026] In addition, in order to better illustrate the present application, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present application can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present application.

[0027] In order to solve the above technical problems, the present application provides a real-time splicing method for video images. The method includes: performing two-stage D trigger synchronization on the received first video data and the second video data to obtain the synchronized first video data and the synchronized second video data, the first video data is the video data of the left channel, the second video data is the video data of the right channel, and the resolution of the image corresponding to the first video data is the same as the resolution of the image corresponding to the second video data; writing the synchronized first video data into a first first-in-first-out queue, and writing the synchronized second video data into a second first-in-first-out queue, and the bit width of each written data is a first preset bit width; determining a first read valid signal and a second read valid signal according to the line synchronization signal and the data valid signal of the synchronized first video data; reading data from the first first-in-first-out queue and the second first-in-first-out queue according to the first read valid signal and the second read valid signal for splicing to obtain the target video data, and the bit width of each read data is a second preset bit width, and the second preset bit width is twice the first preset bit width.

[0028] The real-time splicing method of video images of the embodiment of the present application can perform two-level D flip-flop synchronization on the received first video data and the second video data to obtain the synchronized first video data and the synchronized second video data; then perform bit width conversion on the synchronized first video data through the first first-in-first-out queue, and perform bit width conversion on the synchronized second video data through the second first-in-first-out queue, and at the same time, determine the first read valid signal and the second read valid signal according to the line synchronization signal and the data valid signal of the synchronized first video data; then, read the data from the first first-in-first-out queue and the second first-in-first-out queue according to the first read valid signal and the second read valid signal for splicing to obtain the target video data.

[0029] In this way, the left and right video data (i.e., the video data of the left and right channels) with the same resolution can be spliced ​​into one video data in real time, and then the spliced ​​video image can be obtained. Each frame of the spliced ​​video image has only one field synchronization signal and a line synchronization signal, which is displayed as a complete image. The real-time splicing method of the video image of the embodiment of the present application can not only realize the real-time splicing of two video data, but also has stable timing, is not prone to image tearing, and has strong versatility.

[0030] The real-time splicing method of video images in the embodiment of the present application can be implemented by FPGA. FPGA has powerful parallel processing capabilities and can realize real-time processing of video data, which is crucial for video image splicing, because video image splicing needs to complete the splicing work while receiving the video stream to ensure the continuity and real-time performance of video playback. FPGA can also accurately control the synchronization of video frames, which is particularly critical for the smoothness and consistency of the spliced ​​video. In addition, FPGA can adapt to different video formats and standards, and can be well compatible with various input and output video formats.

[0031] The real-time video image splicing method of the embodiment of the present application is used to splice the video data of the left and right channels in the horizontal direction. Compared with the video data of the left and right channels, after the spliced ​​video data is displayed as an image, its width increases, that is, the number of pixels per row in the image increases.

[0032] Figure 1 FIG. 1 is a flowchart of a method for real-time splicing of video images according to an embodiment of the present application. Figure 1 , the real-time video image stitching method comprises:

[0033] Step S11, performing two-stage D flip-flop synchronization on the received first video data and second video data to obtain synchronized first video data and synchronized second video data.

[0034] FPGA can receive video data of the left and right channels, and can determine the video data of the left channel as the first video data, and the video data of the right channel as the second video data. The resolution of the image corresponding to the first video data is the same as the resolution of the image corresponding to the second video data. For example, the image corresponding to the first video data is the video image of the left channel, and its resolution is 2400*1440, and the image corresponding to the second video data is the video image of the right channel, and its resolution is also 2400*1440, that is, the resolutions of the two are the same. Both the first video data and the second video data can use the RGB888 color format to transmit data. Under the RGB888 color format, each pixel data is 3 bytes, that is, the bit width of the first video data and the second video data is 24 bits.

[0035] Since the timing of the first video data and the second video data may be unstable, the received first video data and the second video data may be synchronized by two-stage D flip-flops to obtain the synchronized first video data and the synchronized second video data.

[0036] In some possible implementations, step S11 may include: performing a two-stage D trigger synchronization on the received first video data through a first trigger to obtain synchronized first video data; and performing a two-stage D trigger synchronization on the received second video data through a second trigger to obtain synchronized second video data.

[0037] When performing two-stage D flip-flop synchronization, the first video signal can be double-beat by the first trigger to achieve two-stage D flip-flop synchronization, and then the synchronized first video signal is output. The first trigger is a two-beat trigger. Performing two-stage D flip-flop synchronization on the first video signal by the first trigger can improve the stability and reliability of the first video data during transmission and reduce the probability of metastable state.

[0038] The second video signal can be double-beat by the second trigger to achieve two-stage D trigger synchronization, and then the synchronized second video signal is output. The second trigger is a two-beat trigger. The second video signal is synchronized with the two-stage D trigger by the second trigger, which can improve the stability and reliability of the second video data during transmission and reduce the probability of metastable state.

[0039] Step S12, writing the synchronized first video data into a first FIFO queue, and writing the synchronized second video data into a second FIFO queue, wherein the bit width of the data written each time is a first preset bit width.

[0040] When writing the synchronized first video data into the first FIFO queue, data of one row is written continuously each time. The data valid signal of the synchronized first video data can be used as the write enable signal of the first FIFO queue. At the rising edge of each clock cycle, when the data valid signal of the synchronized first video data is 1, the data of the first preset bit width in the first video data can be written into the first FIFO queue.

[0041] Among them, the width of the first FIFO queue is the first preset bit width, and the first preset bit width can be used to indicate the size of a pixel data. For example, in the color format of RGB888, each pixel data is 3 bytes, that is, 24 bits (bit), so the first preset bit width can be set to 24 bits. The depth of the first FIFO queue can be set according to the actual situation, as long as it can store a row of data. For example, the image corresponding to the first video data is a video image of the left channel, and its resolution is 2400*1440, then, each row has 2400 pixels, and correspondingly, each row has 2400 pixel data. Based on this, the depth of the first FIFO queue can be set to 2056. It should be noted that only the width and depth of the first FIFO queue are exemplarily described here. In practical applications, those skilled in the art can set the specific values ​​of the width and depth of the first FIFO queue according to the actual situation, and this application does not limit this.

[0042] At the same time, when the synchronized second video data is written into the second FIFO queue, data of one row can be written continuously each time. The data valid signal of the synchronized second video data can be used as the write enable signal of the second FIFO queue. At the rising edge of each clock cycle, when the data valid signal of the synchronized second video data is 1, the data of the first preset bit width in the second video data can be written into the second FIFO queue. The depth and width of the second FIFO queue are the same as the depth and width of the first FIFO queue.

[0043] Step S13, determining a first read valid signal and a second read valid signal according to the synchronized line synchronization signal and the data valid signal of the first video data.

[0044] Step S13 can be performed in parallel with step S12. After the FPGA is powered on, each clock cycle loop detects whether the line synchronization signal (hsync) of the synchronized first video data is valid. When it is detected that the line synchronization signal of the synchronized first video data is valid, the first read valid signal and the second read valid signal can be determined according to the line synchronization signal and the data valid signal (de) of the synchronized first video data. Among them, the value of the first read valid signal is 0 (low level) or 1 (high level). When the first read valid signal is 0, no data is read. When the first read valid signal is 1, the data of the left channel is read. The value of the second read valid signal is 0 (low level) or 1 (high level). When the second read valid signal is 0, no data is read. When the second read valid signal is 1, the data of the right channel is read.

[0045] In some possible implementations, step S13 may include: when it is detected that the line synchronization signal of the synchronized first video data is valid, determining a first read valid signal based on the line synchronization signal and the data valid signal of the synchronized first video data; and determining a second read valid signal based on the first read valid signal.

[0046] When it is detected that the line synchronization signal of the first video data after synchronization is valid, the first read valid signal can be determined first according to the line synchronization signal and the data valid signal of the first video data after synchronization. Specifically, when it is detected that the line synchronization signal of the first video data after synchronization is valid, it is considered that a line of video data will be transmitted next, and the value of the first counter can be set to 0, and then in each clock cycle, it is cyclically detected whether the data valid signal of the first video data after synchronization is 1. When it is detected that the data valid signal of the first video data after synchronization is 1, the value of the first counter is increased by 1, and it is determined whether the value of the first counter is between N and 2N, that is, it is determined whether the value of the first counter is greater than or equal to N and less than or equal to 2N. Among them, 2N is used to indicate the length of the data valid signal of the first video data after synchronization, N is used to indicate half of the length of the data valid signal of the first video data after synchronization, and N is a positive integer.

[0047] When the value of the first counter is between N and 2N, the first read valid signal is set to 1. Then it is determined whether the value of the first counter is greater than 2N; when the value of the first counter is less than or equal to 2N, the next clock cycle detection is performed; when the value of the first counter is greater than 2N, the first read valid signal is set to 0, and the next row synchronization signal is waited to be valid.

[0048] Figure 2 FIG. 2 is a schematic diagram showing a method for determining a first read valid signal according to an embodiment of the present application. Figure 2The specific process of determining the first read valid signal is as follows: after the FPGA is powered on, execute step S201, and cyclically detect whether the line synchronization signal of the synchronized first video data is valid in each clock cycle; if no valid line synchronization signal is detected, continue to execute step S201 for cyclic detection; if the line synchronization signal is detected to be valid, execute step S202, set the value of the first counter to 0, that is, clear the first counter.

[0049] Then execute step S203, and in each clock cycle, cyclically detect whether the data valid signal of the first video data is 1; if the data valid signal of the first video data is detected to be 0, continue to execute step S203 for cyclic detection; if the data valid signal of the first video data is detected to be 1, execute step S204, add 1 to the value of the first counter, and execute step S205 to determine whether the value of the first counter is between N and 2N; if the value of the first counter is not between N and 2N (that is, the value of the first counter is less than N), execute step S203 to perform detection in the next clock cycle; if the value of the first counter is between N and 2N, execute step S206, set the first read valid signal to 1, and then execute step S207 to determine whether the value of the first counter is greater than 2N; if the value of the first counter is not greater than 2N, execute step S203 to perform detection in the next clock cycle; if the value of the first counter is greater than 2N, execute step S208 to set the first read valid signal to 0.

[0050] From the above, it can be seen that when the value of the first counter is less than N, the value of the first read valid signal is 0, and no data is read; when the value of the first counter is between N and 2N, the value of the first read valid signal is 1, and the data of the left channel can be read from the first first-in-first-out queue; when the value of the first counter is greater than 2N, the value of the first read valid signal is 0, and no data is read, waiting for the next row synchronization signal to be valid.

[0051] In some possible implementations, the second read valid signal can be determined based on the first read valid signal. Specifically, after the FPGA is powered on, the falling edge of the first read valid signal can be detected in each clock cycle cycle; when the falling edge of the first read valid signal is detected, the second read valid signal is set to 1, and the value of the second counter is set to 0, that is, the second counter is cleared; then the second counter is incremented by 1, and it is determined whether the value of the second counter is less than N; when the value of the second counter is less than N, in the next clock cycle, the step of "incrementing the second counter by 1, and determining whether the value of the second counter is less than N" is continued; when the value of the second counter is greater than or equal to N, the second read valid signal is set to 0. In this way, it can be ensured that after each line of data in the left channel video data is read, the corresponding line of data in the right channel video data is immediately read.

[0052] Figure 3 FIG. 2 is a schematic diagram showing a method for determining a second read valid signal according to an embodiment of the present application. Figure 3 , the specific process of determining the second read valid signal is as follows: after the FPGA is powered on, execute step S301, and cyclically detect the falling edge of the first read valid signal in each clock cycle; if the falling edge of the first read valid signal is not detected, continue to execute step S301 for cyclic detection. If the falling edge of the first read valid signal is detected, execute step S302, set the second read valid signal to 1, and set the value of the second counter to 0. Then execute step S303, add 1 to the value of the second counter, and step S304, determine whether the value of the second counter is less than N; if the value of the second counter is less than N, then in the next clock cycle, continue to execute step S303 and step S304; if the value of the second counter is greater than or equal to N, execute step S305, and set the second read valid signal to 0.

[0053] From the above, it can be seen that when the value of the second counter is less than N, the value of the second read valid signal is 1, and the data of the right channel can be read from the second first-in-first-out queue; when the value of the second counter is greater than or equal to N, the value of the second read valid signal is 0, and no data is read.

[0054] The length of the data valid signal of the first video data after synchronization is the same as the length of the data valid signal of the second video data after synchronization. N can be used to indicate half of the length of the data valid signal of the first video data after synchronization, and the length of the data valid signal of the first video data after synchronization is 2N clocks. The length of the first read valid signal is N clocks, and the length of the second read valid signal is also N clocks, and the lengths of the two are the same. For example, assuming that the lengths of the data valid signals of the first video data and the second video data after synchronization are both 100 clocks, then N is equal to 50, the length of the first read valid signal is 50 clocks, and the length of the second read valid signal is also 50 clocks.

[0055] Step S14, according to the first read valid signal and the second read valid signal, read data from the first FIFO queue and the second FIFO queue for splicing to obtain target video data.

[0056] The bit width of each read data is the second preset bit width, which is twice the first preset bit width. For example, when the first preset bit width is 24 bits, the second preset bit width is 48 bits.

[0057] The target video data is a row of spliced ​​data, which includes first target data from the left channel and second target data from the right channel.

[0058] In some possible implementations, step S14 may include: when the first read valid signal is 1, at the rising edge of each clock cycle, data of a second preset bit width is read from the first first-in-first-out queue, and the read data is used as the first target data; when the second read valid signal is 1, at the rising edge of each clock cycle, data of a second preset bit width is read from the second first-in-first-out queue, and the read data is used as the second target data.

[0059] During data splicing, when the first read valid signal is 1, at the rising edge of each clock cycle, data of the second preset bit width can be read from the first FIFO queue, and the read data is used as the first target data, and the first target data is the data from the left channel. The bit width of the data read from the first FIFO queue each time is the second preset bit width, which is twice the bit width (first preset bit width) of the data written each time, so that the video data of the left channel can be compressed by reading and writing the first FIFO queue. For example, the video data of 100 clocks of the left channel is compressed into the video data of 50 clocks.

[0060] When the first read valid signal is 0, the second read valid signal is 1, so that after each row of data transmission in the left channel is completed, the data of the corresponding row of the right channel can be transmitted immediately to achieve the splicing of each row of data. When the second read valid signal is 1, at the rising edge of each clock cycle, data of the second preset bit width can be read from the second first-in-first-out queue, and the read data is used as the second target data. The second target data is the data from the right channel. The bit width of the data read from the second first-in-first-out queue each time is the second preset bit width, which is twice the bit width (first preset bit width) of the data written each time, so that the video data of the right channel can be compressed by reading and writing the second first-in-first-out queue. For example, the video data of 100 clocks of the right channel is compressed into video data of 50 clocks.

[0061] The above data splicing method can be implemented through a data selector, the input of the data selector is the first read valid signal, the second read valid signal, the data read from the first first-in-first-out queue and the data read from the second first-in-first-out queue, and the output is the target video data.

[0062] Figure 4 FIG. 2 shows a timing diagram of a first FIFO queue according to an embodiment of the present application. Figure 4, the duration of the data valid signal of the synchronized first video data being 1 is 2N clock cycles. During the 2N clock cycles when the data valid signal of the first video data is 1, a row of data d(1), d(2), …, d(2N-1), d(2N) in the first video data is written into the first FIFO queue. Each data is 24 bits, and one data is written at a time, that is, the bit width of the data written each time is 24 bits.

[0063] The duration of the first read valid signal being 1 is N clock cycles. In the N clock cycles when the first read valid signal is 1, data is read from the first FIFO queue. The bit width of each read data is twice the bit width of the written data, that is, two data are read each time, and the bit width of the read data is 48 bits. When reading, the data is arranged in a way that the high 24 bits are in the front and the low 24 bits are in the back. For example, in the N clock cycles when the first read valid signal is 1, the two data read in the first clock cycle are d(2) and d(1), d(2) is in the front and d(1) is in the back; the two data read in the second clock cycle are d(4) and d(3), d(4) is in the front and d(3) is in the back, ..., the two data read in the Nth clock cycle are d(2N) and d(2N-1), d(2N) is in the front and d(2N-1) is in the back.

[0064] Figure 5 FIG. 2 is a schematic diagram showing a timing diagram of data splicing according to an embodiment of the present application. Figure 4 , N is equal to 50. When the first read valid signal is 1, at the rising edge of each clock cycle, data is read from the first FIFO queue, that is, the data of the left channel is read. The 50 data read are d11, d12, ..., d149, d150, and these 50 data are used as the first target data in the target video data.

[0065] When the first read valid signal becomes 0, the value of the second read valid signal is 1. At the rising edge of each clock cycle, data is read from the second first-in-first-out queue, that is, the data of the right channel is read. The 50 data read are dr1, dr2, ..., dr49, dr50, and these 50 data are used as the second target data in the target video data.

[0066] When each line synchronization signal is valid, the output target video data is: dl1, dl2, ..., dl49, dl50, dr1, dr2, ..., dr49, dr50.

[0067] In some possible implementations, after obtaining the target video data, the target video data can be double-beat by a third trigger to achieve synchronization of two-stage D flip-flops, and then the synchronized target video data is output. In this way, the stability and reliability of the target video data during transmission can be improved.

[0068] Figure 6 A schematic diagram of a real-time video image stitching method according to an embodiment of the present application is shown. Figure 6 When the first video data 601 from the left channel is received, the first video data 601 is beat twice by the first trigger 602 to perform two-stage D trigger synchronization to obtain the synchronized first video data 603; then at the rising edge of each clock cycle, when the data valid signal 604 of the synchronized first video data 603 is 1, the data of the first preset bit width in the synchronized first video data 603 is written into the first first-in-first-out queue 605, wherein the first preset bit width is 24 bits.

[0069] At the same time, when the second video data 606 from the right channel is received, the second video data 606 is beat twice by the second trigger 607 to perform two-stage D trigger synchronization to obtain the synchronized second video data 608; then at the rising edge of each clock cycle, when the data valid signal (not shown in the figure) of the synchronized second video data 608 is 1, the data of the first preset bit width in the synchronized second video data 608 is written into the second first-in-first-out queue 609.

[0070] At the same time, in each clock cycle, it is cyclically detected whether the line synchronization signal (hsync) 610 of the synchronized first video data 603 is valid. When it is detected that the line synchronization signal 610 of the synchronized first video data 603 is valid, a first read valid signal 611 is determined according to the line synchronization signal 610 and the data valid signal 604 of the synchronized first video data 603, and a second read valid signal 612 is determined according to the first read valid signal 611.

[0071] When the first read valid signal 611 is 1, data is read from the first FIFO queue 605; when the second read valid signal 612 is 1, data is read from the second FIFO queue 609. Then the first read valid signal 611, the second read valid signal 612, the data read from the first FIFO queue 605, and the data read from the second FIFO queue 609 are used as inputs of the data selector 613. When the first read valid signal 611 is 1, the data selector 613 outputs the data read from the first FIFO queue 605, and when the second read valid signal 612 is 1, the data selector 613 outputs the data read from the second FIFO queue 609, thereby obtaining the target video data 614.

[0072] Then, the target video data 614 can be played two times by the third trigger 615 to synchronize the two-stage D triggers, thereby obtaining the synchronized target video data 616. The synchronized target video data can be output to obtain a line of the spliced ​​video image.

[0073] In practical applications, the above processing is performed on each line of the left channel video image and the right channel video image to obtain a spliced ​​video image. Each frame of the spliced ​​video image is a complete image, which has only one field synchronization signal and a line synchronization signal. The field synchronization signal and the line synchronization signal of the spliced ​​video image are determined based on the field synchronization signal and the line synchronization signal of the left channel video image.

[0074] It can be understood that the above-mentioned various method embodiments mentioned in this application can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, this application will not go into details. Those skilled in the art can understand that in the above-mentioned method of the specific implementation method, the specific execution order of each step should be determined by its function and possible internal logic.

[0075] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the device, system, method and computer program product according to multiple embodiments of the present application. In this regard, each square frame in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the logical function of the specification. In some alternative implementations, the functions marked in the square frame can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square frames can actually be executed substantially in parallel, and they can also be executed in reverse order sometimes, depending on the functions involved.

[0076] It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented by hardware that performs the corresponding function or action (such as a circuit or ASIC (Application Specific Integrated Circuit)), or can be implemented by a combination of hardware and software, such as firmware.

[0077] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0078] The embodiments of the present application have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those of ordinary skill in the art without departing from the scope of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A real-time video image stitching method, characterized in that: The method comprises: Performing two-stage D flip-flop synchronization on the received first video data and second video data to obtain synchronized first video data and synchronized second video data, wherein the first video data is video data of a left channel, the second video data is video data of a right channel, and the resolution of an image corresponding to the first video data is the same as the resolution of an image corresponding to the second video data; Writing the synchronized first video data into a first first-in-first-out queue, and writing the synchronized second video data into a second first-in-first-out queue, wherein the bit width of each written data is a first preset bit width; Determine a first read valid signal and a second read valid signal according to the synchronized line synchronization signal and the data valid signal of the first video data; According to the first read valid signal and the second read valid signal, data is read from the first FIFO queue and the second FIFO queue for splicing to obtain target video data, and the bit width of the data read each time is the second preset bit width; the second preset bit width is twice the first preset bit width.

2. The method according to claim 1, characterized in that The step of determining the first read valid signal and the second read valid signal according to the synchronized line synchronization signal and the data valid signal of the first video data comprises: When it is detected that the line synchronization signal of the synchronized first video data is valid, determining a first read valid signal according to the line synchronization signal and the data valid signal of the synchronized first video data; A second read valid signal is determined according to the first read valid signal.

3. The method according to claim 2, characterized in that The step of determining the first read valid signal according to the line synchronization signal and the synchronized data valid signal of the first video data comprises: When it is detected that the line synchronization signal of the synchronized first video data is valid, the value of the first counter is set to 0; In each clock cycle, detecting whether a data valid signal of the synchronized first video data is 1; When it is detected that the data valid signal of the synchronized first video data is 1, adding 1 to the value of the first counter; When the value of the first counter is between N and 2N, the first read valid signal is set to 1, where N is used to indicate half of the length of the data valid signal of the synchronized first video data, and N is a positive integer.

4. The method according to claim 3, characterized in that The step of determining the first read valid signal according to the line synchronization signal and the synchronized data valid signal of the first video data comprises: When the value of the first counter is greater than 2N, the first read valid signal is set to 0.

5. The method according to claim 2, characterized in that: The step of determining a second read valid signal according to the first read valid signal comprises: When a falling edge of the first read valid signal is detected, the second read valid signal is set to 1, and the value of the second counter is set to 0; Add 1 to the value of the second counter, and determine whether the value of the second counter is less than N; When the value of the second counter is less than N, in the next clock cycle, the following steps are performed: adding 1 to the value of the second counter, and determining whether the value of the second counter is less than N.

6. The method according to claim 5, characterized in that The step of determining a second read valid signal according to the first read valid signal comprises: When the value of the second counter is greater than or equal to N, the second read valid signal is set to 0.

7. The method according to claim 1, characterized in that Writing the synchronized first video data into a first first-in-first-out queue comprises: At the rising edge of each clock cycle, when the data valid signal of the synchronized first video data is 1, data of a first preset bit width in the first video data is written into the first FIFO queue, wherein the first preset bit width is 24 bits.

8. The method according to claim 1, characterized in that The target video data includes first target data from a left channel and second target data from a right channel, The method of reading data from the first FIFO queue and the second FIFO queue according to the first read valid signal and the second read valid signal for splicing to obtain target video data includes: When the first read valid signal is 1, at the rising edge of each clock cycle, data of a second preset bit width is read from the first FIFO queue, and the read data is used as the first target data; When the second read valid signal is 1, data of a second preset bit width is read from the second FIFO queue at the rising edge of each clock cycle, and the read data is used as the second target data.

9. The method according to claim 1, characterized in that: The method of performing two-stage D flip-flop synchronization on the received first video data and the second video data to obtain the synchronized first video data and the synchronized second video data comprises: Performing two-stage D-type flip-flop synchronization on the received first video data through the first flip-flop to obtain synchronized first video data; The received second video data is synchronized by two-stage D triggers through the second trigger to obtain synchronized second video data.

Images