A CMOS detector readout device and readout method with chopper function

Abstract

This invention relates to aerospace, geological exploration, and low-light detection fields, and particularly to a CMOS detector readout device with chopping, comprising a photoelectric conversion unit, a pixel readout unit, and an image readout unit. The photoelectric conversion unit includes multiple photodiodes. Each pixel readout unit corresponds to one photodiode and reads the corresponding pixel electrical signal. The image readout unit reads the electrical signal of each pixel from the multiple pixel readout units and outputs the entire image electrical signal. In the pixel readout unit, the integration unit obtains the original electrical signal from the photodiode, performs chopping processing before integration, and then performs chopping processing again on the output. After filtering by the filtering unit, the difference voltage obtained by the correlation double sampling unit is output as the pixel electrical signal by the output driving unit. This invention also includes a method. This invention utilizes chopping processing to eliminate circuit noise, increase the bandwidth range of the processable signal, and utilizes a correlation double sampling circuit to eliminate signal glitches introduced by the chopping processing.

Description

Technical Field

[0001] This invention relates to the fields of aerospace, geological exploration and low-light detection, and in particular to a CMOS detector readout device and readout method with chopper. Background Technology

[0002] With the advancement of technology and the continuous development of modern society, the requirements for detecting minute optical signals are becoming increasingly stringent. In recent years, CMOS image sensor technology has demonstrated significant advantages in the field of optical sensors, and the performance and specifications of low-noise photodetectors are constantly improving. In the field of low-light detection, noise has further become a key factor restricting the performance improvement of photodetectors. Therefore, it is necessary to improve the readout circuit structure and reduce circuit noise.

[0003] Modern CMOS integrated circuit technology is increasingly focused on improving the performance of digital circuits. This forces analog signal processing in digital environments to confront challenges posed by reduced power supply voltages and increased noise and offset voltages. For example, the operating voltage of a typical 0.35μm CMOS process has dropped to 3.3V, while the noise corner frequency of a typical MOSFET is generally greater than 100kHz, and the input offset voltage is on the order of mV. With the rapid development of integrated circuit technology, a significant trend in sensing technology is the integration of sensor readout circuits, and even the single-chip integration of microsensors and sensor readout circuits. For microsensors, because their output signals are mainly at low frequencies and have very small amplitudes, the increased offset and low-frequency noise introduced by CMOS technology pose significant challenges to the design of microsensor readout circuits. The continuous development of modern society also places increasingly higher demands on the detection of minute optical signals. Therefore, in the design of CMOS image sensor readout circuits, suppressing and eliminating noise and improving the signal-to-noise ratio are crucial.

[0004] Electronic noise in readout circuits can be mainly categorized into three types based on their generation mechanisms: First, inherent device noise, such as thermal noise and 1 / f noise of MOSFETs; second, noise caused by circuit structure and operating mode, such as channel charge injection, clock feedthrough, and KTC noise; and third, spatial noise caused by manufacturing errors, such as fixed pattern noise. This noise propagates to subsequent stages, reducing the signal-to-noise ratio and limiting the dynamic range of the output. Therefore, noise reduction is essential for readout circuit design. CTIA is one of the most widely used photodetector readout circuits, and research on CTIA noise reduction has been ongoing in recent years, mainly focusing on the treatment of KTC and 1 / f noise. Currently, the use of correlated double sampling techniques can significantly suppress KTC noise in readout circuits, but substantial reduction of 1 / f noise is primarily achieved through manufacturing processes. Summary of the Invention

[0005] The purpose of this invention is to provide a CMOS detector readout device and readout method with chopping, which mainly solves the problems existing in the prior art. It reduces the 1 / f noise of the CT IA core amplifier from the circuit aspect by using the relevant principles of chopping technology, so as to further improve the signal-to-noise ratio of the readout circuit under the existing process conditions, thereby optimizing the performance indicators of the photodetector.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is to provide a CMOS detector readout device with chopper, characterized in that it includes a photoelectric conversion unit, a pixel readout unit and an image readout unit.

[0007] The photoelectric conversion unit includes multiple photodiodes, each photodiode corresponding to a pixel; the pixel readout unit corresponds one-to-one with the photodiodes and reads the pixel electrical signal of the corresponding pixel; the image readout unit reads the pixel electrical signal from the multiple pixel readout units and outputs the entire image electrical signal.

[0008] The pixel readout unit includes an integration unit, a filtering unit, a sampling unit, and an output driving unit. The integration unit is connected to the photodiode, obtains the original electrical signal from the photodiode, performs chopping processing on it, and then performs integration processing to obtain an integrated output signal. The integration unit performs chopping processing on the integrated output signal again, and after filtering by the filtering unit, it is used as the input of the sampling unit. The sampling unit samples the difference voltage at different time points to obtain a sampling output signal, which is output as the pixel electrical signal by the output driving unit.

[0009] Furthermore, the integration unit includes an integrating capacitor, an operational amplifier module, a bias module, an input chopper module, and an output chopper module;

[0010] The integrating capacitor is connected between the input and output terminals of the operational amplifier module; the bias module is a current source connected to the operational amplifier module to provide the bias current required for the operational amplifier module to operate; the input chopper module is located before the input terminal of the operational amplifier module, and the output chopper module is located after the output terminal of the operational amplifier module to perform chopping processing on the input signal and the integrated output signal of the operational amplifier module.

[0011] Furthermore, the operational amplifier module is a capacitor transimpedance amplifier, employing a folded common-source and common-gate structure, comprising a common-source submodule and a common-gate submodule; the common-source submodule is connected to the input terminal, converting the input signal into an intermediate signal before inputting it to the common-gate submodule; the common-gate submodule, under the control of the intermediate signal, forms the amplified integral output signal; the input chopper module is positioned before the common-source submodule to chop the input signal; the output chopper module is positioned after the output of the common-gate submodule to chop the integral output signal.

[0012] Furthermore, the input chopper module and the output chopper module include a first input terminal, a second input terminal, a first output terminal, and a second output terminal, as well as four sets of CMOS devices with the same channel length; the CMOS devices satisfy dynamic element matching conditions and are controlled by a clock signal; when the clock signal is high, the first input terminal is connected to the first output terminal, and the second input terminal is connected to the second output terminal; when the clock signal is low, the first input terminal is connected to the second output terminal, and the second input terminal is connected to the first output terminal.

[0013] Furthermore, the filtering unit is an RC low-pass filter; the cutoff frequency of the RC low-pass filter is less than the chopping frequency of the integrating unit.

[0014] Furthermore, the sampling unit is a correlated dual sampling circuit, comprising a reset switch, a first sampling switch, a second sampling switch, a first sampling capacitor, and a second sampling capacitor; when the reset switch is turned on, the second sampling capacitor is discharged; the first sampling switch is connected to a reference voltage, and the first sampling capacitor is charged with the reference voltage; the second sampling switch is connected to the filtering unit, and the second sampling capacitor is charged with the filtered integral output signal; the voltage difference between the second sampling capacitor and the first sampling capacitor serves as the sampling output signal.

[0015] Furthermore, the output driving unit is a unity-gain buffer;

[0016] Furthermore, the image readout unit includes a shift register; the image readout unit is sequentially connected to different pixel readout units, reads the pixel electrical signals of different pixels, inputs them into the shift register, and is finally read out as a whole to form the entire image electrical signal.

[0017] The invention also discloses a readout method using the above-mentioned CMOS detector readout device with chopper, characterized by comprising the following steps:

[0018] Step S1: Initialize the photoelectric conversion unit, the pixel readout unit, and the image readout unit;

[0019] Step S2, the photoelectric conversion unit transmits the original electrical signal to the pixel readout unit;

[0020] Step S3: Each pixel readout unit outputs a single pixel electrical signal;

[0021] In step S4, the image reading unit sequentially reads the electrical signal of each pixel from the plurality of pixel reading units, and outputs the complete image electrical signal after splicing; if it is necessary to generate the next frame image, then jump to step S3.

[0022] Further, step S3 includes the following steps:

[0023] Step S31: Reset the integration unit and the sampling unit;

[0024] Step S32: The sampling unit starts working and performs the first sampling of the reference voltage;

[0025] Step S33: The integration unit starts working and chops the original electrical signal;

[0026] Step S34: The integration unit outputs an integrated output signal;

[0027] Step S35: The integration unit chops the integrated output signal;

[0028] Step S36: Use the filtering unit to perform low-pass filtering on the integral output signal;

[0029] Step S37: The sampling unit performs a second sampling on the filtered integral output signal;

[0030] Step S38: The sampling unit outputs the pixel electrical signal.

[0031] In view of the above technical features, the present invention has the following significant characteristics compared with the prior art:

[0032] 1. The input chopper module and output chopper module in the CMOS detector readout device with chopper of the present invention adopt the method of low-impedance node chopper and dynamic element matching, which can increase the bandwidth range of the signal that can be processed without significant deterioration of the input equivalent offset voltage.

[0033] 2. In this invention, the output of the integrating unit with chopping processing function in the CMOS detector with chopping function is optimized to a single-ended output circuit. When the common-mode output level of this single-ended output circuit shifts, it can affect the branch current through the change of self-bias voltage, thereby forming a negative feedback effect on the common-mode output level, without the need to design an additional common-mode feedback circuit.

[0034] 3. The two choppers in the output chopper module of the integrating unit with chopper processing function in the CMOS detector with chopper of the present invention dynamically switch the two PMOS transistors in the current mirror of the operational amplifier module, and further reduce the current mismatch of the current mirror by using a dynamic component matching method.

[0035] 4. The sampling unit in the CMOS detector readout device with chopper of the present invention, through the timing design of the related dual sampling circuit, can eliminate the related noise of the circuit, as well as the voltage glitches introduced by the preceding input chopper module and the output chopper module in the chopper processing.

[0036] 5. The sampling unit in the CMOS detector readout device with chopper of the present invention uses two simple capacitors as sampling circuits to obtain the difference integral voltage at two time points, eliminating the need for a subtractor and saving layout area.

[0037] 6. The CMOS detector readout device with chopper of this invention is designed and manufactured using 5V 0.5mm standard CMOS process, which is a mature process and facilitates on-chip integration design. Attached Figure Description

[0038] Figure 1 This is a system block diagram of a preferred embodiment of the CMOS detector readout device with chopper of the present invention;

[0039] Figure 2 This is a system block diagram of the pixel readout unit in a preferred embodiment of the CMOS detector readout device with chopper of the present invention;

[0040] Figure 3 This is a circuit diagram of the integration unit and the filtering unit in a preferred embodiment of the CMOS detector readout device with chopper of the present invention.

[0041] Figure 4 This is a circuit diagram of the input chopper module and the output chopper module in the integration unit of a preferred embodiment of the CMOS detector readout device with chopper of the present invention.

[0042] Figure 5 This is a circuit diagram of the sampling unit in a preferred embodiment of the CMOS detector readout device with chopper of the present invention;

[0043] Figure 6 This is a timing diagram of a preferred embodiment of the CMOS detector readout device with chopper of the present invention;

[0044] Figure 7 This is a flowchart of a preferred embodiment of the readout method of the present invention using a CMOS detector readout device with chopper;

[0045] Figure 8 This is a flowchart illustrating a preferred embodiment of the readout method of the present invention, which utilizes a CMOS detector readout device with chopper, to convert pixel electrical signals using a pixel readout unit.

[0046] In the diagram: 100 - photoelectric conversion unit, 200 - pixel readout unit, 300 - image readout unit;

[0047] 101-Photodiode;

[0048] 210 - Integrating unit, 220 - Filtering unit, 230 - Sampling unit, 240 - Output driving unit;

[0049] 211-Integrating capacitor, 212-Operational amplifier module, 213-Bias module, 214-Input chopper module, 215-Output chopper module. Detailed Implementation

[0050] The present invention will be further described below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0051] Please see Figures 1 to 5 This invention discloses a CMOS detector readout device with chopper. As shown in the figure, a preferred embodiment includes a photoelectric conversion unit 100, a pixel readout unit 200, and an image readout unit 300.

[0052] The photoelectric conversion unit 100, composed of multiple photodiodes 101, converts optical signals into electrical signals. Each photodiode 101 corresponds to a pixel. The electrical signals from all photodiodes 101 are concatenated to form an image from one photoelectric conversion. The pixel readout unit 200 corresponds one-to-one with each photodiode 101, reading the raw electrical signal of a single photodiode 101 and processing it to obtain the pixel electrical signal. The image readout unit 300 is responsible for sequentially acquiring the pixel electrical signal corresponding to each pixel from all pixel readout units 200, concatenating it to form the image electrical signal corresponding to the complete image. A key component in the image readout unit 300 is a shift register, which controls the bus switch to read out each pixel one by one. Under the control of the shift register, the image readout unit 300 is sequentially connected to each pixel readout unit 200, storing the pixel electrical signal corresponding to each pixel in the shift register. Before each new pixel electrical signal is read, the already read pixel electrical signal is shifted to make room for the new pixel electrical signal. Finally, all pixel electrical signals are read out from the shift register in one complete operation to obtain the entire image electrical signal.

[0053] In this invention, the main structural optimization is made to the pixel readout unit 200. The pixel readout unit 200 consists of an integration unit 210, a filtering unit 220, a sampling unit 230, and an output driving unit 240. The integration unit 210 is connected to a photodiode 101 (PD), obtains the original electrical signal from the photodiode 101 (PD), integrates the original electrical signal, and obtains the integrated output signal. At both the input and output terminals of the integration unit 210, the signals input to the integration unit 210 and output to the integration unit 210 are chopping. Thus, the original electrical signal undergoes two chopping processes when entering and exiting the integration unit 210, and the frequency jumps back to the original low-frequency band. However, the noise signal generated inside the integration unit 210 is only chopping processed once at the output terminal and switched to the high-frequency band. Therefore, the filtering unit 220 connected after the integration unit 210 is used to filter out the high-frequency band electrical signal, thereby removing the noise signal generated inside the integration unit 210 and outputting only the integrated output signal based on the original electrical signal. The integrated output signal, filtered by filter unit 220, is input to sampling unit 230. Filter unit 220 is an RC low-pass filter composed of C1 and R1. Its cutoff frequency is lower than the chopping frequency in integrator unit 210, thus filtering out high-frequency signals that only undergo one chopping operation. A compensation capacitor C2 with a value of 1pF is also included in filter unit 220. Sampling unit 230 performs sample-and-hold operations. It reads and holds the integrated output signal according to a preset sampling frequency, allowing image readout unit 300 to sequentially read the outputs of all pixel readout units 200 within a certain period. Sampling unit 230 itself obtains the sampled output signal by sampling the voltage difference at different time points, further eliminating the inherent signal offset of the system. The output signal of sampling unit 230 is amplified by output drive unit 240 and used as the pixel electrical signal of the current sampling unit 230. Output drive unit 240 is specifically implemented as a unity-gain buffer, enabling lossless differential signal readout.

[0054] The integrator unit 210 consists of an integrating capacitor 211, an operational amplifier module 212, a bias module 213, an input chopper module 214, and an output chopper module 215. The core component of the integrator unit 210 is the operational amplifier module 212, which is a capacitor transimpedance amplifier using a folded cascode structure. The operational amplifier module 212 and the integrating capacitor 211 are combined, with the integrating capacitor 211 connected between the input and output terminals of the operational amplifier module 212, thus utilizing the electrical characteristics of the integrating capacitor itself to perform voltage integration. The integrating capacitor 211 is a Cint with a value of 500 fF. The integration starting voltage is provided by a voltage source Vdc, connected to the input of the integrator unit 210, and set to 1V. The operational amplifier module 212 requires an externally supplied bias current for normal operation. The bias module 213 performs this function; it is a current source composed of MOSFETs PM6, PM7, PM8, NM5, NM6, NM7, NM8, and NM9. Its output is connected to the operational amplifier module 212, providing the bias current required for the operational amplifier module 212 to operate. The input chopper module 214 and the output chopper module 215 are new designs in this invention, used to filter internal thermal noise of the operational amplifier module 212. The input chopper module 214 is located before the input terminal of the operational amplifier module 212, while the output chopper module 215 is located after the output terminal of the operational amplifier module 212. The input chopper module 214 chops all input signals (raw electrical signals), while the output chopper module 215 chops all output signals (processed raw electrical signals and noise signals).

[0055] The operational amplifier module 212 is further subdivided into a common-source submodule and a common-gate submodule. The common-source submodule consists of MOSFETs PM1, PM2, and PM3. PM1 and PM2 are connected to the input terminal to convert the input signal into an intermediate signal. The common-gate submodule consists of MOSFETs PM4, PM5, NM1, NM2, NM3, and NM4. The common-gate submodule is controlled by the intermediate signal output from PM1 and PM2, and its output is the amplified integral output signal. The output of the input chopper module is connected to the gates of PM1 and PM2 in the common-source submodule to chop the input signal. There are two output chopper modules, connected to the source and drain of NM1 and NM2 in the common-gate submodule, respectively, to chop the integral output signal. The integration unit 210 includes a reset switch. When the reset switch is closed, Cint is short-circuited, the charge is cleared, and this is the initial stage of the integration unit 210. When the reset switch is turned off, the integration unit 210 starts to work. The current generated by the photodiode 101 (PD) causes the charge to accumulate on Cint, generating a linearly rising voltage at the output terminal. After passing through the filter unit 220 (low-pass filter structure), the voltage is output to the next stage sampling unit 230.

[0056] The input chopper module 214 and the output chopper module 215 have the same internal structure, including a first input terminal INP, a second input terminal INN, a first output terminal OP, and a second output terminal ON, as well as four sets of CMOS devices with the same channel length. The ratio of the PMOS channel width to the NMOS channel width is 2.5:1. The CMOS devices meet the dynamic element matching condition and are controlled by paired clock signals clk and clkb. clk and clkb are opposite square wave signals, with a high level of 5V, a low level of 0V, a duty cycle of 50%, and a period of 40kHz. When the clock signal clk is high, the first input terminal INP and the first output terminal OP are turned on, and the second input terminal INN and the second output terminal ON are turned on. When the clock signal clk is low, the first input terminal INP is connected to the second output terminal ON, and the second input terminal INN is connected to the first output terminal OP. The chopping principle is that when the signal passes through the input chopper module 214 or the output chopper module 215, a 40kHz frequency domain modulation is achieved. For the integrator 210, the input voltage signal undergoes an even number of chopping operations (twice), while the low-frequency noise (1 / f noise) generated by its own circuitry undergoes an odd number of chopping operations (once). According to the principle of chopper frequency modulation, the signal chopped an even number of times returns to the fundamental frequency, but the signal chopped an odd number of times remains at a high frequency (40kHz). Therefore, the signal and noise are separated in the frequency domain. After low-frequency filtering by the filter unit 220, the high-frequency noise is removed, achieving noise reduction.

[0057] Sampling unit 230 is a correlated dual-sampling circuit that samples the voltage difference between two time points on the integral curve to achieve FPN noise removal. It includes a first sampling switch S1, a second sampling switch S2, a reset switch S3, a first sampling capacitor C1, and a second sampling capacitor C2. Its structure is simple and easy to control. Connecting a unity-gain buffer allows for lossless differential signal readout. The first sampling switch S1, the second sampling switch S2, and the reset switch S3 operate in a specific timing sequence to complete dual sampling and hold. When the reset switch S3 is turned on, it discharges the second sampling capacitor C1. The first sampling switch S1 is connected to a reference voltage Vref, which charges the first sampling capacitor C1. The input IN terminal of the second sampling switch S2 is connected to the filter unit 220, which reads the filtered integral output signal to charge the second sampling capacitor C2.

[0058] Please Figures 1 to 5 Based on the combination Figure 6As shown in the figure, a preferred embodiment of the CMOS detector readout device with chopper of the present invention achieves signal integration, sampling, and noise reduction within one sampling period by controlling the timing of the operational amplifier module 212, input chopper module 214, output chopper module 215, and sampling unit 230 in the integration unit 210, resulting in a low-noise voltage output. Specifically, the Choppr signal is the clock signal of the input chopper module 214 and the output chopper module 215, which varies with a period of 25 microseconds (40kHz). The integration unit 210 enters the working state after being reset under the CTIA_reset signal. The sampling unit 230 is reset under the CDS_reset control. In the sampling unit 230, the CDS1 signal controls the first sampling switch S1, the CDS2 signal controls the second sampling switch S2, and the CDS_reset signal controls the reset switch S3. The reset signal CDS_reset first activates the reset switch S3, then uses the first sampling switch S1 to activate Vref for the first sampling, and subsequently uses the second sampling switch S2 to sample the integrated output signal. After the first sampling switch S1 and the second sampling switch S2 are both activated and held for a period of time, the voltage difference between the second sampling capacitor C2 and the first sampling capacitor C1 is obtained, which serves as the sampling output signal of the sampling unit 230. DFF_clk is used to control the operation of the shift register in the image readout unit 300, with a period of 80 microseconds. DFF_in varies depending on the pixel electrical signal.

[0059] The noise measurement results for this embodiment are as follows. At a chopping frequency of 40 kHz, the output noise of the chopper-equipped integrator is 87.9 μVrms. In comparison, the output noise of a CTIA chip without a chopper, manufactured using the same process, is 158.6 μVrms. The introduction of chopping technology reduces the RMS noise of the chip test by 44.58%.

[0060] Please see Figure 7 The present invention also discloses a readout method using the above-mentioned CMOS detector readout device with chopper, a preferred embodiment of which includes the following steps:

[0061] Step S100: Initialize the CMOS detector readout device with chopper.

[0062] After the device is powered on, the photoelectric conversion unit, pixel readout unit, and image readout unit complete initialization under the action of the synchronization signal.

[0063] In step S200, the photoelectric conversion unit samples the optical signal.

[0064] The photodiodes in the photoelectric conversion unit generate raw electrical signals when excited by light signals. Each photodiode transmits its generated raw electrical signal to its corresponding pixel readout unit.

[0065] In step S300, the pixel readout unit generates a pixel electrical signal.

[0066] Each pixel readout unit generates a pixel electrical signal based on the original electrical signal. Before generating a new pixel electrical signal, the pixel readout unit is reset once to clear the previously output pixel electrical signal.

[0067] In step S400, the image readout unit outputs the electrical signal of the entire image.

[0068] The image readout unit uses a shift register to sequentially read pixel electrical signals from each pixel readout unit that makes up the entire image, and outputs the entire image electrical signal after sequential stitching, as the output of one frame. If it is necessary to generate the next frame of the image, the process jumps to step S300.

[0069] Please see Figure 8 In the readout method using the CMOS detector readout device with chopper described above, during the process of the pixel readout unit generating a pixel electrical signal (i.e., in step 300), the following sub-step is included:

[0070] Step S301: Pixel readout unit reset.

[0071] Before each new pixel electrical signal is generated, the integration unit and the sampling unit are reset.

[0072] Step S302: The sampling unit performs its first sampling.

[0073] The sampling unit performs the first sampling in the double sampling process for the reference voltage.

[0074] Step S303: The integration unit processes the input signal.

[0075] The integrator performs chopping processing on the raw electrical signal read at its input terminal.

[0076] Step S304: The integration unit completes the integration operation.

[0077] The integrating unit uses the integrating unit and operational amplifier module to perform integration operations on the original electrical signal and form an integrated output signal.

[0078] Step S305: The integration unit processes the output signal.

[0079] The integrator performs chopping on the integrated output signal, thereby returning the information from the original electrical signal to the fundamental frequency through an even number of chopping operations, while the noise signal generated internally is shifted to a higher frequency through an odd number of chopping operations.

[0080] Step S306: Filter out high-frequency noise signals.

[0081] The filtering unit uses a low-pass RC filter to perform low-pass filtering on the integral output signal, thereby filtering out high-frequency noise signals.

[0082] Step S307: The sampling unit performs a second sampling.

[0083] The sampling unit performs a second sampling in the double sampling process on the filtered integral output signal.

[0084] Step S308: The sampling unit outputs pixel electrical signals.

[0085] After double sampling is completed, the sampling unit subtracts the voltages from the two samples and outputs the pixel electrical signal.

[0086] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A CMOS detector readout device with chopper, characterized in that, It includes a photoelectric conversion unit, a pixel readout unit, and an image readout unit; The photoelectric conversion unit includes multiple photodiodes, each photodiode corresponding to a pixel; the pixel readout unit corresponds one-to-one with the photodiodes and reads the pixel electrical signal of the corresponding pixel; the image readout unit reads the pixel electrical signal from the multiple pixel readout units and outputs the entire image electrical signal. The pixel readout unit includes an integration unit, a filtering unit, a sampling unit, and an output driving unit; The integration unit is connected to the photodiode, obtains the original electrical signal from the photodiode, performs chopping processing and then integration processing to obtain an integrated output signal; the integration unit performs chopping processing on the integrated output signal again, and after filtering by the filtering unit, it is used as the input of the sampling unit; the sampling unit samples the difference voltage at different time points to obtain a sampling output signal, which is output as the pixel electrical signal by the output driving unit.

2. The CMOS detector readout device with chopper as described in claim 1, characterized in that, The integration unit includes an integrating capacitor, an operational amplifier module, a bias module, an input chopper module, and an output chopper module; The integrating capacitor is connected between the input and output terminals of the operational amplifier module; the bias module is a current source connected to the operational amplifier module to provide the bias current required for the operational amplifier module to operate; the input chopper module is located before the input terminal of the operational amplifier module, and the output chopper module is located after the output terminal of the operational amplifier module to perform chopping processing on the input signal and the integrated output signal of the operational amplifier module.

3. The CMOS detector readout device with chopper as described in claim 2, characterized in that, The operational amplifier module is a capacitor transimpedance amplifier with a folded common-source and common-gate structure, including a common-source submodule and a common-gate submodule. The common-source submodule is connected to the input terminal and converts the input signal into an intermediate signal before inputting it to the common-gate submodule. The common-gate submodule, under the control of the intermediate signal, forms the amplified integral output signal; the input chopper module is positioned before the common-source submodule to chop the input signal; the output chopper module is positioned after the output of the common-gate submodule to chop the integral output signal.

4. The CMOS detector readout device with chopper as described in claim 2, characterized in that, The input chopper module and the output chopper module include a first input terminal, a second input terminal, a first output terminal, and a second output terminal, as well as four sets of CMOS devices with the same channel length; the CMOS devices meet the dynamic element matching condition and are controlled by a clock signal; when the clock signal is high, the first input terminal is connected to the first output terminal, and the second input terminal is connected to the second output terminal; When the clock signal is low, the first input terminal is connected to the second output terminal, and the second input terminal is connected to the first output terminal.

5. The CMOS detector readout device with chopper as described in claim 1, characterized in that, The filtering unit is an RC low-pass filter; the cutoff frequency of the RC low-pass filter is less than the chopping frequency of the integrating unit.

6. The CMOS detector readout device with chopper as described in claim 1, characterized in that, The sampling unit is a correlated dual sampling circuit, comprising a reset switch, a first sampling switch, a second sampling switch, a first sampling capacitor, and a second sampling capacitor. When the reset switch is turned on, the second sampling capacitor is discharged. The first sampling switch is connected to a reference voltage, which charges the first sampling capacitor. The second sampling switch is connected to the filtering unit, which charges the second sampling capacitor with the filtered integral output signal. The voltage difference between the second sampling capacitor and the first sampling capacitor serves as the sampling output signal.

7. The CMOS detector readout device with chopper as described in claim 1, characterized in that, The output drive unit is a unity-gain buffer.

8. The CMOS detector readout device with chopper as described in claim 1, characterized in that, The image readout unit includes a shift register; the image readout unit is sequentially connected to different pixel readout units, reads the pixel electrical signals of different pixels, inputs them into the shift register, and is finally read out as a whole to form the entire image electrical signal.

9. A readout method using the CMOS detector readout device with chopper as described in claim 1, characterized in that, Includes the following steps: Step S1: Initialize the photoelectric conversion unit, the pixel readout unit, and the image readout unit; Step S2, the photoelectric conversion unit transmits the original electrical signal to the pixel readout unit; Step S3: Each pixel readout unit outputs a single pixel electrical signal; In step S4, the image reading unit sequentially reads the electrical signal of each pixel from the plurality of pixel reading units, and outputs the complete image electrical signal after splicing; if it is necessary to generate the next frame image, then jump to step S3.

10. The readout method using a CMOS detector readout device with chopper as described in claim 9, characterized in that, Step S3 includes the following steps: Step S31: Reset the integration unit and the sampling unit; Step S32: The sampling unit starts working and performs the first sampling of the reference voltage; Step S33: The integration unit starts working and chops the original electrical signal; Step S34: The integration unit outputs an integrated output signal; Step S35: The integration unit chops the integrated output signal; Step S36: Use the filtering unit to perform low-pass filtering on the integral output signal; Step S37: The sampling unit performs a second sampling on the filtered integral output signal; Step S38: The sampling unit outputs the pixel electrical signal.

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