Preparation method of display panel and display panel

Abstract

The invention relates to a preparation method of a display panel and the display panel. The preparation method of the display panel comprises the following steps: providing a driving substrate; sequentially forming a semiconductor layer and an insulating medium layer on the driving substrate; forming a first mask layer on the insulating dielectric layer, wherein the first mask layer comprises a first region and second regions arranged on two sides of the first region; patterning the insulating dielectric layer and the semiconductor layer according to the first mask layer, wherein the patterned semiconductor layer forms an active region; etching to remove the first mask layer in the second region, and patterning the insulating dielectric layer according to the remaining first mask layer in the first region to form a gate dielectric layer; forming a metal layer, wherein the metal layer covers the gate dielectric layer and the exposed surface of the active region; forming a second mask layer on the metal layer; the metal layer is patterned according to the second mask layer, a grid electrode is formed on the grid dielectric layer, meanwhile, a source electrode and a drain electrode are formed on the active areas on the two sides of the grid dielectric layer, and the source electrode, the drain electrode and the grid dielectric layer are arranged at intervals.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a method for preparing a display panel and a display panel. Background Art

[0002] As an important part of modern display technology, Thin Film Transistor-Liquid Crystal Display (TFT-LCD) is the product of the deep integration of microelectronics technology and liquid crystal display technology. Its core lies in the application of thin film transistor (TFT) as a pixel switch, which realizes the diversified color display of images by precisely controlling the rotation of liquid crystal molecules. The production process of TFT involves the precise deposition of multiple layers of thin films, which include key components such as gate metal layer, gate insulation layer, active layer, ohmic contact layer, source and drain metal layer, passivation layer and pixel electrode.

[0003] Among them, ohmic contact plays a vital role in the structure of thin-film transistors. It is located between the active layer and the metal electrode and is a contact form of the metal-semiconductor interface. Ohmic contact directly affects the performance indicators of the device, such as efficiency, gain and switching speed, and can be used for the input and output of all device and circuit signals and the interconnection between various components. In addition, ohmic contact also has the function of hole blocking, which further enhances the electrical performance of thin-film transistors.

[0004] It is very important to achieve good ohmic contact, reduce contact resistance, and improve the performance and stability of thin film transistors. Both top-gate thin film transistors and bottom-gate thin film transistors have unique advantages and application scenarios, and can meet the needs of ohmic contact.

[0005] In the current display industry, bottom-gate thin-film transistors, i.e., bottom-gate structures of amorphous silicon hydride (a-Si:H), are often used. They are widely used because of their relatively simple process. With the continuous advancement of technology, the preparation process of bottom-gate thin-film transistors has been gradually optimized from the early five-mask process to the four-mask process, and the three-mask process has also achieved initial success in the laboratory stage. The above process improvements not only improve production efficiency, but also reduce production costs, promoting the rapid development of TFT-LCD technology.

[0006] However, compared with bottom-gate thin-film transistors, the development of top-gate thin-film transistors is relatively slow. The preparation process of top-gate thin-film transistors is still at the stage of 6-photomask (mask) process. Its process structure is relatively complex and the process difficulty is high, which makes it difficult to improve the yield and the cost remains high, which seriously limits the application scope of top-gate thin-film transistors in the display industry. Therefore, how to simplify the preparation process, improve the yield and reduce the cost while maintaining the performance advantages of top-gate thin-film transistors has become a technical problem that needs to be solved urgently. Summary of the invention

[0007] The present application provides a method for manufacturing a display panel and a display panel, which can reduce the number of mask plates, effectively simplify the manufacturing process, reduce costs, and improve production yield and market application rate.

[0008] In a first aspect, the present application provides a method for preparing a display panel, comprising:

[0009] Providing a drive substrate;

[0010] forming a semiconductor layer and an insulating dielectric layer in sequence on the driving substrate;

[0011] forming a first mask layer on the insulating dielectric layer, wherein the first mask layer includes a first region and second regions disposed on both sides of the first region, and a thickness of the first region is greater than a thickness of the second region;

[0012] patterning the insulating dielectric layer and the semiconductor layer according to the first mask layer, so that the patterned semiconductor layer forms an active region;

[0013] Etching and removing the first mask layer in the second region, and patterning the insulating dielectric layer according to the first mask layer remaining in the first region to form a gate dielectric layer;

[0014] forming a metal layer, wherein the metal layer covers the gate dielectric layer and the exposed surface of the active region;

[0015] forming a second mask layer on the metal layer;

[0016] The metal layer is patterned according to the second mask layer to form a gate on the gate dielectric layer, and a source and a drain are formed on the active regions on both sides of the gate dielectric layer. The source, the drain and the gate dielectric layer are spaced apart.

[0017] In a possible implementation manner, forming a first mask layer on the insulating dielectric layer includes:

[0018] forming a first photoresist layer on the insulating dielectric layer;

[0019] forming a first light mask above the first photoresist layer, wherein the first light mask comprises a first light shielding area and first semi-light-transmitting areas disposed on both sides of the first light shielding area;

[0020] The first photoresist layer is exposed and developed according to the first photomask to form the first mask layer, the first photoresist layer below the first light-shielding area forms the first region of the first mask layer, and the first photoresist layer below the first semi-transparent area forms the second region of the first mask layer.

[0021] In a possible implementation manner, etching and removing the first mask layer in the second region includes:

[0022] The first mask layer is etched with the top surface of the insulating dielectric layer as an etching end point to remove the first mask layer in the second area, and a portion of the first mask layer in the first area is etched away and remains.

[0023] In a possible implementation manner, forming a second mask layer on the metal layer includes:

[0024] forming a second photoresist layer on the metal layer;

[0025] forming a second photomask above the second photoresist layer, the second photomask comprising a second light-shielding area, a second semi-light-transmitting area, a third light-shielding area and a first light-transmitting area, the second light-shielding area being arranged above the gate dielectric layer, and the second semi-light-transmitting area, the third light-shielding area and the first light-transmitting area being sequentially arranged on both sides in a direction away from the second light-shielding area;

[0026] exposing and developing the second photoresist layer according to the second photomask to form the second initial mask layer;

[0027] The second initial mask layer below the second semi-transparent area is removed by etching to form the second mask layer.

[0028] In a possible implementation manner, after forming the second initial mask layer, the method further includes:

[0029] The metal layer below the first light-transmitting area is removed by etching.

[0030] In a possible implementation manner, the etching removes the second initial mask layer below the second semi-transparent area to form the second mask layer, including:

[0031] The second initial mask layer is etched with the top surface of the metal layer as the etching end point to remove the second initial mask layer below the second semi-transparent area; the second initial mask layer below the second shading area and the second initial mask layer below the third shading area remain.

[0032] In a possible implementation manner, forming a second mask layer on the metal layer includes:

[0033] forming a third photoresist layer on the metal layer;

[0034] forming a third photomask above the third photoresist layer, the third photomask comprising a fourth light-shielding area, a second light-transmitting area and a fifth light-shielding area, the fourth light-shielding area being arranged above the gate dielectric layer, and the second light-transmitting area and the fifth light-shielding area being sequentially arranged on both sides in a direction away from the fourth light-shielding area;

[0035] The third photoresist layer is exposed and developed according to the third photomask to form the second mask layer.

[0036] In a possible implementation, the method for preparing the display panel further includes:

[0037] A protection layer is formed, the protection layer covers the gate, the source, the drain and the exposed area of ​​the active area; wherein the protection layer above the source is formed with an opening to expose the source.

[0038] In a possible implementation, the method for preparing the display panel further includes:

[0039] A pixel electrode layer is formed, wherein the pixel electrode layer covers the opening, the source electrode in the opening, and a surface of the protection layer away from the gate.

[0040] In a second aspect, the present application provides a display panel, including:

[0041] a driving substrate; and

[0042] A transistor, disposed on one side of the driving substrate, the transistor comprising an active region and a gate dielectric layer, the active region being disposed on the driving substrate, and the gate dielectric layer being disposed on the active region;

[0043] A gate is arranged on the gate dielectric layer, a source and a drain are arranged at active regions on both sides of the gate dielectric layer respectively, and the source, the drain and the gate dielectric layer are arranged at intervals.

[0044] The above technical solution provided by the embodiment of the present application has the following advantages compared with the prior art:

[0045] The display panel preparation method and display panel provided in the embodiment of the present application can form the active area and the gate dielectric layer at one time by etching the semiconductor layer and the insulating dielectric layer through the first mask layer to achieve respective patterning, and can form the source, drain and gate at one time by etching the metal layer through the second mask layer to achieve respective patterning, thereby effectively reducing the number of masks and saving production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0047] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0048] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0049] Figure 1 A flow chart of a method for preparing a display panel provided in an embodiment of the present application;

[0050] Figure 2 A cross-sectional schematic diagram of forming a first photoresist layer provided in an embodiment of the present application;

[0051] Figure 3 A flow chart of a method for preparing a display panel provided in an embodiment of the present application;

[0052] Figure 4 A cross-sectional schematic diagram of a first photomask provided in an embodiment of the present application;

[0053] Figure 5 A cross-sectional schematic diagram of forming an active region provided in an embodiment of the present application;

[0054] Figure 6 A cross-sectional schematic diagram of forming a first region provided in an embodiment of the present application;

[0055] Figure 7 A cross-sectional schematic diagram of forming a gate dielectric layer provided in an embodiment of the present application;

[0056] Figure 8 A cross-sectional schematic diagram of forming a second photoresist layer provided in an embodiment of the present application;

[0057] Fig. 9 A flow chart of a method for preparing a display panel provided in an embodiment of the present application;

[0058] Fig.10 A cross-sectional schematic diagram of a second photomask provided in an embodiment of the present application;

[0059] Fig.11 A cross-sectional schematic diagram of forming a second initial mask layer provided in an embodiment of the present application;

[0060] Fig.12 A cross-sectional schematic diagram of forming a second mask layer provided in an embodiment of the present application;

[0061] Fig.13 A schematic cross-sectional view of the etching of the metal layer provided in the embodiment of the present application;

[0062] Fig.14 A flow chart of a method for preparing a display panel provided in an embodiment of the present application;

[0063] Fig.15 A cross-sectional schematic diagram of forming a third photoresist layer provided in an embodiment of the present application;

[0064] Fig.16 A schematic cross-sectional view of a third photomask provided in an embodiment of the present application;

[0065] Fig.17 A flow chart of a method for preparing a display panel provided in an embodiment of the present application;

[0066] Fig.18 A cross-sectional schematic diagram of forming a protective layer provided in an embodiment of the present application;

[0067] Fig.19 A cross-sectional schematic diagram of forming a pixel electrode provided in an embodiment of the present application;

[0068] Fig. 20 is a cross-sectional schematic diagram of a display panel in the related art.

[0069] Description of reference numerals:

[0070] 1. driving substrate; 2. semiconductor layer; 21. active area; 3. insulating dielectric layer; 31. gate dielectric layer; 4. first mask layer; 41. first area; 42. second area; 43. first photoresist layer; 5. first photomask; 51. first light-shielding area; 52. third light-transmitting area; 53. first semi-light-transmitting area; 6. metal layer; 61. gate; 62. source; 63. drain; 7. second mask layer; 71. second photoresist layer; 711. groove; 72. second initial mask layer; 73. third photoresist layer; 8. second photomask; 81. second light-shielding area; 82. second semi-light-transmitting area; 83. third light-shielding area; 84. first light-transmitting area; 9. third photomask; 91. fourth light-shielding area; 92. second light-transmitting area; 93. fifth light-shielding area; 94. fourth light-transmitting area; 10. protective layer; 101. opening; 11. pixel electrode;

[0071] 1', substrate; 2', pixel electrode; 3', source electrode; 4', drain electrode; 5', active layer; 6', gate insulating layer; 7', gate electrode. DETAILED DESCRIPTION

[0072] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0073] The disclosure below provides many different embodiments or examples to implement different structures of the present invention. In order to simplify the disclosure of the present invention, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed.

[0074] For ease of description, spatial relative terms may be used herein to describe the relative positional relationship or movement of one element or feature relative to another element or feature as shown in the figure, such as "inside", "outside", "inner side", "outer side", "below", "below", "above", "above", "front", "back", etc. Such spatial relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figure. For example, if the device in the figure undergoes a position flip or a posture change or a motion state change, then these directional indications also change accordingly, for example: an element described as "below other elements or features" or "below other elements or features" will subsequently be oriented as "above other elements or features" or "above other elements or features". Therefore, the example term "below..." may include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or in other directions) and the spatial relative descriptors used herein are interpreted accordingly.

[0075] In related technologies, such as Fig. 20 As shown, the display panel includes a substrate 1', a pixel electrode 2', a source electrode 3', a drain electrode 4', an active layer 5', a gate insulating layer 6', and a gate electrode 7'. The pixel electrode 2' and the drain electrode 4' are respectively arranged on the substrate 1', the active layer 5' covers the pixel electrode 2', the drain electrode 4' and the exposed area of ​​the substrate 1', and the gate insulating layer 6' and the gate electrode 7' are sequentially stacked on the active layer 5'. The above display panel is prepared by a six-pass photomask process, which has technical problems such as complex process structure, high cost, high process difficulty, and low production yield.

[0076] First embodiment

[0077] Figure 1 A flow chart of a method for preparing a display panel provided in an embodiment of the present application.

[0078] The present invention provides a method for manufacturing a display panel, comprising the following steps:

[0079] S100: providing a driving substrate.

[0080] In step S100, Figure 2As shown, the driving substrate 1 includes a base substrate and a driving array layer, and the base substrate supports the display panel, for example. The base substrate, such as a flexible substrate or a glass substrate, can be made of an insulating material such as a polymer resin (polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP) or a combination thereof, so that it has sufficient mechanical strength to support the entire display structure, and also has good insulation performance to ensure electrical isolation between circuits.

[0081] Flexible substrates are suitable for display devices that need to be bent or folded, such as flexible displays. Glass substrates are suitable for rigid display devices, such as liquid crystal displays (LCDs) and organic light-emitting diode displays (OLEDs). Glass substrates are known for their high light transmittance, high thermal stability, and good flatness.

[0082] S110 , forming a semiconductor layer and an insulating dielectric layer in sequence on a driving substrate.

[0083] In step S110, Figure 2 As shown, a semiconductor layer 2 is formed by deposition using a physical vapor deposition process (PVD) or a chemical vapor deposition process (CVD). The semiconductor layer 2 can be made of semiconductor materials such as amorphous silicon (a-Si), polycrystalline silicon (p-Si), and metal oxides. Amorphous silicon (a-Si) and polycrystalline silicon (p-Si) are usually deposited using a chemical vapor deposition process (CVD) to prepare their thin film layers, and metal oxide semiconductor materials are usually deposited using a physical vapor deposition process (PVD) to prepare their thin film layers. The thickness of the semiconductor layer 2 is, for example,

[0084] The insulating dielectric layer 3 is deposited on the semiconductor layer 2 by a physical vapor deposition process or a chemical vapor deposition process. The insulating dielectric layer 3 is made of, for example, silicon nitride (Si3N4) or silicon dioxide (SiO2) to have good insulation performance and chemical stability. Among them, Si3N4 or SiO2 can be prepared by a chemical vapor deposition process. The thickness of the insulating dielectric layer 3 is

[0085] S120, forming a first mask layer on the insulating dielectric layer.

[0086] In step S120, Figure 2As shown, a first mask layer 4 is formed on the insulating dielectric layer 3. The first mask layer 4 is, for example, a photoresist layer (PR), which is formed on the surface of the insulating dielectric layer 3 by coating. The thickness of the first mask layer 4 is in the range of

[0087] The first mask layer 4 includes a first region 41 and a second region 42. The first region 41 is located in the middle. A second region 42 is disposed on both sides of the first region 41. The thickness of the first region 41 is greater than the thickness of the second region 42. For example, the thickness of the first region 41 is The thickness of the second region 42 is, for example, This helps to achieve accurate etching of the insulating dielectric layer 3 and the semiconductor layer 2 in the subsequent etching steps.

[0088] By utilizing the thickness difference of the first mask layer 4, the insulating dielectric layer 3 and part of the semiconductor layer 2 are removed by selective etching to form the required film structure. During the etching process, the etching conditions need to be strictly controlled to ensure the accuracy and uniformity of the etching.

[0089] Through the above steps, the present embodiment successfully forms the first mask layer 4 with a specific thickness distribution on the insulating dielectric layer 3, providing accurate masking and protection for the subsequent etching steps, and ensuring the accuracy and reliability of the film layer structure.

[0090] Among them, Figure 3 As shown, in step S120, “forming a first mask layer on the insulating dielectric layer” further includes the following steps:

[0091] S1201, forming a first photoresist layer on the insulating dielectric layer.

[0092] In step S1201, Figure 2 As shown, a first photoresist layer (PR) 43 is coated on the insulating dielectric layer 3. The first photoresist layer 43 covers the entire insulating dielectric layer 3 and can be subjected to processes such as exposure and development to form a target pattern. The thickness of the first photoresist layer 43 is, for example,

[0093] S1202 , forming a first photomask on the first photoresist layer.

[0094] In step S1202, if Figure 4As shown, a first light mask 5 is disposed above the first photoresist layer 43. The first light mask 5 is, for example, a half tone mask. The first light mask 5 includes a first light shielding area 51, a third light transmitting area 52 and a first semi-light transmitting area 53. The first semi-light transmitting area 53 is disposed on both sides of the first light shielding area 51. The third light transmitting area 52 is disposed on a side of the first light shielding area 51 away from the first light shielding area 51.

[0095] The third light-transmitting area 52 can be, for example, a hollow area, or a fully light-transmitting film with full light transmittance, so that light can completely pass through the third light-transmitting area 52 and illuminate the first photoresist layer 43 below the third light-transmitting area 52, inducing a photochemical reaction in the first photoresist layer 43. The first photoresist layer 43 that undergoes the photochemical reaction will be dissolved by the developer in the subsequent process.

[0096] The first semi-transparent area 53 is, for example, a semi-transparent film, which absorbs light so that the light transmittance is 40%-50%. The intensity of the transmitted light is weakened, so that the intensity of the photochemical reaction of the first photoresist layer 43 below the first semi-transparent area 53 is also weakened. After passing through the developer, the thickness of the first photoresist layer 43 below the first semi-transparent area 53 is reduced, and the thickness is, for example,

[0097] The first light-shielding area 51 is, for example, a full light-shielding film, so that the area is completely opaque to block light. The first photoresist layer 43 below the first light-shielding area 51 is not affected by light and maintains its original thickness and structure.

[0098] S1203 , exposing and developing the first photoresist layer according to the first photomask to form a first mask layer.

[0099] In step S1203, if Figure 4 As shown, the first photoresist layer 43 is exposed and developed according to the first light-shielding area 51, the third light-transmitting area 52 and the first semi-light-transmitting area 53 of the first photomask 5. During the exposure process, when light passes through the first photomask 5, the first light-shielding area 51, the third light-transmitting area 52 and the first semi-light-transmitting area 53 have different light-transmitting properties, which can have different effects on different areas of the first photoresist layer 43.

[0100] For example, the first photoresist layer 43 below the third light-transmitting area 52 can receive enough light to undergo a photochemical reaction and become easily soluble. The first photoresist layer 43 below the first light-shielding area 51 does not undergo a chemical reaction due to being shielded from light, and maintains its original solubility. The first photoresist layer 43 below the first semi-light-transmitting area 53 receives part of the light and undergoes a certain degree of photochemical reaction, but its solubility is between the third light-transmitting area 52 and the first light-shielding area 51.

[0101] After exposure, the first photoresist layer 43 is developed with a developer, which dissolves the photochemically reacted first photoresist layer 43, thereby removing the first photoresist layer 43 below the third light-transmitting area 52 and thinning the first photoresist layer 43 below the first semi-light-transmitting area 53.

[0102] After exposure and development, a first mask layer 4 having a specific pattern is formed on the first photoresist layer 43. The first photoresist layer 43 below the first light-shielding area 51 that has not undergone chemical reaction constitutes the first region 41 of the first mask layer 4, which has a relatively high thickness and light-shielding performance. The thinned first photoresist layer 43 below the first semi-transparent area 53 constitutes the second region 42 of the first mask layer 4, which, although having a reduced thickness, still has a certain light-shielding capability.

[0103] The method in this embodiment can expose and develop the first photoresist layer 43 according to the first mask 5 to form a first mask layer 4 with a specific pattern and performance, so as to facilitate further use of the first mask layer 4 to dry-etch the insulating dielectric layer 3 and the semiconductor layer 2. It has a wide range of application value, can realize the manufacture of high-precision devices, and improve production yield.

[0104] S130 , patterning the insulating dielectric layer and the semiconductor layer according to the first mask layer, and forming an active region in the patterned semiconductor layer.

[0105] In step S130, if Figure 5 As shown, at this time, the insulating dielectric layer 3 below the third light-transmitting area 52 is in an exposed state, and a dry etching method is adopted, using gases such as chlorine (Cl2), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3) as etching gases, to etch the insulating dielectric layer 3 and the semiconductor layer 2 not covered by the first mask layer 4. Among them, dry etching is a method of removing materials by gas chemical reaction or physical bombardment. In this embodiment, the etching gas reacts chemically with the insulating dielectric layer 3 and the semiconductor layer 2 to generate volatile products, thereby removing these materials from the semiconductor substrate.

[0106] The etching process continues until a predetermined depth is reached to form an active area 21 with a specific pattern, where active devices such as transistors are subsequently manufactured. At this time, the projection area of ​​the active area 21 on the drive substrate 1 overlaps with the projection area of ​​the first mask layer 4 on the drive substrate 1.

[0107] S140 , etching away the first mask layer in the second region, and patterning the insulating dielectric layer according to the remaining first mask layer in the first region to form a gate dielectric layer.

[0108] In step S140, if Figure 6 , Figure 7As shown, the first mask layer 4 is etched using dry etching technology, which can achieve precise control of the etching depth and has high selectivity for materials, thereby improving the etching effect.

[0109] In order to efficiently remove the first mask layer 4 on the second region 42, oxygen (O2) is selected as the etching gas. Oxygen has a strong etching ability on the material of the first mask layer 4 and can quickly and accurately complete the etching task.

[0110] The above structure is placed in a dry etching device, oxygen is introduced, and etching parameters such as etching power, gas flow rate, etc. are adjusted. The first mask layer 4 is etched with the top surface of the insulating dielectric layer 3 as the etching end point to ensure that the first mask layer 4 in the second region 42 is completely removed. Oxygen will also affect the first mask layer 4 in the first region 41, and there will be a certain degree of etching to thin it, and part of the first mask layer 4 in the first region 41 will be etched and remain. The thickness of the first mask layer 4 remaining after the etching of the first region 41 can be the same as the thickness of the first mask layer 4 when the second region 42 has not been etched, so as not to affect the subsequent process.

[0111] After the first mask layer 4 is etched, the etching gas is replaced with gases such as Cl 2 , SF 6 , NF 3 , etc. These gases have a better etching effect on the insulating dielectric layer 3 .

[0112] The remaining first mask layer 4 in the first region 41 is used as a masking layer to etch the insulating dielectric layer 3 in the exposed second region 42. By precisely controlling the etching time and gas flow rate, the insulating dielectric layer 3 is ensured to be etched only according to the pattern of the first mask layer 4 to form a patterned gate dielectric layer 31.

[0113] S150: forming a metal layer.

[0114] In step S150, if Figure 8 As shown, a metal layer 6 is deposited by physical vapor deposition, and the metal layer 6 covers the gate dielectric layer 31 and the exposed surface of the active region 21. Physical vapor deposition utilizes a physical process, such as sputtering or evaporation, to transfer a material from a source to a target film layer to form a desired thin film.

[0115] In the physical vapor deposition process, first, a metal target material, such as copper, aluminum, tungsten, etc., needs to be selected according to the specific situation and placed in an appropriate position in the vacuum chamber. Then, by applying an electric field or a magnetic field, the atoms or molecules on the surface of the target material obtain enough energy to break away from the surface of the target material to form metal vapor. These metal vapors then diffuse in the vacuum and are finally deposited on the semiconductor structure located in the vacuum chamber, that is, on the exposed surface of the gate dielectric layer 31 and the active area 21. Among them, the metal layer 6 is arranged following the gate dielectric layer 31 and the active area 21 to form an uneven shape.

[0116] During the deposition process, it is necessary to precisely control the deposition conditions, such as the vacuum degree, deposition temperature, the distance between the target material and the film layer, and the deposition time, to ensure that the thickness, uniformity, and adhesion of the metal layer 6 meet the design requirements. In addition, in order to obtain good electrical properties and reliability, the metal layer 6 also needs to undergo subsequent processing steps, such as annealing, to eliminate defects generated during the deposition process and improve the interface characteristics between the metal and the semiconductor material.

[0117] S160 , forming a second mask layer on the metal layer.

[0118] In step S160, if Figure 8 As shown, the surface of the metal layer 6 presents an uneven structure. The material of the metal layer 6 can be common metals such as copper, aluminum, gold, silver, etc., and the specific selection depends on the application requirements and process requirements. The metal layer 6 is thoroughly cleaned to remove grease, oxides and other impurities on the surface. This can be achieved by chemical cleaning, ultrasonic cleaning or plasma cleaning. The surface of the metal layer 6 after cleaning should be kept dry and clean to ensure good adhesion of the second mask layer 7.

[0119] A second mask layer 7 is formed on the metal layer 6. The second mask layer 7 is, for example, a photoresist layer, and the photoresist layer material is uniformly applied to the surface of the metal layer 6 by coating. The coating method can be spin coating, dip coating or spray coating, etc., and the specific selection depends on the type of the photoresist layer, the required thickness and the process requirements.

[0120] Control coating parameters, such as coating speed, photoresist concentration, etc., to ensure that the thickness of the second mask layer 7 is within to This thickness range can provide sufficient masking effect and ensure the smooth progress of subsequent processing steps.

[0121] Among them, Fig. 9 As shown, in step S160, “forming a second mask layer on the metal layer” further includes the following steps:

[0122] S1601, forming a second photoresist layer on the metal layer.

[0123] In step S1601, Figure 8 As shown, a second photoresist layer 71 is coated on the metal layer 6, and the second photoresist layer 71 covers the entire metal layer 6. Before coating the second photoresist layer 71, the metal layer 6 is thoroughly cleaned to remove grease, oxides, dust and other impurities on the surface. The cleaning process can be carried out by chemical cleaning, ultrasonic cleaning or plasma cleaning to ensure that the surface of the metal layer 6 is clean and free of contaminants.

[0124] The second photoresist layer 71 is made of a dedicated photoresist material and is uniformly applied to the surface of the metal layer 6 by spin coating, dip coating or spray coating. The coating parameters, such as coating speed, photoresist concentration, temperature, etc., are controlled to ensure that the thickness of the second photoresist layer 71 is within to This thickness range can not only provide sufficient masking effect, but also ensure the smooth progress of subsequent exposure, development and other processes.

[0125] After coating, the second photoresist layer 71 is pre-baked. The purpose of pre-baking is to remove the solvent in the photoresist layer and improve the stability and adhesion of the photoresist layer. The pre-baking process can be performed on a hot plate, and the temperature and time are controlled to ensure that the photoresist layer is not damaged due to excessive heating.

[0126] S1602, forming a second photomask on the second photoresist layer.

[0127] In step S1602, if Fig. 9 , Fig.10 As shown, a second photomask 8 is disposed above the second photoresist layer 71 . The second photomask 8 is, for example, a half tone mask having a complex light transmittance and light shielding design.

[0128] The second light mask 8 includes a second light shielding area 81, a second semi-light-transmitting area 82, a third light shielding area 83 and a first light-transmitting area 84, and the second semi-light-transmitting area 82, the third light shielding area 83 and the first light-transmitting area 84 are sequentially arranged on both sides in a direction away from the second light shielding area 81. These areas are formed on the second light mask 8 by a precise manufacturing process and have precise size and position relationship.

[0129] The second photomask 8 is precisely positioned above the second photoresist layer 71 to ensure that each region of the second photomask 8 is aligned with the target structure below the second photoresist layer 71 , such as the second light shielding region 81 is disposed above the gate dielectric layer 31 .

[0130] It can be understood that the principles of the first light-transmitting area 84 and the aforementioned third light-transmitting area 52, the principles of the second semi-light-transmitting area 82 and the first semi-light-transmitting area 53, and the principles of the second light-shielding area 81 and the third light-shielding area 83 and the first light-shielding area 51 are the same or similar, and they will not be repeated here.

[0131] S1603 , exposing and developing the second photoresist layer according to a second photomask to form a second initial mask layer.

[0132] In step S1603, if Fig. 9 , Fig.10As shown, the second photoresist layer 71 is exposed and developed according to the second light-shielding area 81 , the second semi-light-transmitting area 82 , the third light-shielding area 83 and the first light-transmitting area 84 of the second photomask 8 .

[0133] During the exposure process, various areas of the second photomask 8 transmit or block light to varying degrees, thereby forming a specific exposure pattern on the second photoresist layer 71. For example, the second light-shielding area 81 completely blocks light to form an unexposed area; the second semi-light-transmitting area 82 partially transmits light to form a semi-exposed area; the third light-shielding area 83 also completely blocks light to form an unexposed area similar to the second light-shielding area 81; and the first light-transmitting area 84 completely transmits light to form a fully exposed area.

[0134] After the exposure is completed, the second photoresist layer 71 is developed. The developer will dissolve the unexposed or partially exposed areas, thereby forming a pattern corresponding to the second photomask 8 on the second photoresist layer 71.

[0135] Due to the weak exposure, the second photoresist layer 71 below the second semi-transparent area 82 is partially dissolved to form two grooves 711. The second light-shielding area 81, the second semi-transparent area 82 (although partially dissolved, still retains a certain thickness as a mask) and the second photoresist layer 71 below the third light-shielding area 83 together constitute the second initial mask layer 72.

[0136] Among them, Fig.10 , Fig.11 As shown, the second photoresist layer 71 below the first light-transmitting area 84 is dissolved, exposing a partial area of ​​the metal layer 6, which is then processed.

[0137] For example, the metal layer 6 below the first light-transmitting region 84 is removed by wet etching. According to the material type of the metal layer 6, such as aluminum or copper, a suitable wet etching solution, such as aluminum etching solution or copper etching solution, is selected.

[0138] The wet etching solution reacts with the exposed metal layer 6 to gradually remove the metal layer 6 area below the first light-transmitting area 84. The wet etching process is monitored to ensure that the etching depth and time meet the predetermined requirements to avoid over-etching or under-etching.

[0139] S1604 , etching and removing the second initial mask layer below the second semi-transparent area to form a second mask layer.

[0140] In step S1604, if Fig.10 , Fig.12 As shown, dry etching is used, such as using O2 as etching gas, to etch the second initial mask layer 72. The O2 etching gas is accelerated under the action of the electric field and bombards the surface of the second initial mask layer 72 below the second semi-transparent area 82, so that it is gradually removed.

[0141] The etching process continues until the top surface of the metal layer 6 is reached as the etching end point. At this time, the second initial mask layer 72 under the second semi-transparent area 82 is completely removed, and the second initial mask layer 72 under the second light-shielding area 81 and the second initial mask layer 72 under the third light-shielding area 83 are left, thereby forming the second mask layer 7.

[0142] S170 , patterning the metal layer according to the second mask layer to form a gate on the gate dielectric layer, and simultaneously forming a source and a drain on the active regions on both sides of the gate dielectric layer.

[0143] In step S170, if Fig.10 , Fig.13 As shown, the second mask layer 7 is used as a mask to etch the metal layer 6. For example, dry etching is used to remove the metal layer 6 below the second semi-transparent area 82, so that a gate 61 is formed on the gate dielectric layer 31, and a source 62 and a drain 63 are formed on the active area 21 on both sides of the gate dielectric layer 31. The source 62, the drain 63 and the gate dielectric layer 31 are arranged at intervals to ensure that no unnecessary electrical connection is formed between them.

[0144] After etching is completed, the second mask layer 7 needs to be removed. This is usually done by soaking or washing with a photoresist removal solution to completely remove the remaining mask layer material from the film layer.

[0145] The method in this embodiment uses the different light transmittance properties of the first mask 5 to expose and develop the first mask layer 4, and uses the first mask layer 4 as a mask to etch the semiconductor layer 2 and the insulating dielectric layer 3, so that they are formed into films at one time to achieve their respective patterning, such as forming the active region 21 and the gate dielectric layer 31. The second mask 8 cooperates with the metal layer 6 to form the source 62, the drain 63 and the gate 61 into films at one time to achieve their respective patterning. Compared with the mask process flow in the related art, the number of masks is effectively reduced, the difficulty of preparing the top-gate thin film transistor is reduced, and the production cost is saved.

[0146] Second embodiment

[0147] Fig.14 A flow chart of a method for preparing a display panel provided in an embodiment of the present application.

[0148] The second embodiment of the present application further provides a method for manufacturing a display panel, which is similar to the method for manufacturing a display panel provided in the first embodiment thereof, except that a second mask layer is formed on the metal layer, comprising:

[0149] S200 , forming a third photoresist layer on the metal layer.

[0150] In step S200, Fig.15As shown, a third photoresist layer 73 is coated on the metal layer 6, and the third photoresist layer 73 is used for subsequent exposure and development processes. The third photoresist layer 73 covers the entire metal layer 6 to define the etching pattern of the metal layer 6. The coating method of the third photoresist layer 73 is the same or similar to the coating method of the second photoresist layer 71 or the first photoresist layer 43 in the above embodiment, and will not be repeated here.

[0151] S210 , forming a third photomask on the third photoresist layer.

[0152] In step S210, Fig.16 As shown, a third light mask 9 is formed above the third photoresist layer 73. The third light mask 9 includes, for example, a fourth light shielding area 91, a second light-transmitting area 92, a fifth light shielding area 93 and a fourth light-transmitting area 94. The fourth light shielding area 91 is disposed above the gate dielectric layer 31, and the second light-transmitting area 92, the fifth light shielding area 93 and the fourth light-transmitting area 94 are sequentially arranged on both sides in a direction away from the fourth light shielding area 91. The usage and principle of the light shielding area and the light-transmitting area are the same as those of the light shielding area and the light-transmitting area in the above embodiment, and will not be repeated here.

[0153] S220 , exposing and developing the third photoresist layer according to a third photomask to form a second mask layer.

[0154] In step S220, Fig.12 , Fig.13 , Fig.16 As shown, the third photoresist layer 73 is exposed according to the pattern of the third mask 9. During the exposure process, the photoresist layer below the fourth light shielding area 91 and the fifth light shielding area 93 remains unexposed, while the photoresist layer below the second light transmitting area 92 and the fourth light transmitting area 94 changes due to light exposure.

[0155] Then, a development process is performed to remove the exposed photoresist material under the second light-transmitting area 92 and the fourth light-transmitting area 94, while the photoresist material under the fourth light-shielding area 91 and the fifth light-shielding area 93 is retained. After exposure and development, the third photoresist layer 73 is patterned to form the second mask layer 7.

[0156] The formed second mask layer 7 is used as a masking layer to perform etching on the metal layer 6. Due to the existence of the second mask layer 7, only the area of ​​the metal layer 6 below the second light-transmitting area 92 and the fourth light-transmitting area 94 is etched away, while the remaining area is protected. After the etching process, the metal layer 6 is divided into three parts: the source electrode 62, the drain electrode 63 and the gate electrode 61.

[0157] The method in this embodiment simplifies the forming process of the second mask layer 7, that is, a single exposure and development process is used to directly form a mask layer for etching the metal layer 6. This method not only simplifies the process steps, but also improves the efficiency of the process.

[0158] At the same time, the source 62, the drain 63 and the gate 61 are formed by etching the metal layer 6 at one time, thereby optimizing the etching process, reducing the error and damage that may be caused by multiple etchings, and improving the performance and reliability of the device.

[0159] Third embodiment

[0160] Fig.17 A flow chart of a method for preparing a display panel provided in an embodiment of the present application.

[0161] The third embodiment of the present application further provides a method for manufacturing a display panel, which is similar to the method for manufacturing a display panel provided in the first embodiment or the second embodiment, except that the method for manufacturing a display panel further includes:

[0162] S300: forming a protective layer.

[0163] In step S300, Fig.18 As shown, a protection layer 10 is formed on the gate 61, the source 62, the drain 63 and the exposed area of ​​the active area 21 by using a chemical vapor deposition process. The main function of the protection layer 10 is to provide insulation protection to prevent damage to these key structures in subsequent processes.

[0164] The protective layer 10 is made of insulating material, such as silicon nitride (Si3N4) or silicon dioxide (SiO2), which has good insulating properties and chemical stability and is suitable for use as a protective layer. The thickness of the protective layer 10 is controlled to be So that it can provide sufficient protection and ensure the smooth progress of subsequent processes.

[0165] A uniform layer of photoresist material is coated on the protective layer 10. The selection of the photoresist material should meet the requirements of the subsequent exposure and development process. The protective layer 10 coated with photoresist is exposed using a specific photomask. After exposure, the photoresist material in the area above the source 62 is removed by a development process to form a patterned photoresist layer. The protective layer 10 is etched using dry etching technology. Due to the presence of the photoresist layer, only the protective layer 10 above the source 62 is etched away to form an opening 101, thereby exposing the source 62.

[0166] S310, forming a pixel electrode layer.

[0167] In step S310, Fig.19As shown, a uniform layer of transparent conductive material is deposited on the entire device surface by physical vapor deposition or chemical vapor deposition to form a full-surface pixel electrode layer 11. The selection of the transparent conductive material should meet the requirements of good conductivity and light transmittance, such as indium tin oxide (ITO).

[0168] The thickness of the pixel electrode layer 11 is controlled to be So that it can ensure good conductivity and meet the requirements of light transmittance, ensuring the display effect of the display device.

[0169] A uniform layer of photoresist material is coated on the deposited pixel electrode layer 11, and the pixel electrode layer 11 coated with photoresist is exposed using a specific photomask. After exposure, the photoresist material in the unnecessary area is removed by a development process to form a patterned photoresist layer. The pixel electrode layer 11 not protected by the photoresist layer is etched using wet etching or dry etching technology. After etching, the photoresist layer is removed to obtain a patterned pixel electrode layer 11.

[0170] The patterned pixel electrode layer 11 covers the opening 101, the source electrode 62 in the opening 101 and the surface of the protective layer 10 away from the gate electrode 61. The pixel electrode layer 11 is electrically connected to the source electrode 62 through the opening 101, providing necessary electrical connection for subsequent display operations.

[0171] The method in this embodiment realizes interlayer protection and electrical connection between the pixel electrode 11 and the source 62 by forming a patterned protection layer 10 and a pixel electrode layer 11, thereby providing necessary electrical connection for subsequent display operation. Compared with the top-gate thin film transistor in the related art, which adopts six masking processes, only four masking processes are adopted in this embodiment, which effectively reduces the number of masks and reduces the production cost.

[0172] Fourth embodiment

[0173] Fig.19 A display panel is provided in an embodiment of the present application.

[0174] A display panel includes a driving substrate 1 and a transistor. The transistor is arranged on one side of the driving substrate 1, and includes an active region 21 and a gate dielectric layer 31. The active region 21 is arranged on the driving substrate 1, and the gate dielectric layer 31 is arranged on the active region 21. A gate 61 is arranged on the gate dielectric layer 31, and a source 62 and a drain 63 are respectively arranged in the active region 21 on both sides of the gate dielectric layer 31. The source 62, the drain 63 and the gate dielectric layer 31 are arranged at intervals to ensure that no unnecessary electrical connection is formed between them.

[0175] The gate 61 , the source 62 , the drain 63 and the exposed area of ​​the active region 21 are covered with a protective layer 10 to achieve insulation protection. The protective layer 10 above the source 62 is etched away to form an opening 101 , thereby exposing the source 62 .

[0176] The pixel electrode layer 11 covers the opening 101 , the source electrode 62 in the opening 101 , and the surface of the protective layer 10 away from the gate electrode 61 . The pixel electrode layer 11 is electrically connected to the source electrode 62 through the opening 101 , providing necessary electrical connection for subsequent display operations.

[0177] The display panel in this embodiment provides a top-gate thin film transistor, in which the active region 21 and the gate dielectric layer 31 are formed at one time by the first photomask 5 to achieve respective patterning. The source electrode 62, the drain electrode 63 and the gate electrode 61 are formed at one time by the second photomask 8 to achieve respective patterning. Two more photomasks are selected to complete the protective layer 10 and the pixel electrode layer 11 respectively, so that the top-gate thin film transistor is reduced from six photomask processes in the related art to four photomask processes, effectively saving production costs.

[0178] It should be understood that the terms used herein are only for the purpose of describing specific example embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" as used herein may also be meant to include plural forms. The terms "include", "comprise", "contain", and "have" are inclusive, and therefore specify the existence of stated features, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The method steps, processes, and operations described herein are not interpreted as necessarily requiring them to be performed in the specific order described or illustrated, unless the execution order is clearly indicated. It should also be understood that additional or alternative steps may be used.

[0179] Although the terms first, second, third, etc. can be used in the text to describe multiple elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms can only be used to distinguish an element, component, region, layer or section from another region, layer or section. Unless the context clearly indicates, terms such as "first", "second" and other numerical terms do not imply order or sequence when used in the text. Therefore, the first element, component, region, layer or section discussed below can be referred to as the second element, component, region, layer or section without departing from the teaching of the example embodiments.

[0180] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for preparing a display panel, characterized in that: include: Providing a drive substrate; forming a semiconductor layer and an insulating dielectric layer in sequence on the driving substrate; forming a first mask layer on the insulating dielectric layer, wherein the first mask layer includes a first region and second regions disposed on both sides of the first region, and a thickness of the first region is greater than a thickness of the second region; patterning the insulating dielectric layer and the semiconductor layer according to the first mask layer, so that the patterned semiconductor layer forms an active region; Etching and removing the first mask layer in the second region, and patterning the insulating dielectric layer according to the first mask layer remaining in the first region to form a gate dielectric layer; forming a metal layer, wherein the metal layer covers the gate dielectric layer and the exposed surface of the active region; forming a second mask layer on the metal layer; The metal layer is patterned according to the second mask layer to form a gate on the gate dielectric layer, and a source and a drain are formed on the active regions on both sides of the gate dielectric layer. The source, the drain and the gate dielectric layer are spaced apart.

2. The method for preparing a display panel according to claim 1, characterized in that: Forming a first mask layer on the insulating dielectric layer includes: forming a first photoresist layer on the insulating dielectric layer; forming a first light mask above the first photoresist layer, wherein the first light mask comprises a first light shielding area and first semi-light-transmitting areas disposed on both sides of the first light shielding area; The first photoresist layer is exposed and developed according to the first photomask to form the first mask layer, the first photoresist layer below the first light-shielding area forms the first region of the first mask layer, and the first photoresist layer below the first semi-transparent area forms the second region of the first mask layer.

3. The method for preparing a display panel according to claim 1, characterized in that: Etching and removing the first mask layer in the second area includes: The first mask layer is etched with the top surface of the insulating dielectric layer as an etching end point to remove the first mask layer in the second area, and a portion of the first mask layer in the first area is etched away and remains.

4. The method for preparing a display panel according to claim 1, characterized in that: Forming a second mask layer on the metal layer, comprising: forming a second photoresist layer on the metal layer; forming a second photomask above the second photoresist layer, the second photomask comprising a second light-shielding area, a second semi-light-transmitting area, a third light-shielding area and a first light-transmitting area, the second light-shielding area being arranged above the gate dielectric layer, and the second semi-light-transmitting area, the third light-shielding area and the first light-transmitting area being sequentially arranged on both sides in a direction away from the second light-shielding area; exposing and developing the second photoresist layer according to the second photomask to form a second initial mask layer; The second initial mask layer below the second semi-transparent area is removed by etching to form the second mask layer.

5. The method for preparing a display panel according to claim 4, characterized in that: After forming the second initial mask layer, the method further includes: The metal layer below the first light-transmitting area is removed by etching.

6. The method for preparing a display panel according to claim 4, characterized in that: The etching removes the second initial mask layer below the second semi-transparent area to form the second mask layer, including: The second initial mask layer is etched with the top surface of the metal layer as the etching end point to remove the second initial mask layer below the second semi-transparent area; the second initial mask layer below the second shading area and the second initial mask layer below the third shading area remain.

7. The method for preparing a display panel according to claim 1, characterized in that: Forming a second mask layer on the metal layer, comprising: forming a third photoresist layer on the metal layer; forming a third photomask above the third photoresist layer, the third photomask comprising a fourth light-shielding area, a second light-transmitting area and a fifth light-shielding area, the fourth light-shielding area being arranged above the gate dielectric layer, and the second light-transmitting area and the fifth light-shielding area being sequentially arranged on both sides in a direction away from the fourth light-shielding area; The third photoresist layer is exposed and developed according to the third photomask to form the second mask layer.

8. The method for preparing a display panel according to claim 1, characterized in that: The method for preparing the display panel further includes: A protection layer is formed, the protection layer covers the gate, the source, the drain and the exposed area of ​​the active area; wherein the protection layer above the source is formed with an opening to expose the source.

9. The method for preparing a display panel according to claim 8, characterized in that: The method for preparing the display panel further includes: A pixel electrode layer is formed, wherein the pixel electrode layer covers the opening, the source electrode in the opening, and a surface of the protection layer away from the gate.

10. A display panel, characterized in that: include: Driver substrate; as well as A transistor, disposed on one side of the driving substrate, the transistor comprising an active region and a gate dielectric layer, the active region being disposed on the driving substrate, and the gate dielectric layer being disposed on the active region; A gate is arranged on the gate dielectric layer, a source and a drain are arranged at active regions on both sides of the gate dielectric layer respectively, and the source, the drain and the gate dielectric layer are arranged at intervals.

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