A high-reliability SiC MOSFET device and its manufacturing method

Abstract

This invention relates to the field of semiconductor technology, and more particularly to a high-reliability SiC MOSFET device and its manufacturing method. The device includes: a silicon carbide wafer, two gate regions, two doped regions, and a hybrid PIN Schottky diode region (MPS region). The two gate regions are located on the silicon carbide wafer. The two doped regions are located on the silicon carbide wafer and are respectively located on the opposite side of the two gate regions, where the opposite side is the side of the gate region furthest from the other gate region. The MPS region is located on the silicon carbide wafer and between the two gate regions, thereby improving the device's surge resistance while avoiding bipolar degradation. This device enhances the device's ultimate overcurrent capability, improves reliability under extreme surge conditions, protects the gate oxide layer, extends the gate oxide layer's lifespan, improves the long-term reliability of the gate oxide layer, and reduces device losses.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a high-reliability SiC MOSFET device and its manufacturing method. Background Technology

[0002] Silicon carbide (SiC) MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) possess significant advantages, including a large bandgap, high critical breakdown electric field, fast electron saturation drift velocity, and high thermal conductivity, making them highly promising for applications in high-voltage, high-temperature, and high-frequency fields. In particular, SiC MOSFETs are becoming increasingly important in emerging sectors such as new energy vehicles, photovoltaic energy storage, and charging piles.

[0003] While SiC MOSFETs don't necessarily require anti-parallel freewheeling diodes (FRDs) when replacing high-voltage silicon-based power devices like IGBTs, in demanding applications such as automotive-grade MOSFETs, a freewheeling diode is typically integrated within the SiC MOSFET chip or connected in anti-parallel within the module to prevent the "bipolar degradation effect" caused by prolonged forward conduction of the SiC MOSFET body diode. This effect is primarily triggered by early-present basal plane dislocations on the SiC crystal during bipolar operation, and the on-resistance (Ron) and forward voltage drop (VF) of the SiC MOSFET gradually increase with prolonged bipolar operation. However, existing SiC MOSFET devices with integrated diodes are extremely susceptible to damage from occasional surge currents, resulting in low reliability. Summary of the Invention

[0004] This application provides a highly reliable SiC MOSFET device and its manufacturing method, which solves the technical problem of low reliability in existing SiC MOSFET devices. It enhances the device's extreme overcurrent capability, improves reliability under extreme surge conditions, protects the gate oxide layer, extends the gate oxide layer's lifespan, improves the long-term reliability of the gate oxide layer, and reduces device losses.

[0005] In a first aspect, embodiments of the present invention provide a highly reliable SiC MOSFET device, comprising: a silicon carbide wafer, two gate regions, two doped regions, and a hybrid PIN Schottky diode region (MPS region);

[0006] The two gate regions are located on the silicon carbide wafer;

[0007] The two doped regions are located on the silicon carbide wafer and are respectively located on the far side of the two gate regions, wherein the far side is the side of the gate region that is far away from the other gate region;

[0008] The MPS region is located on the silicon carbide wafer and between the two gate regions, which is used to improve the surge resistance of the device while avoiding the bipolar degradation effect.

[0009] Optionally, the MPS region includes: a first target P+ region, a second target P+ region, and a doping adjustment region, wherein the size of the second target P+ region is larger than that of the first target P+ region;

[0010] The first target P+ region is located on the adjacent side of each of the gate regions, and the adjacent side is the side of the gate region adjacent to another gate region.

[0011] The second target P+ region is located between the first target P+ regions;

[0012] The doping adjustment region is located between the first target P+ region and the second target P+ region.

[0013] Optionally, the conductivity type of the doping adjustment region is N-type or P-type.

[0014] Optionally, it further includes: a source metal layer; the source metal layer is located on the silicon carbide wafer and covers the gate region, the doped region and the MPS region, wherein the first target P+ region and the second target P+ region form an ohmic contact with the source metal layer, and the doping adjustment region forms a Schottky contact with the source metal layer.

[0015] Optionally, each gate region includes: a gate oxide layer, a gate polysilicon layer, and a dielectric layer;

[0016] The gate oxide layer is located on the silicon carbide wafer;

[0017] The gate polysilicon is located on top of the gate oxide layer;

[0018] The dielectric layer encapsulates the gate polysilicon and the gate oxide layer.

[0019] Optionally, each of the doped regions includes: a P-well region, a P+ region, and an N+ region;

[0020] The P-well region is located in the silicon carbide wafer;

[0021] The P+ region and the N+ region are located in the P-well region, the N+ region is located on the side away from the gate region, and the P+ region contacts the side of the N+ region away from the gate region. The surfaces of the P-well region, the P+ region and the N+ region are on the same horizontal plane as the surface of the silicon carbide wafer.

[0022] Optionally, the silicon carbide wafer includes: an N-type silicon carbide substrate and an N-type silicon carbide epitaxial layer, wherein the N-type silicon carbide epitaxial layer is located on the N-type silicon carbide substrate.

[0023] Optionally, it further includes: a current spreading layer, wherein the current spreading layer is located in the N-type silicon carbide epitaxial layer, and the surface of the current spreading layer is at the same horizontal plane as the surface of the N-type silicon carbide epitaxial layer, and the doped region and the MPS region are located on the current spreading layer.

[0024] Optionally, it may also include a drain metal layer located beneath the N-type silicon carbide substrate.

[0025] Based on the same inventive concept, in a second aspect, the present invention also provides a method for manufacturing a high-reliability SiC MOSFET device, for manufacturing the high-reliability SiC MOSFET device described in the first aspect, the method comprising:

[0026] Two gate regions are formed on a silicon carbide wafer;

[0027] A doped region is formed on the far side of each of the two gate regions, wherein the far side is the side of the gate region that is far from the other gate region;

[0028] On the silicon carbide wafer, a hybrid PIN Schottky diode region (MPS) is formed between the two gate regions, wherein the MPS region is used to improve the surge resistance of the device while avoiding bipolar degradation effects.

[0029] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:

[0030] This invention avoids the "bipolar degradation effect" caused by prolonged forward conduction by separating the gate structure, specifically by setting a hybrid PIN Schottky diode region (MPS) between the gate regions. Simultaneously, during the reverse breakdown voltage test, the MPS region between the gate regions widens the depletion layer between the doped region and the epitaxial layer of the silicon carbide wafer, shielding the Schottky junction of the MPS region's Schottky contact region and reducing reverse leakage current. Furthermore, the design of the MPS region in this invention shifts the strong electric field of the gate oxide (i.e., gate oxide layer) near the MPS structure down to the epitaxial layer with a higher critical breakdown field strength, improving the long-term reliability of the gate oxide and reducing device losses. During the forward conduction process, under low current conditions (i.e., normal operating state), only the Schottky contact region in the MPS region carries current; while under abnormally high current conditions (such as surge current), the PIN diode and Schottky contact region in the MPS region share the overcurrent, improving the device's reliability under extreme surge conditions, enhancing its ultimate overcurrent capability, and reducing device losses. Attached Figure Description

[0031] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0032] Figure 1 A schematic diagram of the structure of a high-reliability SiC MOSFET device in an embodiment of the present invention is shown;

[0033] Figure 2a The electric field intensity distribution of a SiC MOSFET device with a conventional split-gate integrated SBD structure in an embodiment of the present invention is shown.

[0034] Figure 2b The electric field intensity distribution of a high-reliability silicon carbide (SiC) MOSFET device in an embodiment of the present invention is shown.

[0035] Figure 3 The diagram illustrates the flow direction of the current path under different conditions in embodiments of the present invention;

[0036] Figure 4a The current-voltage curves of SiC MOSFET devices with different MPS regions in embodiments of the present invention are shown.

[0037] Figure 4b An embodiment of the present invention is shown. Figure 4a Enlarged view of the current-voltage curves of SiCMOSFET devices with different MPS regions under the BB' region;

[0038] Figure 5 This diagram illustrates a structure in which a P-well region and an N+ region are formed on an N-type silicon carbide epitaxial layer according to an embodiment of the present invention.

[0039] Figure 6 A schematic diagram of the structure for forming the doping adjustment region in an embodiment of the present invention is shown;

[0040] Figure 7 A schematic diagram of the structure forming the P+ region, the first target P+ region, and the second target P+ region in an embodiment of the present invention is shown.

[0041] Figure 8 A schematic diagram of the structure for forming a current spreading layer in an embodiment of the present invention is shown;

[0042] Figure 9 A schematic diagram of the structure for forming the gate oxide layer and the gate polysilicon in an embodiment of the present invention is shown;

[0043] Figure 10 A schematic diagram of the structure for forming the dielectric layer and the ohmic contact region in an embodiment of the present invention is shown;

[0044] Figure 11 A schematic diagram of the structure for forming the Schottky contact region in an embodiment of the present invention is shown;

[0045] Figure 12 A schematic flowchart of the manufacturing method of a high-reliability SiC MOSFET device in an embodiment of the present invention is shown;

[0046] In the attached figures, 110 is a silicon carbide wafer; 120 is a gate region; 130 is a doped region; 140 is an MPS region; 150 is a source metal layer; and 160 is a drain metal layer.

[0047] 111. N-type silicon carbide substrate; 112. N-type silicon carbide epitaxial layer; 113. Current spreading layer;

[0048] 121. Gate oxide layer; 122. Gate polysilicon; 123. Dielectric layer;

[0049] 131. P-well region; 132. P+ region; 133. N+ region;

[0050] 141. First target P+ region; 142. Second target P+ region; 143. Doping adjustment region; 144. Ohmic contact hole; 145. Schottky contact hole. Detailed Implementation

[0051] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0052] Example 1

[0053] The first embodiment of the present invention provides a high-reliability silicon carbide (SiC) MOSFET device, such as... Figure 1 As shown, the device includes: a silicon carbide wafer 110, two gate regions 120, two doped regions 130, and a merged pin / Schottky diode (MPS) region 140. The two gate regions 120 are located on the silicon carbide wafer 110. The two doped regions 130 are located on the silicon carbide wafer 110 and are respectively located on the opposite side of the two gate regions 120, where the opposite side is the side of one gate region 120 furthest from the other. The MPS region 140 is located on the silicon carbide wafer 110 and between the two gate regions 120, and is used to improve the surge protection capability of the device while avoiding bipolar degradation effects.

[0054] This embodiment avoids the "bipolar degradation effect" caused by prolonged forward conduction by separating the gate structure, i.e., setting a hybrid PIN Schottky diode region MPS region 140 between the gate regions 120. Simultaneously, during the reverse breakdown voltage process, the MPS region 140 between the gate regions 120 widens the depletion layer between the doped region 130 and the epitaxial layer of the silicon carbide wafer 110, shielding the Schottky junction of the Schottky contact region of the MPS region 140, reducing reverse leakage current. Furthermore, the design of the MPS region 140 in this embodiment shifts the strong electric field of the gate oxide (i.e., gate oxide layer 121) of the gate region 120 near the MPS structure down to the epitaxial layer with a higher critical breakdown field strength, improving the long-term reliability of the gate oxide of the gate region 120 and reducing device losses. During the forward conduction of the device, under low current conditions (i.e., the normal operating state of the device), only the Schottky contact area in MPS region 140 carries current; while under abnormally high current conditions (such as surge current), the PIN diode in MPS region 140 and the Schottky contact area share the current, improving the reliability of the device under extreme surge conditions, enhancing the device's ultimate overcurrent capability, and reducing device losses.

[0055] Below, in conjunction with Figure 1 This embodiment details the specific structure of the high-reliability silicon carbide (SiC) MOSFET device:

[0056] like Figure 1As shown, the silicon carbide wafer 110 includes: an N-type silicon carbide substrate 111, an N-type silicon carbide epitaxial layer 112, and a current spreading layer 113. The N-type silicon carbide epitaxial layer 112 is located on the N-type silicon carbide substrate 111. The doping concentration of the N-type silicon carbide epitaxial layer 112 is lower than that of the N-type silicon carbide substrate 111. The current spreading layer 113 is located within the N-type silicon carbide epitaxial layer 112, and the surface of the current spreading layer 113 is at the same horizontal plane as the surface of the N-type silicon carbide epitaxial layer 112. Doped regions 130 and MPS regions 140 are located on the current spreading layer 113, indicating that both doped regions 130 and MPS regions 140 are within the current spreading layer 113, and the surfaces of doped regions 130 and MPS regions 140 are at the same horizontal plane as the surface of the current spreading layer 113. The surface of the current spreading layer 113 (CSL) or the surface of the N-type silicon carbide epitaxial layer 112 is the surface of the silicon carbide wafer 110. In the region between the doped regions 130 (i.e., the gate region 120 corresponding to the JFET region in the N-type silicon carbide epitaxial layer 112), the current spreading layer 113 (CSL) is introduced by controlling the injection dose and energy to reduce the on-resistance and forward voltage drop of the device, thereby optimizing the device loss.

[0057] like Figure 1 As shown, each gate region 120 on the silicon carbide wafer 110 includes: a gate oxide layer 121, a gate polysilicon layer 122, and a dielectric layer 123. The gate oxide layer 121 is located on the silicon carbide wafer 110. The gate polysilicon layer 122 is located on the gate oxide layer 121. The dielectric layer 123 encloses the gate polysilicon layer 122 and the gate oxide layer 121. In this embodiment, the gate region 120 is a split gate structure, that is, the overall gate is separated into two gate regions 120. The dielectric layer 123 is an ILD (Inter-Layer Dielectric) dielectric layer. An ILD dielectric layer refers to a dielectric material formed between the device and the metal layer to form electrical isolation. The ILD dielectric layer can effectively reduce the parasitic capacitance between the metal and the substrate and improve the parasitic field-effect transistor formed when the metal spans different regions.

[0058] Two doped regions 130 are located on the silicon carbide wafer 110, and are respectively located on the far side of the two gate regions 120. The far side of the gate region 120 is the side of the gate region 120 that is far away from the other gate region 120.

[0059] Specifically, in Figure 1In this design, two gate regions 120, denoted as the left gate region and the right gate region, are provided on the silicon carbide wafer 110. The left side of the left gate region is the side furthest from the right gate region, and the right side of the left gate region is the furthest side of the left gate region. The right side of the left gate region is the side closest to or adjacent to the right gate region, and the right side of the left gate region is the adjacent side of the left gate region. Similarly, the right side of the right gate region is the side furthest from the left gate region, and the right side of the right gate region is the furthest side of the right gate region. The left side of the right gate region is the side closest to or adjacent to the left gate region, and the left side of the right gate region is the adjacent side of the right gate region.

[0060] Two doped regions 130 are located in the current spreading layer 113 of the silicon carbide wafer 110, and the surfaces of the doped regions 130 and the current spreading layer 113 are on the same horizontal plane. The doped regions 130 are located on the far side of the gate region 120, as shown below. Figure 1 As shown, the two doped regions 130 are denoted as the left doped region and the right doped region, respectively. The left doped region is located on the far side of the left gate region (i.e., to the left of the left gate region), and the right doped region is located on the far side of the right gate region (i.e., to the right of the right gate region). Furthermore, the location range of the doped region 130 can correspond to no more than half of the gate region 120 itself.

[0061] Each doped region 130 includes a P-well region 131, a P+ region 132, and an N+ region 133. The P-well region 131 is located within the silicon carbide wafer 110, specifically within the current spreading layer 113. The P+ region 132 and N+ region 133 are located within the P-well region 131. The N+ region 133 is located on the remote side of the gate region 120. The P+ region 132 contacts the N+ region 133 on the remote side of the gate region 120. The surfaces of the P-well regions 131, 132, and 133 are on the same horizontal plane as the surface of the silicon carbide wafer 110.

[0062] Taking the left-doped region as an example, the N+ region of the left-doped region is located on the far side of the left gate region (i.e., to the left of the left gate region). The P+ region of the left-doped region is located to the left of the N+ region of the left-doped region and is in contact with the left side of the N+ region of the left-doped region. The structure of the right-doped region is similar and will not be described in detail here.

[0063] MPS region 140 is located on silicon carbide wafer 110 and between two gate regions 120. MPS region 140 includes a first target P+ region 141, a second target P+ region 142, and a doping adjustment region 143. The second target P+ region 142 is larger than the first target P+ region 141. The first target P+ region 141 is located on the adjacent side of each gate region 120, with the adjacent side being the side of one gate region 120 adjacent to the other. The second target P+ region 142 is located between the first target P+ regions 141, and the doping adjustment region 143 is located between the first target P+ region 141 and the second target P+ region 142.

[0064] Specifically, the fact that the size of the second target P+ region 142 is larger than that of the first target P+ region 141 means that the width of the second target P+ region 142 is greater than that of the first target P+ region 141. The widths of the first target P+ region 141 and the second target P+ region 142 can be set according to actual needs. In the MPS region 140, the first target P+ region 141 can be referred to as the small P+ region, and the second target P+ region 142 can be referred to as the large P+ region.

[0065] Figure 1 The MPS region 140 shown is the simplest MPS region 140, which includes: two first target P+ regions 141, one second target P+ region 142, and two doping adjustment regions 143. The two first target P+ regions 141 are a left first target P+ region and a right first target P+ region, respectively. The left first target P+ region is located adjacent to the left gate region (i.e., to the right of the left gate region), and its location can be close to the left gate region. Similarly, the right first target P+ region is located adjacent to the right gate region (i.e., to the left of the right gate region), and its location can be close to the right gate region. The second target P+ region 142 is located between the two first target P+ regions 141. The two doping adjustment regions 143 are a left doping adjustment region and a right doping adjustment region, respectively. The left doping adjustment region is located between the left first target P+ region and the second target P+ region 142, and the right doping adjustment region is located between the right first target P+ region and the second target P+ region 142.

[0066] The MPS region 140 can also be configured with a more complex structure. The MPS region 140 includes: N first target P+ regions 141, N-1 second target P+ regions 142, and N doping adjustment regions 143, where N > 2. A first target P+ region 141 is provided on each adjacent side of each gate region 120, meaning a first target P+ region 141 is provided at each end of the MPS region 140. The first target P+ regions 141 and second target P+ regions 142 are alternately distributed between these two ends. The doping adjustment regions 143 are located between the first target P+ regions 141 and the second target P+ regions 142.

[0067] The conductivity type of the doped adjustment region 143 is either N-type or P-type. Depending on the application scenario, small-dose, low-energy N-type or P-type implantation is used to form the N-type or P-type doped adjustment region. If the conductivity type of the doped adjustment region 143 is N-type, the Schottky barrier height of the device is reduced, thereby reducing the turn-on voltage and forward voltage drop of the Schottky diode. If the conductivity type of the doped adjustment region 143 is P-type, the influence of the Schottky current on the potential below the first target P+ region 141 and the second target P+ region 142 is reduced by increasing the Schottky barrier height, thereby reducing the bipolar forward voltage (Vturn) of the MPS diode.

[0068] In this embodiment, the first target P+ region 141 in the MPS region 140 forms a PIN diode in the device, and the second target P+ region 142 in the MPS region 140 forms a Schottky contact region, i.e., a Schottky diode. During reverse breakdown, the design of the large and small P+ regions (i.e., the first target P+ region 141 and the second target P+ region 142) can shield the Schottky junction of the Schottky contact region, reducing reverse leakage current. Simultaneously, the small P+ region (i.e., the first target P+ region 141) can also reduce the electric field strength of the gate oxide near the MPS structure, improving the long-term reliability of the gate oxide, extending the lifespan of the gate oxide layer, and reducing device losses. Furthermore, the MPS region 140 structure design in this embodiment improves the reliability of the device under extreme surge conditions. The doping adjustment region 143 can adjust the bipolar forward voltage (Vturn) and forward voltage drop (VF) of the MPS diode according to different application requirements.

[0069] The device in this embodiment further includes a source metal layer 150. The source metal layer 150 is located on the silicon carbide wafer 110 and covers the gate region 120, the doped region 130, and the MPS region 140. The first target P+ region 141 and the second target P+ region 142 form an ohmic contact with the source metal layer 150, and the first target P+ region 141 and the second target P+ region 142 form a PIN diode with the N-type silicon carbide epitaxial layer 112. The doping adjustment region 143 forms a Schottky contact with the source metal layer 150, resulting in a Schottky contact region.

[0070] Specifically, the first target P+ region 141 and the second target P+ region 142 form an ohmic contact with the source metal layer 150 by forming an ohmic contact hole 144 at the interface between the first target P+ region 141 and the second target P+ region 142 and the source metal layer 150, respectively, and filling the ohmic contact hole 144 with metal to obtain an ohmic contact region. The doping adjustment region 143 forms a Schottky contact with the source metal layer 150 by forming a Schottky contact hole 145 at the interface between the doping adjustment region 143 and the source metal layer 150, and filling the Schottky contact hole 145 with metal to form a Schottky contact region.

[0071] The device in this embodiment also includes a drain metal layer 160. The drain metal layer 160 is located beneath the N-type silicon carbide substrate 111.

[0072] The working principle of the SiC MOSFET device in this embodiment:

[0073] The first target P+ region 141 (small P+ region) and the second target P+ region 142 (large P+ region) form an ohmic contact with the upper source metal layer 150, and form a PIN diode with the lower N-type silicon carbide epitaxial layer 112 and N-type silicon carbide substrate 111. The doping adjustment region 143 forms a Schottky contact with the upper source metal layer 150, generating a Schottky contact region. During reverse breakdown, the large and small P+ regions in the MPS region 140 will widen the depletion layer between the P-well region 131 and the N-type silicon carbide epitaxial layer 112, shielding the Schottky junction of the Schottky contact region and reducing reverse leakage current. At the same time, the design of the small P+ region shifts the strong electric field of the gate oxide near the MPS structure to the N-type silicon carbide epitaxial layer 112, which has a higher critical breakdown field strength, protecting the gate oxide, extending the gate oxide lifetime, and improving the long-term reliability of the gate oxide.

[0074] like Figure 2a and Figure 2b As shown, Figure 2a The diagram shows the electric field distribution of a SiC MOSFET device with a conventional split-gate integrated SBD (Schottky Barrier Diode) structure. Figure 2b This diagram shows the electric field distribution of the SiC MOSFET device with integrated MPS region 140 structure in this embodiment. A conventional SiC MOSFET device with a split-gate integrated SBD structure has the SBD structure integrated within the MOSFET gate region, while a Schottky diode contact region is retained in the JFET region below the conventional gate region. It can be understood that the conventional SiC MOSFET device with a split-gate integrated SBD structure is based on removing the MPS region 140 structure of this embodiment without the current spreading layer 113, and directly forming a Schottky contact between the N-type silicon carbide epitaxial layer 112 and the source metal layer 150 between the two gate regions 120. Figure 2a and Figure 2b In this context, "source" represents the source electrode, specifically the source metal layer 150. "gate" represents the gate electrode, specifically the gate region 120.

[0075] from Figure 2a The area outlined in the middle frame shows that... Figure 2a The gate region in the image corresponds to the region in the epitaxial layer. In conventional SiC MOSFET devices with a split-gate integrated SBD structure, a high electric field intensity exists near the gate oxide layer 121 in the gate region. From... Figure 2b The outlined area shows that, Figure 2b The gate region 120 corresponds to the region in the N-type silicon carbide epitaxial layer 112. In this embodiment, based on the MPS region 140 structure, the electric field strength near the gate oxide layer 121 of the gate region 120 of the device is significantly reduced. Therefore, the design of the first target P+ region 141 (i.e., the small P+ region) shifts the strong electric field of the gate oxide near the MPS structure to the N-type silicon carbide epitaxial layer 112, which has a higher critical breakdown field strength, thus protecting the gate oxide, extending its lifetime, and improving its long-term reliability.

[0076] During forward conduction, under low current conditions (i.e., normal device operation), the PIN diodes below the first target P+ region 141 (small P+ region) and the second target P+ region 142 (large P+ region) have high turn-on voltages. Therefore, neither the first target P+ region 141 (small P+ region), the second target P+ region 142 (large P+ region), nor the PIN diodes themselves carry current; only the Schottky contact area carries current. However, under abnormally high current conditions (such as surge current), the PIN diodes turn on, and both the PIN diodes and the Schottky contact area experience current flow. The design of the second target P+ region 142 (large P+ region) reduces the bipolar turn-on voltage (Vturn) of the MPS region 140 diode and provides a spacious current path, improving the device's reliability under extreme surge conditions. The current paths under different conditions are as follows: Figure 3 As shown. In Figure 3 In the normal operating state of the device, the normal current path is such that only the Schottky contact area carries current; the first target P+ region 141 (small P+ region), the second target P+ region 142 (large P+ region), and the underlying PIN diode do not carry current. Under abnormally high current conditions, such as surge current, the surge current path is such that the PIN diode turns on, and the PIN diode and the Schottky contact area share the current. The MPS region 140 structure optimizes the device's ultimate overcurrent capability and improves its reliability under extreme surge conditions.

[0077] This embodiment also proposes that the integrated MPS region 140 structure can be formed into a doped adjustment region 143 by small-dose, low-energy N-type or P-type implantation according to different application scenarios. The N-type doped adjustment region formed by N-type implantation can reduce the Schottky barrier height, thereby reducing the turn-on voltage and forward voltage drop of the Schottky diode. The P-type doped adjustment region formed by P-type implantation can reduce the influence of the Schottky current on the potential below the first target P+ region 141 and the second target P+ region 142 by increasing the Schottky barrier height, thereby reducing the bipolar forward voltage (Vturn) of the MPS diode. Figure 4a As shown. In addition, this embodiment also introduces a current spreading layer 113 (CSL) by controlling the injection dose and energy of the JFET region to reduce the on-resistance and forward voltage drop of the device, thereby optimizing the device loss.

[0078] like Figure 4a and Figure 4b As shown, the horizontal axis represents the forward voltage drop VF of the MPS region 140 diode, and the vertical axis represents the current IF of the MPS region 140 diode. Curve A1 represents a SiC MOSFET device with an MPS region 140 structure featuring P-type implanted doped adjustment region 143, curve A2 represents a SiC MOSFET device with an MPS region 143 featuring N-type implanted doped adjustment region 143, and curve A3 represents a SiC MOSFET device with an MPS region 140 structure without a doped adjustment region. The BB' region represents an enlarged view of the three curves in the Schottky diode-dominated mode of the SiC MOSFET device, as shown in the figure. Figure 4b As shown, the CC' region represents the curve of the SiC MOSFET device in the dominant bipolar conduction mode. Specifically, the bipolar conduction of the SiC MOSFET device is the conduction mode of the PN junction formed by the first target P+ region 141, the second target P+ region 142, and the N+ region 133.

[0079] When there is a low forward voltage between the source and drain, the Schottky diode begins to conduct once it reaches the turn-on voltage. At this time, the MPS region 140 diode is far from reaching its turn-on voltage and is in the off state. Therefore, the IF-VF curve between the source and drain depends only on the Schottky diode, i.e., the BB' region. When there is a high forward voltage between the source and drain, the IF-VF curve between the source and drain depends only on the MPS region 140 diode, i.e., the CC' region (the current of the Schottky diode is very small compared to the MPS region 140 diode and can be ignored in qualitative analysis). The inflection points of the curves in the BB' and CC' regions correspond to the turn-on voltages of the Schottky diode and the MPS region 140 diode, respectively. In the BB' region, the Schottky diode of the SiC MOSFET device with an N-type implanted doped adjustment region 143 has the smallest turn-on voltage, while the Schottky diode of the SiC MOSFET device with a P-type implanted doped adjustment region 143 has the largest turn-on voltage. In the CC' region, the MPS region 140 diode of a SiC MOSFET device with a P-type implanted doped adjustment region 143 has the smallest bipolar on-state voltage / on-state voltage drop, while the MPS region 140 diode of a SiC MOSFET device with an N-type implanted doped adjustment region 143 has the largest bipolar on-state voltage / on-state voltage drop. Therefore, the doped adjustment region 143 is formed by low-dose, low-energy N-type or P-type implantation according to different application scenarios. The bipolar on-state voltage (Vturn) and forward voltage drop (VF) of the MPS region 140 diode are adjusted by the doped adjustment region 143.

[0080] The following describes the specific manufacturing process of the high-reliability SiC MOSFET device in this embodiment:

[0081] First, such as Figure 5 As shown, an N-type silicon carbide epitaxial layer 112 is formed on an N-type silicon carbide substrate 111. A P-well region 131 is formed on the N-type silicon carbide epitaxial layer 112 by defining a region using a photomask and a hard mask and performing multiple high-temperature aluminum ion implantations. Then, an N+ region 133 is formed in the P-well region 131 by defining a region using a self-aligned process and performing multiple high-temperature nitrogen ion implantations. The implantation dose range for the P-well region 131 is 1E13~1E15 cm⁻¹. -2 The junction depth ranges from 0.6 μm to 1.2 μm. The injection dose of 133 in the N+ region ranges from 1E14 to 2E16 cm. -2 The junction depth ranges from 0.2um to 0.5um.

[0082] Second, such as Figure 6As shown, a doping adjustment region 143 is formed in the N-type silicon carbide epitaxial layer 112 by defining the region through a mask and a hard mask and performing high-temperature implantation of aluminum ions or nitrogen ions. The junction depth of the doping adjustment region 143 ranges from 0.2 μm to 0.5 μm.

[0083] Third, such as Figure 7 As shown, by defining regions using a mask and a hard mask and performing multiple high-temperature aluminum ion implantations, a P+ region is formed in the P-well region 131, and a first target P+ region 141 and a second target P+ region 142 are formed in the region corresponding to the MPS region 140. The implantation dose range for P+ region 132, the first target P+ region 141, and the second target P+ region 142 is 1E15~1E17 cm⁻¹. -2 The junction depth ranges from 0.3µm to 0.8µm. The doping concentrations of P+ region 132, the first target P+ region 141, and the second target P+ region 142 can be the same or adjusted according to actual needs.

[0084] Fourth, such as Figure 8 As shown, a current spreading layer 113 is formed on an N-type silicon carbide epitaxial layer 112 through multiple high-temperature nitrogen ion implantations without a mask. Subsequently, a carbon layer is deposited on the surface of the N-type silicon carbide epitaxial layer 112 and subjected to high-temperature activation annealing. This activates the implanted ions while preventing the high-temperature volatilization of silicon atoms. The carbon layer is removed after annealing. The nitrogen ion implantation dose of the current spreading layer 113 ranges from 1E11 to 1E13 cm⁻¹. -2 The junction depth ranges from 0.4µm to 1.2µm. The annealing temperature ranges from 1700℃ to 2000℃, and the annealing time ranges from 10min to 60min.

[0085] Fifth, such as Figure 9 As shown, a gate oxide layer 121 is thermally grown on the surface of the N-type silicon carbide epitaxial layer 112 (a small amount of nitric oxide (NO) is introduced into the oxidizing atmosphere, which can greatly improve the SiO2 / SiC interface quality), followed by chemical deposition of gate polysilicon 122. Photolithography and etching are then performed at designated locations using a mask to form a split gate structure, i.e., a structure with two gate regions 120. The material of the gate oxide layer 121 includes, but is not limited to, SiO2, with a thickness ranging from 0.02 μm to 0.12 μm. The thickness of the gate polysilicon 122 ranges from 0.3 μm to 1 μm.

[0086] Sixth, such as Figure 10As shown, a dielectric layer 123 is deposited on the surface of the N-type silicon carbide epitaxial layer 112 and the separated gate structure (i.e., the gate polysilicon 122 and gate oxide layer 121 of the gate region 120). The dielectric layer is an ILD dielectric layer. Photolithography and dielectric layer etching are performed at designated locations using a mask. An ohmic contact hole 144 is formed at the interface between the first target P+ region 141, the second target P+ region 142, and the source metal layer 150. Subsequently, metallic nickel is sputtered by physical vapor deposition and annealed. An ohmic contact region is formed at the opening of the ohmic contact hole 144. The width of the ohmic contact hole 144 ranges from 0.3 μm to 1.2 μm. The dielectric layer 123 material includes, but is not limited to, silicon dioxide and borosilicate glass, with a thickness ranging from 0.4 μm to 1.2 μm.

[0087] Seventh, such as Figure 11 As shown, photolithography and dielectric layer etching are performed at designated locations using a mask to form a Schottky contact hole 145 at the interface between the doping adjustment region 143 and the source metal layer 150. Subsequently, physical vapor deposition sputtering of titanium is performed followed by annealing. A Schottky contact region is formed at the opening of the Schottky contact hole 145, and the width of the Schottky contact hole 145 ranges from 0.3 μm to 1.2 μm.

[0088] Eighth, such as Figure 1 As shown, a source metal layer 150 is formed above the dielectric layer 123. The material of the source metal layer 150 includes, but is not limited to, aluminum and copper. The thickness of the source metal layer 150 ranges from 2µm to 5µm. A drain metal layer 160 is formed below the N-type substrate. This finally forms the complete SiC MOSFET device structure of this embodiment.

[0089] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:

[0090] This embodiment avoids the "bipolar degradation effect" caused by prolonged forward conduction by separating the gate structure, specifically by setting a hybrid PIN Schottky diode region (MPS region) between the gate regions. Simultaneously, during the reverse breakdown voltage test, the MPS region between the gate regions widens the depletion layer between the doped region and the epitaxial layer of the silicon carbide wafer, shielding the Schottky junction of the MPS region's Schottky contact region and reducing reverse leakage current. Furthermore, the design of the MPS region in this embodiment shifts the strong electric field of the gate oxide (i.e., gate oxide layer) near the MPS structure down to the epitaxial layer with a higher critical breakdown field strength, improving the long-term reliability of the gate oxide and reducing device losses. During the forward conduction process, under low current conditions (i.e., normal operating state), only the Schottky contact region in the MPS region carries current; while under abnormally high current conditions (such as surge current), the PIN diode and Schottky contact region in the MPS region share the overcurrent, improving the device's reliability under extreme surge conditions, enhancing its ultimate overcurrent capability, and reducing device losses.

[0091] Example 2

[0092] Based on the same inventive concept, the second embodiment of the present invention also provides a method for manufacturing a high-reliability SiC MOSFET device, such as... Figure 12 As shown, the method for manufacturing the high-reliability SiC MOSFET device described in Example 1 includes:

[0093] S201, two gate regions are formed on a silicon carbide wafer;

[0094] S202, a doped region is formed on the far side of each of the two gate regions, wherein the far side is the side of the gate region that is far from the other gate region;

[0095] S203, a hybrid PIN Schottky diode region (MPS) is formed on the silicon carbide wafer between the two gate regions, wherein the MPS region is used to improve the surge protection capability of the device while avoiding bipolar degradation effects.

[0096] Since the manufacturing method of the high-reliability SiC MOSFET device described in this embodiment is the same manufacturing method used to implement the high-reliability SiC MOSFET device in Embodiment 1 of this application, those skilled in the art can understand the specific implementation method and various variations of the manufacturing method of the high-reliability SiC MOSFET device in this embodiment based on the high-reliability SiC MOSFET device described in Embodiment 1 of this application. Therefore, how this manufacturing method achieves the high-reliability SiC MOSFET device in Embodiment 1 of this application will not be described in detail here. Any manufacturing method used by those skilled in the art to implement the high-reliability SiC MOSFET device in Embodiment 1 of this application falls within the scope of protection of this application.

[0097] Those skilled in the art will understand that although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0098] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A high-reliability SiC MOSFET device, characterized in that, include: A silicon carbide wafer, two gate regions, two doped regions, and a hybrid PIN Schottky diode region (MPS region); The two gate regions are located on the silicon carbide wafer; The two doped regions are located on the silicon carbide wafer and are respectively located on the far side of the two gate regions, wherein the far side is the side of the gate region that is far away from the other gate region; The MPS region is located on the silicon carbide wafer and between the two gate regions, which is used to improve the surge resistance of the device while avoiding the bipolar degradation effect. The MPS region includes a first target P+ region, a second target P+ region, and a doping adjustment region, wherein the size of the second target P+ region is larger than that of the first target P+ region; the design of the second target P+ region reduces the bipolar forward voltage of the diode in the MPS region and provides a wide current path, thereby improving the reliability of the device under extreme surge conditions. The first target P+ region is located on the adjacent side of each of the gate regions, and the adjacent side is the side of the gate region adjacent to another gate region. The second target P+ region is located between the first target P+ regions; The doping adjustment region is located between the first target P+ region and the second target P+ region; The doping adjustment region is used to adjust the Schottky barrier height of the MPS region; The MPS region is used to widen the depletion layer between the doped region and the epitaxial layer of the silicon carbide wafer, shield the Schottky junction of the Schottky contact region of the MPS region, reduce reverse leakage current, and shift the strong electric field of the gate oxide layer of the gate region near the MPS region to the epitaxial layer of the silicon carbide wafer with a higher critical breakdown field strength, thereby improving the long-term reliability of the gate oxide layer of the gate region and reducing the device loss. The conductivity type of the doping adjustment region is N-type or P-type; In the Schottky diode-dominant mode of the device, the Schottky barrier height is reduced by the N-type doped adjustment region, thereby reducing the turn-on voltage and forward voltage drop of the Schottky diode. In the bipolar conduction-dominant mode of the device, the Schottky barrier height is increased by the P-type doped adjustment region to reduce the influence of the Schottky current on the potential below the first target P+ region and the second target P+ region, thereby reducing the bipolar conduction voltage of the MPS region diode. In the bipolar conduction-dominant mode of the device, the bipolar conduction voltage of the MPS region diode is increased by the N-type doped adjustment region to further improve the bipolar degradation effect of the device. A source metal layer; the source metal layer is located on the silicon carbide wafer and covers the gate region, the doped region and the MPS region, wherein the first target P+ region and the second target P+ region form an ohmic contact with the source metal layer, and the doping adjustment region forms a Schottky contact with the source metal layer.

2. The SiC MOSFET device as described in claim 1, characterized in that, Each gate region includes: a gate oxide layer, a gate polysilicon layer, and a dielectric layer; The gate oxide layer is located on the silicon carbide wafer; The gate polysilicon is located on top of the gate oxide layer; The dielectric layer encapsulates the gate polysilicon and the gate oxide layer.

3. The SiC MOSFET device as described in claim 1, characterized in that, Each of the doped regions includes: a P-well region, a P+ region, and an N+ region; The P-well region is located in the silicon carbide wafer; The P+ region and the N+ region are located in the P-well region, the N+ region is located on the side away from the gate region, and the P+ region contacts the side of the N+ region away from the gate region. The surfaces of the P-well region, the P+ region and the N+ region are on the same horizontal plane as the surface of the silicon carbide wafer.

4. The SiC MOSFET device as described in claim 1, characterized in that, The silicon carbide wafer includes an N-type silicon carbide substrate and an N-type silicon carbide epitaxial layer, wherein the N-type silicon carbide epitaxial layer is located on the N-type silicon carbide substrate.

5. The SiC MOSFET device as described in claim 4, characterized in that, Also includes: A current spreading layer is located within the N-type silicon carbide epitaxial layer, and the surface of the current spreading layer is at the same horizontal plane as the surface of the N-type silicon carbide epitaxial layer. The doped region and the MPS region are located on the current spreading layer.

6. The SiC MOSFET device as described in claim 5, characterized in that, Also includes: A drain metal layer is located beneath the N-type silicon carbide substrate.

7. A method for manufacturing a high-reliability SiC MOSFET device, characterized in that, The method is used to manufacture a high-reliability SiC MOSFET device as described in any one of claims 1-6; the method includes: Two gate regions are formed on a silicon carbide wafer; A doped region is formed on the far side of each of the two gate regions, wherein the far side is the side of the gate region that is far from the other gate region; On the silicon carbide wafer, a hybrid PIN Schottky diode region (MPS) is formed between the two gate regions, wherein the MPS region is used to improve the surge resistance of the device while avoiding bipolar degradation effects.

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