MOSFET device and manufacturing method thereof

Abstract

The invention provides a metal-oxide-semiconductor field effect transistor (MOSFET) device and a manufacturing method thereof. The MOSFET device includes an active region and a termination region. The terminal area is arranged around the periphery of the active area. The MOSFET device comprises a silicon carbide substrate and a silicon carbide epitaxial layer which are stacked. The active region comprises a plurality of gate structures which are arranged at intervals along a first direction and extend along a second direction; the gate structure is arranged on the side, away from the silicon carbide substrate, of the silicon carbide epitaxial layer, the first direction and the second direction are both parallel to the silicon carbide substrate, and a preset angle is formed between the first direction and the second direction. The terminal region comprises a grid line layer which is arranged on one side, far away from the silicon carbide substrate, of the silicon carbide epitaxial layer; and the grid line layer is electrically connected with each grid structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a MOSFET device and a method for manufacturing the same. Background Art

[0002] The breakdown field strength of silicon carbide can reach 3.5 (MV / cm), which is about 10 times that of silicon. Therefore, the thickness of the silicon carbide epitaxial layer required for withstand voltage is reduced, and it has the characteristics of high withstand voltage, low on-resistance, and low on-thermal resistance. The thermal conductivity of silicon carbide can reach 4.0 (W / cm·K), which is about 3 times that of silicon, and is suitable for high-temperature conditions. The saturated electron drift rate of silicon carbide is about 2 times that of silicon, which can be used in high-frequency applications. Therefore, power electronic systems based on silicon carbide MOSFET devices are the development direction of the new generation of power electronic systems.

[0003] However, current MOSFET devices still have the technical problem of low channel density. Summary of the invention

[0004] In view of the shortcomings of the existing methods, the present application proposes a MOSFET device and a manufacturing method thereof, so as to solve the technical problem of low channel density in the existing MOSFET devices.

[0005] In a first aspect, an embodiment of the present application provides a MOSFET device, comprising an active region and a terminal region, wherein the terminal region is arranged around the periphery of the active region, and the MOSFET device comprises: a stacked silicon carbide substrate and a silicon carbide epitaxial layer;

[0006] The active area comprises: a plurality of gate structures, the plurality of gate structures are arranged at intervals along a first direction and extend along a second direction; the gate structure is arranged on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate, the first direction and the second direction are both parallel to the silicon carbide substrate, and the first direction and the second direction have a preset angle;

[0007] The terminal region includes: a gate line layer, the gate line layer is arranged on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate;

[0008] The gate line layer is electrically connected to each of the gate structures.

[0009] Optionally, the active area further includes:

[0010] An interlayer dielectric layer, disposed on the outer surface of the gate structure;

[0011] An ohmic contact layer, disposed between adjacent interlayer dielectric layers, wherein an upper surface of the ohmic contact layer is closer to the silicon carbide substrate than an upper surface of the interlayer dielectric layer;

[0012] The second insulating layer is disposed on the upper surface of a portion of the ohmic contact layer and a portion of the interlayer dielectric layer.

[0013] Optionally, the active area further includes:

[0014] A plurality of well regions, wherein the plurality of well regions are arranged at intervals along the first direction and extend along the second direction, and the upper surface of the well region is flush with the upper surface of the silicon carbide epitaxial layer;

[0015] a plurality of first conductivity type source regions, the plurality of first conductivity type source regions are arranged at intervals along the first direction and extend along the second direction, and two first conductivity type source regions are symmetrically arranged in the well region; an upper surface of the first conductivity type source region is flush with an upper surface of the silicon carbide epitaxial layer;

[0016] A plurality of second conductivity type source regions, wherein the second conductivity type source region is disposed between two of the first conductivity type source regions, and is located in the well region and flush with an upper surface of the well region;

[0017] The ohmic contact layer contacts the second conductive type source region and a portion of the first conductive type source region.

[0018] Optionally, the active region further comprises: an extension layer;

[0019] The extension layer is arranged on a side of the second conductive type source region close to the silicon carbide substrate, and the extension layer is located inside the silicon carbide epitaxial layer.

[0020] Optionally, the active region further comprises: a gate dielectric structure;

[0021] The gate dielectric structure is arranged on a side of the gate structure close to the well region;

[0022] Optionally, the terminal area further includes:

[0023] A field line ring is arranged inside a side of the silicon carbide epitaxial layer away from the silicon carbide substrate, and an upper surface of the field line ring is flush with an upper surface of the silicon carbide epitaxial layer;

[0024] A first insulating layer, disposed between the field line ring and the gate line layer;

[0025] An interlayer dielectric layer is arranged on a side of the gate line layer away from the first insulating layer, the interlayer dielectric layer has a second through hole, and the second through hole exposes a portion of the gate line layer;

[0026] A second insulating layer, disposed on an outer surface of the interlayer dielectric layer, the second insulating layer comprising a third through hole, the third through hole being connected to the second through hole;

[0027] The gate metal layer is disposed on a side of the second insulating layer away from the silicon carbide substrate, and passes through the second through hole and the third through hole to be electrically connected to the gate line layer.

[0028] Optionally, the active area further comprises: a source metal layer; the source metal layer is arranged on top of the interlayer dielectric layer and the ohmic contact layer;

[0029] The power device further comprises:

[0030] A third insulating layer, disposed outside the source metal layer and the gate metal layer;

[0031] The fourth insulating layer is arranged on the outer surface of the third insulating layer.

[0032] A drain metal layer is disposed on a side of the silicon carbide substrate away from the silicon carbide epitaxial layer.

[0033] In a second aspect, an embodiment of the present application provides a method for manufacturing the MOSFET device described in the first aspect, comprising:

[0034] S1: Fabricating a silicon carbide epitaxial layer on one side of a silicon carbide substrate;

[0035] S2: Manufacturing a plurality of gate structures located in an active area on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate, such that the plurality of gate structures are arranged at intervals along a first direction and extend along a second direction, and manufacturing a gate line layer located in a terminal area, such that the gate line layer is electrically connected to each of the gate structures.

[0036] Optionally, after step S2, the method further comprises:

[0037] Manufacturing an interlayer dielectric layer on the outer surface of the gate structure;

[0038] An ohmic contact layer is manufactured at a portion between the interlayer dielectric layers, so that an upper surface of the ohmic contact layer is closer to the silicon carbide substrate than an upper surface of the interlayer dielectric layer.

[0039] Optionally, after step S1 and before step S2, the method further includes:

[0040] Manufacturing a plurality of well regions inside the silicon carbide epitaxial layer located in the active area on a side away from the silicon carbide substrate, so that the plurality of well regions are spaced apart along the first direction and extend along the second direction, and the upper surface of the well region is flush with the upper surface of the silicon carbide epitaxial layer;

[0041] Manufacturing a symmetrically arranged first conductivity type source region inside the well region so that the upper surface of the first conductivity type source region is flush with the upper surface of the well region;

[0042] A second conductive type source region is manufactured between two of the first conductive type source regions. The second conductive type source region is disposed between the two of the first conductive type source regions and is located in the well region and flush with the upper surface of the well region.

[0043] The beneficial technical effects brought about by the technical solution provided by the embodiment of the present application include:

[0044] Setting the gate line layer in the terminal area can save the area of ​​the active area occupied by the gate line layer in the related art, increase the area of ​​the active area, and further increase the density of the well area (channel) set in the active area, which is beneficial to reduce the on-resistance.

[0045] In addition, the gate line layer is arranged in the terminal area and acts as a voltage-resistant field plate, which can improve the voltage-resistant capability; at the same time, because the gate line layer can act as a voltage-resistant field plate, the field line ring 8 arranged in the terminal area can be reduced, further reducing the area occupied by the terminal area, thereby increasing the area of ​​the active area, which is conducive to increasing the conduction current.

[0046] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0048] Figure 1 A schematic top view of a power device provided in an embodiment of the present application;

[0049] Figure 2 for Figure 1 Schematic diagram of the cross section at AA';

[0050] Figure 3 A schematic diagram of a process for manufacturing a power device provided in an embodiment of the present application;

[0051] Figures 4 to 17 This is a structural schematic diagram obtained from each step in a flow diagram for manufacturing a power device provided in an embodiment of the present application.

[0052] Description of reference numerals:

[0053] B-active region; C-terminal region;

[0054] 1-Silicon carbide substrate;

[0055] 2-silicon carbide epitaxial layer; 21-extension layer;

[0056] 31-well region; 32-first conductivity type source region; 33-second conductivity type source region;

[0057] 41-gate dielectric structure; 42-gate structure; 43-gate line layer;

[0058] 5-interlayer dielectric layer;

[0059] 6-Ohmic contact layer;

[0060] 71-source metal layer; 72-gate metal layer;

[0061] 8-field line loop;

[0062] 911 - first insulating layer; 92 - second insulating layer; 93 - third insulating layer; 94 - fourth insulating layer;

[0063] 10- drain metal layer; 103- initial gate dielectric layer. DETAILED DESCRIPTION

[0064] The embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the implementation methods described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0065] It will be understood by those skilled in the art that, unless specifically stated, the "said" and "the" used herein may also include plural forms. It should be further understood that the wording "including" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the present technical field. It should be understood that when we say that an element is "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or it may refer to the connection relationship between the element and the other element through an intermediate element. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein refers to at least one of the items defined by the term, for example, "A and / or B" may be implemented as "A", or as "B", or as "A and B".

[0066] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0067] Currently, the active area of ​​existing power devices needs to be provided with an area for placing the gate metal layer and the gate line layer. There is no channel arrangement in this area, which does not participate in the forward current flow of the power device. As a result, the area of ​​the power device is not fully utilized, the channel density is small, and the on-resistance of the power device cannot be effectively reduced.

[0068] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above technical problems with specific embodiments. It should be noted that the following implementations can refer to, draw on or combine with each other, and the same terms, similar features and similar implementation steps in different implementations will not be described repeatedly.

[0069] The descriptions "first conductivity type" and "second conductivity type" used in this application refer to n-type conductivity (i.e., electron conductivity) and p-type conductivity (i.e., hole conductivity), respectively. Specifically, the first conductivity type is n-type conductivity, and the second conductivity type is p-type conductivity; or, the first conductivity type is p-type conductivity, and the second conductivity type is n-type conductivity.

[0070] The present application embodiment provides a MOSFET device. The structural diagram of the power device is as follows: Figure 1 and Figure 2 shown.

[0071] like Figure 1 and Figure 2 As shown, the power device includes an active region B and a terminal region C, wherein the terminal region C is arranged around the periphery of the active region B.

[0072] like Figure 2 As shown, the power device includes a silicon carbide substrate 1 and a silicon carbide epitaxial layer 2 which are stacked.

[0073] In this embodiment, the silicon carbide substrate 1 may be an n+ type silicon carbide substrate, and the silicon carbide epitaxial layer 2 may be an n- type silicon carbide epitaxial layer. The doping impurities of the silicon carbide substrate 1 and the silicon carbide epitaxial layer 2 both include nitrogen or phosphorus, and the doping impurities of the silicon carbide substrate 1 and the silicon carbide epitaxial layer 2 may be the same or different, and no specific restrictions are made here. The thickness of the silicon carbide substrate 1 is not less than 100 microns and not more than 500 microns, and the doping concentration is 1*10 18 -1*10 20 / cm 2 The thickness of the silicon carbide epitaxial layer 2 is not less than 1 micron and not more than 50 microns, and the doping concentration is 1*10 14 -1*10 19 / cm 2 .

[0074] like Figure 2 As shown, the active area B includes: a plurality of gate structures 42. The plurality of gate structures 42 are arranged in a first direction and extend in a second direction. The gate structure 42 is disposed on a side of the silicon carbide epitaxial layer 2 away from the silicon carbide substrate 1. The first direction and the second direction are both parallel to the silicon carbide substrate 1, and the first direction and the second direction have a preset angle.

[0075] It is understandable that the preset angle can be any angle set according to the requirements. Exemplarily, the first direction of the present application is perpendicular to the second direction.

[0076] like Figure 2 As shown, the terminal region C includes a gate line layer 43. The gate line layer 43 is disposed on a side of the silicon carbide epitaxial layer 2 away from the silicon carbide substrate 1.

[0077] The gate line layer 43 is electrically connected to each gate structure 42 .

[0078] In this embodiment, the gate line layer 43 is set in the terminal area C, which can save the area occupied by the gate line layer in the active area B in the related technology, increase the area of ​​the active area B, and further increase the density of the well area 31 (channel) set in the active area B, which is beneficial to reduce the on-resistance.

[0079] In addition, the gate line layer 43 is arranged in the terminal area C, acting as a voltage-resistant field plate, which can improve the voltage resistance; at the same time, because the gate line layer 43 can play the role of a voltage-resistant field plate, the field line ring 8 set in the terminal area C can be reduced, further reducing the area occupied by the terminal area C, thereby increasing the area of ​​the active area B, which is beneficial to increase the conduction current.

[0080] Optionally, the active region B further includes an interlayer dielectric layer 5, an ohmic contact layer 61 and a second insulating layer 92. The interlayer dielectric layer 5 is disposed on the outer surface of the gate structure 42. The ohmic contact layer 61 is disposed in a portion between adjacent interlayer dielectric layers 5, and the upper surface of the ohmic contact layer 61 is closer to the silicon carbide substrate 1 than the upper surface of the interlayer dielectric layer 5. The second insulating layer 92 is disposed on the upper surface of a portion of the ohmic contact layer 61 and a portion of the interlayer dielectric layer 5.

[0081] In this embodiment, the interlayer dielectric layer 5 can isolate the gate structure 42 and the source metal layer 71. The ohmic contact layer 61 is disposed between adjacent interlayer dielectric layers 5, and the upper surface of the ohmic contact layer 61 is lower than the upper surface of the interlayer dielectric layer 5, that is, the thickness of the ohmic contact layer 61 is thinned, which can reduce the on-resistance of the current. The active area B is filled with the ohmic contact layer 61, which can make the source on-current evenly distributed and the heat generation evenly distributed. The second insulating layer 92 can isolate the ohmic contact layer 61 and the gate metal layer 72 to avoid electrical interference with each other.

[0082] Optionally, refer to Figure 2 The active region B further includes a plurality of well regions 31 , a plurality of first conductivity type source regions 32 , and a plurality of second conductivity type source regions 33 .

[0083] The plurality of well regions 31 are arranged at intervals along the first direction and extend along the second direction. The upper surface of the well region 31 is flush with the upper surface of the silicon carbide epitaxial layer 2 .

[0084] A plurality of first conductivity type source regions 32 are arranged at intervals along the first direction and extend along the second direction. Two first conductivity type source regions 32 are symmetrically arranged in the well region 31 . The upper surface of the first conductivity type source region 32 is flush with the upper surface of the silicon carbide epitaxial layer 2 .

[0085] The second conductive type source region 33 is disposed between the two first conductive type source regions 32 , and is located in the well region 31 and flush with the upper surface of the well region 31 .

[0086] The ohmic contact layer 61 contacts the second conductivity type source region 33 and a portion of the first conductivity type source region 32 .

[0087] In this embodiment, the well region 31 is laid in the active region B, and the first conductive type source region 32 is symmetrically arranged in the well region 31. When the current is turned on, the current can flow to the drain metal layer 10 through the two symmetrically arranged first conductive type source regions 32 through the well region 31, thereby making the forward conduction current generate heat more uniformly, which is beneficial to improving the stability of the power device when working at high temperatures.

[0088] It can be understood that the well region 31 is lightly doped with the second conductivity type, the first conductivity type source region 32 is heavily doped, and the second conductivity type source region 33 is heavily doped.

[0089] Alternatively, if Figure 2 As shown, the active region B further includes an extension layer 21 . The extension layer 21 is disposed on a side of the second conductive type source region 33 close to the silicon carbide substrate 1 , and the extension layer 21 is located inside the silicon carbide epitaxial layer 2 .

[0090] In this embodiment, the extension layer 21 is lightly doped with the first conductivity type, and the doping concentration is higher than that of the silicon carbide epitaxial layer 2. The extension layer 21 can make the current more evenly distributed when it reaches the bottom of the well region 31. The current path is filled with the silicon carbide epitaxial layer 2 in advance, and the area between adjacent well regions 31 has a large resistance. The extension layer 21 can reduce the on-resistance here.

[0091] Alternatively, if Figure 2 As shown, the active region B further includes a gate dielectric structure 41 . The gate dielectric structure 41 is disposed on a side of the gate structure 42 close to the well region 31 .

[0092] In this embodiment, the ohmic contact layer 61 is in contact with the first conductive type source region 32 and the second conductive type source region 33 to form an ohmic contact, which can reduce the flow resistance of the source current.

[0093] Alternatively, if Figure 2 As shown, the terminal region C further includes: a field line ring 8 , a first insulating layer 91 , an interlayer dielectric layer 5 , a second insulating layer 92 , and a gate metal layer 72 .

[0094] The field line ring 8 is disposed inside a side of the silicon carbide epitaxial layer 2 away from the silicon carbide substrate 1 , and an upper surface of the field line ring 8 is flush with an upper surface of the silicon carbide epitaxial layer 2 .

[0095] The first insulating layer 91 is disposed on a side of the silicon carbide epitaxial layer 2 away from the silicon carbide substrate 1 .

[0096] The interlayer dielectric layer 5 is disposed on both sides and the top of the gate line layer 43 away from the first insulating layer 91 . The interlayer dielectric layer 5 has a second through hole, and the second through hole exposes a portion of the gate line layer 43 .

[0097] The second insulating layer 92 is disposed on the outer surface of the interlayer dielectric layer 5 . The second insulating layer includes a third through hole, and the third through hole is connected to the second through hole.

[0098] The gate metal layer 72 is disposed on a side of the second insulating layer 92 away from the silicon carbide substrate 1 , and is electrically connected to the gate line layer 43 through the second through hole and the third through hole.

[0099] In this embodiment, the gate current flows to the gate line layer 43 through the gate metal layer 72, and then flows to each parallel gate structure 42 electrically connected to the gate line layer 43, thereby controlling the gate current. The gate line layer 43 is arranged in the terminal area C, which can save the area occupied by the gate line layer 43, thereby increasing the density of the well area (channel), which is conducive to improving the current conduction capability.

[0100] Optionally, the doping concentration range of the field line loop is not less than 1*10 18 per cubic centimeter and not more than 1*10 19 The manufacturing depth is not less than 0.3 microns and not more than 0.6 microns per cubic centimeter.

[0101] Alternatively, if Figure 2 As shown, the active region B further includes a source metal layer 71 . The source metal layer 71 is disposed on top of the interlayer dielectric layer 5 and the ohmic contact layer 6 .

[0102] The power device further includes: a third insulating layer 93 , a fourth insulating layer 94 and a drain metal layer 10 .

[0103] The third insulating layer 93 is disposed outside the source metal layer 71 and the gate metal layer 72 .

[0104] The fourth insulating layer 94 is disposed on the outer surface of the third insulating layer 93 .

[0105] The drain metal layer 10 is disposed on a side of the silicon carbide substrate 1 away from the silicon carbide epitaxial layer 2 .

[0106] In this embodiment, the third insulating layer 93 and the fourth insulating layer 94 can isolate the source metal layer 71 from the gate metal layer 72. The material of the third insulating layer 93 includes at least one of oxide, nitride and oxynitride. The material of the fourth insulating layer 94 includes polyimide. The fourth insulating layer 94 can better isolate water vapor.

[0107] Based on the same inventive concept, the present application embodiment provides a method for manufacturing the above-mentioned MOSFET device, and the flow chart of the method is as follows: Figure 3 As shown, the method includes step S1 and step S2, which are specifically as follows:

[0108] S1: a silicon carbide epitaxial layer 2 is produced on one side of a silicon carbide substrate 1 .

[0109] In this embodiment, a silicon carbide epitaxial layer 2 is fabricated on one side of a silicon carbide substrate 1 by epitaxial growth, and the obtained structure is as follows: Figure 4 shown.

[0110] Exemplarily, the silicon carbide substrate 1 is heavily doped with the first conductivity type, and the silicon carbide epitaxial layer 2 is lightly doped with the first conductivity type. The thickness of the silicon carbide substrate 1 ranges from 100 microns to 500 microns, and the doping concentration is 1*10 18 -1*10 20 / cm 3 The thickness of the silicon carbide epitaxial layer 2 ranges from 1 micron to 50 microns, and the doping concentration is 1*10 14 -1*10 19 / cm 3 The doping impurities of the silicon carbide substrate 1 and the silicon carbide epitaxial layer 2 both include nitrogen or phosphorus. In this embodiment, the doping impurity is nitrogen.

[0111] Optionally, after step S1 and before step S2, the method further includes:

[0112] A plurality of well regions 31 are fabricated inside the silicon carbide epitaxial layer 2 located in the active region A on a side away from the silicon carbide substrate 1, so that the plurality of well regions 31 are spaced apart along a first direction and extend along a second direction, and the upper surface of the well region 31 is flush with the upper surface of the silicon carbide epitaxial layer 2, and the obtained structure is as follows: Figure 5 shown.

[0113] A symmetrically arranged first conductive type source region 32 is fabricated inside the well region 31 so that the upper surface of the first conductive type source region 32 is flush with the upper surface of the well region 31. The obtained structure is as follows: Figure 6 shown.

[0114] A second conductive type source region 33 located in the active region B is fabricated between the two first conductive type active regions 32 so that the upper surface of the second conductive type source region 33 is flush with the upper surface of the first conductive type source region 32. The obtained structure is as follows: Figure 7 shown.

[0115] In this embodiment, a mask is used to define the injection area (located on the side of the silicon carbide epitaxial layer 2 in the active area B away from the silicon carbide substrate 1) by photolithography and etching on the mask layer (not shown in the figure), and the well region 31 is formed by injection at a temperature between 200 degrees Celsius and 500 degrees Celsius. Since the well region 31 is formed by injection at high temperature, the material of the mask layer is selected as an oxide that is relatively stable at high temperature. The thickness of the mask layer is determined by the type, energy and dose of the injected element to ensure that the element does not penetrate the mask layer and enter the silicon carbide epitaxial layer 2 during injection. The well region 31 is lightly doped with the second conductivity type. The doping concentration range of the well region 31 is 5*10 16 per cubic centimeter to 5*10 17 The depth of the well region 31 ranges from 0.8 micrometers to 1.2 micrometers. The doping elements of the well region 31 of the second conductivity type include boron (B), aluminum (Al), and the like.

[0116] The first conductive type source region 32 is heavily doped, and the doping concentration range is not less than 1*10 18 per cubic centimeter and not more than 1*10 19 The depth of the fabrication is not less than 0.2 micrometers and not more than 0.4 micrometers per cubic centimeter. The doping type of the first conductive type source region 32 includes nitrogen or phosphorus.

[0117] The second conductive type source region 33 is heavily doped, and the doping concentration range is not less than 1*10 18 per cubic centimeter and not more than 1*10 19 The depth of the second conductive type source region 33 is not less than 0.3 micrometers and not more than 0.6 micrometers per cubic centimeter. The lower surface of the second conductive type source region 33 is closer to the silicon carbide substrate 1 than the lower surface of the first conductive type source region 32. The doping elements of the second conductive type source region 33 include boron (B), aluminum (Al), and the like.

[0118] Optionally, after the step of manufacturing the second conductivity type source region 33 located in the active region B between the two first conductivity type active regions 32 and before step S2, the method further comprises:

[0119] In the active region B, an extension layer 21 is fabricated on the side of the well region 31 close to the silicon carbide substrate 1, and the resulting structure is as follows: Figure 8 shown.

[0120] In the terminal region C, a first insulating layer 91 is formed on the side of the silicon carbide epitaxial layer 2 away from the silicon carbide substrate 1, and the obtained structure is as follows: Fig. 9 shown.

[0121] In the active region B, a primary gate dielectric layer 103 is manufactured on the upper surface of the structure obtained after manufacturing the second conductive type source region 33. The obtained structure is as follows: Fig.10 shown.

[0122] In this embodiment, the extension layer 21 is formed by photolithography and etching implantation on a mask layer (not shown) through a mask plate at a high temperature (200°C to 500°C). Both the extension layer 21 and the silicon carbide epitaxial layer 2 are lightly doped with the first conductivity type, and the doping concentration of the extension layer 21 is not less than 5*10 15 per cubic centimeter and not more than 2*10 16 The doping depth is not less than 0.8 micrometers and not more than 2 micrometers per cubic centimeter. The doping type of the extension layer 21 includes nitrogen or phosphorus.

[0123] The first insulating layer 91 is obtained by photolithography on the dielectric layer through a mask, and is disposed in the terminal region C. The material of the first insulating layer 91 includes oxide. The thickness of the first insulating layer 91 is set according to the withstand voltage of the terminal region C. Exemplarily, the thickness of the first insulating layer 91 is not less than 0.1 micrometers and not more than 2 micrometers.

[0124] The primary gate dielectric layer 103 forms silicon dioxide by an oxidation reaction of oxygen and silicon carbide in a high temperature environment, and the oxidation temperature is not less than 1200° C. and not higher than 1400° C. The thickness of the primary gate dielectric layer 103 is not less than 10 nanometers and not more than 100 nanometers. In order to ensure the compactness and withstand voltage of the primary gate dielectric layer 103, it is necessary to use N-doped annealing to reduce the interface state density, improve the carrier mobility, and thus reduce the channel resistance.

[0125] S2: A plurality of gate structures 42 are fabricated in the active region B on the side of the silicon carbide epitaxial layer 2 away from the silicon carbide substrate 1, so that the gate structures 42 are arranged at intervals along the first direction and extend along the second direction. At the same time, a gate line layer 43 is fabricated in the terminal region C, so that the gate line layer 43 is electrically connected to each gate structure 42. The obtained structural schematic diagram is shown in FIG. Fig.11 shown.

[0126] In the present embodiment, the gate structure 42 is formed by photolithography and etching on the gate layer using a mask, and the thickness of the gate structure 42 is not less than 0.1 micron and not more than 1 micron. The material of the gate structure 42 includes polysilicon or metal doped with P. The gate line layer 43 is arranged in the terminal area C, which can save the area occupied by the gate line layer 43, thereby increasing the density of the well area 31, which is beneficial to reducing the on-resistance of the current. In addition, the gate line layer 43 is arranged in the terminal area C, which acts as a voltage-resistant field plate, and can also increase the voltage-resistant capacity of the terminal area C, and can also reduce the area of ​​the field line ring 8 with voltage-resistant capacity, thereby further increasing the area of ​​the well area 31 of the active area B, which is beneficial to reducing the on-resistance.

[0127] Optionally, after step S2, the method further comprises:

[0128] An interlayer dielectric layer 5 is formed on the outer surface of the gate structure 42 .

[0129] An ohmic contact layer 6 is fabricated between the interlayer dielectric layers 5 so that the upper surface of the ohmic contact layer 6 is closer to the silicon carbide substrate 1 than the upper surface of the interlayer dielectric layer 5. The obtained structure is as follows: Fig.13 shown.

[0130] In this embodiment, the ohmic contact layer 61 is formed by ohmic contact metal deposition, rapid thermal annealing (RTA), and metal stripping on the insulating layer.

[0131] Optionally, the material of the ohmic contact layer 61 includes nickel silicide, and the thickness of the ohmic contact layer 61 is not less than 50 nanometers and not more than 500 nanometers.

[0132] Optionally, the step of manufacturing the interlayer dielectric layer 5 on the outer surface of the gate structure 42 includes:

[0133] An initial interlayer dielectric layer is manufactured on the surface of the structure obtained after manufacturing the gate structure 42 , and the initial interlayer dielectric layer covers the active area B and the terminal area C.

[0134] The initial interlayer dielectric layer not covering the surface of the gate structure 42 in the active region B is removed to form an interlayer dielectric layer 5, and then the initial gate dielectric layer 103 not covered by the gate structure 42 and the interlayer dielectric layer 5 in the active region B is removed to form a gate dielectric structure 41. The obtained structural schematic diagram is shown in FIG. Fig.12 In this embodiment, the gate dielectric structure 42 covers the well region 31 and a portion of the first conductive type source region 32 .

[0135] Optionally, after manufacturing the ohmic contact layer 6 in the portion between the interlayer dielectric layers 5, the method further comprises:

[0136] An initial second insulating layer is produced on the side of the ohmic contact layer 6 away from the silicon carbide substrate 1 , and the initial second insulating layer extends to the terminal region C.

[0137] The initial second insulating layer in the area of ​​the source metal layer 71 to be subsequently manufactured is removed, and the interlayer dielectric layer 5 and the initial second insulating layer on the top of the gate line layer 43 are removed to obtain the second insulating layer 92 .

[0138] In this embodiment, the structural diagram after obtaining the second insulating layer 92 is as follows: Fig.14 As shown. The material of the first insulating layer 91 includes one or more combinations of oxide or boron-phosphorus oxide. The material of the second insulating layer 92 includes at least one of silicon nitride, silicon oxynitride and polymer. The first insulating layer 91 and the second insulating layer 92 have a high selective etching ratio, which can ensure that the first insulating layer 91 will not be damaged when etching the second insulating layer 92.

[0139] Optionally, after obtaining the second insulating layer 92, the method further comprises:

[0140] A source metal layer 71 is fabricated on top of the interlayer dielectric layer 5 and the ohmic contact layer 6 .

[0141] A gate metal layer 72 is manufactured on the side of the second insulating layer 92 away from the silicon carbide substrate 1. The gate metal layer 72 is electrically connected to the gate line layer 43. The obtained structure is as follows: Fig.15 shown.

[0142] In this embodiment, the gate metal layer 72 extends to part of the active area B. The source metal layer 71 and the gate metal layer 72 are both formed by depositing metal and photolithography. The source metal layer 71 and the gate metal layer 72 are both stacked metal layers. The materials of each layer of the stacked metal layer may include titanium, titanium nitride and aluminum, or include titanium, titanium nitride and aluminum copper, or include titanium, titanium nitride and aluminum silicon copper. Among them, the thickness of titanium is not less than 10 nanometers and not more than 500 nanometers, the thickness of titanium nitride is not less than 10 nanometers and not more than 200 nanometers, and the thickness of aluminum, aluminum copper and aluminum silicon copper is not less than 1 micrometer and not more than 8 micrometers.

[0143] The gate metal layer 72 is electrically connected to the gate line layer 43, and the gate current flows through the gate metal layer 72 and the gate line layer 43 to reach all parallel gate structures 42 in the active area B to achieve control of the gate current. The source current flows through the source metal layer 71 and the ohmic contact layer 61 to reach all parallel first conductivity type source regions 32 and second conductivity type source regions 33 in the active area B to facilitate control of the source current. It can be understood that the gate metal layer 72 is the subsequent electrical test gate needle position or the package gate wire position. The source metal layer 71 is the subsequent electrical test source needle position or the package source wire position.

[0144] Optionally, after manufacturing the gate metal layer 72 on the side of the second insulating layer 92 away from the silicon carbide substrate 1, the method further comprises:

[0145] A third insulating layer 93 is manufactured on the outer surface of the source metal layer 71 and the gate metal layer 72. The obtained structural schematic diagram is as follows: Fig.16 shown.

[0146] A fourth insulating layer 94 is manufactured on the outer surface of the third insulating layer 93. The obtained structural schematic diagram is as follows: Fig.17 shown.

[0147] In this embodiment, the third insulating layer 93 is formed by photolithography on the deposited insulating layer using a mask. The third insulating layer 93 covers the side and part of the upper surface of the source metal layer 71 and the gate metal layer 72. The third insulating layer 93 can play the role of insulating, isolating and moisture-proofing the source metal layer 71 and the gate metal layer 72. The material of the third insulating layer 93 includes at least one of oxide, nitride and oxynitride. The thickness of the third insulating layer 93 is not less than 0.1 micrometer and not more than 10 micrometers.

[0148] The fourth insulating layer 94 is formed by photoresist spin coating, photolithography, and baking and curing. The fourth insulating layer 94 covers the surface of the third insulating layer 93, and can further insulate and isolate the source metal layer 71 and the gate metal layer 72. The material of the fourth insulating layer 94 includes polyimide. The thickness of the fourth insulating layer 94 is not less than 1 micron and not more than 20 microns. The fourth insulating layer 94 can be conducive to water vapor.

[0149] Optionally, after manufacturing the fourth insulating layer 94, the method further comprises: manufacturing a drain metal layer 10 on a side of the silicon carbide substrate 1 away from the silicon carbide epitaxial layer 2, and the obtained structure is as follows: Figure 2 shown.

[0150] In this embodiment, the drain metal layer 10 is formed by thinning the back side of the silicon carbide substrate 1, evaporating the ohmic contact metal, annealing, and drain metal evaporation, wherein the annealing is generally laser annealing or rapid thermal annealing (RTA). The material of the drain metal layer 10 includes stacked nickel silicide, titanium, nickel and silver. The thickness of the nickel silicide is not less than 50 nanometers and not more than 500 nanometers, the thickness of the titanium is not less than 0.1 micrometer and not more than 2 micrometers, the thickness of the nickel is not less than 0.1 micrometer and not more than 1.5 micrometers, and the thickness of the silver is not less than 0.5 micrometer and not more than 3 micrometers. After the silicon carbide substrate 1 is thinned, the thickness of the silicon carbide substrate 1 can be reduced, which is beneficial to reducing the forward on-resistance and heat generation, and is also beneficial to reducing the volume of the subsequent packaged power device.

[0151] It can be understood that the drain metal layer 10 is the location where the metal test carrier is contacted during electrical testing and the location where the conductive frame is connected during packaging.

[0152] Those skilled in the art will appreciate that the various operations, methods, steps, measures, and schemes in the processes discussed in this application may be alternated, changed, combined, or deleted. Furthermore, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be alternated, changed, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and schemes in the related art that are similar to those disclosed in this application may also be alternated, changed, rearranged, decomposed, combined, or deleted.

[0153] In the description of the present application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", and "outside" are exemplary directions or positional relationships based on the accompanying drawings. They are for the convenience of describing or simplifying the description of the embodiments of the present application, and do not indicate or imply that the referred device or component must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0154] The terms "first", "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0155] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0156] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0157] The above is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the scheme of the present application, other similar implementation methods based on the technical ideas of the present application are also within the protection scope of the embodiments of the present application.

Claims

1. A MOSFET device, comprising an active region and a terminal region, wherein the terminal region is disposed around the periphery of the active region, characterized in that: include: A stacked silicon carbide substrate and a silicon carbide epitaxial layer; The active area comprises: a plurality of gate structures, the plurality of gate structures are arranged at intervals along a first direction and extend along a second direction; the gate structure is arranged on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate, the first direction and the second direction are both parallel to the silicon carbide substrate, and the first direction and the second direction have a preset angle; The terminal region includes: a gate line layer, the gate line layer is arranged on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate; The gate line layer is electrically connected to each of the gate structures.

2. The MOSFET device according to claim 1, characterized in that The active region further comprises: An interlayer dielectric layer, disposed on the outer surface of the gate structure; An ohmic contact layer is disposed between adjacent interlayer dielectric layers, wherein the upper surface of the ohmic contact layer is closer to the silicon carbide substrate than the upper surface of the interlayer dielectric layer. The second insulating layer is disposed on the upper surface of a portion of the ohmic contact layer and a portion of the interlayer dielectric layer.

3. The MOSFET device according to claim 2, characterized in that: The active region further comprises: A plurality of well regions, wherein the plurality of well regions are arranged at intervals along the first direction and extend along the second direction, and the upper surface of the well region is flush with the upper surface of the silicon carbide epitaxial layer; a plurality of first conductivity type source regions, the plurality of first conductivity type source regions are arranged at intervals along the first direction and extend along the second direction, and two first conductivity type source regions are symmetrically arranged in the well region; an upper surface of the first conductivity type source region is flush with an upper surface of the silicon carbide epitaxial layer; A plurality of second conductivity type source regions, wherein the second conductivity type source region is disposed between two of the first conductivity type source regions, and is located in the well region and flush with an upper surface of the well region; The ohmic contact layer contacts the second conductive type source region and a portion of the first conductive type source region.

4. The MOSFET device according to claim 3, characterized in that: The active region further includes: an extension layer; The extension layer is arranged on a side of the second conductive type source region close to the silicon carbide substrate, and the extension layer is located inside the silicon carbide epitaxial layer.

5. The MOSFET device according to claim 3, characterized in that: The active area further includes: a gate dielectric structure; The gate dielectric structure is arranged on a side of the gate structure close to the well region.

6. The MOSFET device according to claim 2, characterized in that: The terminal area also includes: A field line ring is arranged inside a side of the silicon carbide epitaxial layer away from the silicon carbide substrate, and an upper surface of the field line ring is flush with an upper surface of the silicon carbide epitaxial layer; A first insulating layer, disposed between the field line ring and the gate line layer; An interlayer dielectric layer is disposed on both sides of the gate line layer away from the first insulating layer and on the top thereof, the interlayer dielectric layer having a second through hole, and the second through hole exposes a portion of the gate line layer; A second insulating layer, disposed on an outer surface of the interlayer dielectric layer, the second insulating layer comprising a third through hole, the third through hole being connected to the second through hole; The gate metal layer is disposed on a side of the second insulating layer away from the silicon carbide substrate, and passes through the second through hole and the third through hole to be electrically connected to the gate line layer.

7. The MOSFET device according to claim 5, characterized in that: The active area further includes: a source metal layer; the source metal layer is arranged on top of the interlayer dielectric layer and the ohmic contact layer; The power device further comprises: A third insulating layer, disposed outside the source metal layer and the gate metal layer; The fourth insulating layer is arranged on the outer surface of the third insulating layer. A drain metal layer is disposed on a side of the silicon carbide substrate away from the silicon carbide epitaxial layer.

8. A method for manufacturing a MOSFET device according to any one of claims 1 to 7, characterized in that: include: S1: Fabricating a silicon carbide epitaxial layer on one side of a silicon carbide substrate; S2: Manufacturing a plurality of gate structures located in an active area on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate, such that the plurality of gate structures are arranged at intervals along a first direction and extend along a second direction, and manufacturing a gate line layer located in a terminal area, such that the gate line layer is electrically connected to each of the gate structures.

9. The method according to claim 8, characterized in that After step S2, the method further comprises: Manufacturing an interlayer dielectric layer on the outer surface of the gate structure; An ohmic contact layer is manufactured at a portion between the interlayer dielectric layers, so that an upper surface of the ohmic contact layer is closer to the silicon carbide substrate than an upper surface of the interlayer dielectric layer.

10. The method according to claim 8, characterized in that After step S1 and before step S2, the method further includes: Manufacturing a plurality of well regions inside the silicon carbide epitaxial layer located in the active area on a side away from the silicon carbide substrate, so that the plurality of well regions are spaced apart along the first direction and extend along the second direction, and the upper surface of the well region is flush with the upper surface of the silicon carbide epitaxial layer; Manufacturing a symmetrically arranged first conductivity type source region inside the well region so that the upper surface of the first conductivity type source region is flush with the upper surface of the well region; A second conductive type source region is manufactured between two of the first conductive type source regions. The second conductive type source region is disposed between the two of the first conductive type source regions and is located in the well region and flush with the upper surface of the well region.

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