HEMT device with improved HD-GIT structure
By introducing a P-drain region between the gate and drain of the GaN HEMT device and using a high K stack connection, the problem that traditional GaN HEMT devices are prone to current collapse effect under high electric fields is solved, and the device's withstand voltage performance and overall performance are significantly improved.
Patent Information
- Application Number
- CN202411910704.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-24
- Publication Date
- 2025-04-22
AI Technical Summary
Traditional GaN HEMT devices are prone to current collapse effect in high electric field operating states, affecting device performance, reliability and voltage resistance.
By adding an additional P-doped GaN gate between the gate and drain, and connecting between the two gates through a high K stack layer, the evacuation power line distribution is optimized and the electric field peak is suppressed, thereby improving the voltage withstand performance of the device.
Effectively eliminate surface traps and charge accumulation near the gate, suppress current collapse effect, improve the device's voltage resistance, meet the device's high voltage resistance requirements, and significantly improve device performance.
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Figure CN119866051A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of semiconductor devices, and in particular to a HEMT device with an improved HD-GIT structure. Background Art
[0002] One of the characteristics of gallium nitride (GaN) materials is the presence of two-dimensional electron gas (2DEG) in heterostructures such as AlGaN / GaN, AlN / GaN, and InAlN / GaN, which provides a basis for the manufacture of high electron mobility transistors (HEMTs). Gallium nitride high electron mobility transistor (GaN HEMT) devices are divided into normally-on type and normally-off type. Normally-on type is also called depletion type. The device is turned on when no voltage is applied between the gate and the source. It is cut off and prone to overshoot when negative voltage is applied. For safety reasons, normally-on transistors are rarely used in switching power supply applications. Normally-off type is also called enhancement type. The device is closed when voltage is applied between the gate and the source, and is turned on when positive voltage is applied. Therefore, normally-off transistors are often considered in switching power supply applications, especially in high-frequency fields.
[0003] The cell structure of the traditional GaN HEMT device includes GaN layer and AlGaN layer from bottom to top, with source and drain at both ends of the AlGaN layer, and a gate between the source and drain. During the epitaxial growth of AlGaN material, atoms are arranged in order according to the material's unique lattice structure. When AlGaN and GaN form a heterojunction, lattice mismatch and spontaneous polarization effects will occur at the interface, thereby generating a built-in electric field pointing from AlGaN to the surface of the material. As the thickness of the AlGaN layer increases during the growth process, the built-in electric field strength will gradually increase. When the electric field strength exceeds a certain threshold, the atoms in the AlGaN material are ionized, thereby releasing free electrons. When the free electrons generated by ionization and the free electrons and negatively charged surface states originally existing in the material are "pushed" to the vicinity of the AlGaN / GaN heterojunction interface under the action of the electric field and gathered at the heterojunction interface close to the GaN side, a high-density, high-mobility two-dimensional electron gas (2DEG) is formed. As the concentration of 2DEG increases, it will shield the built-in electric field, causing the polarization electric field strength to gradually weaken, and finally reach a dynamic equilibrium state, that is, a stable relationship is reached between the concentration of 2DEG and the built-in electric field strength. This equilibrium state ensures the stable existence of 2DEG and provides a basis for the high-performance operation of GaN HEMT devices. The working principle of GaN HEMT devices is roughly as follows: the electron concentration (or intensity) in the 2DEG channel changes with the change of the gate voltage; when the applied gate voltage is reverse biased, the electrons under the gate move to both sides to form a depletion layer channel, so that the device has a certain voltage resistance; when the applied gate voltage is less than the threshold voltage, the GaN layer will deplete the free carriers in the 2DEG channel under the gate, and the device is turned off. In the off state, since there are still a small number of electrons that can connect the drain and the source, the device GaN layer will have leakage current flowing through the device; when the applied gate voltage value is higher than the threshold voltage, the free carriers in the depleted 2DEG channel under the gate will increase and form a channel (electrons move in the opposite direction of the electric field), thereby turning on the device. However, conventional GaN HEMT devices are prone to current collapse effect under high electric field working conditions. The possible reason is the accumulation of surface traps and negative charges near the gate under high electric field. This is manifested as a decrease in the output current of the device under high electric field or pulse operation conditions, thus affecting the device performance, reliability and voltage resistance.
[0004] Therefore, how to reduce the current collapse effect and improve the voltage resistance performance of the device is a technical problem to be solved by the present invention. Summary of the invention
[0005] In order to solve the above technical problems, a HEMT device with an improved HD-GIT structure is provided. The structure of the present invention can effectively eliminate surface traps and charge accumulation near the gate, inhibit the current collapse effect, optimize the distribution of evacuated power lines, inhibit the electric field peak, more effectively improve the withstand voltage, meet the high voltage withstand requirements of the device, and effectively improve the device performance.
[0006] In order to achieve the above objectives, the present invention is implemented by the following technical solutions:
[0007] A HEMT device with an improved HD-GIT structure, wherein the cross-sectional structure of the device comprises, from bottom to top, a substrate layer, an unintentionally doped GaN layer and a barrier layer;
[0008] The bandgap width of the barrier layer is wider than the bandgap width of the GaN layer, and a heterojunction is formed between the GaN layer and the barrier layer, and a two-dimensional electron gas channel (2DEG) is formed at the interface between the two;
[0009] A source and a drain are provided on both sides of the barrier layer, a first gate is provided on the barrier layer between the source and the drain, a second gate is provided on the barrier layer between the first gate and the drain, the source is non-contacted with the first gate, the second gate is non-contacted with the drain, and the first gate and the second gate are contacted and connected by a high-K stacking layer;
[0010] An ohmic contact is formed between the source electrode, the drain electrode and the two-dimensional electron gas channel;
[0011] A first metal layer forming a Schottky contact is disposed on the first gate; and a second metal layer forming an ohmic contact is disposed on the second gate.
[0012] Furthermore, the first gate is a P-type doped GaN gate, which is recessed on the barrier layer to form a recessed gate structure, and the P-type ion doping concentration of the first gate is 1×10 19 / cm 3 The recessed setting can make the 2DEG fully depleted or partially depleted when no voltage is applied; the second gate is a P-type doped GaN gate, which is not recessed and is directly set on the surface of the barrier layer. It introduces an additional P-type doped gate (second gate) between the drain region and the first gate region to form a P-drain region so that the 2DEG cannot be completely depleted. When the device is in the off state, holes will be injected into the P-drain region, and these holes will recombine with the 2DEG electrons, which can reduce the trap concentration in the drain region and near the first gate.
[0013] Furthermore, the spacing between the first gate and the second gate is in the range of 0μm-20μm; preferably, the spacing between the first gate and the second gate is in the range of 1μm-18μm; more preferably, the spacing between the first gate and the second gate is 2μm-15μm. Since the source is at a low potential and the drain is at a high potential, although adding a second gate between the first gate and the drain can eliminate trapped electrons near the first gate, it also makes the electric lines near the first gate densely distributed, which has a certain counter-effect. Therefore, a high-K stack is connected between the first gate and the second gate to disperse the densely distributed electric lines, so that the electric field distribution is more uniform. If the spacing between the first gate and the second gate is too small, the effective withstand voltage area will be shortened. Therefore, the width of the high-K stack connected between the first gate and the second gate needs to be within a reasonable range.
[0014] Furthermore, the material of the high-K stack is selected from metal alloys or metal compounds with a relative dielectric constant ε value greater than 20. The higher the ε value, the more obvious the improvement effect on the internal electric field of the semiconductor.
[0015] Preferably, the material of the high-K stack is selected from one or more of group IIIB metal oxides, group IVB metal oxides, group VB metal oxides, group IIIA metal oxides, and group IVA metal oxides, wherein group IIIA metal oxides or group IVA metal oxides are not used alone, for example, a sub-group metal element oxide such as HfO2 can be selected alone as the high-K stack, or a main group metal element oxide such as Al2O3 and a sub-group metal element oxide can be selected as the high-K stack. Due to its high relative dielectric constant, the high-K stack can effectively alleviate the surface trap effect and optimize the electric field distribution in the device.
[0016] Furthermore, the device further comprises a high resistance layer, and the source electrode, the second gate electrode, and the drain electrode are respectively provided with a second metal layer on their upper surfaces to form an ohmic contact with the high resistance layer, thereby obtaining an electrical connection capable of conducting current, wherein the first gate electrode is covered by the high resistance layer but has no contact connection with the high resistance layer; the material of the high resistance layer has a room temperature resistivity of 10 8 Ω·cm-10 14 The thickness and thickness of the high resistance layer can be designed and adjusted by photolithography according to the needs. The material of the high resistance layer can be GeO2 (resistivity of about 10 9 Ω·cm-10 12 Ω·cm), etc. In order to make the resistance controllable, some semiconductor materials can also be used, such as polysilicon doping, to reduce the resistance, thereby achieving controllable resistance. Different electrode voltages and induced charges can be provided in different parts of the device as required, providing effective electric field regulation for high-voltage (650V and above) GaN HEMT devices.
[0017] Furthermore, the device further comprises a passivation layer, and the non-contact connection area formed between the high resistance layer and the source electrode, the first gate electrode, the second gate electrode, and the drain electrode is filled with the passivation layer, and the material of the passivation layer has a room temperature resistivity greater than 10 14 Ω·cm, the optional passivation layer insulating dielectrics include Al2O3, AlN, Si3N4, etc.
[0018] Furthermore, the device further comprises a nucleation layer, wherein the nucleation layer is arranged between the substrate layer and the GaN layer; and the thickness of the nucleation layer is in the range of 10 nm-10 μm.
[0019] Furthermore, the material of the barrier layer is one of unintentionally doped AlGaN, AlN, and InAlN; the thickness of the barrier layer is in the range of 10nm-40nm; and the thickness of the GaN layer is in the range of 0.5μm-5μm.
[0020] Beneficial technical effects: The present invention forms a HD-GIT (Hybrid Drain-Gate Injection Transistor) structure by adding an additional gate between the gate and the drain to form a p-drain, and connects the two gates through a high-K stack layer, and connects the source, p-drain and drain through a high resistance layer to form a HEMT device with an improved HD-GIT structure; the structure of the present invention can effectively eliminate surface traps near the gate and the accumulation of charges, inhibit the current collapse effect, optimize the distribution of evacuated power lines, inhibit the electric field peak, more effectively improve the withstand voltage, meet the high voltage withstand requirements of the device, and effectively improve the device performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 Schematic diagram of the cross-sectional structure of the GaN HEMT device of Comparative Example 1; wherein 1 is a substrate layer, 2 is a nucleation layer, 3 is a GaN layer, 4 is a barrier layer, 5 is a source electrode, 7 is a first gate electrode, 8 is a first metal layer, 11 is a second metal layer, and 12 is a drain electrode;
[0022] Figure 2 Schematic diagram of the cross-sectional structure of the GaN HEMT device of Comparative Example 2; wherein 1-substrate layer, 2-nucleation layer, 3-GaN layer, 4-barrier layer, 5-source electrode, 7-first gate electrode, 8-first metal layer, 10-second gate electrode, 11-second metal layer, 12-drain electrode;
[0023] Figure 3Schematic diagram of the cross-sectional structure of the GaN HEMT device of Comparative Example 3; wherein 1-substrate layer, 2-nucleation layer, 3-GaN layer, 4-barrier layer, 5-source electrode, 7-first gate electrode, 8-first metal layer, 10-second gate electrode, 11-second metal layer, 12-drain electrode, 6-high resistance layer;
[0024] Figure 4 Schematic diagram of the cross-sectional structure of the GaN HEMT device of Comparative Example 4; wherein 1-substrate layer, 2-nucleation layer, 3-GaN layer, 4-barrier layer, 5-source electrode, 7-first gate electrode, 8-first metal layer, 10-second gate electrode, 12-drain electrode, 6-high resistance layer;
[0025] Figures 5 to 8 Schematic diagrams of cross-sectional structures of GaN HEMT devices according to Embodiments 1 to 4 of the present invention respectively; 1-substrate layer, 2-nucleation layer, 3-GaN layer, 4-barrier layer, 5-source electrode, 7-first gate electrode, 8-first metal layer, 9-high-K stack layer, 10-second gate electrode, 11-second metal layer, 12-drain electrode, 6-high resistance layer; wherein the distance between the first gate electrode and the second gate electrode increases in accordance with 0.1, 0.25, 0.5, and 0.75 times the distance of Lg1d, respectively; Figures 5 to 8 It is shown in FIG. 1 that Lg1d is the distance between the first gate electrode side close to the drain electrode edge and the drain electrode side close to the gate electrode edge;
[0026] Fig. 9 1 is a simulation result diagram of the electric field intensity on the lower surface of the barrier layer of the device of Comparative Example 3, Comparative Example 4 and Example 3 as a function of the distance X from the gate;
[0027] Fig.10 It is a diagram showing the simulation results of the distribution of electric lines of force between the first gate electrode with a recessed configuration and the edge of the drain electrode in the devices of comparative example 3, comparative example 4 and embodiment 3. DETAILED DESCRIPTION
[0028] The technical solutions in the embodiments of the present invention will be described clearly and completely below in combination with the embodiments of the present invention and the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present invention and its application or use. All other embodiments obtained by ordinary technicians in this field without creative work based on the embodiments of the present invention are within the scope of protection of the present invention.
[0029] Unless otherwise specifically stated, the numerical value set forth in these embodiments does not limit the scope of the present invention. The technology and method known to those of ordinary skill in the relevant art may not be discussed in detail, but in appropriate cases, the technology and method should be considered as a part of the specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values.
[0030] In addition, it should be noted that the use of terms such as "first" and "second" to describe the gate, metal layer, etc. is only to facilitate the distinction between the various components. Unless otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of the present invention.
[0031] The experimental methods in the following examples without specifying specific conditions are usually measured in accordance with national standards; if there is no corresponding national standard, they are carried out in accordance with general standard requirements or general methods.
[0032] The following case takes AlGaN / GaN heterojunction material as an example. AlN / GaN heterojunction material and InAlN / GaN heterojunction material are also applicable to the structure of the present invention.
[0033] In AlGaN / GaN heterojunction devices, the atomic percentage of the Al component in the AlGaN material is usually in the range of 0%-50%, and the atomic percentage of the Al component is preferably in the range of 10%-40%. Within this preferred range, when the Al component content is low, the heterojunction has a higher breakdown voltage, smaller gate-drain capacitance and gate-source capacitance; when the Al component content is high, the heterojunction has a higher interface charge density, a larger saturated output current, a wider bandgap width and a more controllable threshold voltage; the electron mobility of the device increases with the increase of the Al component. When designing a device, different Al component contents can be selected according to different applications to achieve the best effect. The following embodiments only show one ratio, but other ratios can also be selected as needed in other embodiments.
[0034] The bottom-up structure of the metal layers of the ohmic contact involved below (such as the second metal layer, source, and drain) often adopts a Ti / Al / Ni / Au composite structure, or a Ti / Al / Ti / Au composite structure, or replaces Au in the former two composite structures with TiW, TiN, Ta, etc. to form a gold-free ohmic contact.
[0035] The metal layer (such as the first metal layer) of the Schottky contact involved in the following is usually made of Ni, which has good adhesion and low cost, and can also use precious metals Pt or Au. The metal layer used in the Schottky contact involved in the following case adopts a Ni / Au composite structure from bottom to top to reduce the overall resistance and improve stability.
[0036] The nucleation layer involved in the following description is made of aluminum nitride material, which can improve the growth quality of the GaN layer and reduce defects.
[0037] The material of the substrate layer mentioned below is usually one of sapphire, silicon and silicon carbide.
[0038] Comparative Example 1
[0039] The cross-sectional structure diagram of the GaN HEMT device in this case is as follows Figure 1 As shown, from bottom to top, it includes: a 1 mm thick silicon substrate layer 1, a 25 nm thick nucleation layer 2, a 2 μm thick unintentionally doped GaN layer 3, and a 15 nm thick unintentionally doped barrier layer 4, wherein the barrier layer is made of AlGaN material (the atomic percentage content of Al component is 18%, and the atomic percentage content of Ga component is 82%);
[0040] A heterojunction is formed between the GaN layer 3 and the barrier layer 4, and a two-dimensional electron gas channel (2DEG) is formed at the interface between the two; a source electrode 5 and a drain electrode 12 are provided on both sides of the barrier layer 4, and a first gate electrode 7 is provided on the barrier layer 4 between the source electrode 5 and the drain electrode 12;
[0041] The first gate 7 is a P-type doped GaN gate, which is recessed and arranged on the barrier layer 4 to form a recessed gate structure;
[0042] There is no contact connection between the source electrode 5 and the first gate electrode 7, and the distance between the two is 0.5 μm;
[0043] There is no contact connection between the first gate 7 and the drain 12, and the distance between them is Lg1d=20 μm;
[0044] An ohmic contact is formed between the source electrode 5, the drain electrode 12 and the two-dimensional electron gas channel; a second metal layer 11 forming an ohmic contact is provided on the source electrode 5 and the drain electrode 12;
[0045] A first metal layer 8 is deposited on the upper surface of the first gate 7 to form a Schottky contact;
[0046] The blank space between the source 5, the first gate 7 and the drain 12 is filled with a passivation layer ( Figure 1 not shown).
[0047] When the device in this case is working, the electric field distribution between the first gate and the drain forms a peak at the edge of the first gate depletion region. This is because the electric lines emitted from the drain mainly pass through the AlGaN semiconductor to reach the first gate, causing the device to break down, thereby limiting the device output power.
[0048] The device of this case structure was simulated and tested, and the breakdown voltage results are shown in Table 1.
[0049] Comparative Example 2
[0050] The cross-sectional structure diagram of the GaN HEMT device in this case is as follows Figure 2 As shown, from bottom to top, it includes: a 1 mm thick silicon substrate layer 1, a 25 nm thick nucleation layer 2, a 2 μm thick unintentionally doped GaN layer 3, and a 15 nm thick unintentionally doped barrier layer 4, wherein the barrier layer is made of AlGaN material (the atomic percentage content of Al component is 18%, and the atomic percentage content of Ga component is 82%);
[0051] A heterojunction is formed between the GaN layer 3 and the barrier layer 4, and a two-dimensional electron gas channel (2DEG) is formed at the interface between the two; a source electrode 5 and a drain electrode 12 are provided on both sides of the barrier layer 4, a first gate electrode 7 is provided on the barrier layer 4 between the source electrode 5 and the drain electrode 12, and a second gate electrode 10 is provided on the barrier layer 4 between the first gate electrode 7 and the drain electrode 12;
[0052] The spacing between the source electrode 5 and the first gate electrode 7 is 0.5 μm; the spacing between the first gate electrode 7 and the drain electrode 12 is Lg1d=20 μm; the second gate electrode 10 is arranged at a position 0.5 times the spacing between the first gate electrode 7 and the drain electrode 12, that is, the spacing between the first gate electrode 7 and the second gate electrode 10 is Lg1g2=10 μm;
[0053] The first gate 7 is a P-type doped GaN gate, which is recessed on the barrier layer 4 to form a recessed gate structure; the second gate 10 is a P-type doped GaN gate, which is not recessed but directly disposed on the surface of the barrier layer 4 to form a P-drain hole injection structure;
[0054] An ohmic contact is formed between the source electrode 5, the drain electrode 12 and the two-dimensional electron gas channel;
[0055] The source electrode 5, the second gate electrode 10 and the drain electrode 12 are respectively provided with a second metal layer 11 for forming an ohmic contact, and the second gate electrode 10 and the drain electrode 12 are effectively connected by the second metal layer 11;
[0056] A first metal layer 8 is deposited on the upper surface of the first gate 7 to form a Schottky contact;
[0057] The blanks between the source electrode 5, the first gate electrode 7, the second gate electrode 10 and the drain electrode 12 are filled with a passivation layer ( Figure 2 not shown).
[0058] In this case, when the device is in the off state, holes are effectively injected under the second gate, thereby suppressing the current collapse effect from two aspects: first, the holes injected by the second gate in the off state can compensate for the hole generation in the GaN layer and prevent the area under the first gate from being occupied by too many negative charges, thereby ensuring a uniform distribution of the electric field between the drain and the first gate; second, the holes emitted by the second gate will be recombined with hot electrons captured by traps on the surface of the barrier layer, thereby suppressing the current collapse effect.
[0059] The device of this case structure was simulated and tested, and the breakdown voltage results are shown in Table 1.
[0060] Comparative Example 3
[0061] The cross-sectional structure diagram of the GaN HEMT device in this case is as follows Figure 3 As shown, its structure is the same as that of Example 3 of the present invention, except that the high-K stack layer in Example 3 does not exist. Figure 3 The blank area is provided with a passivation layer (not shown).
[0062] Comparative Example 4
[0063] The cross-sectional structure diagram of the GaN HEMT device in this case is as follows Figure 4 As shown, from bottom to top, it includes: a 1 mm thick silicon substrate layer 1, a 25 nm thick nucleation layer 2, a 2 μm thick unintentionally doped GaN layer 3, and a 15 nm thick unintentionally doped barrier layer 4, wherein the barrier layer is made of AlGaN material (the atomic percentage content of Al component is 18%, and the atomic percentage content of Ga component is 82%);
[0064] A heterojunction is formed between the GaN layer 3 and the barrier layer 4, and a two-dimensional electron gas channel (2DEG) is formed at the interface between the two; a source electrode 5 and a drain electrode 12 are provided on both sides of the barrier layer 4;
[0065] Two gates 7 and 10 are provided on the barrier layer 4 between the source 5 and the drain 12, and one of the first gates 7 near the source 5 region is recessed on the barrier layer 4;
[0066] There is no contact connection between the source electrode 5 and the first gate electrode 7 which is recessed, and the spacing between the source electrode 5 and the first gate electrode 7 is 0.5 μm; the spacing between the first gate electrode 7 and the drain electrode 12 is Lg1d=20 μm, and the second gate electrode 10 is arranged at a position 0.5 times the spacing between the first gate electrode 7 and the drain electrode 12, that is, the spacing between the first gate electrode 7 and the second gate electrode 10 is Lg1g2=10 μm;
[0067] Both the first gate 7 and the second gate 10 are P-type doped GaN gates.
[0068] An ohmic contact is formed between the source electrode 5, the drain electrode 12 and the two-dimensional electron gas channel;
[0069] A first metal layer 8 is deposited on the upper surface of the first gate 7 to form a Schottky contact;
[0070] A high resistance layer 6 is filled between and on the surface of the barrier layer 4, the source electrode 5, the first gate electrode 7, the second gate electrode 10 and the drain electrode 12, and the material of the high resistance layer 6 is GeO2;
[0071] The device of this case structure was simulated and tested, and the breakdown voltage results are shown in Table 1.
[0072] Example 1
[0073] A HEMT device with improved HD-GIT structure, the cross-sectional structure diagram is as follows Figure 5 As shown, from bottom to top, it includes: a 1 mm thick silicon substrate layer 1, a 25 nm thick nucleation layer 2, a 2 μm thick unintentionally doped GaN layer 3, and a 15 nm thick unintentionally doped barrier layer 4, wherein the barrier layer is made of AlGaN material (the atomic percentage content of Al component is 18%, and the atomic percentage content of Ga component is 82%);
[0074] A heterojunction is formed between the GaN layer 3 and the barrier layer 4, and a two-dimensional electron gas channel (2DEG) is formed at the interface between the two; a source electrode 5 and a drain electrode 12 are provided on both sides of the barrier layer 4, a first gate electrode 7 is provided on the barrier layer 4 between the source electrode 5 and the drain electrode 12, and a second gate electrode 10 is provided on the barrier layer 4 between the first gate electrode 7 and the drain electrode 12;
[0075] The first gate 7 is a P-type doped GaN gate, which is recessed on the barrier layer 4 to form a recessed gate structure, and the second gate 10 is a P-type doped GaN gate, which is non-recessed and directly disposed on the surface of the barrier layer 4 to form a P-drain hole injection structure;
[0076] The source electrode 5 and the first gate electrode 7 have a spacing of 0.5 μm; the spacing between the first gate electrode 7 and the drain electrode 12 is Lg1d=20 μm, and the second gate electrode 10 is arranged at a position 0.1 times the spacing between the first gate electrode 7 and the drain electrode 12, that is, the spacing between the first gate electrode 7 and the second gate electrode 10 is Lg1g2=2 μm, and the first gate electrode 7 and the second gate electrode 10 are filled and connected by a high-K stacking layer 9, and the material of the high-K stacking layer is HfO2;
[0077] An ohmic contact is formed between the source electrode 5, the drain electrode 12 and the two-dimensional electron gas channel;
[0078] A first metal layer 8 is deposited on the upper surface of the first gate 7 to form a Schottky contact; a second metal layer 11 is deposited on the upper surface of the second gate 10 to form an ohmic contact;
[0079] A high resistance layer 6 is provided to cover the source 5 and the drain 12, and the source 5, the second gate 10, and the drain 12 are respectively in ohmic contact with the high resistance layer 6 by providing a second metal layer 11 on the upper surface, thereby obtaining an electrical connection capable of conducting current, wherein the first gate 7 is covered by the high resistance layer 6 but has no contact connection with the high resistance layer 6; the area without contact connection formed between the high resistance layer 6 and the source 5, the first gate 7, the second gate 10, and the drain 12 is filled with a passivation layer; the material of the high resistance layer 6 is GeO2.
[0080] The manufacturing process of the above device is as follows: the bottom layer of the device is a silicon substrate layer 1, and a nucleation layer 2 is deposited on the substrate layer. An unintentionally doped GaN layer 3 and an unintentionally doped AlGaN barrier layer 4 are sequentially grown on the nucleation layer by MOCVD to form an AlGaN / GaN heterojunction. The barrier layer 4 is thinned at the position where the first gate 7 needs to be set, and then a p-type GaN cap layer is deposited, and the structure of the first gate 7 and the second gate 10 is etched to achieve the normally-off working characteristics of the device. Active area isolation is achieved by injection isolation. Then, a source 5 and a drain 12 are prepared on the surface of the active area to form an ohmic contact with the two-dimensional conductive channel, a Schottky contact metal 8 is made above the first gate 7, and a high-K material is deposited between the first gate 7 and the second gate 10 to form a high-K stack 9. By depositing a high-resistance material through a photolithography patterning process, an ohmic contact (i.e., a second metal layer 11) is formed between the source 5, the second gate 10, the drain 12 and the high-resistance path. In order to achieve the same order of magnitude of leakage current between the source and drain as in previous power devices, high-resistance materials such as GeO2 (resistivity 1×10 9 Ω·cm). In order to make the resistance controllable, some semiconductor materials can also be used, and polysilicon doping can be used to reduce the resistance, thereby achieving controllable resistance.
[0081] Example 2
[0082] The HEMT device with improved HD-GIT structure in this case has a cross-sectional structure as shown in the figure. Figure 6 As shown, its structural parameters and materials are the same as those of Example 1, except that: a second gate 10 is arranged at a position 0.25 times the spacing between the first gate 7 and the drain 12, that is, the spacing between the first gate 7 and the second gate 10 is Lg1g2 = 5 μm.
[0083] Example 3
[0084] The HEMT device with improved HD-GIT structure in this case has a cross-sectional structure as shown in the figure. Figure 7 As shown, its structural parameters and materials are the same as those of Example 1, except that: a second gate 10 is arranged at a position 0.5 times the spacing between the first gate 7 and the drain 12, that is, the spacing between the first gate 7 and the second gate 10 is Lg1g2 = 10 μm.
[0085] Example 4
[0086] The HEMT device with improved HD-GIT structure in this case has a cross-sectional structure as shown in the figure. Figure 8 As shown, its structural parameters and materials are the same as those of Example 1, except that: a second gate 10 is arranged at a position 0.75 times the spacing between the first gate 7 and the drain 12, that is, the spacing between the first gate 7 and the second gate 10 is Lg1g2 = 15 μm.
[0087] The above devices were simulated by Sentaurus device simulation software, and the corresponding gate and drain breakdown voltage values were obtained. The judgment criterion was the voltage on the drain when the electric field peak of the AlGaN / GaN heterojunction channel at the first gate edge of the recessed setting was 3.6MV / cm. The results are shown in Table 1.
[0088] Table 1 Device simulation withstand voltage results
[0089] Devices Breakdown voltage(V) Comparative Example 1 99.7 Comparative Example 2 98.2 Comparative Example 3 125 Comparative Example 4 166 Example 1 285 Example 2 298 Example 3 276 Example 4 276
[0090] As can be seen from Table 1, the breakdown voltage of Comparative Example 1 is 99.7V. In the structure of Comparative Example 2, the benefit of directly connecting the second gate and the drain is that the injection of holes eliminates the current collapse effect. However, since the position of the second gate p-drain is closer to the first gate, the effective withstand voltage area is shortened, so the withstand voltage of Comparative Example 2 is reduced (98.2V). But at the same time, due to the recombination of the injected holes and the electrons in the traps near the barrier layer, the distribution of the electric lines is changed, the peak electric field is reduced, and the withstand voltage is improved. As a result, the withstand voltage of the device in Comparative Example 2 is not much different from the withstand voltage of 99.7V of the original structure of Comparative Example 1. Comparative Example 3, which has a high electron mobility transistor structure with a high resistance line connecting the source, the second gate and the drain without a high-K stack and the same other parameters, is simulated, and its breakdown voltage is 125V, and the withstand voltage is improved; using the structure of Comparative Example 4, since the high resistance layer covering the barrier layer also has a certain effect of dispersing the electric lines, its withstand voltage is increased to 166V. However, the withstand voltage of the structure of Example 2 of the present invention is up to 298V, which is much higher than the withstand voltage of other structures (for example, it is 200% higher than that of Comparative Example 2, and about 80% higher than that of Comparative Example 4); the withstand voltages of the structures of Examples 1 and 3 of the present invention are 285V and 276V respectively, which shows that the structure of the present invention can significantly improve the withstand voltage. It is worth noting that in the structures of Examples 1 to 4, the withstand voltage of the device first rises and then falls, and then there is almost no change, indicating that there is an optimal second gate position such as Example 2 to maximize its hole injection efficiency, which not only eliminates the current collapse effect, but also effectively realizes the optimization of the power line distribution by the high-K stack, and realizes the maximization of the withstand voltage of the device.
[0091] The electric field distribution simulation is performed on the structures of Comparative Example 3, Comparative Example 4, and Example 3. The simulation results of the electric field strength under the barrier layer of the three devices as the distance X from the gate changes are as follows: Fig. 9 As shown, the electric field peak value corresponding to the structure of comparative example 3 (similar to the structure of the present invention but without the high K stack) is the highest, the electric field peak value corresponding to comparative example 4 (similar to the structure of the present invention but with a high resistance layer fully covering the active area of the device) is second, and the electric field peak value corresponding to the structure of embodiment 3 of the present invention is the lowest. The above results show that the structure of comparative example 4 with a high resistance layer fully covering the active area of the device has a certain improvement effect on the electric field distribution (compared with comparative example 3, the withstand voltage of the device of comparative example 4 is increased by 32.8%), but the improvement effect of the structure of the present invention on the electric field distribution is more obvious, and the withstand voltage value is higher (compared with comparative example 3, the withstand voltage of the device of the present invention is increased by at least 120%).
[0092] The simulation results of the distribution of electric lines between the first gate and the edge of the drain in the structures of Comparative Example 3, Comparative Example 4 and Example 3 are as follows: Fig.10 As shown by Fig.10It can be seen that the electric line densities corresponding to the three structures decrease in sequence, indicating that the structure of the present invention has the most obvious effect on improving the electric field distribution near the gate.
[0093] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.
Claims
1. A HEMT device with an improved HD-GIT structure, characterized in that: The cross-sectional structure of the device comprises, from bottom to top, a substrate layer (1), an unintentionally doped GaN layer (3) and a barrier layer (4); The bandgap width of the barrier layer (4) is wider than the bandgap width of the GaN layer (3), a heterojunction is formed between the GaN layer (3) and the barrier layer (4), and a two-dimensional electron gas channel is formed at the interface between the two; A source electrode (5) and a drain electrode (12) are provided on both sides of the barrier layer (4); a first gate electrode (7) is provided on the barrier layer (4) between the source electrode (5) and the drain electrode (12); a second gate electrode (10) is provided on the barrier layer (4) between the first gate electrode (7) and the drain electrode (12); the source electrode (5) and the first gate electrode (7) are non-contact connected; the second gate electrode (10) and the drain electrode (12) are non-contact connected; the first gate electrode (7) and the second gate electrode (10) are contact-connected by a high-K stack layer (9); An ohmic contact is formed between the source electrode (5), the drain electrode (12) and the two-dimensional electron gas channel; A first metal layer (8) for forming a Schottky contact is provided on the first gate (7); and a second metal layer (11) for forming an ohmic contact is provided on the second gate (10).
2. The HEMT device with improved HD-GIT structure according to claim 1, characterized in that: The first gate (7) is a P-type doped GaN gate, which is recessed and arranged on the barrier layer (4) to form a recessed gate structure; the second gate (10) is a P-type doped GaN gate, which is not recessed and is directly arranged on the surface of the barrier layer (4).
3. The HEMT device with improved HD-GIT structure according to claim 2, characterized in that: The distance between the first gate (7) and the second gate (10) is in the range of 0 μm-20 μm.
4. The HEMT device with improved HD-GIT structure according to claim 3, characterized in that: The distance between the first gate (7) and the second gate (10) is 2 μm-15 μm.
5. The HEMT device with improved HD-GIT structure according to claim 4, characterized in that: The material of the high-K stack (9) is selected from metal alloys or metal compounds with a relative dielectric constant ε value greater than 20.
6. The HEMT device with improved HD-GIT structure according to claim 5, characterized in that: The material of the high-K stack (9) is selected from one or more of group IIIB metal oxides, group IV B metal oxides, group VB metal oxides, group IIIA metal oxides, and group IVA metal oxides, wherein group IIIA metal oxides or IVA metal oxides are not used alone.
7. A HEMT device with an improved HD-GIT structure according to any one of claims 1 to 6, characterized in that: The device further comprises a high resistance layer (6); the source electrode (5), the second gate electrode (10), and the drain electrode (12) are each respectively provided with a second metal layer (11) on their upper surfaces to form an ohmic contact with the high resistance layer (6), thereby obtaining an electrical connection capable of conducting current; wherein the first gate electrode (7) is covered by the high resistance layer (6) but has no contact connection with the high resistance layer (6); the material of the high resistance layer (6) has a room temperature resistivity of 10 8 Ω·cm-10 14 In the range of Ω·cm.
8. The HEMT device with improved HD-GIT structure according to claim 7, characterized in that: The device further comprises a passivation layer, wherein the non-contact connection area formed between the high resistance layer (6) and the source electrode (5), the first gate electrode (7), the second gate electrode (10), and the drain electrode (12) is filled with the passivation layer, and the material of the passivation layer has a room temperature resistivity greater than 10 14 Ω·cm.
9. The HEMT device with improved HD-GIT structure according to claim 8, characterized in that: The device further comprises a nucleation layer (2), wherein the nucleation layer (2) is arranged between the substrate layer (1) and the GaN layer (3); the thickness of the nucleation layer (2) is in the range of 10 nm-10 μm.
10. The HEMT device with improved HD-GIT structure according to claim 9, characterized in that: The material of the barrier layer (4) is one of unintentionally doped AlGaN, AlN, and InAlN; the thickness of the barrier layer (4) is in the range of 10nm-40nm; and the thickness of the GaN layer (3) is in the range of 0.5μm-5μm.