Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device, relates to the technical field of display, and is used for increasing the wiring space of a driving signal line. A display area of the display panel comprises a circuit area and a wiring area, the circuit area comprises a plurality of circuit units arranged in a second direction, and each circuit unit comprises a pixel driving circuit; the display area further comprises a first control signal line, and the first control signal line is electrically connected with at least part of the pixel driving circuit; at least part of the circuit area comprises a driving circuit, at least part of the driving circuit is located between two adjacent circuit units in the second direction, and the driving circuit is electrically connected with the first control signal line; the display panel further comprises a plurality of driving signal lines extending in the second direction, and the driving signal lines are electrically connected with the driving circuit. In the first direction, at least part of the driving signal lines electrically connected to the same driving circuit are located on the first side of the corresponding driving circuit, and at least the other part of the driving signal lines are located on the second side of the corresponding driving circuit.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In order to control the pixel driving circuit in the display panel, a driving circuit that provides a control signal to the pixel driving circuit and a plurality of wirings connected to the driving circuit need to be provided in the display panel. Currently, the driving circuit and wirings occupy a large space in the display panel, which limits the performance improvement of the display panel. Summary of the invention

[0003] Embodiments of the present invention provide a display panel and a display device, which are used to increase the wiring space of a driving signal line.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, including:

[0005] The display area includes a circuit area and a wiring area alternately arranged along a first direction, the circuit area includes a plurality of circuit units arranged along a second direction, the circuit unit includes a pixel driving circuit, and the first direction intersects with the second direction;

[0006] The display area further includes a first control signal line, the first control signal line being electrically connected to at least a portion of the pixel driving circuit;

[0007] At least part of the circuit area includes a driving circuit, the driving circuit is at least partly located between two adjacent circuit units in the second direction, and the driving circuit is electrically connected to the first control signal line;

[0008] The display panel further includes a plurality of drive signal lines extending along the second direction, the drive signal lines being electrically connected to the drive circuit;

[0009] Along the first direction, at least part of the driving signal lines electrically connected to the same driving circuit are located on a first side of the corresponding driving circuit, and at least another part of the driving signal lines are located on a second side of the corresponding driving circuit.

[0010] In a second aspect, an embodiment of the present invention provides a display device, comprising the above-mentioned display panel.

[0011] Adopting the scheme provided by the embodiment of the present invention is equivalent to dispersing a plurality of driving signal lines on both sides of the corresponding driving circuit in the first direction. Compared with the method of centrally arranging a plurality of driving signal lines on the same side of the corresponding driving circuit, the available wiring space for the driving signal lines is increased, and the space on both sides of the driving circuit in the first direction in the display panel can be fully utilized, which is beneficial to improving the space utilization rate at different positions in the display panel.

[0012] Moreover, by adopting this arrangement, the number of driving signal lines located on either side of the driving circuit can be reduced. When the space on either side of the driving circuit is fixed, the line width of a single driving signal line can be increased, which is beneficial to reducing the resistance of the driving signal line and reducing the delay of the signal during transmission. In addition, the number of driving signal lines that can be accommodated can also be increased. For example, more input terminals can be set in the driving circuit according to different needs, and more driving signal lines electrically connected to the input terminals of the driving circuit can be set to increase the design flexibility of the driving circuit, reduce the design restrictions of the driving circuit due to space factors, and avoid the space factors restricting the performance improvement of the driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0014] Figure 1 A schematic top view of a display panel provided by an embodiment of the present invention;

[0015] Figure 2 A schematic diagram of wiring of a driving signal line provided by an embodiment of the present invention;

[0016] Figure 3 A schematic diagram of another wiring arrangement of a driving signal line provided by an embodiment of the present invention;

[0017] Figure 4 A schematic diagram of a driving signal line and a first signal line provided by an embodiment of the present invention;

[0018] Figure 5 A schematic diagram of another driving signal line and a first signal line provided by an embodiment of the present invention;

[0019] Figure 6 A schematic diagram of another driving signal line and a first signal line provided by an embodiment of the present invention;

[0020] Figure 7 A schematic diagram of another driving signal line and a first signal line provided by an embodiment of the present invention;

[0021] Figure 8 A schematic cross-sectional view of a display panel provided by an embodiment of the present invention;

[0022] Fig. 9 A schematic diagram of wiring of another driving signal line and a driving unit provided in an embodiment of the present invention;

[0023] Fig.10 A circuit diagram of a driving unit provided by an embodiment of the present invention;

[0024] Fig.11 A schematic diagram of a connection between a driving circuit and a first input signal line provided by an embodiment of the present invention;

[0025] Fig.12 A schematic diagram of another display panel provided by an embodiment of the present invention;

[0026] Fig.13 A circuit diagram of a pixel driving circuit and a light-emitting element provided by an embodiment of the present invention;

[0027] Fig.14 A working timing diagram of a driving circuit provided by an embodiment of the present invention;

[0028] Fig.15 Another working timing diagram of a driving circuit provided by an embodiment of the present invention;

[0029] Fig.16 A schematic diagram of an electrostatic protection circuit provided by an embodiment of the present invention;

[0030] Fig.17 A circuit schematic diagram of an electrostatic protection circuit provided by an embodiment of the present invention;

[0031] Fig.18 A schematic diagram of another display panel provided by an embodiment of the present invention;

[0032] Fig.19 A schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0034] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0036] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0037] An embodiment of the present invention provides a display panel, such as Figure 1 As shown, Figure 1 A top view schematic diagram of a display panel 100 provided in an embodiment of the present invention, the display panel 100 includes a display area AA, the display area AA includes a circuit area A1 and a routing area A2 alternately arranged along a first direction h11, the circuit area A1 includes a plurality of circuit units 1 arranged along a second direction h12, the circuit unit 1 includes a pixel driving circuit 10, and the first direction h11 intersects with the second direction h12.

[0038] like Figure 1 As shown, the display area AA further includes a first control signal line 21, and the first control signal line 21 is electrically connected to at least part of the pixel driving circuit 10; the first control signal line 21 can control the pixel driving circuit 10 to generate a driving current to drive the light emitting element ( Figure 1 not shown) emits light.

[0039] In the embodiment of the present invention, at least part of the circuit area A1 includes a driving circuit 30, which includes a plurality of cascaded driving units 300; the driving unit 300 is at least partially located between two adjacent circuit units 1 in the second direction h12, and the driving unit 300 is electrically connected to the first control signal line 21.

[0040] The driving circuit 30 is arranged in the circuit area A1, which can realize reasonable utilization of the space of the circuit area A1, so that the driving circuit 30 does not need to occupy the left and right frame space of the display panel 100 in the first direction h11, and can better realize the left and right ultra-narrow frame design or left and right frameless design of the display panel 100.

[0041] Moreover, when the display panel 100 is used in a spliced ​​display device, for two adjacent display panels 100 in the first direction h11, the distance between the display areas AA of the two display panels 100 can be reduced, which is beneficial to weakening the visual seams in the spliced ​​display device in the first direction h11.

[0042] like Figure 1As shown, the display panel 100 further includes a plurality of drive signal lines 4 extending along the second direction h12, the drive signal lines 4 are located in the routing area A2, and the drive signal lines 4 are electrically connected to the drive circuit 30; illustratively, at least part of the drive signal lines 4 are electrically connected to the input end of the drive circuit 30. The drive circuit 30 may include a plurality of input ends, and the plurality of drive signal lines 4 are electrically connected to the plurality of input ends in a one-to-one correspondence.

[0043] When the display panel 100 is working, the driving signal line 4 provides a driving signal to the driving circuit 30. Under the action of the driving signal, the driving circuit 4 generates a first control signal, and the first control signal is provided to the pixel driving circuit 10 through the first control signal line 21 to control the pixel driving circuit 10 to generate a driving current and light up the light-emitting element electrically connected to the pixel driving circuit 10.

[0044] In the embodiment of the present invention, along the first direction h11, at least part of the driving signal lines 4 electrically connected to the same driving circuit 30 are located on a first side of the corresponding driving circuit 30, and at least another part of the driving signal lines 4 are located on a second side of the corresponding driving circuit 30. The driving circuit 30 corresponding to the driving signal line 4 refers to the driving circuit 30 electrically connected to the driving signal line 4.

[0045] Based on this arrangement, it is equivalent to dispersing the plurality of drive signal lines 4 on both sides of the corresponding drive circuit 30 in the first direction h11. Compared with the arrangement in which the plurality of drive signal lines 4 are concentrated on the same side of the corresponding drive circuit 30, the available wiring space for the drive signal lines 4 is increased, and the space on both sides of the drive circuit 30 in the display panel 100 in the first direction h11 can be fully utilized, which is beneficial to improving the space utilization rate at different positions in the display panel 100.

[0046] Moreover, by adopting this arrangement, the number of driving signal lines 4 located on any side of the driving circuit 30 can be reduced. When the space on any side of the driving circuit 30 is fixed, the line width of a single driving signal line 4 can be increased, which is beneficial to reducing the resistance of the driving signal line 4 and reducing the delay of the signal during transmission. In addition, the number of driving signal lines 4 that can be accommodated can also be increased. For example, more input terminals can be set in the driving circuit 30 according to different requirements, and more driving signal lines 4 electrically connected to the input terminals of the driving circuit 30 can be set to increase the design flexibility of the driving circuit 30, reduce the design restrictions of the driving circuit 30 due to space factors, and avoid the space factors restricting the performance improvement of the driving circuit 30.

[0047] It should be noted that Figure 1The position of the driving circuit 30 in the display area AA is only a schematic diagram. The circuit area A1 including the driving circuit 30 is defined as the first circuit area A11, and the circuit area A1 not including the driving circuit 30 is defined as the second circuit area A12. In the embodiment of the present invention, the first circuit area A11 can be set close to the edge of the display area AA, that is, the second circuit area A12 is not set between the first circuit area A11 and the edge of the display area AA.

[0048] Alternatively, in the embodiment of the present invention, the first circuit area A11 may be disposed in the middle area of ​​the display area AA, for example, the second circuit area A12 may be disposed between the first circuit area A11 and the edge of the display area AA.

[0049] When the first circuit area A11 is set in the middle area of ​​the display area AA, an embodiment of the present invention can center the first circuit area A11 relative to the display area AA, that is, the same number or a difference of 1 in the number of second circuit areas A12 are set on the first side and the second side of the first circuit area A11 in the first direction h11.

[0050] Alternatively, the embodiment of the present invention may also make the number of second circuit areas A12 on one of the first side and the second side greater than the number of second circuit areas A12 on the other side. For example, when the display area AA includes K circuit areas A1 in total, and K is an odd number greater than 3, the embodiment of the present invention may make the first side of the first circuit area A11 include (K-1) / 4 second circuit areas A12, and the second side include 3(K-1) / 4 second circuit areas A12.

[0051] For example, Figure 1 As shown, the driving circuit 30 includes a control module 31 and an output module 32, and the control module 31 and the output module 32 are electrically connected.

[0052] In the embodiment of the present invention, the control module 31 and the output module 32 are arranged along the first direction h11 to reduce the width of the driving circuit 30 in the second direction h12.

[0053] Optional, such as Figure 1 As shown, along the first direction h11, the control module 31 is located on a side of the driving circuit 30 close to the first side, and the output module 32 is located on a side of the driving circuit 30 close to the second side.

[0054] In an embodiment of the present invention, the display panel 100 includes q1 drive signal lines 4 located on the first side of the corresponding drive circuit 30, and q2 drive signal lines 4 located on the second side of the corresponding drive circuit 30; wherein q1<q2, and at least one of the drive signal lines 4 located on the first side of the corresponding drive circuit 30 is electrically connected to the control module 31, and at least one of the drive signal lines 4 located on the second side of the corresponding drive circuit 30 is electrically connected to the output module 32. Figure 1 With q1=4, q2=8, the four drive signal lines 4 located on the first side of the corresponding drive circuit 30 are all electrically connected to the control module 31, the seven drive signal lines 4 located on the second side of the corresponding drive circuit 30 are electrically connected to the output module 32, and one drive signal line 4 is electrically connected to the control module 31 as an illustration.

[0055] For example, Figure 1 As shown, the display panel also includes a plurality of connection lines 34 connecting the drive signal lines 4 and the corresponding drive circuits 30, the plurality of connection lines 34 including a first connection line 341 located on the first side of the corresponding drive circuit 30 and a second connection line 342 located on the second side of the drive circuit 30, at least part of the first connection line 341 is connected to the control module 31, and at least part of the second connection line 342 is connected to the output module 32.

[0056] The embodiment of the present invention can shorten the distance between the drive signal line 4 and the control module 31 connected thereto by electrically connecting at least one of the drive signal lines 4 located on the first side of the corresponding drive circuit 30 to the control module 31 in the drive circuit 30 close to the first side, thereby shortening the length of the first connection line 341 connecting the drive signal line 4 and the drive circuit 30, which is beneficial to reducing the resistance of the first connection line 341 and reducing the delay of the signal transmitted by the first connection line 341.

[0057] Furthermore, the embodiment of the present invention can shorten the distance between the drive signal line 4 and the output module 32 to which it is connected by electrically connecting at least one of the drive signal lines 4 located on the second side of the corresponding drive circuit 30 to the output module 32 in the drive circuit 30 close to the second side, thereby shortening the length of the second connection line 342 connecting the drive signal line 4 and the drive circuit 30, which is beneficial to reducing the resistance of the second connection line 342 and reducing the delay of the signal transmitted by the second connection line 342.

[0058] Exemplarily, in an embodiment of the present invention, Figure 2 As shown, Figure 2A wiring diagram of a driving signal line provided in an embodiment of the present invention, wherein the line width of at least one driving signal line 4 located on the first side of the corresponding driving circuit 30 is greater than the line width of at least one driving signal line 4 located on the second side of the corresponding driving circuit 30. The driving signal line 4 has a certain reflectivity, and based on this setting, combined with the above-mentioned setting of q1<q2, the area of ​​the driving signal line 4 set on the first side and the second side of the driving circuit 30 in the display panel can be balanced, which is beneficial to improving the reflection uniformity of the first side and the second side of the driving circuit 30 and improving the display effect of the display panel.

[0059] Exemplarily, the driving signal line 4 located on the first side of the driving circuit 30 includes at least two first driving signal line groups 410, and the first driving signal line group 410 includes at least one driving signal line 4; along the first direction h11, at least one circuit unit 1 is included between two adjacent first driving signal line groups 410; Figure 3 As shown, Figure 3 Another schematic diagram of wiring of driving signal lines provided in an embodiment of the present invention, wherein the driving signal lines 4 located on the first side of the driving circuit 30 include two first driving signal line groups 410 as an example. In the embodiment of the present invention, by further dividing the driving signal lines 4 located on the first side of the driving circuit 30 into at least two first driving signal line groups 410, the driving signal lines 4 located on the first side of the driving circuit 30 can be dispersedly arranged, and the number of driving signal lines 4 between two adjacent circuit units 1 located on the first side of the driving circuit 30 can be reduced, which is conducive to increasing the line width of the driving signal lines 4 located on the first side of the driving circuit 30.

[0060] And / or, the driving signal line 4 located on the second side of the driving circuit 30 includes at least two second driving signal line groups 420, and the second driving signal line group 420 includes at least one driving signal line 4; along the first direction h11, at least one circuit unit 1 is included between two adjacent second driving signal line groups 420. Figure 2 As an example, the driving signal line 4 located at the second side of the driving circuit 30 includes two second driving signal line groups 420. Figure 3 As an example, the driving signal line 4 located on the second side of the driving circuit 30 includes three second driving signal line groups 420. In the embodiment of the present invention, by further dividing the driving signal line 4 located on the second side of the driving circuit 30 into at least two second driving signal line groups 420, the driving signal lines 4 located on the second side of the driving circuit 30 can be dispersedly arranged, and the number of driving signal lines 4 between two adjacent circuit units 1 located on the second side of the driving circuit 30 can be reduced, which is conducive to increasing the line width of the driving signal line 4 located on the second side of the driving circuit 30.

[0061] For example, Figure 2As shown, at least two second driving signal line groups 420 located on the second side of the driving circuit 30 include at least a first subgroup 421 and a second subgroup 422, and the second subgroup 422 is located on the side of the first subgroup 421 away from the corresponding driving circuit 30; wherein the first subgroup 421 includes q21 driving signal lines 4, and the second subgroup 422 includes q22 driving signal lines 4, q21>q22. Figure 2 Based on this configuration, more drive signal lines 4 can be located closer to the drive circuit 30 , so that more second connection lines 342 can have shorter lengths, which is beneficial to reducing the resistance of the second connection lines 342 and reducing the delay of the signals transmitted by the second connection lines 342 .

[0062] For example, Figure 3 As shown, the drive signal line 4 located on the first side of the drive circuit 30 includes two first drive signal line groups 410, and the drive signal line 4 located on the second side of the drive circuit 30 includes three second drive signal line groups 420; and, the two first drive signal line groups 410 each include two drive signal lines 4; the three second drive signal line groups 420 include a third subgroup 423, a fourth subgroup 424 and a fifth subgroup 425, the third subgroup 423 is located on a side of the fourth subgroup 424 close to the corresponding drive circuit 30, and the fifth subgroup 425 is located on a side of the fourth subgroup 424 away from the corresponding drive circuit 30; the third subgroup 423 includes two drive signal lines 4, and the fourth subgroup 424 and the fifth subgroup 425 each include three drive signal lines 4. Based on this arrangement, on the one hand, the drive signal lines 4 located on the first side and the second side of the drive circuit 30 can be arranged more dispersedly, which is beneficial to further reduce the number of drive signal lines 4 between two adjacent circuit units 1 on both sides of the drive circuit 30 and increase the line width of the drive signal lines 4 on both sides of the drive circuit 30; on the other hand, the number of drive signal lines 4 in the first drive signal line group 410, the third subgroup 423, the fourth subgroup 424 and the fifth subgroup 425 can be made consistent, which is beneficial to improve the reflection uniformity of different positions of the display panel.

[0063] For example, Figure 3 As shown, the total bus width of the two driving signal lines 4 in the third subgroup 423 is equal to the total bus width of the two driving signal lines 4 in the first driving signal line group 410; the line width of at least one driving signal line 4 in the fourth subgroup 424 and the fifth subgroup 425 is smaller than the line width of at least one driving signal line 4 in the third subgroup 423. Based on this arrangement, the total bus width of the driving signal lines 4 in the first driving signal line group 410, the third subgroup 423, the fourth subgroup 424 and the fifth subgroup 425 can be made consistent, which is beneficial to improving the reflection uniformity of different positions of the display panel.

[0064] Exemplarily, the bus width of the plurality of driving signal lines 4 in the third subgroup 423 is d1, the bus width of the plurality of driving signal lines 4 in the fourth subgroup 424 is d2, and the bus width of the plurality of driving signal lines 4 in the fifth subgroup 425 is d3, wherein, Based on this configuration, the total bus widths of the driving signal lines 4 in the first driving signal line group 410 , the third subgroup 423 , the fourth subgroup 424 and the fifth subgroup 425 can be made consistent, which is beneficial to improving the reflection uniformity at different positions of the display panel.

[0065] For example, Figure 1 and Figure 4 As shown, Figure 4 A schematic diagram of a driving signal line and a first signal line provided in an embodiment of the present invention, the display panel 100 also includes a first signal line 5 extending along a first direction h11, and the first signal line 5 and the driving signal line 4 transmit different signals; along a direction h2 perpendicular to the plane where the display panel 100 is located, the driving signal line 4 and the first signal line 5 at least partially overlap.

[0066] like Figure 4 As shown, the driving signal line 4 includes at least one through hole K, and the through hole K and the first signal line 5 at least partially overlap in a direction perpendicular to the plane where the display panel 100 is located. The provision of the through hole K can reduce the overlapping area of ​​the driving signal line 4 and the first signal line 5, which is beneficial to reducing the coupling capacitance between the two.

[0067] For example, Figure 2 As shown, the display panel 100 further includes a second control signal line 22, which is electrically connected to at least part of the pixel driving circuit 10, and the second control signal line 22 is not connected to the driving circuit 30. The second control signal line 22 may be a signal line other than the first control signal line 21 for controlling the pixel driving circuit 10.

[0068] In the embodiment of the present invention, combined with Figure 2 and Figure 4 As shown, part of the first signal line 5 includes the first control signal line 21, part of the first signal line 5 includes the second control signal line 22, and part of the first signal line 5 includes the connection line 34. Figure 4 As shown, a portion of the first signal lines 5 includes an electrostatic protection signal line 60 located in the non-display area NA of the display panel.

[0069] Or, if Figure 5 As shown, Figure 5A schematic diagram of another driving signal line and a first signal line provided in an embodiment of the present invention, wherein the driving signal line 4 includes a first driving signal line 41 and a second driving signal line 42, and the line width of the first driving signal line 41 is greater than the line width of the second driving signal line 42;

[0070] The area of ​​the through hole K in the first driving signal line 41 is greater than the area of ​​the through hole K in the second driving signal line 42. Based on this setting, the area of ​​the through hole K can be matched with the line width of the driving signal line 4, and through holes K with different areas can be set for driving signal lines 4 with different line widths, so that the coupling capacitance between the multiple driving signal lines 4 with different line widths and the first signal line 5 can be reduced, which is conducive to reducing the signal delay of the multiple driving signal lines 4 with different line widths and improving the display effect.

[0071] For example, Figure 6 As shown, Figure 6 A schematic diagram of another driving signal line and a first signal line provided in an embodiment of the present invention, wherein at least one through hole K includes a first through hole K1, and along a direction h2 perpendicular to the plane where the display panel 100 is located, the first through hole K1 overlaps with at least two adjacent first signal lines 5. Based on this arrangement, the overlapping capacitance of the driving signal line 4 and the two first signal lines 5 can be reduced at the same time, and the difficulty of arranging the first through hole K1 is reduced.

[0072] For example, Figure 7 As shown, Figure 7 A schematic diagram of another driving signal line and a first signal line provided in an embodiment of the present invention, wherein the first signal line 5 includes a first sub-signal line 51 and a second sub-signal line 52. Optionally, the first sub-signal line 51 and the second sub-signal line 52 may be electrically connected, and the two may be regarded as two parts in the extension direction of the first signal line 5. Along a direction h2 perpendicular to the plane where the display panel 100 is located, the first sub-signal line 51 and the through hole K at least partially overlap, and the second sub-signal line 52 and the through hole K at least partially do not overlap, as shown in FIG. Figure 7 As shown, the line width of the first signal line 51 is greater than or equal to the line width of the second signal line 52. Based on this configuration, the cross-sectional area of ​​the first signal line 51 can be increased, thereby reducing the resistance of the first signal line 51 and thus reducing the resistance of the first signal line 5.

[0073] For example, Figure 8 As shown, Figure 8A cross-sectional schematic diagram of a display panel provided in an embodiment of the present invention, the display panel 100 further includes a substrate 01, and along a direction h2 perpendicular to the plane where the substrate is located, the drive signal line 4 is located on a side of the first signal line 5 away from the substrate 01. Exemplarily, the conductivity of the drive signal line 4 may be greater than the conductivity of the first signal line 5. In the embodiment of the present invention, by starting a through hole in the drive signal line 4 and avoiding opening a through hole on the first signal line 5, the resistance of the first signal line 5 can be avoided from being increased.

[0074] For example, Figure 8 As shown, the display panel 100 also includes a first metal layer M0, a semiconductor layer S, a second metal layer M1, a third metal layer MC, a fourth metal layer M2 and a fifth metal layer M3 which are arranged in sequence along a direction away from the substrate 01. The first signal line 5 can be located in the second metal layer M1, and the drive signal line 4 can be located in the fourth metal layer M2.

[0075] like Figure 8 As shown, the driving circuit further includes a transistor TFT and a capacitor C, the first metal layer M0 includes a bottom gate of the transistor TFT, the second metal layer M1 includes a top gate of the transistor TFT, the semiconductor layer S includes a channel of the transistor TFT, and the third metal layer MC includes the capacitor C.

[0076] For example, Fig. 9 As shown, Fig. 9 Another wiring schematic diagram of a driving signal line and a driving unit provided in an embodiment of the present invention, a plurality of circuit units 1 at least include a first circuit unit 11 and a second circuit unit 12 arranged along a first direction h11, a driving circuit 30 includes a first portion 301 and a second portion 302 arranged along the first direction h11, the first portion 301 corresponds to the first circuit unit 11, and the second portion 302 corresponds to the second circuit unit 12, that is, the first portion 301 and the first circuit unit 11 at least partially overlap in the second direction h12, and the second portion 302 and the second circuit unit 12 at least partially overlap in the second direction h12.

[0077] like Fig. 9 As shown, the plurality of driving signal lines 4 further include a third driving signal line group 430, and the third driving signal line group 430 is located between the first portion 301 and the second portion 302. Based on this arrangement, the width of the driving circuit 30 in the first direction h11 can be increased, and by arranging the third driving signal line group 430, the wiring space of the driving signal line 4 can be increased. When the total number of driving signal lines 4 is constant, the number of driving signal lines in the first driving signal line group 410 or the second driving signal line group 420 can be reduced, which is conducive to further increasing the line width of the driving signal line 4 in the first driving signal line group 410 or the second driving signal line group 420, reducing resistance, and reducing signal delay.

[0078] For example, Figure 1 As shown, the driving circuit 30 includes a control module 31 and an output module 32 arranged along a first direction h11, the control module 31 is located on a side of the driving circuit 30 close to the first side, and the output module 32 is located on a side of the driving circuit 30 close to the second side; the driving signal line 4 includes at least one first input signal line I electrically connected to the output module 32, and at least one first input signal line I is located on the second side of the driving circuit 30. Based on this arrangement, the distance between the first input signal line I and the output module 32 can be reduced, which is conducive to shortening the length of the connection line connecting the two, reducing the resistance of the connection line, and reducing signal delay.

[0079] Optional, such as Fig.10 As shown, Fig.10 A circuit diagram of a driving unit provided in an embodiment of the present invention, wherein the control module 31 includes a first sub-control module 311, a second sub-control module 312 and a third sub-control module 313, wherein the first sub-control module 311 is used to provide a first node signal to the first node N1, and the second sub-control module 312 is used to provide a second node signal to the second node N2; the third sub-control module 313 is used to electrically connect the second level signal terminal VGH and the first output signal terminal OUT1 under the control of the first node signal, and, under the control of the second node signal, electrically connect the first level signal terminal VGL and the first output signal terminal OUT1. The output module 32 is used to electrically connect the second input signal terminal IN12 and the second output signal terminal OUT2 under the control of the first node signal, and, under the control of the output signal of the first output signal terminal OUT1, electrically connect the first input signal terminal IN11 and the second output signal terminal OUT2. When the first output signal terminal OUT1 outputs an enable level, the signal of the first input signal terminal IN11 can be input into the pixel driving circuit 10 of the current row through the second output signal terminal OUT2.

[0080] Optional, such as Fig.10 As shown, the first sub-control module 311 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4_1, a reset transistor T50, a seventh transistor T7, an eighth transistor T8, and a twelfth transistor T12.

[0081] The second sub-control module 312 includes a fourth transistor T4_2 , a fifth transistor T5 , a sixth transistor T6 , a thirteenth transistor T13 , and a regulating transistor T40 .

[0082] The gates of the fourth transistors T4_1 and T4_2 are electrically connected to the first clock signal terminal CK, and the first electrodes are electrically connected to the third input signal terminal IN2. The gates of the second transistors T2 and T3, and the first electrode of the sixth transistor T6 are electrically connected to the second clock signal terminal CKB.

[0083] For the next stage driving unit 300, the gates of the fourth transistors T4_1 and T4_2 are electrically connected to the second clock signal terminal CKB, and the first electrodes are electrically connected to the third input signal terminal IN2. The gates of the second transistors T2 and T3, and the first electrode of the sixth transistor T6 are electrically connected to the first clock signal terminal CK.

[0084] The third sub-control module 313 includes a first output transistor T21 and a second output transistor T22 . The first output transistor T21 is electrically connected to the second level signal terminal VGH, and the second output transistor T22 is electrically connected to the first level signal terminal VGL.

[0085] The output module 32 includes a third output transistor T31 and a fourth output transistor T32 . The third output transistor T31 is electrically connected to the second input signal terminal IN12 , and the fourth output transistor T32 is electrically connected to the first input signal terminal IN11 .

[0086] For example, Figure 1 , Figure 2 , Figure 3 and Fig.11 As shown, Fig.11 A schematic diagram of the connection between a driving circuit and a first input signal line provided in an embodiment of the present invention, wherein the driving signal line 4 includes at least two first input signal lines I.

[0087] like Fig.11 As shown, the driving circuit 30 includes at least two sub-driving circuits 3000, and the sub-driving circuit 3000 includes multiple driving units 300. The multiple driving units 300 in the same sub-driving circuit 3000 are electrically connected to the same first input signal line I, and the driving units 300 in different sub-driving circuits 3000 are electrically connected to different first input signal lines I.

[0088] Fig.11 Taking the driving signal line 4 including six first input signal lines I, the driving circuit 30 includes six sub-driving circuits 3000 as an illustration, for distinction, the six first input signal lines are marked as I1, I2, I3, I4, I5 and I6, and the six sub-driving circuits are marked as 3000_1, 3000_2, 3000_3, 3000_4, 3000_5 and 3000_6, respectively.

[0089] Based on this setting method, compared with setting only one first input signal line, the number of driving units 300 connected to a single first input signal line can be reduced, which can reduce the load of the first input signal line, reduce signal delay time and in-plane non-uniformity, and improve display effect.

[0090] For example, Figure 1 and Fig.11 As shown, in an embodiment of the present invention, multiple first input signal lines I can be set on the second side of the corresponding driving circuit 30 to shorten the distance between each first input signal line I and the output module 32 of the corresponding driving unit 300, thereby shortening the length of the connecting line connecting the first input signal line I and the output module 32, reducing resistance and reducing signal delay.

[0091] Alternatively, in the embodiment of the present invention, part of the first input signal lines I may be arranged on the first side of the corresponding driving circuit 30 .

[0092] Taking the example that the driving signal line 4 includes n first input signal lines I, where n is an integer greater than or equal to 3, the embodiment of the present invention can place p31 first input signal lines I on the first side of the driving circuit 30, and p32 first input signal lines I on the second side of the driving circuit 30, wherein p31<p32. Fig.12 As shown, Fig.12 A schematic diagram of another display panel provided by an embodiment of the present invention, wherein n=6, p31=1, p32=5, and the first input signal line I6 is located at the first side of the corresponding driving circuit 30 as an illustration. When the display panel includes a plurality of first input signal lines I, by arranging some of the first input signal lines I at the first side of the driving circuit 30, compared with the method of arranging all the first input signal lines I at the second side of the driving circuit 30, the distance between some of the first input signal lines I and the driving circuit 30 can be shortened, such as Fig.12 As shown, the embodiment of the present invention can shorten the distance between the first input signal line I6 and the driving circuit 30 by setting the first input signal line I6 on the first side of the driving circuit 30, compared with setting the first input signal line I6 on the side of the first input signal line I5 away from the driving circuit 30, thereby shortening the length of the connecting line 343 between the two, which is beneficial to reducing the resistance of the connecting line 343 and reducing signal delay.

[0093] Exemplarily, the display panel 100 includes m pixel driving circuit rows arranged along the second direction h12, and the pixel driving circuit rows include a plurality of the above-mentioned pixel driving circuits 10 arranged along the first direction h11; in the embodiment of the present invention, m=N×n, and m, n and N are all positive integers. That is, the pixel driving circuit row is an integer multiple of the number of the above-mentioned first input signal lines I. Among them, N can be set according to the display requirements, and the embodiment of the present invention does not limit this.

[0094] For example, Fig.13 As shown, Fig.13 A circuit diagram of a pixel driving circuit and a light-emitting element provided in an embodiment of the present invention, the pixel driving circuit 10 includes a pulse width modulation (PWM) module 101 and a pulse amplitude modulation (PAM) module 102, the pulse width modulation module 101 outputs a pulse width setting signal based on a swept frequency driving signal SWEEP to control the light-emitting duration of the light-emitting element 12; the pulse amplitude light-emitting control module 102 controls the magnitude of the driving current.

[0095] Optional, such as Fig.13 As shown, the pulse amplitude modulation module 102 may include a pulse amplitude light emitting control module, and the pulse amplitude light emitting control module includes a first light emitting control transistor T21 and a second light emitting control transistor T22. The pulse amplitude modulation module 102 also includes a first driving transistor Td1, a pulse amplitude data writing transistor T23, a pulse amplitude compensation transistor T24, a pulse amplitude gate reset transistor T25, a pulse amplitude anode reset transistor T26 and a first storage capacitor Cst11.

[0096] The first electrode of the first light emitting control transistor T21 is electrically connected to the first power supply terminal PAM_VDD, and the second electrode is electrically connected to the first electrode of the first driving transistor Td1.

[0097] A first electrode of the second light emission control transistor T22 is electrically connected to a second electrode of the first driving transistor Td1 , and a second electrode of the second light emission control transistor T22 is electrically connected to a first electrode of the light emitting element 12 .

[0098] The gate of the first light emission control transistor T21 and the gate of the second light emission control transistor T22 receive the pulse amplitude light emission control signal provided by the pulse amplitude light emission control signal terminal PAM_EM.

[0099] A first electrode of the pulse amplitude data writing transistor T23 is electrically connected to the first data signal terminal PAM_DATA, and a second electrode is electrically connected to the first electrode of the first driving transistor Td1 .

[0100] A first electrode of the pulse amplitude compensation transistor T24 is electrically connected to a second electrode of the first driving transistor Td1 , and a second electrode of the pulse amplitude compensation transistor T24 is electrically connected to a gate of the first driving transistor Td1 .

[0101] A first electrode of the pulse amplitude gate reset transistor T25 is electrically connected to the first reset signal line PAM_REF, and a second electrode is electrically connected to the gate of the first driving transistor Td1.

[0102] A first electrode of the pulse amplitude anode reset transistor T26 is electrically connected to the initial signal terminal Vint, and a second electrode is electrically connected to the first electrode of the light emitting element 12 .

[0103] The gate of the pulse amplitude gate reset transistor T25 and the gate of the pulse amplitude anode reset transistor T26 receive the first scanning signal provided by the first scanning signal line PAM_S1, and the gate of the pulse amplitude data writing transistor T23 and the gate of the pulse amplitude compensation transistor T24 receive the second scanning signal provided by the second scanning signal line PAM_S2.

[0104] Continue to refer to Fig.13 The pulse width modulation module 1011 may include a third light emission control transistor T31, a pulse width data writing transistor T32, a second driving transistor Td2, a pulse width compensation transistor T33, a pulse width gate reset transistor T34, a fourth light emission control transistor T35 and a second storage capacitor Cst2.

[0105] The first electrode of the third light emitting control transistor T31 is electrically connected to the second power supply terminal PWM_VDD, and the second electrode is electrically connected to the first electrode of the second driving transistor Td2.

[0106] A first electrode of the fourth light emitting control transistor T35 is electrically connected to a second electrode of the second driving transistor Td2 , and a second electrode of the fourth light emitting control transistor T35 is electrically connected to a gate of the first driving transistor Td1 in the pulse amplitude modulation module 102 .

[0107] A first electrode of the pulse width data writing transistor T32 is electrically connected to the second data signal terminal PWM_DATA, and a second electrode is electrically connected to a first electrode of the second driving transistor Td2 .

[0108] A first electrode of the pulse width compensation transistor T33 is electrically connected to a second electrode of the second driving transistor Td2 , and a second electrode of the pulse width compensation transistor T33 is electrically connected to a gate of the second driving transistor Td2 .

[0109] A first electrode of the pulse width gate reset transistor T34 is electrically connected to the second reset signal line PWM_REF, and a second electrode is electrically connected to the gate of the second driving transistor Td2 .

[0110] A first plate of the second storage capacitor Cst2 is electrically connected to the sweep signal terminal SWEEP, and a second plate of the second storage capacitor Cst2 is electrically connected to the gate of the second driving transistor Td2.

[0111] A gate of the third light emission control transistor T31 and a gate of the fourth light emission control transistor T35 are electrically connected to the pulse width light emission control signal line PWM_EM to receive a pulse width light emission control signal provided by the pulse width light emission control signal line PWM_EM.

[0112] A gate of the pulse width gate reset transistor T34 is electrically connected to the third scan signal line PWM_S1 to receive the third scan signal provided by the third scan signal line PWM_S1.

[0113] Gates of the pulse width data writing transistor T32 and the pulse width compensating transistor T33 are electrically connected to the fourth scanning signal line PWM_S2 to receive the fourth scanning signal provided by the fourth scanning signal line PWM_S2.

[0114] For example, Fig.13 As shown, the pulse amplitude modulation module 102 further includes a first compensation transistor T28, a second compensation transistor T29, a third compensation transistor T30 and a third storage capacitor Cst12. Among them, the first electrode of the first compensation transistor T28 and the first electrode of the second compensation transistor T29 are both electrically connected to the second power supply terminal PWM_VDD, the first electrode of the third compensation transistor T30 is electrically connected to the first power supply terminal PAM_VDD, the second electrode of the first compensation transistor T28, the second electrode of the second compensation transistor T29 and the second electrode of the third compensation transistor T30 are all electrically connected to the first electrode plate of the first storage capacitor Cst11, and the second electrode plate of the first storage capacitor Cst11 is electrically connected to the gate of the first driving transistor Td1. In addition, the gate of the first compensation transistor T28 receives the first scanning signal provided by the first scanning signal line PAM_S1, the gate of the second compensation transistor T29 receives the second scanning signal provided by the second scanning signal line PAM_S2, and the gate of the third compensation transistor T30 is electrically connected to the pulse width light emitting control signal line PWM_EM to receive the pulse width light emitting control signal provided by the pulse width light emitting control signal line PWM_EM.

[0115] A first plate of the third storage capacitor Cst12 is electrically connected to the initial signal terminal Vint, and a second plate is electrically connected to the first plate of the first storage capacitor Cst11.

[0116] Continue to refer to Fig.13 As shown, the pulse width modulation module 101 further includes a sweep control transistor T36. The sweep control transistor T36 is electrically connected to the fourth scan signal line PWM_S2, a first electrode is electrically connected to the sweep ground signal line SWEEP_GND, and a second electrode is electrically connected to the first plate of the second storage capacitor Cst2.

[0117] When the pixel driving circuit 10 is working, a reference voltage (such as the voltage on the second power supply terminal PWM_VDD) is set at the first electrode of the second driving transistor Td2 of the pulse width modulation module 101, and a variable potential is formed at the gate of the second driving transistor Td2 through the data voltage on the second data signal terminal PWM_DATA and the sweep signal on the sweep signal terminal SWEEP. When the voltage difference between the gate and the first electrode of the second driving transistor Td2 is greater than the threshold voltage of the second driving transistor Td2, the second driving transistor Td2 is in a cut-off state, so that the pulse width modulation module 101 does not provide a control signal to the pulse amplitude modulation module 102, and the first driving transistor Td1 in the pulse amplitude modulation module 102 provides a light-emitting driving current to the light-emitting element 12 according to the voltage on the first data signal line PAM_DATA.

[0118] As the voltage of the signal transmitted by the sweep signal terminal SWEEP changes, the potential of the gate of the second driving transistor Td2 changes synchronously, until the voltage difference between the gate and the first electrode of the second driving transistor Td2 is equal to (or less than) the threshold voltage of the second driving transistor Td2, the second driving transistor Td2 is turned on, and the second driving transistor Td2 transmits the voltage on the second power supply terminal PWM_VDD as the cut-off voltage to the pulse amplitude modulation module 102, so that the first driving transistor Td1 in the pulse amplitude modulation module 102 is cut off, thereby stopping the supply of driving current to the light-emitting element 12. It can be seen that the pulse width modulation module 101 can control the duration of the pulse amplitude modulation module 102 outputting the light-emitting driving current, so as to adjust the effective light-emitting duration of the light-emitting element 12 within a frame time, and then adjust the light-emitting brightness of the light-emitting element 12.

[0119] In the embodiment of the present invention, the first control signal includes a sweep frequency driving signal SWEEP. Accordingly, the first input signal line I can transmit a sweep frequency input signal SWEEP_IN. Fig.14 As shown, Fig.14 The working timing diagram of a driving circuit provided by an embodiment of the present invention, wherein the sweep frequency input signal SWEEP_IN includes a ramp signal. The start signal STV_S is provided to the third input terminal IN2 of the first stage driving unit 300 in the driving circuit 30 .

[0120] Alternatively, the first control signal includes a pulse amplitude light emitting control signal PAM_EM, and accordingly, the first input signal line I may also transmit a pulse amplitude light emitting control input signal PAM_EM_IN. Fig.15 As shown, Fig.15Another working timing diagram of a driving circuit provided by an embodiment of the present invention, wherein the pulse amplitude light emitting control input signal PAM_EM_IN comprises a square wave signal. The start signal STV_E is provided to the third input terminal IN2 of the first stage driving unit 300 in the driving circuit 30 .

[0121] Optional, combined Figure 1 , Figure 2 , Figure 3 and Fig.12 As shown, the drive signal line 4 also includes a reset signal line R, a first clock signal line K, a second clock signal line B, a first level signal line L, a second level signal line H, and a second input signal line O electrically connected to the control module 31, wherein the reset signal line R is electrically connected to the reset signal terminal RST of the drive circuit 30, the first clock signal line K is electrically connected to the first clock signal terminal CK of the drive circuit 30, the second clock signal line B is electrically connected to the second clock signal terminal CKB of the drive circuit 30, the first level signal line L is electrically connected to the first level signal terminal VGL of the drive circuit 30, the second level signal line H is electrically connected to the second level signal terminal VGH of the drive circuit 30, and the second input signal line O is electrically connected to the second input signal terminal IN12 of the drive circuit 30.

[0122] In the embodiment of the present invention, at least one of the reset signal line R, the first clock signal line K, the second clock signal line B and the first level signal line L is located at the first side of the corresponding driving circuit 30 . Figure 2 As an example, the reset signal line R, the first clock signal line K, the second clock signal line B, and the first level signal line L are all located on the first side of the corresponding driving circuit 30 .

[0123] Exemplarily, the wiring area A2 also includes a plurality of pixel signal lines required for the operation of the pixel driving circuit 10, such as Figure 1 As shown, the pixel signal line includes at least one first data signal line PAMD, at least one second data signal line PWMD and at least one first power supply voltage line PWMV, wherein the first data signal line PAMD and Fig.13 The first data signal terminal PAM_DATA of the pixel driving circuit 10 is electrically connected to the second data signal line PWMD. Fig.11 The second data signal terminal PWM_DATA of the pixel driving circuit 10 is electrically connected to the first power supply voltage line PWMV. Fig.13 The second power supply terminal PWM_VDD of the pixel driving circuit 10 is shown to be electrically connected.

[0124] Exemplarily, when the circuit unit 1 includes a plurality of pixel driving circuits 10, such as a first pixel driving circuit 101, a second pixel driving circuit 102, and a third pixel driving circuit 103 that respectively provide driving currents to the first color light emitting element, the second color light emitting element, and the third color light emitting element, the routing area A2 includes three first data signal lines PAMD and three second data signal lines PWMD, the three first data signal lines PAMD are respectively electrically connected to the first pixel driving circuit 101, the second pixel driving circuit 102, and the third pixel driving circuit 103, and the three second data signal lines PWMD are respectively electrically connected to the first pixel driving circuit 101, the second pixel driving circuit 102, and the third pixel driving circuit 103. Figure 1 As shown, a plurality of first data signal lines PAMD and a plurality of second data signal lines PWMD may be located at a first side and a second side of a corresponding circuit unit 1 , respectively.

[0125] like Figure 1 As shown, the driving signal line 4 also includes a cascade signal line 401, and the cascade signal line 401 is used to connect two adjacent driving units 300 in the driving circuit 30. Fig.10 As shown, the first output signal terminal OUT1 of the previous stage driving unit can be connected to the third input signal terminal IN2 of the next stage driving unit through the above-mentioned cascade signal line 401.

[0126] like Figure 1 As shown, the wiring area A2 also includes a control connection line 402 electrically connecting the driving circuit 3 and the first control signal line 21 .

[0127] like Figure 1 As shown, at least a portion of the cascade signal line 401 can be located on the first side of the corresponding driving circuit 3, and at least a portion of the control connection line 402 can be located on the second side of the corresponding driving circuit 3, so as to further balance the number of routings on both sides of the driving circuit 3 in the first direction h11, so that the coverage area of ​​the routings on both sides of the driving circuit 3 is as consistent as possible, so as to improve display uniformity.

[0128] For example, Fig.16 As shown, Fig.16 A schematic diagram of an electrostatic protection circuit provided in an embodiment of the present invention, the display panel 100 further includes a non-display area NA, the non-display area NA includes a plurality of first electrostatic protection circuits 61, and the first electrostatic protection circuits 61 are electrically connected to the drive signal lines 4 one by one.

[0129] Combination Fig.17 As shown, Fig.17A circuit schematic diagram of an electrostatic protection circuit provided in an embodiment of the present invention, the electrostatic protection circuit includes a first electrostatic protection transistor ME1 and a second electrostatic protection transistor ME2, wherein the gate and the first electrode of the first electrostatic protection transistor ME1 are electrically connected to the first constant level signal line PAM_VGH, and the second electrode is electrically connected to the signal terminal SIG to be protected, and illustratively, the signal terminal SIG to be protected is electrically connected to any one of the above-mentioned multiple driving signal lines 4. The gate and the first electrode of the second electrostatic protection transistor ME2 are electrically connected to the second constant level signal line PAM_VGL, and the second electrode is electrically connected to the signal terminal SIG to be protected.

[0130] When static electricity is generated in the driving signal line 4, the electrostatic protection circuit will be automatically turned on by the control of the electrostatic signal, and the static electricity can be conducted away through the first constant level signal line PAM_VGH or the second constant level signal line PAM_VGL through the turned-on electrostatic protection circuit. Specifically, when the electrostatic voltage in the driving signal line 4 is high voltage static electricity, the first electrostatic protection transistor ME1 is turned on, and the high voltage static electricity signal is released to the first constant level signal line PAM_VGH through the first electrostatic protection transistor ME1; when the electrostatic voltage in the driving signal line 4 is low voltage static electricity, the second electrostatic protection transistor ME2 is turned on, and the low voltage static electricity signal is released to the second constant level signal line PAM_VGL through the second electrostatic protection transistor ME2, thereby realizing static electricity release.

[0131] In the embodiment of the present invention, Fig.16 As shown, the plurality of first electrostatic protection circuits 61 are arranged along the first direction h11 to reduce the occupied space of the plurality of first electrostatic protection circuits 61 in the second direction h12.

[0132] Exemplarily, the non-display area NA further includes a plurality of pads (not shown), and the plurality of pads are electrically connected to the driving signal lines 4 in a one-to-one correspondence.

[0133] like Fig.16 As shown, the display panel also includes a first data signal line PAMD and a second data signal line PWMD, wherein the number of first electrostatic protection circuits 61 between the first data signal line PAMD and the second data signal line PWMD is only for illustration, and the embodiment of the present invention can adjust the number of first electrostatic protection circuits 61 according to the space between the first data signal line PAMD and the second data signal line PWMD, and the embodiment of the present invention is not limited to this.

[0134] like Fig.16As shown, the display panel further includes at least a second electrostatic protection circuit 62, and the second electrostatic protection circuit 62 is electrically connected to the output end of the last-stage driving unit 300. In the second electrostatic protection circuit 62, the second electrode of the first electrostatic protection transistor, the gate electrode and the first electrode of the second electrostatic protection transistor are all electrically connected to the output end of the last-stage driving unit 300.

[0135] The second electrostatic protection circuit 62 is used to protect the last-stage driving unit 300 from being damaged by electrostatic discharge.

[0136] like Fig.16 As shown, the first electrostatic protection circuit 61 and the second electrostatic protection circuit 62 are arranged along the first direction h11 to reduce the occupied space of the first electrostatic protection circuit 61 and the second electrostatic protection circuit 62 in the second direction h12.

[0137] For example, Fig.18 As shown, Fig.18 A schematic diagram of another display panel provided by an embodiment of the present invention, wherein the plurality of drive signal lines 4 include at least a third drive signal line 43, the third drive signal line 43 includes at least two third sub-drive signal lines 431 that transmit the same signal and are located in different routing areas A2, and two adjacent third sub-drive signal lines 431 are electrically connected through a fourth sub-drive signal line 432. The third sub-drive signal line 431 extends along the second direction h12, and the fourth sub-drive signal line 432 extends along the first direction h11. Based on this arrangement, the resistance of the third drive signal line 43 can be reduced, and the uniformity of the signal surface can be increased.

[0138] Optionally, the third driving signal line 43 includes any one of the reset signal line R, the first clock signal line K, the second clock signal line B, the first level signal line L, the second level signal line H, the second input signal line O, and the first input signal line I mentioned above.

[0139] Based on the same inventive concept, an embodiment of the present invention further provides a display device, such as Fig.19 As shown, Fig.19 A schematic diagram of a display device provided in an embodiment of the present invention, the display device includes the above-mentioned display panel 100.

[0140] For example, Fig.19 As shown, the display device includes a spliced ​​display device. The spliced ​​display device includes at least two display panels 100 described above, so as to be applicable to a large-screen display device with a display function, such as a frameless spliced ​​display device.

[0141] For example, this type of spliced ​​display device can be used in public information display (PID) scenarios such as stations and airports. When the spliced ​​display device includes the above display panel 100, a seamless / borderless splicing effect of the spliced ​​display device can be achieved.

[0142] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0143] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: comprising a display area, the display area comprising a circuit area and a wiring area alternately arranged along a first direction, the circuit area comprising a plurality of circuit units arranged along a second direction, the circuit unit comprising a pixel driving circuit, the first direction intersecting the second direction; The display area further includes a first control signal line, wherein the first control signal line is electrically connected to at least a portion of the pixel driving circuit; At least part of the circuit area includes a driving circuit, the driving circuit includes a plurality of driving units, the driving unit is at least partially located between two adjacent circuit units in the second direction, and the driving circuit is electrically connected to the first control signal line; The display panel further comprises a plurality of driving signal lines extending along the second direction, wherein the driving signal lines are electrically connected to the driving circuit; Along the first direction, at least part of the driving signal lines electrically connected to the same driving circuit is located on a first side of the corresponding driving circuit, and at least another part of the driving signal lines is located on a second side of the corresponding driving circuit.

2. The display panel according to claim 1, characterized in that: The driving circuit comprises a control module and an output module arranged along the first direction, the control module is located on a side of the driving circuit close to the first side, and the output module is located on a side of the driving circuit close to the second side; The display panel includes q1 driving signal lines located on a first side of the corresponding driving circuit, and q2 driving signal lines located on a second side of the corresponding driving circuit; wherein q1<q2, and At least one of the driving signal lines located on the first side of the corresponding driving circuit is electrically connected to the control module, and at least one of the driving signal lines located on the second side of the corresponding driving circuit is electrically connected to the output module.

3. The display panel according to claim 1, characterized in that: The line width of at least one of the driving signal lines located on the first side of the corresponding driving circuit is greater than the line width of at least one of the driving signal lines located on the second side of the corresponding driving circuit.

4. The display panel according to claim 1, characterized in that: The driving signal lines located at the first side of the driving circuit include at least two first driving signal line groups, each of which includes at least one driving signal line; along the first direction, at least one circuit unit is included between two adjacent first driving signal line groups; and / or, The driving signal lines located on the second side of the driving circuit include at least two second driving signal line groups, each of which includes at least one driving signal line; along the first direction, at least one circuit unit is included between two adjacent second driving signal line groups.

5. The display panel according to claim 4, characterized in that: The at least two second drive signal line groups located on the second side of the drive circuit include at least a first subgroup and a second subgroup, and the second subgroup is located on a side of the first subgroup away from the drive circuit; wherein, The first subgroup includes q21 driving signal lines, and the second subgroup includes q22 driving signal lines, wherein q21>q22.

6. The display panel according to claim 4, characterized in that: The driving signal lines located on the first side of the driving circuit include two first driving signal line groups, and the driving signal lines located on the second side of the driving circuit include three second driving signal line groups; Furthermore, each of the two first driving signal line groups includes two driving signal lines; The three second drive signal line groups include a third subgroup, a fourth subgroup and a fifth subgroup, the third subgroup is located on a side of the fourth subgroup close to the drive circuit, and the fifth subgroup is located on a side of the fourth subgroup away from the drive circuit; the third subgroup includes two drive signal lines, and the fourth subgroup and the fifth subgroup each include three drive signal lines.

7. The display panel according to claim 6, characterized in that: The total width of the two driving signal lines in the third subgroup is equal to the total width of the two driving signal lines in the first driving signal line group; A line width of at least one of the driving signal lines in the fourth subgroup and the fifth subgroup is smaller than a line width of at least one of the driving signal lines in the third subgroup.

8. The display panel according to claim 7, characterized in that: The total width of the plurality of driving signal lines in the third subgroup is d1, The total width of the plurality of driving signal lines in the fourth subgroup is d2, The total width of the plurality of driving signal lines in the fifth subgroup is d3, in, 9. The display panel according to claim 1, characterized in that: It also includes a first signal line extending along the first direction, wherein the first signal line and the driving signal line transmit different signals; The driving signal line comprises at least one through hole, and along a direction perpendicular to the plane where the display panel is located, the through hole and the first signal line at least partially overlap; The driving signal line comprises a first driving signal line and a second driving signal line, wherein the line width of the first driving signal line is greater than the line width of the second driving signal line; An area of ​​the through hole in the first driving signal line is greater than an area of ​​the through hole in the second driving signal line.

10. The display panel according to claim 9, characterized in that: At least one of the through holes includes a first through hole, and along a direction perpendicular to a plane where the display panel is located, the first through hole overlaps with at least two adjacent first signal lines.

11. The display panel according to claim 9, characterized in that: The first signal line includes a first sub-signal line and a second sub-signal line. Along a direction perpendicular to the plane where the display panel is located, the first sub-signal line and the through hole at least partially overlap, and the second sub-signal line and the through hole at least partially do not overlap, and the line width of the first sub-signal line is greater than or equal to the line width of the second sub-signal line.

12. The display panel according to claim 9, characterized in that: It also includes a substrate, and along a direction perpendicular to a plane where the substrate is located, the driving signal line is located on a side of the first signal line away from the substrate.

13. The display panel according to claim 1, characterized in that: The plurality of circuit units at least include a first circuit unit and a second circuit unit arranged along the first direction, The driving circuit includes a first part and a second part arranged along the first direction, The first part corresponds to the first circuit unit, the second part corresponds to the second circuit unit, The plurality of driving signal lines further include a third driving signal line group, and the third driving signal line group is located between the first portion and the second portion.

14. The display panel according to claim 1, characterized in that: The driving circuit comprises a control module and an output module arranged along the first direction, the control module is located on a side of the driving circuit close to the first side, and the output module is located on a side of the driving circuit close to the second side; The driving signal line includes at least one first input signal line electrically connected to the output module, and the at least one first input signal line is located at the second side of the driving circuit.

15. The display panel according to claim 14, characterized in that: The driving signal lines include at least two of the first input signal lines, The driving circuit includes at least two sub-driving circuits, each of which includes a plurality of driving units. The plurality of driving units in the same sub-driving circuit are electrically connected to the same first input signal line, and the driving units in different sub-driving circuits are electrically connected to different first input signal lines.

16. The display panel according to claim 15, characterized in that: The driving signal lines include n first input signal lines, where n is an integer greater than or equal to 3, wherein: p31 of the first input signal lines are located at a first side of the driving circuit, and p32 of the first input signal lines are located at a second side of the driving circuit, wherein p31<p32.

17. The display panel according to claim 15, characterized in that: The display panel comprises m pixel driving circuit rows arranged along the second direction, and the pixel driving circuit row comprises a plurality of the pixel driving circuits arranged along the first direction; Wherein, m=N×n, m, n and N are all positive integers.

18. The display panel according to claim 14, characterized in that: The pixel driving circuit includes a pulse width modulation module, which outputs a pulse width setting signal based on the sweep frequency driving signal to control the light emitting duration of the light emitting element; The first input signal line transmits a frequency sweep input signal, the first control signal includes the frequency sweep drive signal, and the frequency sweep input signal includes a ramp signal; or, The pixel driving circuit includes a pulse amplitude light-emitting control module, the driving circuit provides a pulse amplitude light-emitting control signal to the pulse amplitude light-emitting control module, the first input signal line transmits the pulse amplitude light-emitting control input signal, the first control signal includes the pulse amplitude light-emitting control signal, and the pulse amplitude light-emitting control input signal includes a square wave signal.

19. The display panel according to claim 14, characterized in that: The driving signal line also includes a reset signal line, a first clock signal line and a second clock signal line electrically connected to the control module; At least one of the reset signal line, the first clock signal line, and the second clock signal line is located on a first side of the drive circuit.

20. The display panel according to claim 1, characterized in that: It also includes a plurality of first electrostatic protection circuits, wherein the first electrostatic protection circuits are electrically connected to the driving signal lines in a one-to-one correspondence; A plurality of the first electrostatic protection circuits are arranged along the first direction.

21. The display panel according to claim 20, characterized in that: The driving circuit comprises a plurality of cascaded driving units; The electrostatic protection circuit further includes at least a second electrostatic protection circuit, in which the second electrode of the first electrostatic protection transistor, the gate electrode and the first electrode of the second electrostatic protection transistor are all electrically connected to the output end of the last-stage driving unit; The first electrostatic protection circuit and the second electrostatic protection circuit are arranged along the first direction.

22. The display panel according to claim 1, characterized in that: The driving signal line includes a third driving signal line, the third driving signal line includes at least two third sub-driving signal lines that transmit the same signal and are located in different routing areas, and two adjacent third sub-driving signal lines are electrically connected through a fourth sub-driving signal line; The third sub-driving signal line extends along the second direction, and the fourth sub-driving signal line extends along the first direction.

23. A display device, characterized in that: A display panel comprising any one of claims 1-22.

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