IBC battery and preparation method thereof

Abstract

The embodiment of the invention provides an IBC battery and a preparation method thereof, in the embodiment of the invention, laser oxidation is performed on a P region after boron doping, a more compact borosilicate glass layer mask with stronger barrier performance can be formed, so that the prepared p-type doped region has the advantages of high surface concentration, high passivation performance and low contact resistance, and the reliability of the IBC battery is improved. And the pollution problem caused by blocking or etching slurry printing is also avoided, the manufacturing precision and the productivity are higher, and the method is suitable for mass production.

Description

Technical Field

[0001] The present invention relates to the technical field of crystalline silicon solar cell manufacturing, and in particular to an IBC cell and a preparation method thereof. Background Art

[0002] The interdigitated back contact (IBC) battery is a new type of battery in which the contact electrodes of the P / N junction, substrate and emitter region are made in an interdigitated shape on the back of the battery. Its core technology is to prepare high-quality p-regions and n-regions arranged in an interdigitated shape on the back of the battery.

[0003] In the prior art, the preparation of passivated contact IBC cells involves post-boron oxide diffusion + laser etching or barrier slurry printing + etching steps. The boron-doped polysilicon layer (poly-Si (p+) region) is affected by the post-boron oxide diffusion process, and its surface doping concentration is low, which is not conducive to metal contact and has poor passivation performance. There are also slurry contamination problems and alignment offset problems. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide an IBC battery and a preparation method thereof, so as to solve the problem that the existing IBC battery is affected by the post-oxidation boron diffusion process, resulting in a low boron doping concentration in the p-type doping area.

[0005] In order to solve the above problems, the present invention is achieved through the following technical solutions:

[0006] The present invention provides a method for preparing an IBC battery, which comprises:

[0007] forming a first silicon oxide layer and a first polysilicon layer in sequence on the back side of the single crystal silicon wafer, and doping the first polysilicon layer with boron;

[0008] Performing chain pickling on the boron-doped silicon wafer;

[0009] Performing laser oxidation treatment on the first area on the back of the silicon wafer after chain pickling to form an oxide layer; the first area is used to form a p-type doped area;

[0010] Performing double-sided alkaline etching on the silicon wafer after laser oxidation treatment;

[0011] forming a second silicon oxide layer and a second polysilicon layer in sequence on the back side of the silicon wafer subjected to double-sided alkali etching, and doping the second polysilicon layer with phosphorus;

[0012] Removing the phosphorus-silicate glass layer outside the second region on the back side of the silicon wafer after phosphorus doping, wherein the second region and the first region are arranged in an interdigitated manner;

[0013] After removing the phosphosilicate glass layer outside the second region, removing the phosphosilicate glass layer on the front side of the silicon wafer by pickling, and etching and texturing the silicon wafer to expose the n-type doped region and the p-type doped region arranged in an interdigitated manner;

[0014] After etching and texturing, a passivation film layer and an anti-reflection film layer are formed on both sides of the silicon wafer, and a positive gate line connected to the p-type doped area and a negative gate line connected to the n-type doped area are formed on the back to produce an IBC battery.

[0015] Furthermore, in the preparation method, the single crystal silicon wafer is an N-type silicon wafer or a P-type silicon wafer.

[0016] Furthermore, in the preparation method, boron doping is performed on the first polysilicon layer, comprising:

[0017] First, BCl3 and O2 with a flow ratio of 1:2 to 1:5 are introduced at a temperature of 800 to 900°C for low-temperature deposition, and then high-temperature advancement is carried out at a temperature of 900 to 950°C, and after the high-temperature advancement is completed, the boat is cooled down without oxygen.

[0018] Furthermore, in the preparation method, the boron doping concentration of the silicon surface after high temperature advancement is 1E20-4E20cm -3 ; and / or

[0019] The phosphorus doping concentration on the silicon surface after phosphorus diffusion is 3E20~7E20cm -3 .

[0020] Furthermore, in the preparation method, in the laser oxidation treatment of the first area on the back side of the silicon wafer after chain pickling, the laser power is 15W to 55W and the marking speed is 3000 to 50000 mm / second; and / or

[0021] The phosphorus-silicate glass layer outside the second area on the back side of the silicon wafer after the phosphorus doping is removed comprises:

[0022] The phosphorus-silicate glass layer outside the second area on the back side of the silicon wafer after phosphorus doping is removed by laser, wherein the laser power is 15W-55W and the marking speed is 3000-50000mm / sec.

[0023] Furthermore, in the preparation method, the thickness of the oxide layer formed by laser oxidation treatment is 10 to 100 nm.

[0024] Furthermore, in the preparation method, etching and texturing the silicon wafer include:

[0025] The silicon wafer is alkaline etched using 1% to 5% by mass of NaOH and etching additives, and then the silicon wafer is groove-textured using 0.5% to 3% by mass of NaOH and texturizing additives, and then cleaned using 5% to 30% by mass of hydrofluoric acid and O3 to remove the borosilicate glass layer and the phosphosilicate glass layer on the back of the silicon wafer.

[0026] Furthermore, in the preparation method, before sequentially forming the first silicon oxide layer and the first polysilicon layer on the back side of the single crystal silicon wafer, the method further comprises:

[0027] The silicon wafer is subjected to alkali polishing treatment.

[0028] Furthermore, in the preparation method, the phosphosilicate glass layer on the front side of the silicon wafer is removed by pickling, comprising:

[0029] The front side of the silicon wafer is cleaned by using hydrofluoric acid with a mass percentage of 5 to 30%.

[0030] The present invention also provides an IBC battery, which is prepared by the above method.

[0031] Compared with the prior art, the embodiments of the present invention have the following advantages:

[0032] In an embodiment of the present invention, after forming a first polysilicon layer and performing boron doping and chain pickling, a first area on the back side of the silicon wafer for forming a p-type doped area is subjected to laser oxidation treatment, and then the silicon wafer after the laser oxidation treatment is subjected to double-sided alkaline etching treatment, and a second silicon oxide layer and a second polysilicon layer are sequentially formed on the back side of the silicon wafer and phosphorus doped, and then the phosphosilicate glass layer other than the second area on the back side of the silicon wafer after phosphorus doping is laser removed, and the first area and the second area are arranged in a finger-like manner, and then the phosphosilicate glass layer on the front side of the silicon wafer is removed by pickling, and the silicon wafer is etched and textured to expose the n-type doped area and the p-type doped area arranged in a finger-like manner, and finally a passivation film layer, an anti-reflection film layer and positive and negative gate lines are formed. In the above process, laser oxidation of the P region after boron doping can form a denser borosilicate glass layer mask with stronger blocking performance. Not only does it make the prepared p-type doped region have the advantages of high surface concentration, high passivation performance, and low contact resistance, it also avoids the pollution problems caused by blocking or etching slurry printing, and has higher production accuracy and production capacity, making it suitable for mass production.

[0033] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a flow chart of a method for preparing an IBC battery provided in an embodiment of the present invention;

[0035] Figure 2 is a schematic structural diagram of an IBC in an embodiment of the present invention when the single crystal silicon wafer is an N-type silicon wafer;

[0036] Figure 3 1 is a schematic diagram of the structure of the IBC in an embodiment of the present invention when the single crystal silicon wafer is a P-type silicon wafer. DETAILED DESCRIPTION

[0037] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] The applicant of the present invention has found that the preparation of current IBC batteries generally requires post-boron oxide diffusion + laser etching or barrier slurry printing + etching steps. The boron-doped polysilicon layer (poly-Si (p+) region) is affected by the post-boron oxide diffusion process, and the surface doping concentration is low, which is not conducive to metal contact and has poor passivation performance. There are also slurry contamination problems and alignment offset problems.

[0039] In order to solve the above problems, the embodiment of the present invention provides a method for preparing an IBC battery, which includes steps 101 to 105:

[0040] Step 101, forming a first silicon oxide layer and a first polysilicon layer in sequence on the back side of a single crystal silicon wafer, and doping the first polysilicon layer with boron;

[0041] Step 102, chain pickling the boron-doped silicon wafer;

[0042] Step 103, performing laser oxidation treatment on the first area on the back side of the silicon wafer after chain pickling to form an oxide layer; the first area is used to form a p-type doped area;

[0043] Step 104, performing double-sided alkaline etching on the silicon wafer after the laser oxidation treatment;

[0044] Step 105, forming a second silicon oxide layer and a second polysilicon layer in sequence on the back side of the silicon wafer subjected to double-sided alkali etching, and doping the second polysilicon layer with phosphorus;

[0045] Step 106, laser removal of the phosphorus-silicate glass layer outside the second region on the back side of the silicon wafer after phosphorus doping, wherein the second region is arranged in an interdigitated manner with the first region;

[0046] Step 107, after removing the phosphosilicate glass layer in the second region, removing the phosphosilicate glass layer on the front side of the silicon wafer by pickling, and etching and texturing the silicon wafer to expose the n-type doped region and the p-type doped region arranged in an interdigitated manner;

[0047] Step 108, after etching and texturing, a passivation film layer and an anti-reflection film layer are formed on both sides of the silicon wafer, and a positive gate line connected to the p-type doped area and a negative gate line connected to the n-type doped area are formed on the back side to obtain an IBC battery.

[0048] In the embodiment of the present invention, laser oxidation is performed on the P region after boron doping to form a denser borosilicate glass layer mask with stronger blocking performance. Not only does the prepared p-type doped region have the advantages of high surface concentration, high passivation performance, and low contact resistance, it also avoids the pollution problems caused by blocking or etching slurry printing, and has higher production accuracy and production capacity, making it suitable for mass production.

[0049] In the above step 101, an N-type single crystal silicon wafer or a P-type single crystal silicon wafer is taken, and low pressure chemical vapor deposition (LPCVD) is used to first pass oxygen with a flow rate of 10 to 30 sccm to form an ultra-thin silicon oxide layer on the back of the silicon wafer, that is, the above-mentioned first silicon oxide layer, as an ultra-thin tunneling oxide layer. The thickness of the first silicon oxide layer can be specifically 1 to 2 nm, for example, 1.5 nm; then, a segmented low-pressure deposition method is used, and silane with a flow rate of 100 to 400 sccm is passed under the condition of a temperature of 550 to 600° C., and a first polysilicon layer with a thickness that can meet the passivation effect is prepared on both sides or on one side; the thickness can be specifically 200 to 400 nm, for example, a range of one or any two of 200 nm, 250 nm, 300 nm, 350 nm, and 400 nm. Among them, because the double-sided preparation of the polysilicon layer is conducive to the subsequent removal of the front polysilicon layer, the two extreme situations of excessive removal or insufficient removal are not prone to occur, and the yield is better controlled.

[0050] In the above step 101, after preparing the first polysilicon layer, the silicon wafer is sent into a furnace tube to boron-dope the first polysilicon layer to form a p-type doped region, thereby forming a passivation contact structure composed of a first silicon oxide layer and a boron-doped polysilicon layer, effectively reducing surface recombination and metal contact recombination.

[0051] The first polysilicon layer is doped with boron by boron diffusion. Optionally, the first polysilicon layer is doped with boron, including:

[0052] First, BCl3 and O2 with a flow ratio of 1:2 to 1:5 are introduced at a temperature of 800 to 900°C for low-temperature deposition, and then high-temperature advancement is carried out at a temperature of 900 to 950°C, and after the high-temperature advancement is completed, the boat is cooled down without oxygen.

[0053] Specifically, in the boron diffusion process, the silicon wafer is first deposited for 0 to 50 minutes at a temperature of 800 to 900°C, a flow ratio of BCl3 to O2 of 1:2 to 1:5, and a flow rate of BCl3 of 100 to 300 sccm / min, and then the silicon wafer is heated to 900 to 950°C for high-temperature advancement, and after the high-temperature advancement is completed, the silicon wafer is cooled out of the boat without oxygen, that is, the cooling process is without oxygen, and the surface boron doping concentration of 1E20 to 4E20 cm -3 p-type doped region.

[0054] In the above step 102, the boron-doped silicon wafer is chain-picked to remove the thin borosilicate glass film on the surface of the silicon wafer; optionally, the boron-doped silicon wafer is chain-picked with hydrofluoric acid at a mass percentage of 5 to 30%, which can effectively remove the thin borosilicate glass film on the front and back of the silicon wafer.

[0055] In the above step 103, the first region on the back of the silicon wafer for forming the p-type doped region is oxidized by laser to form a dense surface oxide layer, wherein the laser power is 15W to 55W and the marking speed is 3000 to 50000 mm / s, that is, the first region on the back of the silicon wafer can be effectively oxidized to form a dense oxide layer, and the boron doping surface concentration after oxidation is 1E21-3E21cm -3 .

[0056] Optionally, in the above step 103, the thickness of the oxide layer formed by the laser oxidation process is controlled to be 10-100 nm, which can effectively mask the p-type doped region and facilitate subsequent etching removal. For example, the thickness of the above oxide layer can be one of 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, or any two of the range values.

[0057] In the above step 104, a trough-type tank is used to perform double-sided alkaline etching on the silicon wafer after laser oxidation treatment using an alkaline solution to remove the laser damaged layer and the boron doped layer in the non-laser area. Optionally, in one embodiment, in the double-sided alkaline etching, the alkaline solution includes an etching additive and 3% to 10% by mass of NaOH or KOH, the processing temperature is 60 to 90° C., and the processing time is 150s to 600s.

[0058] In the above step 105, after completing the double-sided alkaline etching treatment, low pressure chemical vapor deposition (LPCVD) is used to first pass oxygen with a flow rate of 10 to 30 sccm to form an ultra-thin silicon oxide layer on the back of the silicon wafer, that is, the above-mentioned second silicon oxide layer, as an ultra-thin tunneling oxide layer, and the thickness of the second silicon oxide layer can be specifically 1 to 2 nm, for example, 1.5 nm; then, a segmented low-pressure deposition method is used, at a temperature of 550 to 600° C., silane with a flow rate of 100 to 400 sccm is passed, and a second polysilicon layer with a thickness that can meet the passivation effect is prepared on both sides or on one side; the thickness can be specifically 100 to 300 nm, for example, a range of one or any two of 100 nm, 150 nm, 200 nm, 250 nm, and 300 nm. Among them, because the double-sided preparation of the polysilicon layer is conducive to the subsequent removal of the front polysilicon layer, the two extreme situations of excessive removal or insufficient removal are not prone to occur, and the yield is better controlled.

[0059] In the above step 105, after preparing the second polysilicon layer, the silicon wafer is sent into the furnace tube to phosphorus-dope the first polysilicon layer to form an n-type doped region, thereby forming a passivation contact structure composed of a second silicon oxide layer and a phosphorus-doped polysilicon layer, effectively reducing surface recombination and metal contact recombination.

[0060] Wherein, phosphorus is doped into the second polysilicon layer by phosphorus diffusion. Optionally, phosphorus is doped into the second polysilicon layer, including:

[0061] First, the deposition was carried out for 15 to 55 minutes at a temperature of 780 to 880°C, a POCl3 flow rate of 80 to 150 sccm / min, an oxygen flow rate of 500 to 800 sccm / min, a nitrogen flow rate of 1000 to 2000 sccm / min, and a pressure of 150 to 200 mbar. Then, the silicon wafer was heated to 850 to 900°C, and the temperature was kept constant for 10 to 60 minutes. The silicon wafer was treated for 40 to 80 minutes at a pressure of 300 to 900 mbar and an oxygen flow rate of 2000 to 20000 sccm / min to obtain a surface doping concentration of 3E20 to 7E20 / cm 3 n-type doped region.

[0062] In the above step 106, other regions outside the second region on the back side of the silicon wafer are acted on by laser or by etching slurry plus screen printing. The second region is used to form an n-type doped region, and the second region and the first region are arranged in interdigital spacing.

[0063] Optionally, when the laser is used to remove the phosphosilicate glass layer outside the second area on the back side of the silicon wafer after phosphorus doping, the laser power is 15W to 55W and the marking speed is 3000 to 50000 mm / second, that is, the phosphosilicate glass layer on other areas outside the second area on the back side of the silicon wafer can be effectively removed, thereby achieving the effect of opening the P area and the PN isolation area.

[0064] Optionally, when removing the phosphosilicate glass layer outside the second area on the back side of the silicon wafer after phosphorus doping by etching slurry plus screen printing, an etching slurry such as NH4F is printed on other areas outside the second area on the back side of the silicon wafer to remove the borosilicate glass layer on the surface, thereby opening the film in the above-mentioned laser area, and then cleaning the polysilicon layer and etching slurry in the opening area by wet cleaning.

[0065] In the above step 107, the phosphosilicate glass layer on the front side of the silicon wafer is firstly removed on one side, so as to facilitate the subsequent etching and removal of the phosphorus-doped polysilicon layer on the front side and to perform texturing treatment.

[0066] Optionally, in one embodiment, hydrofluoric acid with a mass percentage of 5 to 30% is used to clean the front side of the silicon wafer, thereby removing the phosphosilicate glass layer on the front side of the silicon wafer by acid washing.

[0067] In the above step 107, after removing the front phosphosilicate glass layer, a trough-type wet process is used to remove the phosphorus-doped polysilicon layer in the laser areas on the front and back sides of the silicon wafer by etching and texturing, and a pyramid texturing morphology is formed in the gap areas (PN isolation areas) on the front and back sides of the silicon wafer.

[0068] Optionally, in one implementation, etching and texturing the silicon wafer includes:

[0069] The silicon wafer is alkaline etched using 1% to 5% by mass of NaOH and etching additives, and then the silicon wafer is groove-textured using 0.5% to 3% by mass of NaOH and texturizing additives, and then cleaned using 5% to 30% by mass of hydrofluoric acid and O3 to remove the borosilicate glass layer and the phosphosilicate glass layer on the back of the silicon wafer.

[0070] In this embodiment, the other areas outside the second area on the back side (that is, the area where the phosphosilicate glass layer has been removed) and the phosphorus-doped polysilicon layer on the front side are first removed through an alkali bath, and then a texturing bath is used to form a velvet surface in the gap areas on the front and back sides. The phosphosilicate glass layer in the second area on the back side, the dense oxide layer in the first area, and other surface additives are removed by cleaning with hydrofluoric acid and O3, thereby exposing the n-type doped area and the p-type doped area arranged in a finger-like manner.

[0071] Optionally, in another embodiment, the phosphosilicate glass layer on the front side of the silicon wafer is removed by pickling, and the silicon wafer is etched, comprising:

[0072] The silicon wafer is cleaned with a mixed acid, wherein the mixed acid comprises 25% to 35% by mass of HNO3 and 5% to 15% by mass of HF.

[0073] In this embodiment, a mixed acid of nitric acid and hydrofluoric acid is used, and one-step acid etching is performed to achieve the effect of removing the phosphosilicate glass layer on the front side of the silicon wafer and performing etching.

[0074] In the above step 108, an atomic layer deposition (ALD) process is used to coat the entire front and back of the product as a passivation layer to form field passivation; after the aluminum oxide film is formed, a plasma enhanced chemical vapor deposition (PECVD) process is used to coat an anti-reflection film layer on the back of the battery, and then an anti-reflection film layer is coated on the front to further enhance the passivation effect of the battery cell.

[0075] Optionally, the passivation layer is an aluminum oxide film layer, that is, the aluminum oxide film layer is plated on the entire front surface and the entire back surface as the passivation layer; the thickness of the passivation layer may be 1-10 nm.

[0076] Optionally, the back anti-reflection film layer may be a silicon nitride layer, and the thickness may be 50 to 120 nm, that is, the silicon nitride layer is plated on the entire back surface as the back anti-reflection film;

[0077] Optionally, the front anti-reflection film layer may be a silicon nitride film, or a stack of silicon nitride and silicon oxide, or a silicon oxynitride layer, and may have a thickness of 50 to 120 nm, which can further enhance the anti-reflection effect.

[0078] Optionally, in one embodiment, in the above step 108, forming a positive gate line conductive to the p-type doped region and a negative gate line conductive to the n-type doped region on the back side includes:

[0079] The silicon wafer with the anti-reflection film formed thereon is screen printed to form a positive electrode grid line connected to the p+ doped area and a negative electrode grid line connected to the n+ doped area on the back side, and then high-temperature sintering is performed to prepare an IBC cell.

[0080] Optionally, in another embodiment, in the above step 108, forming a positive gate line conductive to the p-type doped region and a negative gate line conductive to the n-type doped region on the back side includes:

[0081] A metal seed layer film is deposited on the back of a silicon wafer by physical vapor deposition. The material of the metal seed layer film is copper, and the thickness of the metal seed layer is 150-300nm. A layer of photosensitive ink is coated on the back seed layer and then dried. The drying temperature is 100°C and the time is 8-15min. The photosensitive ink on the back of the silicon wafer is exposed by laser direct writing to form a main and secondary grid perpendicular to each other. After the front and back of the silicon wafer are exposed, the silicon wafer is transferred to a chemical solution for development and drying, and finally a groove pattern to be electroplated is presented on the front and back of the silicon wafer. The silicon wafer with patterned front and back sides is placed in the electroplating tank for electroplating. The chemical solution in the electroplating tank includes copper sulfate and different types of additives. Different current parameters are set for the surface of the silicon wafer. The copper ions in the solution receive electrons to form copper atoms and adhere to the surface of the silicon wafer. Among them, since only a part of the grooved area on the surface of the silicon wafer has the seed layer exposed and is a conductive area, while other areas are covered with photosensitive ink on the back and are not conductive, the copper atoms will only gather on the surface of the seed layer in the groove to form copper grid lines. The electroplating time is controlled so that the height of the electroplated copper grid lines does not exceed the height of the patterned grooves.

[0082] The silicon wafer after copper plating on the back is placed in a KOH solution for film removal treatment, wherein the KOH mass percentage concentration is 5% and the film removal time is 6 minutes, which can remove the residual photosensitive ink on the surface of the silicon wafer;

[0083] The silicon wafer is then placed in an acid solution with a certain oxidizing property to remove the metal seed layer other than the gate lines on the surface of the silicon wafer, that is, a positive gate line conductive to the p-type doped area and a negative gate line conductive to the n-type doped area can be formed on the back.

[0084] Optionally, in one embodiment, the preparation method provided in the embodiment of the present invention further includes step 100 before the above step 101:

[0085] The silicon wafer is subjected to alkali polishing treatment.

[0086] In this embodiment, before forming the first silicon oxide layer and the first polysilicon layer, the silicon wafer is subjected to alkali polishing to remove organic contamination and metal impurities on the surface of the silicon wafer. Optionally, the silicon wafer is double-sided polished by tank alkali polishing, the alkali polishing solution includes water, alkali polishing additives and 1% to 10% by mass of NaOH or KOH, and the treatment time is 50s to 250s.

[0087] See also Figure 2, shows a schematic structural diagram of an IBC in an embodiment of the present invention when the single crystal silicon wafer is an N-type silicon wafer, wherein the first silicon oxide layer 21 and the second silicon oxide layer 22 are arranged in a finger-like manner at intervals on the back of the N-type silicon wafer 10, and a passivation layer 24 is arranged between the first silicon oxide layer 21 and the second silicon oxide layer 22, a boron-doped polysilicon layer 23 and a positive electrode gate line 25 are arranged in sequence on the surface of the first silicon oxide layer 21, and a phosphorus-doped polysilicon layer 26 and a negative electrode gate line 27 are arranged in sequence on the surface of the second silicon oxide layer 22; wherein the passivation layer 24 is a laminate of aluminum oxide and silicon nitride.

[0088] See also Figure 3 , shows a schematic structural diagram of an IBC in an embodiment of the present invention when the single crystal silicon wafer is a P-type silicon wafer, wherein a first silicon oxide layer 21 and a second silicon oxide layer 22 are arranged in a finger-like manner on the back of an N-type silicon wafer 20, and a passivation layer 24 is arranged between the first silicon oxide layer 21 and the second silicon oxide layer 22, a boron-doped polysilicon layer 23 and a positive electrode gate line 25 are arranged in sequence on the surface of the first silicon oxide layer 21, and a phosphorus-doped polysilicon layer 26 and a negative electrode gate line 27 are arranged in sequence on the surface of the second silicon oxide layer 22; wherein the passivation layer 24 is a laminate of aluminum oxide and silicon nitride.

[0089] The present invention also provides an IBC battery, wherein the battery is prepared by the above-mentioned IBC battery preparation method.

[0090] The present invention is described in detail below by way of examples.

[0091] Example 1

[0092] (1) A 182*182 N-type silicon wafer was subjected to double-sided alkali polishing treatment, wherein the alkali polishing solution included an alkali polishing additive and 5% by mass of NaOH, and the treatment time was 100 s;

[0093] (2) forming an ultra-thin silicon oxide layer with a thickness of 1.5 nm on the back of the silicon wafer by passing oxygen gas with a flow rate of 20 sccm as the first silicon oxide layer; then, using a segmented low-pressure deposition method, at a temperature of 580° C., passing silane with a flow rate of 250 sccm, a first polysilicon layer with a thickness of 200 nm is prepared on both sides;

[0094] (3) Boron doping is performed on the first polysilicon layer by boron diffusion, wherein the first polysilicon layer is deposited for 25 min at a temperature of 850°C, a flow ratio of BCl3 to O2 of 1:4, and a flow rate of BCl3 of 200 sccm / min, and then the silicon wafer is heated to 920°C for high temperature advancement, and then cooled out of the boat without oxygen after the high temperature advancement, that is, oxygen is not passed during the cooling process, and the surface doping concentration of 1E20-4E20cm -3 A p-type doped region;

[0095] (4) using 15% by mass hydrofluoric acid to chain pickle the boron-doped silicon wafer to remove the thin borosilicate glass film on the front and back of the silicon wafer;

[0096] (5) The first region on the back of the silicon wafer for forming a p-type doped region is oxidized by laser to form a surface dense oxide layer with a thickness of 50 nm, wherein the laser power is 35 W and the marking speed is 20000 mm / s;

[0097] (6) using a trough body, using an alkaline solution to perform double-sided alkaline etching on the silicon wafer after laser oxidation treatment to remove the laser damaged layer and the boron doped layer in the non-laser area, wherein the alkaline solution includes an etching additive and 8% by mass of NaOH, the treatment temperature is 80° C., and the treatment time is 300 s;

[0098] (7) forming an ultra-thin silicon oxide layer with a thickness of 1.5 nm on the back of the silicon wafer by passing oxygen gas with a flow rate of 20 sccm as a second silicon oxide layer; then, using a segmented low-pressure deposition method, at a temperature of 580° C., passing silane with a flow rate of 250 sccm, a second polysilicon layer with a thickness of 200 nm is prepared on both sides;

[0099] (8) The second polysilicon layer is doped with phosphorus by phosphorus diffusion. In the phosphorus diffusion treatment, the phosphorus is first deposited for 10 minutes at a temperature of 880° C., a POCl3 flow rate of 120 sccm / min, an oxygen flow rate of 700 sccm / min, a nitrogen flow rate of 1800 sccm / min, and a pressure of 160 mbar. Then, the silicon wafer is heated to 980° C. and treated for 70 minutes at a pressure of 800 mbar and an oxygen flow rate of 12000 sccm / min to obtain a surface doping concentration of 2E20-5E20 / cm 3 n-type doped region;

[0100] (9) removing the phosphorus-silicate glass layer outside the second area on the back side of the silicon wafer after phosphorus doping by laser, wherein the laser power is 35 W and the marking speed is 20000 mm / s, so as to achieve the effect of opening the P area and the PN isolation area;

[0101] (10) Cleaning the front side of the silicon wafer with 15% by mass hydrofluoric acid to remove the phosphosilicate glass layer on the front side of the silicon wafer;

[0102] (11) using 2% by mass of NaOH and an etching additive to perform alkaline etching on the silicon wafer, then using 1% by mass of NaOH and a texturing additive to perform groove texturing on the silicon wafer, and then using 15% by mass of hydrofluoric acid and O3 to clean and remove the borosilicate glass layer and the phosphosilicate glass layer on the back of the silicon wafer;

[0103] (12) Take the silicon wafer after chain pickling, and use the atomic layer deposition process to plate a 5 nm thick aluminum oxide film on the entire front and back of the product to form field passivation;

[0104] (13) After forming the aluminum oxide film layer by PECVD, a first silicon nitride layer with a thickness of 80 nm is firstly plated on the back side of the battery as a back side anti-reflection film layer, and then a second silicon nitride layer with a thickness of 80 nm is plated on the front side as a front side anti-reflection film layer;

[0105] (14) printing a positive electrode paste conductive to the p-type doped region on the third region of the anti-reflection film layer on the back side of the silicon wafer, and printing a negative electrode paste conductive to the n-type doped region on the fourth region of the anti-reflection film layer on the back side;

[0106] (15) The silicon wafer is subjected to high temperature sintering to obtain an IBC battery.

[0107] To sum up, in this embodiment, laser oxidation of the P region after boron doping can form a denser borosilicate glass layer mask with stronger blocking performance, which not only makes the prepared p-type doped region have the advantages of high surface concentration, high passivation performance, and low contact resistance, but also avoids the pollution problems caused by blocking or etching slurry printing, and has higher production accuracy and production capacity, which is suitable for mass production.

[0108] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concept. Therefore, the claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0109] The IBC battery and its preparation method provided by the present invention are introduced in detail above. The principle and implementation mode of the present invention are explained in this article by using specific examples. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation mode and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A method for preparing an IBC battery, characterized in that: include: forming a first silicon oxide layer and a first polysilicon layer in sequence on the back side of the single crystal silicon wafer, and doping the first polysilicon layer with boron; Performing chain pickling on the boron-doped silicon wafer; Performing laser oxidation treatment on the first area on the back of the silicon wafer after chain pickling to form an oxide layer; the first area is used to form a p-type doped area; Performing double-sided alkaline etching on the silicon wafer after laser oxidation treatment; forming a second silicon oxide layer and a second polysilicon layer in sequence on the back side of the silicon wafer subjected to double-sided alkali etching, and doping the second polysilicon layer with phosphorus; Removing the phosphorus-silicate glass layer outside the second region on the back side of the silicon wafer after phosphorus doping, wherein the second region and the first region are arranged in an interdigitated manner; After removing the phosphosilicate glass layer outside the second region, removing the phosphosilicate glass layer on the front side of the silicon wafer by pickling, and etching and texturing the silicon wafer to expose the n-type doped region and the p-type doped region arranged in an interdigitated manner; After etching and texturing, a passivation film layer and an anti-reflection film layer are formed on both sides of the silicon wafer, and a positive gate line connected to the p-type doped area and a negative gate line connected to the n-type doped area are formed on the back to produce an IBC battery.

2. The preparation method according to claim 1, characterized in that: The single crystal silicon wafer is an N-type silicon wafer or a P-type silicon wafer.

3. The preparation method according to claim 1, characterized in that: The first polysilicon layer is doped with boron, comprising: First, BCl3 and O2 with a flow ratio of 1:2 to 1:5 are introduced at a temperature of 800 to 900°C for low-temperature deposition, and then high-temperature advancement is carried out at a temperature of 900 to 950°C, and after the high-temperature advancement is completed, the boat is cooled down without oxygen.

4. The preparation method according to claim 3, characterized in that: The boron doping concentration on the silicon surface after high temperature advancement is 1E20~4E20cm -3 ; and / or The phosphorus doping concentration on the silicon surface after phosphorus diffusion is 3E20~7E20cm -3 .

5. The preparation method according to claim 1, characterized in that: In the laser oxidation treatment of the first area on the back side of the silicon wafer after chain pickling, the laser power is 15W to 55W and the marking speed is 3000 to 50000 mm / second; and / or The phosphorus-silicate glass layer outside the second area on the back side of the silicon wafer after the phosphorus doping is removed comprises: The phosphorus-silicate glass layer outside the second area on the back side of the silicon wafer after phosphorus doping is removed by laser, wherein the laser power is 15W-55W and the marking speed is 3000-50000mm / sec.

6. The preparation method according to claim 5, characterized in that: The thickness of the oxide layer formed by laser oxidation treatment is 10 to 100 nm.

7. The preparation method according to claim 1, characterized in that: The silicon wafer is subjected to etching and texturing treatment, including: The silicon wafer is alkaline etched using 1% to 5% by mass of NaOH and etching additives, and then the silicon wafer is groove-textured using 0.5% to 3% by mass of NaOH and texturizing additives, and then cleaned using 5% to 30% by mass of hydrofluoric acid and O3 to remove the borosilicate glass layer and the phosphosilicate glass layer on the back of the silicon wafer.

8. The preparation method according to claim 1, characterized in that: Before sequentially forming a first silicon oxide layer and a first polysilicon layer on the back side of the single crystal silicon wafer, the method further comprises: The silicon wafer is subjected to alkali polishing treatment.

9. The preparation method according to claim 1, characterized in that: Pickling to remove the phosphorus-silicate glass layer on the front side of the silicon wafer comprises: The front side of the silicon wafer is cleaned by using hydrofluoric acid with a mass percentage of 5 to 30%.

10. An IBC battery, characterized in that: The invention is prepared by the method described in claims 1 to 9.

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