Solar cell and preparation method thereof

Abstract

The invention discloses a solar cell and a preparation method thereof. The preparation method comprises the following steps: cleaning and polishing an N-type silicon substrate; depositing a tunneling oxide layer and an intrinsic amorphous silicon layer on the back surface; performing phosphorus diffusion to form an N-type doped polycrystalline silicon layer and a PSG layer; laser grooving is used to obtain a P region in which a P + doped region is to be formed; texturing is carried out; sequentially depositing an intrinsic amorphous silicon layer and an anti-reflection film on the front surface; sequentially depositing an intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer on the back surface; partially splitting the film by using laser to expose the PSG layer of the N region; pickling the PSG layer, and exposing the N-type doped polycrystalline silicon layer below the PSG layer; depositing a TCO conductive film layer on the whole back surface; and laser grooving is used to form an isolation groove, the N region and the P region are insulated, a metal electrode is prepared, and sintering and curing are carried out. The advantages of HBC and TBC are combined, the process is simplified, the cost is reduced, compared with a traditional H solar cell, the solar cell has more advantages in temperature control, thermal stress of high temperature on a silicon wafer is avoided, and the quality of the silicon wafer is improved.

Description

Technical Field

[0001] The invention relates to the field of solar cell manufacturing, and in particular to a solar cell and a method for preparing the same. Background Art

[0002] BC battery, or back contact battery, is a solar cell that combines multiple technical routes. The current mainstream BC batteries are HPBC, TBC, and HBC, which improve the photoelectric conversion efficiency of the battery through different technical paths.

[0003] Among them, the TBC cell is a cell formed by combining TOPCon and IBC technologies, also known as the POLO-IBC cell; its structural feature is the use of tunneling oxide passivation contact (TOPCon) technology and its application to the back contact structure. This design takes advantage of the high passivation quality and good contact characteristics of the TOPCon technology and has a high efficiency potential. The HBC cell is a high-efficiency solar cell that combines heterojunction (HJT) technology and interdigitated back contact (IBC) technology; its structural feature is the formation of a heterojunction on the back of the cell and combining it with a back contact structure to achieve efficient carrier collection.

[0004] The experimental efficiency of N-type HBC cells can reach 26.63% because it combines the advantages of full light reception of back contact cells and high-quality passivation of heterojunction cells. The significant improvement in efficiency can greatly increase the power generation of the battery itself per watt on the one hand, and help reduce the LCOE of the entire industry chain on the other hand. TBC cells are one of the high-efficiency cells that can be compared with HBC cells. They have well solved the shortcomings of the original HBC cells in the back doping concentration and intrinsic amorphous silicon passivation, and are a structure of high-efficiency crystalline silicon cells.

[0005] However, TBC cells require a high temperature process when forming polycrystalline silicon, which makes them lack the low temperature advantage of HBC cells. Therefore, a new BC cell preparation method is developed, which not only combines the respective advantages of HBC and TBC, but also simplifies the preparation process and reduces the preparation cost. Summary of the invention

[0006] The present invention aims to provide a solar cell and a method for preparing the same, combining the respective advantages of HBC and TBC while simplifying the preparation process and reducing the preparation cost.

[0007] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0008] A method for preparing a solar cell comprises the following steps:

[0009] Step S1: cleaning and polishing the N-type silicon substrate;

[0010] Step S2: depositing a tunneling oxide layer and an intrinsic amorphous silicon layer in sequence on the back side of the N-type silicon substrate;

[0011] The deposition temperature of the tunnel oxide layer is 500° C. to 700° C.;

[0012] The deposition temperature of the intrinsic amorphous silicon layer is 550° C. to 650° C.;

[0013] Step S3: performing phosphorus diffusion on the intrinsic amorphous silicon layer to form an N-type doped polysilicon layer, and forming a PSG layer on the surface of the N-type doped polysilicon layer;

[0014] The phosphorus diffusion temperature is 700°C to 900°C;

[0015] Step S4: using a laser to groove the N-type doped polysilicon layer, and etching and cleaning to obtain a P region to be formed as a P+ doped region; the region not grooved is the N region;

[0016] Step S5: performing texturing on the front side of the N-type silicon substrate;

[0017] Step S6: depositing an intrinsic amorphous silicon layer and an anti-reflection layer in sequence on the front surface of the N-type silicon substrate;

[0018] Step S7: depositing an intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer in sequence on the back side of the N-type silicon substrate;

[0019] The deposition temperature of the intrinsic amorphous silicon layer is 180° C. to 220° C.;

[0020] The deposition temperature of the P-type doped amorphous silicon layer is 200° C. to 220° C.;

[0021] Step S8: using a laser to partially open the P-type doped amorphous silicon layer and the intrinsic amorphous silicon layer on the N region on the back side of the N-type silicon substrate to expose the PSG layer on the N region;

[0022] Step S9: pickling the PSG layer on the exposed N region to expose the N-type doped polysilicon layer thereunder;

[0023] Step S10: depositing a TCO conductive thin film layer on the entire back surface of the N-type silicon substrate;

[0024] Step S11: using a laser to open a groove on the back side of the N-type silicon substrate to expose the PSG layer and form an isolation groove to insulate the N region and the P region;

[0025] Step S12: preparing metal electrodes in the P region and the N region on the back side of the N-type silicon substrate, and sintering and curing them.

[0026] In some embodiments, in step S2, the thickness of the tunnel oxide layer is 1 nm to 3 nm, and the thickness of the intrinsic amorphous silicon layer is 280 nm to 330 nm.

[0027] In some embodiments, in step S3, the square resistance of the N-type doped polysilicon layer is 30Ω-60Ω, and the thickness of the PSG layer is 40nm-60nm.

[0028] In some embodiments, in step S7, the intrinsic amorphous silicon layer and the P-type doped amorphous silicon layer are deposited using CVD equipment, the intrinsic amorphous silicon layer is an intrinsic hydrogenated amorphous layer, the thickness of the intrinsic hydrogenated amorphous layer is 10nm, the P-type doped amorphous silicon layer is a P-type hydrogenated doped amorphous silicon layer, the thickness of the P-type hydrogenated doped amorphous silicon layer is 20nm to 25nm.

[0029] In certain embodiments, in step S4, the etching cleaning is performed by immersion or floating on a solution, and the reagent used for the etching cleaning is a KOH solution or a HF / HCl mixed solution.

[0030] In some embodiments, in step S6, PECVD equipment is used to deposit the intrinsic amorphous silicon layer and the anti-reflection layer, the intrinsic amorphous silicon layer is an intrinsic hydrogenated amorphous layer, the thickness of the intrinsic hydrogenated amorphous layer is 6nm to 10nm, and the anti-reflection layer is a silicon nitride layer, the thickness of the silicon nitride layer is 80nm to 100nm.

[0031] In some embodiments, in step S10, the TCO conductive thin film layer is deposited using CVD equipment, and the thickness of the TCO conductive thin film layer is 70 nm to 100 nm.

[0032] The present invention also relates to a solar cell, which is manufactured by the above-mentioned method for manufacturing a solar cell, wherein the solar cell comprises an N-type silicon substrate, wherein the N-type silicon substrate has a front side and a back side opposite to each other, and the back side of the N-type silicon substrate has first regions and second regions alternately arranged along a first direction, wherein the first direction intersects with a thickness direction of the N-type silicon substrate;

[0033] The first region includes a tunneling oxide layer and an N-type doped polysilicon layer sequentially arranged in a direction away from the back side of the substrate, and the second region includes a back intrinsic amorphous silicon layer, a P-type doped amorphous silicon layer, and a TCO conductive film layer sequentially arranged in a direction away from the back side of the substrate;

[0034] The surface of the N-type doped polysilicon layer comprises a third region, a fourth region arranged at both ends of the third region along the first direction, and a spacing region dividing the fourth region into two sub-regions, and the two sub-regions are arranged at intervals along the first direction;

[0035] The sub-region includes a back intrinsic amorphous silicon layer, a P-type doped amorphous silicon layer, and a TCO conductive film layer arranged in sequence in a direction away from the back side of the substrate, and the P-type doped amorphous silicon layer of the second region is in contact with the back intrinsic amorphous silicon layer of the adjacent sub-region;

[0036] A TCO conductive film layer is disposed on the third region of the surface of the N-type doped polysilicon layer;

[0037] The front side of the N-type silicon substrate is provided with a suede structure, a front intrinsic amorphous silicon layer and an anti-reflection layer in sequence in a direction away from the front side of the substrate.

[0038] In some embodiments, the TCO conductive film layers of the two sub-regions are connected to the TCO conductive film layers of the adjacent third region and the second region respectively.

[0039] In some embodiments, the invention further comprises a first electrode and a second electrode, wherein the first electrode is printed on the TCO conductive film layer located in the third region, and the second electrode is printed on the TCO conductive film layer located in the second region.

[0040] Due to the application of the above technical solution, the beneficial effects of the present invention compared with the prior art are:

[0041] (1) This application combines diffusion doping and amorphous silicon doping technology. This combination can simplify the manufacturing process through low-temperature amorphous silicon doping process while ensuring efficient electron transmission, reducing energy consumption and cost. The application of amorphous silicon layer not only improves the surface passivation effect of silicon wafers, reduces defects, and improves the effective collection of electrons and holes, but also optimizes optical properties and improves light absorption, thereby enhancing photoelectric conversion efficiency. Compared with traditional HBC cells, this design has more advantages in temperature control, avoids thermal stress on silicon wafers caused by high temperature, improves silicon wafer quality, and the amorphous silicon doping process is simpler, improving production efficiency.

[0042] (2) In step S4 of the present application, a laser is used to groove the N-type doped polysilicon layer to expose the P-type doped layer. Compared with the existing HBC battery preparation process, it does not need to use masking and demasking technology multiple times to form patterning, which reduces the process difficulty and improves production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0044] Figure 1 is a process flow chart of preparing a solar cell in Example 1 of the present invention;

[0045] Figure 2 It is a schematic diagram of the cross-sectional structure of the solar cell in Example 2 of the present invention.

[0046] Description of reference numerals:

[0047] 1-N-type silicon substrate; 2-tunneling oxide layer; 3-N-type doped polysilicon layer; 4-back intrinsic amorphous silicon layer; 5-P-type doped amorphous silicon layer; 6-TCO conductive film layer; 7-spacer; 8-texture structure; 9-front intrinsic amorphous silicon layer; 10-anti-reflection layer; 20-first electrode; 30-second electrode. DETAILED DESCRIPTION

[0048] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0049] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the present invention described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0050] In the present invention, the directions or positional relationships indicated by the terms "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal" and the like are based on the directions or positional relationships shown in the drawings. These terms are mainly used to better describe the present invention and its embodiments, and are not used to limit the indicated devices, elements or components to have a specific direction, or to be constructed and operated in a specific direction.

[0051] In addition, some of the above terms may be used to express other meanings in addition to indicating orientation or positional relationship. For example, the term "on" may also be used to express a certain dependency or connection relationship in some cases. For those skilled in the art, the specific meanings of these terms in the present invention can be understood according to specific circumstances.

[0052] In addition, the terms "installed", "set", "provided with", "connected", "connected", and "socketed" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0053] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0054] Example 1

[0055] See also Figure 1 This embodiment provides a method for preparing a solar cell, comprising the following steps:

[0056] Step S1: cleaning and polishing the N-type silicon substrate.

[0057] In this embodiment, the thickness of the N-type silicon substrate is 150 microns, and the resistivity is 2Ω·cm~5

[0058] Ω·cm.

[0059] In detail, the N-type silicon substrate is placed in a tank-type alkali polishing machine for polishing and cleaning: the N-type silicon substrate is pre-cleaned to remove organic and other contaminants generated during the cutting and transportation of the N-type silicon substrate; the N-type silicon substrate is then placed in a hydrogen peroxide alkali solution with a concentration of 0.2% to 1% to clean the surface oil; then, after washing the residual chemicals with water, an alkali polishing treatment is performed, and the alkali solution used is a KOH solution with a concentration of 5% to 20%, the polishing temperature is 70°C, and the polishing time is 300S; finally, SC1 cleaning, ozone cleaning, and finally acid washing and dehydration are performed to complete the polishing and cleaning;

[0060] Step S2: depositing a tunneling oxide layer and an intrinsic amorphous silicon layer in sequence on the back side of the N-type silicon substrate;

[0061] The details are as follows: put the cleaned and polished N-type silicon substrate into the LPCVD equipment, grow a 1nm to 3nm tunneling oxide layer at 500℃ to 700℃; grow an intrinsic amorphous silicon layer at 550℃ to 650℃ with a thickness of 280 to 330nm;

[0062] Step S3: performing phosphorus diffusion on the intrinsic amorphous silicon layer to form an N-type doped polysilicon layer, and forming a PSG layer on the surface of the N-type doped polysilicon layer;

[0063] Specifically, an N-type silicon substrate is placed in a tubular diffusion device for phosphorus diffusion. The phosphorus diffusion temperature is 700°C to 900°C, and the diffusion time is 30 minutes to 50 minutes. The sheet resistance of the N-type doped polysilicon layer formed after diffusion is 30Ω to 60Ω. At the same time, a PSG layer is formed on the surface of the N-type doped polysilicon layer for isolation. The thickness of the PSG layer is 40nm to 60nm.

[0064] Step S4: using a laser to groove the N-type doped polysilicon layer, and etching and cleaning to obtain a P region to be formed as a P+ doped region; the region not grooved is the N region;

[0065] In detail, the laser uses a green nanosecond laser with a wavelength of 532nm and a pulse width of nanoseconds; the etching and cleaning is an immersion method or a floating method on a solution, and the reagents used for etching and cleaning are a KOH solution and a HF / HCl mixed solution;

[0066] Step S5: performing texturing on the front side of the N-type silicon substrate;

[0067] In this embodiment, the front side of the N-type silicon substrate is textured by RIE plasma etching method. The process of RIE plasma etching method is as follows: the N-type silicon substrate is placed in a carrier for plasma etching and sent into the cavity of the plasma etching equipment; the cavity is evacuated, and the vacuum degree of the equipment is maintained at 100mtorr~1000mtorr at room temperature 25°C, and the pressure is maintained stable, and 1000sccm~1000sccm of SF6 and 1000sccm~5000sccm of SO3 are introduced. The method comprises the following steps: using a mixed solution of BOE:H2O2:H2O=1:2:3 in volume ratio to perform texture optimization on the front side of the N-type silicon substrate after RIE, with a reaction time of 6 to 8 minutes and a reaction temperature of 40°C, and then washing with water, HF washing, water washing, HCl washing, and water washing in order to remove the oxide layer or metal impurities on the surface of the N-type silicon substrate;

[0068] Step S6: depositing an intrinsic amorphous silicon layer and an anti-reflection layer in sequence on the front surface of the N-type silicon substrate;

[0069] In this embodiment, a PECVD device is used to deposit an intrinsic amorphous silicon layer and an anti-reflection layer. The intrinsic amorphous silicon layer is an intrinsic hydrogenated amorphous layer, the thickness of the intrinsic hydrogenated amorphous layer is 6nm-10nm, and the deposition temperature of the intrinsic hydrogenated amorphous layer is 180°C-220°C; the anti-reflection layer is a silicon nitride layer, the thickness of the silicon nitride layer is 80nm-100nm, and the deposition temperature of the silicon nitride layer is 500°C-550°C;

[0070] Step S7: depositing an intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer in sequence on the back side of the N-type silicon substrate;

[0071] In this embodiment, a CVD device is used to deposit an intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer, wherein the intrinsic amorphous silicon layer is an intrinsic hydrogenated amorphous layer, the thickness of the intrinsic hydrogenated amorphous layer is 10 nm, and the deposition temperature of the intrinsic amorphous silicon layer is 180° C. to 220° C.; the P-type doped amorphous silicon layer is a P-type hydrogenated doped amorphous silicon layer, the thickness of the P-type hydrogenated doped amorphous silicon layer is 20 nm to 25 nm, and the deposition temperature of the P-type doped amorphous silicon layer is 200° C. to 220° C.;

[0072] Step S8: using a laser to partially open the P-type doped amorphous silicon layer and the intrinsic amorphous silicon layer on the N region on the back side of the N-type silicon substrate to expose the PSG layer on the N region;

[0073] In detail, nanosecond laser is used to partially open the P-type doped amorphous silicon layer and the intrinsic amorphous silicon layer on the N region, and the laser power is 10w to 14w;

[0074] Step S9: acid-washing the PSG layer on the exposed N region to expose the N-type doped polysilicon layer thereunder;

[0075] In this embodiment, a chain machine is used to remove the exposed PSG: 5% wt hydrofluoric acid is used to clean the exposed PSG layer, thereby removing the PSG layer in the grooved area to expose a portion of the N-type doped polysilicon layer;

[0076] Step S10: depositing a TCO conductive thin film layer on the entire back surface of the N-type silicon substrate;

[0077] In this embodiment, a TCO conductive film layer is deposited using CVD equipment, and the thickness of the TCO conductive film layer is 70nm to 100nm;

[0078] Step S11: using a laser to open a groove on the back side of the N-type silicon substrate to expose the PSG layer and form an isolation groove to insulate the N region and the P region;

[0079] In detail, a UV picosecond laser is used to open a groove to expose the PSG layer and form an isolation groove to insulate the N region and the P region to prevent leakage caused by the interconnection between the N region and the P region; the insulation resistance of the insulating region is tested to be >10MΩ, and the laser width is 75 microns;

[0080] Step S12: preparing metal electrodes in the P region and the N region on the back side of the N-type silicon substrate, and sintering and curing them.

[0081] Example 2

[0082] See also Figure 2 This embodiment provides a solar cell, which is manufactured by the method for manufacturing a solar cell in Embodiment 1. The solar cell includes an N-type silicon substrate 1, a first electrode 20 and a second electrode 30. The N-type silicon substrate 1 has a front surface and a back surface opposite to each other. The back surface of the N-type silicon substrate 1 has first regions and second regions alternately arranged along a first direction. The first direction intersects with a thickness direction of the N-type silicon substrate 1.

[0083] The first region includes a tunneling oxide layer 2 and an N-type doped polysilicon layer 3 arranged in sequence in a direction away from the back side of the substrate, and the second region includes a back intrinsic amorphous silicon layer 4, a P-type doped amorphous silicon layer 5, and a TCO conductive film layer 6 arranged in sequence in a direction away from the back side of the substrate;

[0084] The surface of the N-type doped polysilicon layer 3 has a third region, a fourth region arranged at both ends of the third region along the first direction, and a spacing region 7 that divides the fourth region into two sub-regions, and the two sub-regions are arranged in intervals along the first direction. The sub-regions include a back intrinsic amorphous silicon layer 4, a P-type doped amorphous silicon layer 5, and a TCO conductive film layer 6 that are sequentially arranged in a direction away from the back of the substrate, and the P-type doped amorphous silicon layer 5 of the second region is in contact with the back intrinsic amorphous silicon layer 4 of the adjacent sub-region. A TCO conductive film layer 6 is provided on the third region of the surface of the N-type doped polysilicon layer 3;

[0085] The front side of the N-type silicon substrate 1 is provided with a velvet structure 8, a front intrinsic amorphous silicon layer 9 and an anti-reflection layer 10 in sequence in a direction away from the front side of the substrate;

[0086] In this embodiment, the first electrode 20 is printed on the TCO conductive film layer 6 located in the third area, and the second electrode 30 is printed on the TCO conductive film layer 6 located in the second area. In other embodiments, copper electroplating may also be used. This is a conventional technology and will not be described in detail here.

[0087] In this embodiment, the TCO conductive film layers 6 of the two sub-regions are connected to the TCO conductive film layers 6 of the adjacent third region and the second region, respectively. That is, the two sub-regions and the TCO conductive film layers 6 of the adjacent third region and the second region are formed synchronously.

[0088] Finally, it should be noted that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments, or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a solar cell, characterized in that: The steps include: Step S1: cleaning and polishing the N-type silicon substrate; Step S2: depositing a tunneling oxide layer and an intrinsic amorphous silicon layer in sequence on the back side of the N-type silicon substrate; The deposition temperature of the tunnel oxide layer is 500° C. to 700° C.; The deposition temperature of the intrinsic amorphous silicon layer is 550° C. to 650° C.; Step S3: performing phosphorus diffusion on the intrinsic amorphous silicon layer to form an N-type doped polysilicon layer, and forming a PSG layer on the surface of the N-type doped polysilicon layer; The phosphorus diffusion temperature is 700°C to 900°C; Step S4: using a laser to groove the N-type doped polysilicon layer, and etching and cleaning to obtain a P region to be formed as a P+ doped region; the region not grooved is the N region; Step S5: performing texturing on the front side of the N-type silicon substrate; Step S6: depositing an intrinsic amorphous silicon layer and an anti-reflection layer in sequence on the front surface of the N-type silicon substrate; Step S7: depositing an intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer in sequence on the back side of the N-type silicon substrate; The deposition temperature of the intrinsic amorphous silicon layer is 180° C. to 220° C.; The deposition temperature of the P-type doped amorphous silicon layer is 200° C. to 220° C.; Step S8: using a laser to partially open the P-type doped amorphous silicon layer and the intrinsic amorphous silicon layer on the N region on the back side of the N-type silicon substrate to expose the PSG layer on the N region; Step S9: pickling the PSG layer on the exposed N region to expose the N-type doped polysilicon layer thereunder; Step S10: depositing a TCO conductive thin film layer on the entire back surface of the N-type silicon substrate; Step S11: using a laser to open a groove on the back side of the N-type silicon substrate to expose the PSG layer and form an isolation groove to insulate the N region and the P region; Step S12: preparing metal electrodes in the P region and the N region on the back side of the N-type silicon substrate, and sintering and curing them.

2. The method for preparing a solar cell according to claim 1, characterized in that: In step S2, the thickness of the tunnel oxide layer is 1 nm to 3 nm, and the thickness of the intrinsic amorphous silicon layer is 280 nm to 330 nm.

3. The method for preparing a solar cell according to claim 1, wherein: In step S3, the square resistance of the N-type doped polysilicon layer is 30Ω-60Ω, and the thickness of the PSG layer is 40nm-60nm.

4. The method for preparing a solar cell according to claim 1, wherein: In step S7, CVD equipment is used to deposit the intrinsic amorphous silicon layer and the P-type doped amorphous silicon layer, the intrinsic amorphous silicon layer is an intrinsic hydrogenated amorphous layer, the thickness of the intrinsic hydrogenated amorphous layer is 10nm, the P-type doped amorphous silicon layer is a P-type hydrogenated doped amorphous silicon layer, the thickness of the P-type hydrogenated doped amorphous silicon layer is 20nm to 25nm.

5. The method for preparing a solar cell according to claim 1, wherein: In step S4, the etching cleaning is performed by immersion or floating on a solution, and the reagents used for the etching cleaning are KOH solution and HF / HCl mixed solution.

6. The method for preparing a solar cell according to claim 1, characterized in that: In step S6, PECVD equipment is used to deposit the intrinsic amorphous silicon layer and the anti-reflection layer, the intrinsic amorphous silicon layer is an intrinsic hydrogenated amorphous layer, the thickness of the intrinsic hydrogenated amorphous layer is 6nm to 10nm, and the anti-reflection layer is a silicon nitride layer, the thickness of the silicon nitride layer is 80nm to 100nm.

7. The method for preparing a solar cell according to claim 1, characterized in that: In step S10, the TCO conductive thin film layer is deposited by using PVD equipment, and the thickness of the TCO conductive thin film layer is 70nm-100nm.

8. A solar cell prepared by the preparation method according to any one of claims 1 to 7.

9. The solar cell according to claim 8, characterized in that An N-type silicon substrate is included, wherein the N-type silicon substrate has a front side and a back side opposite to each other, and the back side of the N-type silicon substrate has first regions and second regions alternately arranged along a first direction, and the first direction intersects with a thickness direction of the N-type silicon substrate; The first region includes a tunneling oxide layer and an N-type doped polysilicon layer sequentially arranged in a direction away from the back side of the substrate, and the second region includes a back intrinsic amorphous silicon layer, a P-type doped amorphous silicon layer, and a TCO conductive film layer sequentially arranged in a direction away from the back side of the substrate; The surface of the N-type doped polysilicon layer comprises a third region, a fourth region arranged at both ends of the third region along the first direction, and a spacing region dividing the fourth region into two sub-regions, and the two sub-regions are arranged at intervals along the first direction; The sub-region includes a back intrinsic amorphous silicon layer, a P-type doped amorphous silicon layer, and a TCO conductive film layer arranged in sequence in a direction away from the back side of the substrate, and the P-type doped amorphous silicon layer of the second region is in contact with the back intrinsic amorphous silicon layer of the adjacent sub-region; A TCO conductive film layer is disposed on the third region of the surface of the N-type doped polysilicon layer; The front side of the N-type silicon substrate is provided with a suede structure, a front intrinsic amorphous silicon layer and an anti-reflection layer in sequence in a direction away from the front side of the substrate.

10. The solar cell according to claim 9, characterized in that The TCO conductive film layers of the two sub-areas are connected to the TCO conductive film layers of the adjacent third area and the second area respectively.

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