Arc protection for chip stack bonded wafers

Abstract

The invention relates to arc protection for bonded wafers of chip stacks. A semiconductor device may include a first chip having a first wafer and a first dielectric layer; and a second chip including a second wafer and a second dielectric layer, the second chip having a back side surface and a front side surface opposite the back side surface, and bonded to the first chip at the front side surface to define a bonding wire between the first dielectric layer and the second dielectric layer. The semiconductor device may include: a die encapsulation layer on the backside surface, the die encapsulation layer having a die encapsulant ground contact in contact with the second wafer; and an electrostatic discharge path including the die encapsulant, the die encapsulant ground contact, a first die encapsulant in the first dielectric layer, a second die encapsulant in the second dielectric layer, and a hybrid bonding portion connecting the first die encapsulant and the second die encapsulant through the bonding wire.

Description

Technical Field

[0001] This specification relates to chip stacking. Background Art

[0002] Examples of chip stacking include structures in which one chip (also referred to as the top chip or second chip) is flipped and bonded to another chip (also referred to as the bottom chip or first chip). In other words, the front side of the top chip can be bonded to the front side of the bottom chip so that the back side of the top chip and the back side of the bottom chip can be used for electrical connections and other functions.

[0003] For example, when the top chip is an optical sensor chip, the optical sensing element can be disposed on or near the back side of the top chip so that light incident on the exposed back side of the top chip can easily reach the optical sensing element. More generally, this chip stacking technology enables reliable, low-latency connections to be formed between circuits / devices of the stacked chips.

[0004] These stacked chips typically include an insulating material, such as an oxide, disposed between a bottom wafer material of the bottom chip and a top wafer material of the top chip. Such an oxide can be used to bond the bottom chip and the top chip to each other and to achieve electrical connection between the two, such as when implementing copper (Cu) hybrid bonding. Summary of the invention

[0005] Components of the chip stack may be configured to provide electrostatic discharge paths and to prevent arcing events.

[0006] According to a general aspect, a semiconductor device includes: a first chip, the first chip including a first wafer and a first dielectric layer disposed thereon; and a second chip, the second chip including a second wafer and a second dielectric layer disposed thereon, the second chip having a backside surface and a frontside surface opposite to the backside surface, the second chip being bonded to the first chip at the frontside surface to define a bonding wire between the first dielectric layer and the second dielectric layer. The semiconductor device includes: an opening extending through the backside surface of the second chip into the second dielectric layer, and a bonding pad disposed in the second dielectric layer between the second wafer and the bonding wire and extending beyond the opening in a direction parallel to the bonding wire.

[0007] According to another general aspect, a semiconductor device includes: a first chip, the first chip including a first wafer and a first dielectric layer disposed thereon; and a second chip, the second chip including a second wafer and a second dielectric layer disposed thereon, wherein a bonding pad is disposed within the second dielectric layer, the second chip having a backside surface and a frontside surface opposite to the backside surface, and bonded to the first chip at the frontside surface to define a bonding wire between the first dielectric layer and the second dielectric layer. The semiconductor device also includes an opening through the backside surface of the second chip and through the second wafer, the opening extending into the second dielectric layer so as to expose only a portion of the upper surface of the bonding pad for electrical connection therewith.

[0008] According to another general aspect, a method for manufacturing a semiconductor device includes: forming a first chip, the first chip including a first wafer and a first dielectric layer disposed thereon; forming a second dielectric layer on the second wafer of a second chip; and forming a bonding pad in the second dielectric layer. The method also includes bonding a front side surface of the second chip to the first chip to define a bonding wire between the first dielectric layer and the second dielectric layer, and etching an opening through a back side surface of the second chip, the opening extending through the second wafer and extending into the second dielectric layer to the bonding pad for electrical connection thereto.

[0009] The details of one or more implementations are set forth in the accompanying drawings and the description that follows. Other features will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram of a die stack with arc protection.

[0011] Figure 2 yes Figure 1 00140] Figure 2 is a top view of an exemplary implementation of a chip stack.

[0012] Figure 3 Shows Figure 1 and Figure 2 A first cross section of a first exemplary implementation of a chip stack.

[0013] Figure 4 Shows Figure 1 and Figure 2 A second cross-section of the first exemplary implementation of a chip stack.

[0014] Figure 5A Shown for manufacturing Figure 1 A first exemplary operation of a second exemplary implementation of a chip stack.

[0015] Figure 5B Shown for manufacturing Figure 5A A second exemplary operation of a second exemplary implementation of a chip stack.

[0016] Figure 5C Shown for manufacturing Figure 5A and Figure 5B A third exemplary operation of the second exemplary implementation of the chip stack.

[0017] Figure 5D Shown for manufacturing FIG. 5A to FIG. 5C A fourth exemplary operation of the second exemplary implementation of the chip stack.

[0018] Fig. 6A Shown for manufacturing Figure 1 The first exemplary operation of the third exemplary implementation of the chip stack.

[0019] Figure 6B Shown for manufacturing Fig. 6A A second exemplary operation of a third exemplary implementation of chip stacking.

[0020] Figure 6C Shown for manufacturing Fig. 6A and Figure 6B A third exemplary operation of a third exemplary implementation of chip stacking.

[0021] Fig.6D Shown for manufacturing FIG. 6A to FIG. 6C A fourth exemplary operation of the third exemplary implementation of the chip stack.

[0022] Figure 7 Shows Figure 1 A fourth exemplary implementation of a chip stack.

[0023] Figure 8 is shown for manufacturing Figure 1 A flow chart of an exemplary operation of chip stacking. DETAILED DESCRIPTION

[0024] Conventional chip stacking is subject to electrostatic discharge events such as may occur during various manufacturing processes, including plasma etching or plasma deposition. Such electrostatic discharge events may result in damage to components of the chip stack, and associated loss of time and resources.

[0025] For example, as described above, a chip stack typically includes a top dielectric of a top wafer bonded to a bottom dielectric of a bottom wafer. For example, a top oxide may be bonded to a bottom oxide. As an insulating material, such a dielectric may not provide an adequate discharge path for electrostatic discharge.

[0026] Additional doping of the top wafer may be provided to facilitate electrostatic discharge. However, such additional doping may need to be added during front-side processing of the top chip and prior to bonding the top chip to the bottom chip to avoid damage to components of the active circuitry, for example, during subsequent activation of such doping. Therefore, it may be difficult or impossible to add sufficient doping near the back side (top) of the top chip, where doping is most beneficial for facilitating electrostatic discharge.

[0027] An electrostatic discharge path may also be provided that passes through metal contact layers and / or other conductive elements associated with the active circuitry of the chip stack and via one or more Cu hybrid bonds between the bottom dielectric layer and the top dielectric layer. However, the layout of such metal elements and the available wafer area may be determined by the size, function, and connections of the active circuitry and may not be optimal for electrostatic discharge purposes (e.g., a sufficiently straight path to ground may not be provided). Furthermore, even where present, the efficacy of such an electrostatic discharge path may be limited by the ability of the top wafer to facilitate a path to ground, as described above.

[0028] The chip stack may include a die seal structure or die seal designed to prevent moisture from entering from outside the chip stack. For example, a conventional chip stack may be susceptible to failure or malfunction due to moisture ingress. Specifically, moisture may diffuse into the chip stack and cause corrosion of the bonds at the bond wires where the top chip is joined to the bottom chip.

[0029] To reduce moisture ingress, the die seal may include a connected die seal layer in each of the bottom dielectric and the top dielectric.Such a die seal structure may extend around the periphery of the chip stack to minimize moisture intrusion and associated damage to the chip stack.

[0030] The technology defines an electrostatic discharge path that includes a die seal structure with discrete or non-continuous hybrid bonds. This electrostatic discharge path can be defined as providing a straight and effective ground path regardless of where charge accumulation occurs within the chip stack. In addition, the technology ensures reliable bonding between the top dielectric layer and the bottom dielectric layer while still providing the above-mentioned type of moisture protection. In addition, because the die seal structure is located at the periphery of the chip stack, the die seal structure does not interfere with or disrupt the operation of any active circuit of the chip stack.

[0031] In some implementations, the die seal structure can be connected to a metal element associated with or located near an active circuit, such as a light shield. For example, a die seal layer of the die seal structure can be connected to the light shield. Thus, charge accumulation associated with such a metal element (e.g., a light shield) can also be effectively discharged using the die seal structure.

[0032] Furthermore, additional processing of the top wafer may be performed to enhance the operation of the electrostatic discharge path. For example, additional doping of the top wafer described above may be provided. Additionally or alternatively, trenches may be added within the top wafer, wherein such trenches and associated trench doping and / or trench filling materials may facilitate the desired electrostatic discharge.

[0033] Figure 1 is a block diagram of a chip stack 100 with arc protection. It should be understood that Figure 1 as well as Figures 2 to 7 1 is a simplified example intended to illustrate and explain various aspects described with respect to the chip stack 100. For the purpose of clarity and brevity, Figure 1 Many aspects, features, and components of the chip stack 100 and its variations are omitted. Figure 1 and Figures 2 to 7 None of the figures should be construed as necessarily being drawn to scale.

[0034] As mentioned above and as Figure 1 As shown, the chip stack 100 includes a first chip 102, which may also be referred to as a main chip or a bottom chip. The first chip 102 may represent, for example, an ASIC chip, an image sensor processor (ISP) chip, an integrated passive chip (IPC), or any digital processing chip.

[0035] The second chip 104 may be disposed on the first chip 102. For example, the second chip 104 may include an optical sensor chip, including, for example, an image sensor chip such as a complementary metal oxide semiconductor (CMOS) chip.

[0036] As shown, the front side surface 106 of the first (bottom) chip 102 is Figure 1 The upper surface is shown in FIG. 1 , which may face the front side surface 107 of the second (top) chip 104. The back side surface 108 of the second chip 104 is Figure 1 104 is shown facing in an upward direction, which may be away from the first chip 102 and opposite the front side surface 106. Thus, the second chip 104 is located above the first chip 102 along the y-direction and joined (eg, bonded) to the first chip 102 along the xz plane to define bonding wires 110.

[0037] As further shown, the first chip 102 includes a first wafer 112 and a first dielectric layer 114. Similarly, the second chip 104 includes a second wafer 116 and a second dielectric layer 118. For example, the first wafer 112 and the second wafer 116 can be formed using silicon (Si). The dielectric layers 114, 118 can each include multiple dielectric layers, as shown in various examples below. For example, such dielectric layers can include various types of silicon nitride (SiN) or silicon dioxide (SiO2).

[0038] The first chip 102 and the second chip 104 may have various types of circuits formed therein. Such circuits may be formed in or on any of the first wafer 112, the first dielectric layer 114, the second wafer 116, and / or the second dielectric layer 118. For example, when the second chip 104 includes an image sensor chip, the image sensor provided may include a pixel array for generating a color image by forming a color filter array (CFA) and associated microlenses on the pixel array. For example, a complementary metal oxide semiconductor (CMOS) image sensor may include or utilize a photodiode, related circuits, dielectric layers, and metal interconnects, all of which are formed on a substrate to provide an image sensor chip. The second chip 104 may include any type of image sensor chip, and the first chip 102 may include any circuit chip configured to operate and / or receive the output of such an image sensor chip. Additional or alternative details and examples of these and related image sensor circuits are provided below.

[0039] Figure 1 The chip stack 100 in FIG. 1 is depicted as being positioned on a mounting carrier 120, which may occur during the manufacturing process of the chip stack 100. In addition to providing mechanical support for the chip stack 100, the mounting carrier 120 also provides electrical grounding, which can be used to prevent damage from arcing events caused by the discharge of charge accumulation.

[0040] For example, in Figure 1 1, the etched opening 122 provides access to a metal (e.g., aluminum) bonding pad 124. The walls of the opening are covered with a passivation material 125. The etched opening 122 can provide access to the bonding pad 124 for providing an electrical connection, such as a connection to an external circuit. For example, in a subsequent operation, the chip stack 100 can be removed from the mounting carrier and attached to a substrate supporting an external circuit, which can be attached to the bonding pad 124 using the opening 122.

[0041] During etching of the opening 122, such as during plasma etching, charge accumulation may occur at various metal elements when an electric field is present for etching. As described above, conventional chip stacks fail to provide a sufficient discharge path for such charge accumulation to the ground potential of the mounting carrier 120, so that arcing events may occur, resulting in damage to the second wafer 116 or other elements of the chip stack 100.

[0042] For example, various active circuits 126 may be positioned in or on the backside surface of the second wafer 116, such as a color filter array and a microlens array. The active circuits 126 may include or utilize a light shield 128, including a metal light shield, such as a tungsten (W) light shield. More generally, various anti-reflective materials and materials that facilitate image sensing operations may be used. Figure 1 Other elements not shown in the simplified example of FIG. 1 , such as trench isolation structures for electrical and / or optical isolation purposes, and metal layers for connecting active circuit 126 to first chip 102 . In addition, other dielectric materials may be included on backside surface 108 , which are not shown for simplicity. Figure 1 Not shown in FIG.

[0043] because Figure 1 In the example of FIG. 1 , the light shield 128 is made of metal, so charge accumulation of the type described above can occur in the light shield 128. A ground contact 130 connecting the light shield 128 to the second wafer 116 can be included, wherein the ground contact 130 can be intended to facilitate electrostatic discharge to the ground potential of the mounting carrier 120. The ground contact 130 can be positioned through the intervening dielectric ( Figure 1 The ground contact 130 is sometimes referred to as a "light shielding ground contact".

[0044] As described above, the second wafer 116, the second dielectric layer 118, the first dielectric layer 114, and the intermediate portion of the first wafer 112, and any metal elements or layers included therein, may be insufficient or suboptimal with respect to providing a ground connection to the mounting carrier 120. In addition, there may be other metal layers or metal elements as the die seal layer 132, including, for example Figure 1 Therefore, charge accumulation may also occur at such additional metal elements, which may also lead to arc damage, for example, during plasma etching of opening 122.

[0045] To prevent this arc damage, Figure 1The chip stack 100 includes an electrostatic discharge path 135 that provides an appropriate path to the ground potential of the mounting carrier 120. For example, the electrostatic discharge path 135 includes a first die seal 136 in the first dielectric layer 114, a second die seal 138 in the second dielectric layer 118, and a hybrid bond 140 connecting the first die seal 136 and the second die seal 138 at the bond wire 110.

[0046] The hybrid bond 140 and other hybrid bonds described herein generally enable electrical connections to be formed and form a mechanically stable structure between the two wafers 112, 116. In some implementations, the hybrid bond pads of the hybrid bond 140 can be metal, such as copper, nickel, gold, or other suitable metals known in the art. In other implementations, the hybrid bond pads can be made of other non-metallic conductive materials. The hybrid bond can also be referred to as a direct bond interconnect (DBI).

[0047] The hybrid bonding portion 140 is Figure 1 , and may not be present in other cross-sections of the chip stack 100. In other words, the hybrid bonding portions 140 may represent discrete or non-continuous hybrid bonding portions that may be positioned at desired intervals below the die encapsulation layer 132. Thus, a sufficient number of hybrid bonding portions 140 may be included to facilitate a desired electrostatic discharge level while still utilizing oxide-oxide bonding between the first dielectric layer 114 and the second dielectric layer 118 at the bond wires 110 to provide safe and reliable formation of the chip stack 100 while also avoiding bonding voids.

[0048] The electrostatic discharge path 135 may include various other elements and aspects that facilitate adequate electrostatic discharge through the second wafer 116, the second dielectric layer 118, the first dielectric layer 114, and the first wafer 112. In particular, the second wafer 116 itself may not provide a sufficient or desired level of conductivity between the die seal layer 132 and the second die seal 138 for electrostatic discharge potential levels. Figure 1 In the embodiment, one or more elements may be added to the second wafer 116 below the die seal layer 132 to promote this desired level of conductivity between the die seal layer 132 and the second die seal 138 (and thereby promote the desired level of conductivity with the hybrid bond 140 and the first die seal 136).

[0049] For example, the ground contact 142 can connect the die encapsulation layer 132 to the second wafer 116. Similar to the ground contact 130, the ground contact 142 can be positioned through the intervening dielectric ( Figure 1 In the through hole formed by (not explicitly shown in the simplified example).

[0050] A deep trench 146 may be provided extending from the backside surface 108 toward the second dielectric layer 118. As described in more detail below, the deep trench 146 may be filled with an insulating material and the outer perimeter of the deep trench may be provided with a doping layer to enhance conductivity of electrostatic discharge from the die encapsulation layer 132 along the electrostatic discharge path 135.

[0051] In other exemplary implementations, in addition to or in lieu of the deep trench 146, a conductive deep trench extending from the backside surface 108 toward the second dielectric layer 118 may be included. Figure 1 As shown, the conductive deep trench 147 may extend from the ground contact 142 to the second die seal 138. More specifically, the conductive deep trench may be filled with a conductive material, such as metal or polysilicon, to enhance conduction between the ground contact 142 and the second die seal 138.

[0052] exist Figure 1 In the example of , the conductive deep trench 147 can be connected to the doped layer 148 of the second die seal 138. For example, the doped layer 148 can be provided with additional doping to facilitate conduction along the electrostatic discharge path 135. A similar doped layer 149 can be provided as part of the first die seal 136 and located near the boundary of the first dielectric layer 114 and the first wafer 112.

[0053] exist Figure 1 In the simplified example of FIG, deep trench 146 and conductive deep trench 147 are shown, where deep trench 146 is positioned laterally away from ground contact 142. However, in other examples, the conductive deep trench may be omitted, in which case deep trench 146 may be positioned to contact ground contact 142. Additionally, in such implementations, two or more deep trenches (similar to deep trench 146) may be included, where at least one of the deep trenches may be in contact with ground contact 142. In other examples, deep trench 146 may be omitted, and conductive deep trench 147 may be included, or both deep trench 146 and conductive deep trench 147 may be omitted.

[0054] exist Figure 1 In the final example of FIG. 1 , a shield connector 150 may be added to electrically connect the light shield 128 and the die seal layer 132 . The shield connector 150 may be provided at Figure 1 is shown as a dotted line to indicate that the shielding connector 150 is Figure 1 The light shield 128 is not visible in the cross section of FIG. 1 , but is positioned to connect the light shield 128 and the die encapsulation layer 132 outside the perimeter of the opening 122 .

[0055] Figure 2 Shows Figure 1 A partial top view of an exemplary implementation of a chip stack 100 is shown. Figure 2In the example of FIG. 1 , the die encapsulation layer 132 and the light shield 128 are shown as well as the opening 122 . The shield connector 150 is shown to include a first shield connector 150 a located on a first side of the opening 122 and a second shield connector 150 b located on a second side of the opening 122 .

[0056] Figure 2 FIG. 1 shows that the die seal layer 132 may be located at the edge or perimeter of the chip stack 100 . Figure 2 In the specific example of FIG. 1 , a portion of the die encapsulation layer 132 is shown near a corner of the chip stack 100 and includes an angled portion that is not directly connected to the light shield 128. In some implementations, the die encapsulation layer 132 can be used for alignment purposes, such as when dicing the chip stack 100. Thus, more generally, the die encapsulation layer 132 can be positioned relative to the chip stack 100 and connected to the light shield 128 using the shield connector 150 at any convenient or available location along the backside surface 108 of the chip stack 100.

[0057] Figure 3 Shown along Figure 2 The line A-A' intercepts Figure 1 and Figure 2 A first cross section of a first exemplary implementation of a chip stack. Figure 4 Shown along Figure 2 The line B-B' intercepts Figure 1 and Figure 2 A second cross-section of a first exemplary implementation of a chip stack. Figure 3 and Figure 4 and in Figures 5A-5D , Figures 6A-6D and Figure 7 The following examples include a number of common or similar elements, many of which correspond to or provide previously discussed Figure 1 and Figure 2 For clarity and consistency, such elements are numbered to correspond to Figure 1 The numbering scheme.

[0058] For example, in Figure 3 In the exemplary chip stack 300, the ASIC chip 302 provides Figure 1 The first chip 102 is an example of an ASIC wafer 312 that provides Figure 1 The first dielectric layer 314 provides an example of the first dielectric layer 114. As described above, and as Figure 3 As shown, the first dielectric layer 314 includes a variety of different dielectric materials / layers, which will not be described in further detail herein.

[0059] Further in Figure 3In the embodiment, the contact image sensor (CIS) chip 304 provides Figure 1 The second chip 104 of the embodiment of the present invention is provided as an example, and the CIS wafer 316 provides an example of the second wafer 116, and the second dielectric layer 318 provides an example of the second dielectric layer 118. As described with respect to the first dielectric layer 314, the second dielectric layer 318 includes a variety of different dielectric materials / layers. As described above and described in more detail below, the second dielectric layer 318 may include one or more oxide layers and one or more SiN layers 339 or other dielectric materials.

[0060] and Figure 1 The example is consistent with Figure 3 The chip stack 300 comprises a bonding wire 310 at which the first chip 302 and the CIS chip 304 are bonded. A bonding pad 324 is accessible by etching an opening 322. The opening 322 is lined with a passivation layer 325.

[0061] like Figure 3 As shown, the bond pad 324 extends beyond the opening 322 in a direction parallel to the bond wire 310. The sealing ring 331 is shown in cross-section and extends around the opening 322. The sealing ring 331 extends around the perimeter of the opening 322. For example, the sealing ring 331 can be formed using a suitable metal or other moisture resistant material such as tungsten, polysilicon, or a combination thereof.

[0062] As is typical in chip stacking devices, ASIC chip 302 may be connected to CIS chip 304 and configured to control various operations of the CIS chip. For example, ASIC wafer 312 may include various circuits (not shown), and dielectric layer 314 may include various connecting metal layers 333.

[0063] In addition, as shown in the figure, dielectric layers 314, 318 can be used to construct the desired bonding portion between ASIC wafer 312 and CIS wafer 316. Figure 3 Shown in FIG. 3 is a hybrid bond 354. Saw street 337 refers to a portion of the illustrated chip stack used to perform sawing or dicing activities.

[0064] Various active circuits 326 may be positioned in or on the backside surface of the CIS wafer 316. For example, a color filter array and a microlens array may be included. The active circuits 326 may include or utilize a tungsten shield 328 (as a Figure 1 The example of the light shield 128 of the embodiment of the present invention is shown in Figure 1 and / or various other light shields and / or anti-reflective materials for facilitating image sensing operations, and trench isolation structures 353 for electrical and / or optical isolation purposes. The metal layer 355 can be used to connect the active circuit 326 to the hybrid bonding portion 354 and thus to the ASIC chip 302.

[0065] Further in Figure 3 and as relative to Figure 1 As described, because the light shield 328 is made of metal, charge accumulation of the type described above may occur in the light shield 328. A ground contact 330 may be included to connect the light shield 328 to the second wafer 316. In some implementations, a connection between the light shield 328 and the second wafer 316 may be formed using a via formed through the intervening dielectric 343 and the doped layer 344.

[0066] Thus, as shown, an electrostatic discharge path 352 exists through the second wafer 316, the second dielectric layer 318, the first dielectric layer 314, and the intermediate portion of the first wafer 312, and the included metal layer 355, the hybrid bonding portion 354, and the metal layer 333. In addition, other metal layers or metal elements, such as the die encapsulation layer 132, may experience charge accumulation. Therefore, it may be advantageous to provide an additional or alternative discharge path to provide a ground connection.

[0067] For example, Figure 3 The chip stack includes an additional electrostatic discharge path 351 that provides an appropriate ground path. For example, the electrostatic discharge path 351 includes a first die seal 336 in the first dielectric layer 314, a second die seal 338 in the second dielectric layer 318, and a hybrid bond 340 connecting the first die seal 336 and the second die seal 338 at the bonding wire 310.

[0068] The hybrid bonding portion 340 is Figure 3 The cross section of the example is shown in FIG. Figure 1 As described, the hybrid bonds may not exist in other cross sections of the chip stack 300 , for example, may represent discrete or non-continuous hybrid bonds located below the die encapsulation layer 332 at desired intervals.

[0069] The electrostatic discharge path 351 may include a conductive path that facilitates sufficient electrostatic discharge and is relatively Figure 1 135. For example, a ground contact 342 can connect the die seal layer 332 to the second wafer 316. Similar to the ground contact 330, the ground contact 342 can be located within a via formed through the intervening dielectric 343 and the doped layer 344. In addition, the doped layer 348 can be provided with additional doping to facilitate conduction along the electrostatic discharge path 351. A similar doped layer 349 can be provided as part of the first die seal 336 and located near the boundary of the first dielectric layer 314 and the first wafer 312.

[0070] Further in Figure 3 , a shielding connector 350 is shown, which corresponds to Figure 1Shielded connecting piece 150. Figure 4 exemplified in Figure 2 The cross section BB' of FIG. 1 shows that a shield connector 350 can be added to electrically connect the light shield 128 and the die encapsulation layer 132. Specifically, Figure 4 A shield connector 450 is shown as a metal element or metal portion between the light shield 328 and the die encapsulation layer 332 .

[0071] FIG. 5A to FIG. 5D Shown for manufacturing Figure 1 The exemplary operation of the second exemplary implementation of the chip stack is as follows. Figure 5A In FIG. 5 , ASIC wafer 512 has a first dielectric layer 514 formed thereon, in which a metal layer 533 is formed. Sensor wafer 516 has a second dielectric layer 518 formed thereon, including a SiN layer 539 . Figure 5A The sensor wafer 516 in includes a bulk portion 500 .

[0072] Bond pads 524 are formed in one of the second dielectric layers 514. Active circuits 526 are formed in wafer 516 and second dielectric layer 518, and seal ring 531 and second die seal 538 are formed in second dielectric layer 518. First die seal 536 is formed in dielectric layer 514. Doping layer 549 is formed in dielectric layer 514 and wafer 512.

[0073] like Figure 5A As shown in FIG. 5 , the sensor wafer 516 and the second dielectric layer 518 are flipped to be mounted on the first dielectric layer 514 so that the second dielectric layer 518 is located between the first dielectric layer 514 and the sensor wafer 516. Thus, the interconnects (eg, hybrid bonding portions) 540 and 554 can be bonded, as shown in FIG. Figure 5B , thereby defining a bond wire 510. A metal layer 555 may be included to connect the active circuit 526 to the hybrid bond 554, and thereby to the ASIC chip 502.

[0074] Figure 5A The sensor wafer 516 in the embodiment may be thinned by removing the bulk portion 500, for example to a range of 3 microns to 6 microns. Figure 5B For example, various known thinning techniques may be used, such as rough grinding, fine grinding, wet etching, and / or combinations thereof. In some examples, the ASIC wafer 512 may also be thinned (in FIG. 5A to FIG. 5D (not shown separately in the simplified process flow).

[0075] exist Figure 5C, a backside process is performed that includes forming a deep trench 546 that can be filled with an insulating material (e.g., silicon dioxide) and lined with a doped layer 547 (e.g., doped with boron). For example, the deep trench 546 can be formed simultaneously with the deep trench 560 (e.g., isolation trench) of the active circuit 526. Figure 1 As described above with deep trench 146 / electrostatic discharge path 135, deep trench 546 provides a doped layer 547 close to second die seal 538, thereby facilitating Figure 3 and Figure 4 The conductivity of the electrostatic discharge path 351 is improved (the resistance is reduced). Figure 5C As shown, deep trenches 546 may be formed during backside processing of sensor wafer 516 (as opposed to frontside processing which would need to be performed prior to bonding) in an efficient manner that does not damage active circuitry 526 or other elements of the chip stack.

[0076] A dielectric layer 543 (eg, silicon dioxide) may then be formed through which vias are opened to provide ground contacts 530 to the tungsten shield 528 and to provide ground contacts 542 to the die encapsulation layer 532 .

[0077] exist Figure 5D , the opening 522 may be etched to contact the bond pad 524 and lined with a passivation layer 525. As described herein, during the plasma etching of the opening 522, charge accumulation may occur on, for example, the tungsten shield 528 and the die seal layer 532. Discharging of such charge accumulation may be facilitated by contacting the ground contact 542, the second die seal layer 538, the hybrid bond 540, and the first die seal 536 through the trench 546. Similar to Figure 1 and Figure 2 Shielded connector 150 or Figure 3 and Figure 4 Shield connector 350 / 450 (in FIG. 5A to FIG. 5D 528 and the die seal layer 532), discharge can also be facilitated by means of a shield connection between the tungsten shield 528 and the tube core sealing layer 532.

[0078] FIG. 6A to FIG. 6D Shown for manufacturing Figure 1 The exemplary operation of the third exemplary implementation of the chip stack is as follows. Fig. 6A In FIG. 6 , the ASIC wafer 612 has a first dielectric layer 614 formed thereon, in which a metal layer 633 is formed. The sensor wafer 616 has a second dielectric layer 618 formed thereon, including a SiN layer 639 . Fig. 6A The sensor wafer 616 in includes a bulk portion 600 .

[0079] Bond pads 624 are formed in one of the second dielectric layers 614. Active circuits 626 are formed in wafer 616 and second dielectric layer 618, while seal ring 631 and second die seal 638 are formed in second dielectric layer 618. First die seal 636 is formed in dielectric layer 614.

[0080] like Fig. 6A As shown in FIG. 1 , the sensor wafer 616 and the second dielectric layer 618 are flipped to be mounted on the first dielectric layer 614 so that the second dielectric layer 618 is located between the first dielectric layer 614 and the sensor wafer 616. Thus, the interconnects (eg, hybrid bonding portions) 640 and 654 can be bonded, as shown in FIG. Figure 6B , thereby defining a bond wire 610. A metal layer 655 may be included to connect the active circuit 626 to the hybrid bond 654, and thereby to the ASIC chip 602.

[0081] Fig. 6A The sensor wafer 616 in the embodiment may be thinned by removing the bulk portion 600, for example to a range of 3 microns to 6 microns. Figure 6B As shown. The ASIC wafer 612 can also be thinned (in FIG. 6A to FIG. 6D (not shown separately in the simplified process flow).

[0082] exist Figure 6C , backside processing is performed, which includes forming a conductive trench 647, which can be filled with a conductive material 648 (e.g., polysilicon or metal) and lined with an insulating layer 649. For example, the conductive trench 647 can be formed simultaneously with the deep trench 660 (e.g., isolation trench) of the active circuit 626. Figure 1 As described above with conductive groove 147 / electrostatic discharge path 135, conductive groove 647 promotes Figure 3 and Figure 4 The conductivity of the electrostatic discharge path 351 is improved (the resistance is reduced). Figure 6C As shown, conductive trenches 647 may be formed during backside processing of sensor wafer 616 (as opposed to frontside processing which would need to be performed prior to bonding) in an efficient manner that does not damage active circuitry 626 or other elements of the chip stack.

[0083] A dielectric layer 643 (eg, silicon dioxide) may then be formed through which vias are opened to provide ground contacts 630 to the tungsten shield 628 and to provide ground contacts 642 to the die encapsulation layer 632 .

[0084] exist Fig.6D, the opening 622 may be etched to contact the bond pad 624 and lined with a passivation layer 625. As described herein, during the plasma etching of the opening 622, charge accumulation may occur on, for example, the tungsten shield 628 and the die seal layer 632. Discharging of such charge accumulation may be facilitated by contacting the ground contact 642, the second die seal 638, the hybrid bond 640, and the first die seal 636 through the conductive trench 647. Similar to Figure 1 and Figure 2 Shielded connector 150 or Figure 3 and Figure 4 Shield connector 350 / 450 (in FIG. 5A to FIG. 5D 628 and the die seal layer 632), discharge can also be facilitated by means of a shield connection between the tungsten shield 628 and the tube core sealing layer 632.

[0085] Figure 7 Shows Figure 1 A fourth exemplary implementation of a chip stack. Figure 7 In the example of FIG. 7 , saw streets 737 may be utilized for additional or alternative electrostatic discharge protection prior to the sawing operation.

[0086] For example, in Figure 7 , the die encapsulation layer 732 may extend to the saw street 737. Ground contacts 742a and 742b may be established through corresponding through holes. Similar to ground contacts 342, 542, 642, ground contact 742a may be formed in the chip, and ground contact 742b may be formed in the saw street 737, as shown. Ground contact 742b may sometimes be referred to as a "saw street ground contact".

[0087] The saw street 737 may include a doped layer 754 as part of a first saw street die seal 756, a hybrid bond 760 (sometimes referred to as a "saw street hybrid bond"), and a second saw street die seal 758 including a doped layer 755. Thus, using the techniques described herein, a saw street electrostatic discharge path 751 is established that provides arc protection prior to sawing the chip stack.

[0088] Figure 8 is shown for manufacturing Figure 1 A flowchart of an exemplary operation of chip stacking is shown. Figure 8 In the example of , a first chip can be formed, the first chip having a first wafer and a first dielectric layer disposed thereon (802). A second chip can be formed, the second chip having a second wafer and a second dielectric layer disposed thereon (804).

[0089] The second chip can be flipped over, and the front side surface of the second chip can be bonded to the first chip to define a bonding wire (806). Then, after thinning the second wafer, a circuit element can be formed on the back side surface of the second chip. The circuit element includes a discharge path element that forms at least a portion of a discharge path. The discharge path element may include one or more doped or conductive grooves, a light shield, a die seal layer, and / or a shielding connector located between the light shield and the die seal layer (808).

[0090] An opening may be etched through the backside surface of the second chip to expose the bonding pad (810). During etching, arcing caused by the presence of the plasma and associated electric field used for etching may be prevented by a discharge path formed by a discharge path element. For example, the discharge path may include the described die seal structure, the light shielding connector, the included hybrid bond portion, and any included groove structure.

[0091] External connections to the bond pads, such as wire bond connections, may be provided through the etched openings (812). Testing and dicing may be performed (814).

[0092] It should be understood that Figure 8 The simplified example of FIG. 1 shows an exemplary order of manufacturing operations, but the various operations may occur in a different order than shown and / or there may be more or fewer operations than shown. For example, depending on available testing and packaging options or preferences, dicing may occur before some or all testing operations.

[0093] The above specific implementations are for purposes of example, and the associated descriptions and terminology are non-limiting. For example, although the term chip is used herein with respect to the cut elements of a processed wafer, it should be understood that each such element may include and / or may be referred to as a die or semiconductor die. Thus, for example, in Figure 1 In the present invention, the first chip 102 may be referred to as a first die, and the second chip 104 may be referred to as a second die. Other suitable terms may also be used. In addition, although Figure 1 The simplified chip stack 100 includes only two chips 102 , 104 , but it should be understood that some implementations of the chip stack 100 may include three or more stacked chips.

[0094] Additionally, although the above examples are primarily described with respect to image sensors and associated circuitry, other active circuits may also be used. For example, Figure 1 The first chip 102 may be an integrated passive chip (IPC), and the second chip 104 may be a silicon photomultiplier (SiPM) chip.

[0095] A first exemplary implementation, referred to as Embodiment 1, includes a semiconductor device comprising:

[0096] A first chip, the first chip comprising a first wafer and a first dielectric layer disposed thereon;

[0097] a second chip including a second wafer and a second dielectric layer disposed thereon, the second chip being bonded to the first chip to define a bonding wire between the first dielectric layer and the second dielectric layer; and

[0098] An electrostatic discharge path includes a die seal layer on the second wafer, a die seal ground contact for the die seal layer, a first die seal in the first dielectric layer, a second die seal in the second dielectric layer, and a hybrid bond connecting the first die seal and the second die seal through the bonding wire.

[0099] Embodiment 2 includes the semiconductor device according to embodiment 1, further comprising:

[0100] Light shielding parts;

[0101] an opening through a surface of the second chip, the opening extending through the second wafer and into at least the second dielectric layer; and

[0102] A shielding connector electrically connects the light shield and the die encapsulation layer to include the light shield in the electrostatic discharge path.

[0103] Embodiment 3 includes the semiconductor device according to embodiment 1, further comprising:

[0104] A trench is formed in the second wafer of the second chip and extends in the direction of the second die seal.

[0105] Embodiment 4 includes the semiconductor device of embodiment 3, wherein the trench includes a doped layer.

[0106] Embodiment 5 includes the semiconductor device of embodiment 3, wherein the trench includes a conductive material in contact with the die seal ground contact and the second die seal.

[0107] Embodiment 6 includes the semiconductor device according to embodiment 1, further comprising:

[0108] A saw street electrostatic discharge path is formed in the saw street and includes a saw street grounding contact connected to the tube core sealing layer, a first saw street tube core seal located in the first dielectric layer, a second saw street tube core seal located in the second dielectric layer, and a saw street hybrid bonding portion connecting the first saw street tube core seal and the saw street second tube core seal through the bonding wire.

[0109] Embodiment 7 includes the semiconductor device of embodiment 1, wherein the first die encapsulant includes a first doped layer in the first wafer, and the second die encapsulant includes a second doped layer in the second wafer.

[0110] Embodiment 8 includes the semiconductor device according to embodiment 1, further comprising:

[0111] a color filter array (CFA) and a microlens array disposed on a surface of the second wafer opposite to the second dielectric layer;

[0112] a light shield disposed on the second wafer; and

[0113] A light shield ground contact is in contact with the second wafer.

[0114] Embodiment 9 includes the semiconductor device of embodiment 1, wherein the hybrid bond includes a copper-copper hybrid bond.

[0115] Embodiment 10 includes the semiconductor device of Embodiment 1, wherein the second chip includes an optical sensor circuit, and the first chip includes a circuit chip circuit configured to operate or receive an output of the optical sensor circuit.

[0116] An eleventh exemplary implementation referred to as Embodiment 11 includes a semiconductor device comprising:

[0117] A first chip, the first chip comprising a first wafer and a first dielectric layer disposed thereon;

[0118] a second chip, the second chip comprising a second wafer and a second dielectric layer disposed thereon, the second chip having a backside surface and a frontside surface opposite the backside surface, the second chip being bonded to the first chip at the frontside surface to define a bond line between the first dielectric layer and the second dielectric layer;

[0119] a die seal layer, the die seal layer being located on the backside surface;

[0120] a first die seal disposed in the first dielectric layer;

[0121] a second die seal disposed in the second dielectric layer;

[0122] a hybrid bond connecting the first die seal to the second die seal; and

[0123] A light shield is located on the backside surface and is electrically connected to the die encapsulation layer.

[0124] Embodiment 12 includes the semiconductor device according to embodiment 11, further comprising:

[0125] an opening that passes through the backside surface of the second chip and extends at least into the second dielectric layer; and

[0126] A shielding connector electrically connects the light shielding member and the die encapsulation layer.

[0127] Embodiment 13 includes the semiconductor device according to embodiment 11, further comprising:

[0128] A groove is formed in the backside surface of the second chip and extends in the direction of the second die seal.

[0129] Embodiment 14 includes the semiconductor device of embodiment 13, wherein the trench includes a doped layer.

[0130] Embodiment 15 includes the semiconductor device of embodiment 13, wherein the trench includes a conductive material in contact with the die encapsulation layer and the second die encapsulation.

[0131] Embodiment 16 includes the semiconductor device according to embodiment 11, further comprising:

[0132] a saw street ground contact connected to the die encapsulation layer;

[0133] a first saw street die seal located in the first dielectric layer;

[0134] a second saw street die seal located in the second dielectric layer; and

[0135] A saw street hybrid bonding portion connects the first saw street die seal and the second saw street die seal through the bonding wire.

[0136] Embodiment 17 includes the semiconductor device of embodiment 11, further comprising a die seal ground contact in contact with the second wafer.

[0137] An eighteenth exemplary implementation, referred to as Embodiment 18, includes a method of manufacturing a semiconductor device, the method comprising:

[0138] forming a first chip, the first chip comprising a first wafer and a first dielectric layer disposed thereon, the first chip comprising a first die seal;

[0139] forming a second chip, the second chip comprising a second wafer and a second dielectric layer disposed thereon, the second chip having a backside surface and a frontside surface opposite the backside surface, the second chip comprising a second die seal;

[0140] bonding the second chip to the first chip at the frontside surface to define a bond wire between the first dielectric layer and the second dielectric layer, the bond wire comprising a hybrid bond connecting the first die encapsulant and the second die encapsulant; and

[0141] A die seal layer is formed on the backside surface to define an electrostatic discharge path, the die seal layer having a die seal ground contact in contact with the second wafer, the electrostatic discharge path including the die seal layer, the die seal ground contact, the first die seal, the second die seal and the hybrid bonding portion.

[0142] Embodiment 19 includes the semiconductor device according to embodiment 18, further comprising:

[0143] forming a light shield on the backside surface of the second wafer;

[0144] electrically connecting the light shield to the die encapsulation layer so as to include the light shield in the electrostatic discharge path; and

[0145] An opening is formed through the backside surface of the second chip, the opening extending at least into the second dielectric layer.

[0146] Embodiment 20 includes the semiconductor device according to embodiment 18, further comprising:

[0147] A trench is formed in the backside surface of the second chip and extends in the direction of the second die encapsulant.

[0148] It should be understood that in the foregoing description, when an element such as a layer, region, substrate or part is mentioned as being on another element, connected to another element, electrically connected to another element, coupled to another element, or electrically coupled to another element, the element may be directly on another element, connected to or coupled to another element, or one or more intermediate elements may be present. On the contrary, when an element is mentioned as being directly on another element or layer, directly connected to another element or layer, or directly coupled to another element or layer, there is no intermediate element or layer. Although the term directly on, directly connected to, or directly coupled to may not be used in the entire specific embodiment, the element shown as being directly on an element, directly connected, or directly coupled can be mentioned in this manner. The claims of the present application (if any) may be revised to narrate the example relationships described in the specification or shown in the accompanying drawings.

[0149] As used in this specification and claims, singular forms may include plural forms unless the context clearly indicates a particular case. Spatially relative terms (e.g., above, above, above, below, below, below, below, etc.) are intended to cover different orientations of the device in use or operation, in addition to the orientations shown in the drawings. In some specific implementations, the relative terms above and below may include vertically above and vertically below, respectively. In some specific implementations, the term adjacent can include lateral adjacent or horizontal adjacent.

[0150] Some implementations may be implemented using various semiconductor processing and / or packaging technologies. Some implementations may be implemented using various types of semiconductor processing technologies associated with semiconductor substrates, including but not limited to, for example, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), etc.

[0151] Although certain features of the described implementations have been described as described herein, those skilled in the art will now appreciate that many modifications, alternatives, variations, and equivalents are contemplated. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the implementations. It should be understood that these modifications and variations are presented only by way of example and not limitation, and that various changes in form and detail may be made. In addition to mutually exclusive combinations, any portion of the apparatus and / or method described herein may be combined in any combination. The implementations described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different implementations described.

[0152] Although certain features of the described specific implementations have been illustrated as described herein, many modifications, substitutions, variations and equivalents will now occur to those skilled in the art. It should therefore be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the embodiments.

Claims

1. A semiconductor device, comprising: A first chip, the first chip comprising a first wafer and a first dielectric layer disposed thereon; a second chip, the second chip comprising a second wafer and a second dielectric layer disposed thereon, the second chip being bonded to the first chip to define a bonding line between the first dielectric layer and the second dielectric layer; and An electrostatic discharge path includes a die seal layer on the second wafer, a die seal ground contact for the die seal layer, a first die seal in the first dielectric layer, a second die seal in the second dielectric layer, and a hybrid bond connecting the first die seal and the second die seal through the bonding wire.

2. The semiconductor device according to claim 1, further comprising: Light shielding parts; an opening through a surface of the second chip, the opening extending through the second wafer and extending at least into the second dielectric layer; and A shielding connector electrically connects the light shield and the die encapsulation layer to include the light shield in the electrostatic discharge path.

3. The semiconductor device according to claim 1, further comprising: A trench is formed in the second wafer of the second chip and extends in a direction of the second die seal.

4. The semiconductor device according to claim 1, further comprising: A saw street electrostatic discharge path is formed in the saw street and includes a saw street grounding contact connected to the tube core sealing layer, a first saw street tube core seal located in the first dielectric layer, a second saw street tube core seal located in the second dielectric layer, and a saw street hybrid bonding portion connecting the first saw street tube core seal and the saw street second tube core seal through the bonding wire.

5. A semiconductor device, comprising: A first chip, the first chip comprising a first wafer and a first dielectric layer disposed thereon; a second chip, the second chip comprising a second wafer and a second dielectric layer disposed thereon, the second chip having a backside surface and a frontside surface opposite to the backside surface, the second chip being bonded to the first chip at the frontside surface to define a bonding wire between the first dielectric layer and the second dielectric layer; a die seal layer, the die seal layer being located on the backside surface; a first die seal disposed in the first dielectric layer; a second die seal disposed in the second dielectric layer; a hybrid bond connecting the first die seal to the second die seal; and A light shield is located on the backside surface and is electrically connected to the die encapsulation layer.

6. The semiconductor device according to claim 5, further comprising: an opening that passes through the backside surface of the second chip and extends at least into the second dielectric layer; and A shielding connector electrically connects the light shielding member and the die encapsulation layer.

7. The semiconductor device according to claim 5, further comprising: A groove is formed in the backside surface of the second chip and extends in the direction of the second die seal. 8 . The semiconductor device of claim 5 , further comprising a die seal ground contact in contact with the second wafer.

9. A method for manufacturing a semiconductor device, the method comprising: forming a first chip, the first chip comprising a first wafer and a first dielectric layer disposed thereon, the first chip comprising a first die seal; forming a second chip, the second chip comprising a second wafer and a second dielectric layer disposed thereon, the second chip having a backside surface and a frontside surface opposite the backside surface, the second chip comprising a second die seal; bonding the second chip to the first chip at the frontside surface to define a bond wire between the first dielectric layer and the second dielectric layer, the bond wire comprising a hybrid bond connecting the first die encapsulant and the second die encapsulant; as well as A die seal layer is formed on the backside surface to define an electrostatic discharge path, the die seal layer having a die seal ground contact in contact with the second wafer, the electrostatic discharge path including the die seal layer, the die seal ground contact, the first die seal, the second die seal and the hybrid bonding portion.

10. The method according to claim 9, further comprising: forming a light shield on the backside surface of the second wafer; electrically connecting the light shield to the die encapsulation layer so as to include the light shield in the electrostatic discharge path; as well as An opening is formed through the backside surface of the second chip, the opening extending at least into the second dielectric layer.

11. The method according to claim 9, further comprising: A groove is formed in the backside surface of the second chip, and the groove extends in the direction of the second die seal.

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