Display device and method for manufacturing display device

Abstract

A display device and a method for manufacturing the same are provided, the display device including: a main display area, and first and second sub-display areas surrounded by the main display area and positioned adjacent to each other; a plurality of pixel electrodes in the main display area and spaced apart from each other; a plurality of first sub-pixel electrodes in the first sub-display area and spaced apart from each other; a plurality of first replica pixel electrodes in the first sub-display area and connected to the plurality of first sub-pixel electrodes via a first bridge electrode; a first pixel defining layer in the main display area and the first sub-display area, and having a plurality of openings therein overlapping the plurality of pixel electrodes, the plurality of first sub-pixel electrodes, and the plurality of first replica pixel electrodes; and a plurality of second sub-pixel electrodes and a plurality of second replica pixel electrodes in the second sub-display area and spaced apart from each other.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0138663 filed in the Korean Intellectual Property Office on October 17, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The disclosure relates to a display device and a method for manufacturing the display device. Background Art

[0003] With the progress of the information society, higher and higher requirements are put forward for display devices for displaying images in various ways. For example, display devices are used in various electronic devices (such as smart phones, digital cameras, laptop computers, navigation devices and / or smart TVs). The display device can be a flat panel display device (such as a liquid crystal display device, a field emission display device and an organic light emitting display device). Among the flat panel display devices, in the light emitting display device, because each of the pixels of the display panel includes a light emitting element capable of emitting light by itself, it is possible to display an image without a backlight unit that provides light to the display panel.

[0004] The display device may further include pixels emitting predetermined light, scan lines, data lines, and power lines for driving the pixels, a scan driver outputting scan signals to the scan lines, and a display driver outputting data voltages to the data lines. Summary of the invention

[0005] Aspects and features of embodiments of the present disclosure provide a display device in which electrodes and pixel defining layers disposed in different adjacent display areas have different structures.

[0006] Aspects and features of embodiments of the present disclosure also provide a display device and a method for manufacturing the display device, wherein the display device includes pixels in which electrodes and pixel defining layers have different structures and can ensure transmittance due to the arrangement of pixels.

[0007] However, the aspects and features of the embodiments of the present disclosure are not limited to the aspects and features set forth herein. The above and other aspects and features of the embodiments of the present disclosure will become more apparent to those skilled in the art by referring to the detailed description of the present disclosure given below.

[0008] According to one or more embodiments of the present disclosure, a display device includes: a main display area and a first sub-display area and a second sub-display area, the first sub-display area and the second sub-display area being surrounded by the main display area and positioned adjacent to each other; a plurality of pixel electrodes located in the main display area and spaced apart from each other; a plurality of first sub-pixel electrodes located in the first sub-display area and spaced apart from each other; a plurality of first replica pixel electrodes located in the first sub-display area and connected to the plurality of first sub-pixel electrodes via a first bridging electrode; a first pixel defining layer located in the main display area and the first sub-display area and having a plurality of openings therein respectively overlapping with the plurality of pixel electrodes, the plurality of first sub-pixel electrodes and the plurality of first replica pixel electrodes ; a plurality of second sub-pixel electrodes and a plurality of second replica pixel electrodes, which are located in the second sub-display area and are spaced apart from each other; a plurality of connection patterns, which are located in the second sub-display area and are each connected to one of the plurality of second sub-pixel electrodes and one of the plurality of second replica pixel electrodes; and a second pixel defining layer, which is located on the plurality of connection patterns and has a plurality of openings therein, which are respectively overlapped with the plurality of second sub-pixel electrodes and the plurality of second replica pixel electrodes, wherein the second pixel defining layer includes valleys around a second sub-pixel electrode among the plurality of second sub-pixel electrodes and a second replica pixel electrode among the plurality of second replica pixel electrodes, and the second sub-pixel electrode and the second replica pixel electrode are connected to each other via a connection pattern among the plurality of connection patterns.

[0009] The connection pattern may be recessed inwardly from a sidewall of the valley and an opening among the plurality of openings of the second pixel defining layer.

[0010] The plurality of connection patterns may be separated from one another with respect to the valley portion of the second pixel defining layer.

[0011] The connection pattern may be in contact with a side surface of each of the second sub-pixel electrode and the second replica pixel electrode.

[0012] The connection pattern may contact a portion of a top surface of each of the second sub-pixel electrode and the second replica pixel electrode.

[0013] The display device may further include a common electrode located in the main display area, the first sub display area, and the second sub display area, wherein the common electrode may be located in a valley of the second pixel defining layer in the second sub display area.

[0014] The common electrode may not be in contact with the connection pattern.

[0015] The first pixel defining layer may include an organic insulating material, and the second pixel defining layer may include an inorganic insulating material.

[0016] The display device may further include a first bridge pattern extending from the first sub display area to the second sub display area and connected to one second sub pixel electrode among the plurality of second sub pixel electrodes.

[0017] The display device may further include: a second bridge pattern overlapping another second sub-pixel electrode of the plurality of second sub-pixel electrodes; and a third bridge pattern connected to the second bridge pattern and extending from the first sub-display area to the second sub-display area.

[0018] The display device may further include a plurality of interlayer insulating layers in the second sub-display area, wherein the first bridging pattern and the second bridging pattern may be located on an interlayer insulating layer among the plurality of interlayer insulating layers, and the interlayer insulating layer is different from another interlayer insulating layer among the plurality of interlayer insulating layers on which the third bridging pattern is positioned.

[0019] The display device may also include multiple first sub-pixel circuits and multiple second sub-pixel circuits, and the multiple first sub-pixel circuits and the multiple second sub-pixel circuits are located in the first sub-display area, wherein the multiple first sub-pixel electrodes can be overlapped with at least one of the multiple first sub-pixel circuits, at least some of the multiple first replica pixel electrodes are overlapped with at least one of the multiple second sub-pixel circuits, and the first bridging pattern can be electrically connected to one of the multiple second sub-pixel circuits.

[0020] The display device may also include: a first interlayer insulating layer located in the main display area, the first sub-display area, and the second sub-display area; and a first insulating layer located on the first interlayer insulating layer and located in the main display area and the first sub-display area, wherein the first insulating layer may include an organic insulating material, and the first interlayer insulating layer may include an inorganic insulating material.

[0021] The first insulating layer may not overlap the connection pattern, the second sub-pixel electrode, and the second replica pixel electrode.

[0022] The plurality of first sub-pixel electrodes, the plurality of first replica pixel electrodes, and the first bridge electrode located in the first sub-display area may be integrated into one body.

[0023] According to one or more embodiments of the present disclosure, a method for manufacturing a display device includes the following steps: preparing a substrate having a plurality of bridging patterns and an interlayer insulating layer located on the plurality of bridging patterns, and forming a plurality of sub-pixel electrodes and a plurality of replica pixel electrodes spaced apart from each other on the interlayer insulating layer; forming a connection pattern layer on the interlayer insulating layer and covering the plurality of sub-pixel electrodes and the plurality of replica pixel electrodes, and forming an inorganic insulating layer on the connection pattern layer; forming a photoresist including a plurality of openings on the inorganic insulating layer, some of the plurality of openings surrounding a pair of sub-pixel electrodes and the replica pixel electrodes without overlapping with the plurality of sub-pixel electrodes and the plurality of replica pixel electrodes, and other of the plurality of openings overlapping with at least one of the plurality of sub-pixel electrodes and the plurality of replica pixel electrodes; forming a pixel defining layer by etching the inorganic insulating layer along the openings of the photoresist, and etching the connection pattern layer along the openings formed in the pixel defining layer to partially expose the top surfaces of the sub-pixel electrodes and the replica pixel electrodes; and forming a light-emitting layer on each of the sub-pixel electrodes and the replica pixel electrodes, and forming a common electrode on the light-emitting layer and the pixel defining layer.

[0024] The pixel defining layer may include a valley formed by etching along an opening around a pair of sub-pixel electrodes and a replica pixel electrode among a plurality of openings, and in forming the connection pattern layer, the connection pattern layer may be etched along the valley to form a plurality of connection patterns separated from each other relative to the valley.

[0025] The connection pattern may be in contact with each of the pair of sub-pixel electrodes and the replica pixel electrode.

[0026] In forming the connection pattern layer, the connection pattern layer may be etched along the opening of the pixel defining layer, and the connection pattern may partially expose top surfaces of the sub-pixel electrode and the replica pixel electrode.

[0027] The connection pattern may be recessed inwardly from the sidewall of the valley and the opening of the pixel defining layer.

[0028] Because the organic insulating layer is not in the sub-display area where the optical device is located, the display device according to one or more embodiments can ensure sufficient light transmittance. The display device includes a pixel defining layer including an inorganic insulating material and a connection pattern structure that can be formed by different etching processes, so that a connection structure of different electrodes can be formed without an additional process.

[0029] However, the effects, aspects, and features according to the embodiments of the present disclosure are not limited to the effects, aspects, and features discussed above, and various other effects, aspects, and features are included herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of the embodiments of the present disclosure will become more apparent by describing in detail the embodiments of the present disclosure with reference to the accompanying drawings, in which: Figure 1 is a perspective view of a display device according to one or more embodiments; Figure 2 It is shown Figure 1 A plan view of a display device; Figure 3 It is along Figure 2 A cross-sectional view taken along line AA'; Figure 4 is a plan view showing a display panel according to one or more embodiments; Figure 5 is a pixel circuit diagram of a sub-pixel according to one or more embodiments; Figure 6 is a plan view showing pixel arrangement in a main display area and a sub display area of ​​a display device according to one or more embodiments; Figure 7 It is shown that the Figure 6 a plan view of an arrangement of pixel electrodes in primary pixels in a primary display area; Figure 8 It is shown that the Figure 6 a plan view of an arrangement of pixel electrodes in sub-pixels in a sub-display area; Fig. 9 is a cross-sectional view showing an example of a main display area of ​​a display device according to one or more embodiments; Fig.10 and Fig.11 is a cross-sectional view showing an example of a sub display area of ​​a display device according to one or more embodiments; Fig.12 is a cross-sectional view showing connection between a pixel electrode and a connection pattern provided in a second sub display area of ​​a display device according to one or more embodiments; Fig.13 It is specifically shown that the setting Fig.12 a cross-sectional view of a connection between a pixel electrode and a connection pattern in a second sub-display area; Figures 14 to 28 are diagrams sequentially illustrating a manufacturing process of a display device according to one or more embodiments; and Fig.29 is a diagram illustrating one pixel of a second sub display area of ​​a display device according to one or more embodiments. DETAILED DESCRIPTION

[0031] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. However, the present disclosure may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0032] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Throughout the specification, the same reference numerals refer to the same components.

[0033] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0034] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0035] Figure 1 is a perspective view of a display device according to one or more embodiments.

[0036] Reference Figure 1 The display device 10 is a device for displaying moving images and / or still images. The display device 10 can be used as a display screen of various devices such as a television, a laptop computer, a monitor, a billboard, and / or an Internet of Things (IOT) device, and a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, and an ultra mobile PC (UMPC).

[0037] The display device 10 may be a light-emitting display device (such as an organic light-emitting display including an organic light-emitting diode (OLED), a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including an inorganic semiconductor, or a micro-light-emitting display using a micro light-emitting diode (LED) or a nano light-emitting diode (LED). Hereinafter, an embodiment in which the display device 10 is an organic light-emitting display device is described, but the type of the display device 10 is not limited thereto.

[0038] In one or more embodiments, the display device 10 may be formed to be flat. For example, the display device 10 may be formed to be substantially flat on a plane defined by the first direction DR1 and the second direction DR2, and may have a suitable thickness (e.g., a predetermined thickness or height) in the third direction DR3. In another embodiment, the display device 10 may include a curved surface in at least a portion including an edge region, etc. In addition, the display device 10 may be formed to be flexible so that the display device 10 can be bent, curved, folded, and / or rolled.

[0039] In one or more embodiments, the first direction DR1 may be a length direction, a column direction, or a vertical direction, and the second direction DR2 may be a direction (e.g., a width direction, a row direction, or a horizontal direction) crossing (e.g., intersecting) the first direction DR1 with respect to the image display surface of the display device 10. The third direction DR3 may be a thickness direction or a height direction of the display device 10.

[0040] The display device 10 may include a display panel 100 , a driver 200 , and a circuit board 300 .

[0041] The display panel 100 may include a main area MA including a display area DA in which an image is displayed, and a sub area SBA located at one side of the main area MA.

[0042] The main area MA may include a display area DA and a non-display area NA around the display area DA along an edge or periphery of the display area DA (e.g., surrounding the display area DA). The display area DA may be located at the center of the main area MA and may occupy most of the area in the main area MA. The non-display area NA may be located at an edge of the main area MA and may contact the sub-area SBA.

[0043] The display area DA may be a region where pixels (eg, Figure 4 In one or more embodiments, the display area DA may also be provided with a sensing pattern (e.g., a touch electrode) for detecting a touch input, etc., and the display area DA may include a sensing area for detecting a touch input through the sensing pattern.

[0044] In one or more embodiments, the display area DA may include long sides in the first direction DR1 and short sides in the second direction DR2, and may be formed as a plane having a substantially rectangular shape. The corners at which the long sides and short sides of the display area DA meet may be rounded (rounded) or right-angled. The shape of the display area DA may be changed differently according to the embodiment. For example, the display area DA may be formed in a polygonal shape other than a quadrilateral shape, a circular shape, and / or an elliptical shape, etc.

[0045] The display area DA may include a main display area MDA and a sub display area SDA. The sub display area SDA may be an area where components for adding various functions to the electronic device are disposed, and the sub display area SDA may correspond to the component area.

[0046] The non-display area NA may be located immediately around the display area DA. The non-display area NA may surround the display area DA. An embedded circuit may be disposed in the non-display area NA. For example, an embedded circuit including a scan drive circuit and the like may be disposed in the non-display area NA located on one side (e.g., the left side or the right side) or both sides of the display area DA.

[0047] The sub-region SBA may be located at one side of the main region MA. For example, the sub-region SBA may be a region protruding from one side of the main region MA in the first direction DR1. For example, the sub-region SBA may protrude from the lower end of the main region MA in the first direction DR1. In one or more embodiments, the sub-region SBA may have a narrower width than the main region MA. For example, with respect to the second direction DR2, the sub-region SBA may have a narrower width than the main region MA.

[0048] Wiring and pads (also referred to as "pads" or "solder pads") may be provided in the sub-area SBA. For example, wiring and pads connected to pixels and / or embedded circuits located in the main area MA and connected to the driver 200 and / or the circuit board 300 located in the sub-area SBA may be provided in the sub-area SBA. When describing embodiments, the term "connection" may include electrical connection and / or physical connection.

[0049] In one or more embodiments, the driver 200 (eg, a display driving circuit) may be mounted in the sub-area SBA. The circuit board 300 may be disposed in a portion of the sub-area SBA.

[0050] The driver 200 may include a data driving circuit to drive the pixel. In one or more embodiments, the driver 200 may be formed as an integrated circuit chip (IC) and disposed in the sub-area SBA. In one or more embodiments, the driver 200 may be disposed on the circuit board 300 in the sub-area SBA, or may be disposed on another circuit board connected to the display panel 100 through the circuit board 300.

[0051] The circuit board 300 may be disposed in a portion of the sub-area SBA. For example, the circuit board 300 may be bonded to a pad located in a portion (e.g., a lower edge) of the sub-area SBA, and may supply or transmit a power voltage and a driving signal for driving the display panel 100 to the display panel 100. For example, the circuit board 300 may supply input image data (e.g., digital image data), a driving signal including a timing signal, and a driving voltage to the display panel 100. The circuit board 300 may be a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a flexible film such as a chip on film (COF), but is not limited thereto.

[0052] Figure 2 It is shown Figure 1 A plan view of a display device. Figure 3 It is along Figure 2 A cross-sectional view taken along line AA'.

[0053] Figure 1 The unfolded display device 10 is shown unbent, and Figure 2 and Figure 3 The display device 10 is shown curved in the sub-area SBA. Figure 1 A sub-area SBA is shown extending along an edge of the main area MA, and Figure 2 and Figure 3 A part of the sub-area SBA is shown in a bent state.

[0054] Reference Figure 2 and Figure 3 , the display panel 100 may include a substrate 110 including a main area MA and a sub-area SBA, and a circuit layer 120, a light emitting element layer 130, an encapsulation layer 140, a touch sensing layer TSU, and a color filter layer CFL sequentially disposed on the substrate 110. The circuit layer 120 may also be located in the main area MA and the sub-area SBA on the substrate 110. The light emitting element layer 130 and the encapsulation layer 140 may be located on a portion of the substrate 110 and the circuit layer 120. For example, the light emitting element layer 130 and the encapsulation layer 140 may be located in the main area MA.

[0055] In one or more embodiments, the display device 10 may further include additional elements disposed on the display panel 100. For example, the display device 10 may further include at least one of a polarizing layer and a protective layer (e.g., a window) disposed on the encapsulation layer 140. Each of the polarizing layer and the protective layer may be manufactured integrally with the display panel 100, or may be manufactured separately from the display panel 100 and attached to the display panel 100 by an adhesive layer or the like.

[0056] The substrate 110 may include an insulating material such as a polymer resin. For example, the substrate 110 may be made of polyimide or other insulating materials. The substrate 110 may be a flexible substrate that can be deformed (such as bent, folded and / or curled). Alternatively, the substrate 110 may include an insulating material such as glass.

[0057] The circuit layer 120 may include pixel circuits and wiring. For example, the circuit layer 120 may include circuit elements (e.g., pixel transistors and / or capacitors) constituting a pixel circuit for each pixel and wiring connected to the pixel. In one or more embodiments, the circuit layer 120 may also include circuit elements (such as a scan drive circuit) constituting an embedded circuit and wiring connected to the embedded circuit.

[0058] The light emitting element layer 130 may include a light emitting element disposed in an emission region of a pixel. For example, each of the pixels may include at least one light emitting element and a pixel circuit connected to the light emitting element. Each of the pixels may be located in a pixel region, the pixel region including an emission region in which a light emitting element is disposed and a pixel circuit region in which a pixel circuit is disposed. The emission region and the pixel circuit region of each pixel may overlap each other, but the present disclosure is not limited thereto.

[0059] When describing the embodiment, the circuit layer 120 and the light emitting element layer 130 are described separately, but the present disclosure is not limited thereto. For example, the circuit layer 120 and the light emitting element layer 130 may be integrated.

[0060] The encapsulation layer 140 may cover the light emitting element layer 130, and may extend to the non-display area NA to contact the circuit layer 120. In one or more embodiments, the encapsulation layer 140 may have a multilayer structure including at least two inorganic encapsulation layers stacked on each other and at least one organic encapsulation layer interposed between the inorganic encapsulation layers.

[0061] The touch sensing layer TSU may be disposed on the encapsulation layer 140. The touch sensing layer TSU may include a plurality of touch electrodes for capacitively sensing a user's touch and touch lines connecting the plurality of touch electrodes to the touch driver 400. For example, the touch sensing layer TSU may sense the user's touch by using a mutual capacitance method or a self capacitance method.

[0062] In one or more embodiments, the touch sensing layer TSU may be provided on a separate substrate provided on the display panel 100. In this case, the substrate supporting the touch sensing layer TSU may be a base member encapsulating the display panel 100.

[0063] A plurality of touch electrodes of the touch sensing layer TSU may be disposed in a touch sensor region overlapping the display area DA. A touch line of the touch sensing layer TSU may be disposed in a touch peripheral region overlapping the non-display area NA.

[0064] In one or more embodiments, the display device 10 may further include an optical device 500. The optical device 500 may be disposed in the sub-display area SDA. The optical device 500 may emit or receive light in infrared, ultraviolet, and / or visible light bands. For example, the optical device 500 may be an optical sensor (such as a proximity sensor, an illumination sensor, and a camera sensor) and / or an image sensor that detects light incident on the display device 10.

[0065] The color filter layer CFL may be disposed on the touch sensing layer TSU. The color filter layer CFL may include a plurality of color filters corresponding to the plurality of emission regions, respectively. Each of the color filters may selectively transmit light of a specific wavelength, and may block or absorb light of a different wavelength. The color filter layer CFL may absorb a portion of light from outside the display device 10 to reduce reflected light due to external light. Therefore, the color filter layer CFL may prevent or reduce color distortion caused by reflection of external light.

[0066] Since the color filter layer CFL is directly disposed on the touch sensing layer TSU, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display panel 100 may be relatively small.

[0067] In one or more embodiments, the display panel 100 may be bent in the bending area BA. The bending area BA may be a part of the sub area SBA and may be spaced apart from the main area MA.

[0068] The substrate 110 and the circuit layer 120 may be bent in the bending area BA corresponding to a partial section of the sub-area SBA. Therefore, a bezel area recognized as the non-display area NA by a user may be reduced or minimized.

[0069] Figure 4 is a plan view showing a display panel according to one or more embodiments. Figure 4 The display panel 100 is shown in an unbent and unfolded state.

[0070] Reference Figure 4 , the display panel 100 may include a main area MA and a sub area SBA. The main area MA may include a display area DA and a non-display area NA, and the sub area SBA may include a bank area BNKA, a driving circuit mounting area ICA, and a pad area PA.

[0071] The display area DA may be an area where a plurality of pixels PX are disposed. The pixels PX and wirings (or some of the wirings) connected to the pixels PX may be disposed in the display area DA.

[0072] The pixels PX may be disposed in the circuit layer 120 and the light emitting element layer 130 of the display panel 100. As an example, each pixel PX may include a pixel circuit (eg, Figure 5 The pixel circuit PCA / PXC) and the light emitting element (eg, Figure 5 light emitting element EL).

[0073] The pixel PX may include at least two color sub-pixels (eg, Figure 5 For example, the pixel PX may include a first color sub-pixel SPX1 emitting light of a first color (e.g., red light), a second color sub-pixel SPX2 emitting light of a second color (e.g., green light), and a third color sub-pixel SPX3 emitting light of a third color (e.g., blue light).

[0074] At least one first color sub-pixel SPX1, at least one second color sub-pixel SPX2, and at least one third color sub-pixel SPX3 adjacent to each other may constitute a unit pixel (also referred to herein as a "pixel") PX. For example, one first color sub-pixel SPX1, two second color sub-pixels SPX2, and one third color sub-pixel SPX3 adjacent to each other may constitute a unit pixel PX. Each unit pixel PX may emit light of various colors including white light by mixing the colors of light emitted from the sub-pixels SPX1, SPX2, and SPX3 constituting the unit pixel PX. In one or more embodiments, the first color sub-pixels SPX1 and the third color sub-pixels SPX3 may be alternately arranged along the first direction DR1 and / or the second direction DR2, and the second color sub-pixels SPX2 may be continuously and / or sequentially arranged along the first direction DR1. The type, shape, and / or arrangement structure of the sub-pixels SPX1, SPX2, and SPX3 may vary according to the embodiment. In addition, the type, number, ratio, and / or arrangement structure of the sub-pixels SPX1 , SPX2 , and SPX3 constituting each unit pixel PX may also be changed according to embodiments.

[0075] The encapsulation layer 140 may be disposed on the pixel PX. For example, the encapsulation layer 140 may be disposed at least in the display area DA to cover the pixel PX, and a portion of the encapsulation layer 140 may extend into the non-display area NA.

[0076] The wiring may be provided in the circuit layer 120 and may be located in the display area DA and the non-display area NA. In addition, the wiring may also be located in the sub-area SBA. For example, the wiring may extend from the sub-area SBA through the non-display area NA to the display area DA.

[0077] The non-display area NA may be located around the display area DA. For example, the non-display area NA may be an edge area of ​​the main area MA located outside the display area DA.

[0078] The non-display area NA may include a dam area DAMA spaced apart from the display area DA, a first non-display area NA1 between the display area DA and the dam area DAMA, and a second non-display area NA2 outside the dam area DAMA. The dam area DAMA may be an area in which a dam around the display area DA (e.g., surrounding the display area DA) is provided. The second non-display area NA2 may include an inorganic encapsulation area IEA (also referred to as a "bonding area") in which inorganic encapsulation layers of the encapsulation layer 140 are bonded to each other.

[0079] The sub-region SBA may include a bank region BNKA, a driving circuit mounting region ICA, and a pad region PA sequentially disposed on one side of the main region MA. Wiring (or portions of wiring), banks, and pads PD may be disposed in the sub-region SBA. At least some of the wirings may extend into the main region MA and may be connected to the pixels PX.

[0080] The bank area BNKA may be an area in which a bank including at least one organic layer is disposed. In one or more embodiments, the bank area BNKA may include a bending area BA. For example, the bank area BNKA may include a bending area BA spaced apart from the main area MA and a first edge area BEA1 and a second edge area BEA2 located on both sides of the bending area BA in the first direction DR1. The bank may be disposed in the bending area BA and a peripheral area thereof (e.g., the first edge area BEA1 and the second edge area BEA2 of the bank area BNKA) to cover wiring passing through the bending area BA. The display panel 100 may be bent in the bending area BA so that a portion of the sub-area SBA may be located behind the main area MA.

[0081] The driving circuit mounting area ICA may be an area in which the driver 200 is disposed. Pads for connecting at least some of the wirings to the driver 200 may be disposed in the driving circuit mounting area ICA. For example, input pads for connecting the driver 200 to specific pads (e.g., data input pads) of the pad area PA and output pads for connecting the driver 200 to the pixels PX may be disposed in the driving circuit mounting area ICA.

[0082] In one or more embodiments, the driver 200 may not be disposed on the display panel 100. In this case, the display panel 100 may not include the driving circuit mounting area ICA, and the wiring may be disposed only in an area between the bank area BNKA and the pad area PA.

[0083] The pad area PA may be an area where a pad PD for connecting the display panel 100 and / or the driver 200 to the circuit board 300, etc. is disposed. The circuit board 300 may be disposed or bonded in the pad area PA.

[0084] A plurality of pads PD including power pads and signal pads connected to the pixels PX, the driver 200, and / or the embedded circuit may be provided in the pad area PA. A power voltage for driving the pixels PX, the driver 200, and / or the embedded circuit, etc. may be supplied to the power pads. A driving signal and / or image data for driving the pixels PX, the driver 200, and / or the embedded circuit, etc. may be supplied to the signal pad (e.g., the pad PD). The type, position, arrangement order, and / or number of the pads PD may be variously changed according to the embodiment.

[0085] Figure 5 is a pixel circuit diagram of a sub-pixel according to one or more embodiments.

[0086] Reference Figure 5 , each pixel circuit PCA of the display device 10 according to one or more embodiments may include first to seventh transistors T1 to T7. The scan lines SL connected to the sub-pixel SPX may include first scan lines SL1, second scan lines SL2, third scan lines SL3, and fourth scan lines SL4, and the power lines PL connected to the sub-pixel SPX may include first pixel power lines VDL, second pixel power lines VSL, first initialization power lines VIL, and second initialization power lines VAIL. In addition, the pixel circuit PCA may also be connected to the emission control line ECL.

[0087] The sub-pixel SPX may include a light emitting unit EMU including at least one light emitting element EL and a pixel circuit PCA (also referred to as a “pixel driver”) connected to the light emitting unit EMU.

[0088] The light emitting element EL may be connected between the pixel circuit PCA and the second pixel power line VSL to which the second pixel power voltage ELVSS is applied. In one or more embodiments, the second pixel power voltage ELVSS may be a low potential pixel drive voltage. The light emitting element EL as the light source of the sub-pixel SPX may emit light in response to the drive current supplied from the pixel circuit PCA.

[0089] The light emitting element EL may be an organic light emitting diode (OLED), but is not limited thereto. For example, the light emitting element EL may be an inorganic light emitting element, a quantum dot light emitting element, or other types of light emitting elements.

[0090] The pixel circuit PCA can control the light emission timing and brightness of the light emitting element EL by controlling the driving current supplied to the light emitting element EL. The pixel circuit PCA may include at least one pixel transistor T and a capacitor Cst. In one or more embodiments, the pixel circuit PCA may include a pixel transistor T including a first transistor T1 to a seventh transistor T7.

[0091] The first transistor T1 may include a gate electrode connected to the first node N1, a first electrode electrically connected to the first pixel power line VDL through a fifth transistor T5, and a second electrode electrically connected to the light emitting unit EMU through a sixth transistor T6. One of the first electrode and the second electrode may be a source electrode, and the other may be a drain electrode. The first transistor T1 may control a source-drain current (hereinafter, referred to as a "driving current") flowing between the first electrode and the second electrode of the first transistor T1 according to a voltage applied to the gate electrode of the first transistor T1 (e.g., a voltage of the first node N1 corresponding to a voltage of a data signal). For example, the first transistor T1 may be a driving transistor of the sub-pixel SPX.

[0092] The second transistor T2 may include a gate electrode connected to the first scan line SL1, a first electrode connected to the data line DL, and a second electrode connected to the first electrode of the first transistor T1. The second transistor T2 may be turned on by a first scan signal supplied to the first scan line SL1 to electrically connect the first electrode of the first transistor T1 to the data line DL. When the second transistor T2 is turned on, a voltage of a data signal supplied to the data line DL may be applied to the first electrode of the first transistor T1.

[0093] The third transistor T3 may include a gate electrode connected to the second scan line SL2, a first electrode connected to the second electrode of the first transistor T1, and a second electrode connected to the gate electrode (or the first node N1) of the first transistor T1. The third transistor T3 may be turned on by a second scan signal supplied to the second scan line SL2 to electrically connect the gate electrode of the first transistor T1 to the second electrode of the first transistor T1. When the third transistor T3 is turned on, the first transistor T1 may be driven as a diode (e.g., the first transistor T1 may be diode-connected).

[0094] The fourth transistor T4 may include a gate electrode connected to the third scan line SL3, a first electrode connected to the gate electrode (or the first node N1) of the first transistor T1, and a second electrode connected to the first initialization power line VIL. The fourth transistor T4 may be turned on by a third scan signal supplied to the third scan line SL3 to electrically connect the gate electrode of the first transistor T1 to the first initialization power line VIL. When the fourth transistor T4 is turned on, a first initialization voltage VINT (e.g., a gate initialization voltage) of the first initialization power line VIL may be applied to the gate electrode of the first transistor T1.

[0095] The fifth transistor T5 may include a gate electrode connected to an emission control line ECL, a first electrode connected to a first pixel power line VDL, and a second electrode connected to a first electrode of the first transistor T1. The fifth transistor T5 may be turned on by an emission control signal supplied to the emission control line ECL, and thus the first electrode of the first transistor T1 may be electrically connected to the first pixel power line VDL to which the first pixel power voltage ELVDD is applied. When the fifth transistor T5 is turned on, the first pixel power voltage ELVDD may be applied to the first electrode of the first transistor T1. In one or more embodiments, the first pixel power voltage ELVDD may be a high potential pixel drive voltage.

[0096] The sixth transistor T6 may include a gate electrode connected to an emission control line ECL, a first electrode connected to a second electrode of the first transistor T1, and a second electrode connected to the light emitting element EL. The sixth transistor T6 may be turned on by an emission control signal supplied to the emission control line ECL to electrically connect the first transistor T1 to the light emitting element EL. When all of the fifth transistor T5 and the sixth transistor T6 are turned on, a driving current having a magnitude corresponding to a voltage of the gate electrode of the first transistor T1 may flow through the light emitting element EL.

[0097] The seventh transistor T7 may include a gate electrode connected to the fourth scan line SL4, a first electrode connected to the anode electrode of the light emitting element EL, and a second electrode connected to the second initialization power line VAIL. The seventh transistor T7 may be turned on by a fourth scan signal supplied to the fourth scan line SL4 to electrically connect the anode electrode of the light emitting element EL to the second initialization power line VAIL. The fourth scan signal may be the same signal as the first scan signal or a different signal. When the seventh transistor T7 is turned on, a second initialization voltage VAINT (e.g., an anode initialization voltage) of the second initialization power line VAIL may be applied to the anode electrode of the light emitting element EL.

[0098] The capacitor Cst may be connected between the gate electrode of the first transistor T1 and the first pixel power line VDL (eg, connected between the first node N1 and the first pixel power line VDL). The capacitor Cst may be charged with a voltage corresponding to a voltage of a data signal applied to the gate electrode of the first transistor T1 (eg, applied to the first node N1).

[0099] The active layer (e.g., semiconductor pattern including the channel region) of each of the pixel transistors T (e.g., the first transistor T1 to the seventh transistor T7) may include one semiconductor material among polysilicon, amorphous silicon, and an oxide semiconductor. In one or more embodiments, some of the pixel transistors T and others thereof may be formed by transistors of different conductivity types. In addition, some of the pixel transistors T and others thereof may include semiconductor materials of different types.

[0100] For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be formed by a P-type transistor (e.g., a P-type MOSFET) including a corresponding active layer formed of polysilicon, and the third transistor T3 and the fourth transistor T4 may be formed by an N-type transistor (e.g., an N-type MOSFET) including a corresponding active layer formed of an oxide semiconductor. In one or more embodiments, the transistor including the corresponding active layer formed of polysilicon and the transistor including the corresponding active layer formed of an oxide semiconductor may be disposed at different layers in the circuit layer 120.

[0101] Figure 6 is a plan view showing the arrangement of pixels in a main display area and a sub display area of ​​a display device according to one or more embodiments. Figure 6 An arrangement of pixels MDX and SDX in a sub display area SDA in a display area DA of the display device 10 and in a main display area MDA disposed around the sub display area SDA is shown.

[0102] Reference Figure 6 In the display device 10 according to one or more embodiments, the display area DA may include a main display area MDA and a sub display area SDA. As described above, the sub display area SDA may be an area where components are disposed under the substrate 110 of the display device 10. A plurality of main display pixels MDX may be arranged in the main display area MDA, and a plurality of sub display pixels SDX may be arranged in the sub display area SDA. The main display pixels MDX and the sub display pixels SDX may each include one or more emission areas EA, and the light emitting elements EL (see Fig. 9 and Fig.10 ) can be set in each emission area EA to emit light.

[0103] A plurality of light emitting elements EL that emit light and a pixel circuit PCA that is electrically connected to the light emitting elements EL and applies a signal for light emission of the light emitting elements EL may be disposed in the main display area MDA. The main display area MDA may be an area where the light emitting elements EL and the pixel circuit PCA are arranged in a specific arrangement. Each of the light emitting elements EL may form an emission area EA, and a plurality of emission areas EA may constitute one main display pixel MDX. For example, in the main display area MDA, four emission areas EA may constitute one main display pixel MDX, and each of the emission areas EA may correspond to the pixel circuit PCA of the sub-pixel SPX. Figure 4 As shown in FIG. 1 , one main display pixel MDX may include four sub-pixels SPX1 , SPX2 , and SPX3 , and may include four emission areas EA corresponding to the sub-pixels SPX1 , SPX2 , and SPX3 . The four emission areas EA may constitute one main display pixel MDX to express a white grayscale.

[0104] The light emitting element EL that emits light may also be disposed in the sub-display area SDA to form an emission area EA, and a plurality of emission areas EA may constitute one sub-display pixel SDX. However, unlike the main display area MDA, the sub-display area SDA may be an area overlapped with a component (e.g., an optical device 500) disposed on the rear surface of the substrate 110 of the display panel 100, and may have a structure in which the transmittance of light is considered. Therefore, the sub-display area SDA of the display area DA may include a first sub-display area SDA1 in which the emission area EA and the pixel circuit PCA are disposed, and a second sub-display area SDA2 in which the emission area EA is formed and the pixel circuit PCA is not disposed.

[0105] The first sub display area SDA1 may be disposed around the second sub display area SDA2. In one or more embodiments, the second sub display area SDA2 of the sub display area SDA may be disposed at the center, and the first sub display area SDA1 of the sub display area SDA may surround the second sub display area SDA2. However, the present disclosure is not limited thereto, and the first sub display area SDA1 may be disposed only on at least one side of the second sub display area SDA2.

[0106] The pixel circuit PCA (eg, Figure 7 The pixel circuits PXC1, PXC2, PXC3) may be disposed in the first sub display area SDA1 of the sub display area SDA. On the other hand, the pixel circuit PCA may not be disposed in the second sub display area SDA2.

[0107] The pixel circuit PCA electrically connected to the light emitting element EL provided in the sub display area SDA may be provided in the first sub display area SDA1. Some of the pixel circuits PCA provided in the first sub display area SDA1 may be electrically connected to the light emitting element EL provided in the first sub display area SDA1, and other of the pixel circuits PCA may be electrically connected to the light emitting element EL provided in the second sub display area SDA2. Since the pixel circuit PCA is not provided in the second sub display area SDA2, the second sub display area SDA2 of the display panel 100, which is an area overlapping the optical device 500, may have high transmittance. The second sub display area SDA2 provided with the emission area EA may emit light and have high transmittance so that the optical device 500 provided on the rear surface of the display panel 100 may receive light.

[0108] Unlike the main display area MDA, in the sub-display area SDA, one light emitting element EL and one pixel circuit PCA may not correspond to each other. For example, one pixel circuit PCA provided in the main display area MDA may be electrically connected to one light emitting element EL. In the main display area MDA, the pixel circuit PCA may be connected to one light emitting element EL or to a first pixel defining layer 131 (see FIG. 1 ) to be described later. Fig. 9 ). On the other hand, in the sub-display area SDA, the pixel circuit PCA disposed in the first sub-display area SDA1 may be electrically connected to the light-emitting elements EL disposed in the first sub-display area SDA1 and the second sub-display area SDA2. Therefore, the pixel circuit PCA disposed in the first sub-display area SDA1 may be connected to a plurality of light-emitting elements EL or to the light-emitting elements EL formed in the first pixel defining layer 131 (see FIG. 1 ) to be described later. Fig. 9 ) corresponds to the light-emitting elements EL at multiple openings.

[0109] The sub-display pixel SDX formed by the multiple emission areas EA of the sub-display area SDA may have an arrangement different from that of the main display pixel MDX. For example, the main display pixel MDX may include four emission areas EA, and the sub-display pixel SDX may include six emission areas EA. Each of the four emission areas EA of the main display pixel MDX may correspond to a pixel circuit PCA, and the main display pixel MDX may include four pixel circuits PCA. On the other hand, in the sub-display pixel SDX, two emission areas EA may form a pair to correspond to one pixel circuit PCA. That is, the sub-display pixel SDX may include six emission areas EA that emit light through three pixel circuits PCA. Therefore, the brightness and resolution of the sub-display area SDA may be different from those of the main display area MDA.

[0110] Hereinafter, the arrangement and structure of the pixels MDX and SDX in the main display area MDA and the sub display area SDA of the display device 10 will be described in detail with further reference to other drawings.

[0111] Figure 7 It is shown that the Figure 6 A plan view of the arrangement of pixel electrodes in primary pixels in a primary display area. Figure 8 It is shown that the Figure 6 A plan view of the arrangement of pixel electrodes in sub-pixels in a sub-display area.

[0112] Figure 7 The arrangement of pixel electrodes AE1 , AE2 , and AE3 and pixel circuits PXC1 , PXC2 , and PXC3 of four main display pixels MDX is shown. Figure 8 The arrangement of a sub-display pixel SDX1 of the first sub-display area SDA1, sub-pixel electrodes SAE1, SAE2 and SAE3 of the sub-display pixel SDX1, sub-pixel electrodes SAE4, SAE5 and SAE6 of a sub-display pixel SDX2 of the second sub-display area SDA2, and sub-pixel circuits SPC1 and SPC2 is shown.

[0113] Reference Figure 7 , the display device 10 may include a plurality of pixel electrodes AE1, AE2, and AE3 disposed in the main display area MDA. The pixel electrodes AE1, AE2, and AE3 may be anode electrodes of light-emitting elements EL that emit light of different colors. For example, a first pixel electrode AE1, which is an anode electrode of a light-emitting element that emits light of a first color, may be disposed in a first emission region. A second pixel electrode AE2, which is an anode electrode of a light-emitting element that emits light of a second color, may be disposed in a second emission region, and a third pixel electrode AE3, which is an anode electrode of a light-emitting element that emits light of a third color, may be disposed in a third emission region. In one or more embodiments, the first emission region may emit a red first light, the second emission region may emit a green second light, and the third emission region may emit a blue third light. However, the present disclosure is not limited thereto. A plurality of emission regions may be defined by openings formed in a first pixel defining layer 131 of a light-emitting element layer 130 to be described later, respectively.

[0114] The plurality of pixel electrodes AE1, AE2 and AE3 may be arranged in a PENTILE ® Type structure (for example, diamond-shaped PENTILE ® PENTILE ®is a registered trademark of Samsung Display Co., Ltd. of the Republic of Korea. For example, the first pixel electrode AE1 and the third pixel electrode AE3 may be disposed to be spaced apart from each other in the vertical direction and the horizontal direction, and they may be disposed alternately. The second pixel electrode AE2 may be spaced apart from another adjacent second pixel electrode AE2 in the vertical direction and the horizontal direction, and may be spaced apart from the adjacent first pixel electrode AE1 and the adjacent third pixel electrode AE3 in the oblique direction.

[0115] Each of the first to third pixel electrodes AE1, AE2, and AE3 is a pixel electrode belonging to one sub-pixel SPX, and a plurality of pixel electrodes AE1, AE2, and AE3 may be included in one main display pixel MDX. For example, the main display pixel MDX may include one first color sub-pixel SPX1, two second color sub-pixels SPX2, and one third color sub-pixel SPX3, and the main display pixel MDX may include one first pixel electrode AE1, two second pixel electrodes AE2, and one third pixel electrode AE3.

[0116] Each of the plurality of pixel circuits PXC1, PXC2, and PXC3 provided in the main display area MDA may correspond to one of the pixel electrodes AE1, AE2, and AE3. For example, the first pixel circuit PXC1 may correspond to one first pixel electrode AE1 and may be electrically connected to one first pixel electrode AE1. The second pixel circuit PXC2 may correspond to one second pixel electrode AE2 and may be electrically connected to one second pixel electrode AE2, and the third pixel circuit PXC3 may correspond to one third pixel electrode AE3 and may be electrically connected to one third pixel electrode AE3. The main display pixel MDX including four pixel electrodes AE1, AE2, and AE3 may include four pixel circuits PXC1, PXC2, and PXC3.

[0117] Reference Figure 8 , the display device 10 may include a plurality of sub-pixel electrodes SAE, a replica pixel electrode CPE, and a bridge electrode BAE arranged in the sub-display area SDA. One sub-pixel electrode SAE and one replica pixel electrode CPE may both be anode electrodes of the light emitting element EL. That is, similar to the main display area MDA, the light emitting element EL may also be arranged in the sub-display areas SDA1 and SDA2 to emit light.

[0118] In the display device 10, the configuration of the sub-display pixels SDX of the sub-display area SDA may be different from the configuration of the main display pixels MDX of the main display area MDA. In the first sub-display pixel SDX1, one sub-pixel electrode SAE and one replica pixel electrode CPE may be electrically connected to each other through the bridge electrode BAE. The sub-pixel electrode SAE and the replica pixel electrode CPE connected through the bridge electrode BAE may be anode electrodes of the light emitting elements EL emitting light of the same color.

[0119] For example, the first sub-pixel electrode SAE1 and the first replica pixel electrode CPE1 disposed in the first sub-display area SDA1 may be electrically connected to each other through the first bridging electrode BAE1, and the first sub-pixel electrode SAE1 and the first replica pixel electrode CPE1 may constitute a light-emitting element emitting light of a first color. The emission area in which the first sub-pixel electrode SAE1 and the first replica pixel electrode CPE1 are disposed may emit light of the same color.

[0120] Similarly, the second sub-pixel electrode SAE2 and the second replica pixel electrode CPE2 disposed in the first sub-display area SDA1 may be electrically connected to each other via the second bridging electrode BAE2, and the third sub-pixel electrode SAE3 and the third replica pixel electrode CPE3 disposed in the first sub-display area SDA1 may be electrically connected to each other via the third bridging electrode BAE3. The second sub-pixel electrode SAE2 and the second replica pixel electrode CPE2 may constitute a light-emitting element that emits light of a second color, and the third sub-pixel electrode SAE3 and the third replica pixel electrode CPE3 may constitute a light-emitting element that emits light of a third color. The emission region provided with the second sub-pixel electrode SAE2 and the second replica pixel electrode CPE2 may emit light of the same color, and the emission region provided with the third sub-pixel electrode SAE3 and the third replica pixel electrode CPE3 may emit light of the same color.

[0121] According to one or more embodiments, the sub-pixel electrodes SAE4, SAE5, and SAE6 and the duplicate pixel electrodes CPE4, CPE5, and CPE6 disposed in the second sub display area SDA2 may be connected to each other through a connection pattern BAP (see FIG. Fig.11 and Fig.12) are electrically connected to each other. The fourth to sixth sub-pixel electrodes SAE4, SAE5 and SAE6 and the fourth to sixth replica pixel electrodes CPE4, CPE5 and CPE6 may also be arranged in the second sub-display area SDA2 in the same arrangement as in the first sub-display area SDA1. However, a pair of sub-pixel electrodes SAE and the replica pixel electrode CPE may be connected by a connection pattern disposed around them, and the connection pattern may be formed on the second pixel defining layer 132 (see Fig.11 ) of the valley VA (see Fig.11 ) are separated from each other.

[0122] The fourth subpixel electrode SAE4 and the fourth replica pixel electrode CPE4 can constitute a light-emitting element that emits light of the first color, the fifth subpixel electrode SAE5 and the fifth replica pixel electrode CPE5 can constitute a light-emitting element that emits light of the second color, and the sixth subpixel electrode SAE6 and the sixth replica pixel electrode CPE6 can constitute a light-emitting element that emits light of the third color.

[0123] Similar to the pixel electrode AE ​​of the main display area MDA, a plurality of sub-pixel electrodes SAE and a plurality of replica pixel electrodes CPE may be arranged in a PENTILE ® Type structure (for example, diamond-shaped PENTILE ® The first sub-pixel electrode SAE1 and the third sub-pixel electrode SAE3 may be arranged in a horizontal direction, and the third replica pixel electrode CPE3 and the first replica pixel electrode CPE1 may be arranged to be spaced apart from the first sub-pixel electrode SAE1 and the third sub-pixel electrode SAE3 in the vertical direction. The fourth sub-pixel electrode SAE4 and the sixth sub-pixel electrode SAE6 may be spaced apart from each other in the horizontal direction, and the sixth replica pixel electrode CPE6 and the fourth replica pixel electrode CPE4 may be arranged to be spaced apart from the fourth sub-pixel electrode SAE4 and the sixth sub-pixel electrode SAE6 in the vertical direction. The second sub-pixel electrode SAE2 and the second replica pixel electrode CPE2 may be spaced apart from each other in the oblique direction, and the first sub-pixel electrode SAE1 is placed between the second sub-pixel electrode SAE2 and the second replica pixel electrode CPE2. The fifth sub-pixel electrode SAE5 and the fifth replica pixel electrode CPE5 may be spaced apart from each other in the oblique direction, and the fourth replica pixel electrode CPE4 is placed between the fifth sub-pixel electrode SAE5 and the fifth replica pixel electrode CPE5. The plurality of bridge electrodes BAE may connect a pair of sub-pixel electrodes SAE and the replica pixel electrode CPE to each other, and may be disposed to bypass so as not to cross another sub-pixel electrode SAE, another replica pixel electrode CPE, and another bridge electrode BAE.

[0124] The first sub-display pixel SDX1 disposed in the first sub-display area SDA1 may include six pixel electrodes or six emission areas, the six pixel electrodes including the first to third sub-pixel electrodes SAE1, SAE2 and SAE3 and the first to third replica pixel electrodes CPE1, CPE2 and CPE3. The second sub-display pixel SDX2 disposed in the second sub-display area SDA2 may include six pixel electrodes or six emission areas, the six pixel electrodes including the fourth to sixth sub-pixel electrodes SAE4, SAE5 and SAE6 and the fourth to sixth replica pixel electrodes CPE4, CPE5 and CPE6. Unlike the main display pixel MDX of the main display area MDA, the sub-display pixel SDX disposed in the sub-display area SDA may have a larger number of emission areas emitting light of the same color. However, the number or density of emission areas per unit area in the main display pixel MDX may be greater than the number or density of emission areas per unit area in the sub-display pixel SDX. In addition, the number of light-emitting elements emitting light of the first color and the number of light-emitting elements emitting light of the third color in the sub-display pixel SDX may be greater than the number of light-emitting elements emitting light of the first color and the number of light-emitting elements emitting light of the third color in the main display pixel MDX, but the number of light-emitting elements emitting light of the second color in the sub-display pixel SDX and the main display pixel MDX may be the same. Therefore, in the display device 10, the resolution of the main display area MDA may be higher than the resolution of the sub-display area SDA. Considering the transmittance of light incident on the optical device 500 provided in the sub-display area SDA, the sub-display area SDA may have a resolution lower than that of the main display area MDA.

[0125] In one or more embodiments, a first sub-pixel circuit SPC1 electrically connected to the first sub-display pixel SDX1 and a second sub-pixel circuit SPC2 electrically connected to the second sub-display pixel SDX2 may be disposed in the first sub-display area SDA1 of the sub-display area SDA. On the other hand, in the second sub-display area SDA2, no pixel circuit may be disposed, and a plurality of sub-pixel electrodes SAE, a plurality of replica pixel electrodes CPE, a plurality of connection patterns BAP (for example, see Fig.11 ) and the bridge patterns BRE1, BRE2 and BRE3 (see Fig.11 and Fig.12 ).

[0126] As will be described later, a plurality of sub-pixel electrodes SAE and a plurality of replica pixel electrodes CPE are disposed in the sub-display areas SDA1 and SDA2 of the display device 10, and they can be distinguished according to the arrangement position and the connection structure. For example, the first to third sub-pixel electrodes SAE1, SAE2, and SAE3 disposed in the first sub-display area SDA1 can be disposed in the same layer (e.g., at), and can be connected to the first to third replica pixel electrodes CPE1, CPE2, and CPE3 through the integrated first to third bridging electrodes BAE1, BAE2, and BAE3. The sub-pixel electrode SAE, the replica pixel electrode CPE, and the bridging electrode BAE disposed in the first sub-display area SDA1 can constitute substantially the same electrode, and can have substantially the same material and substantially the same cross-sectional structure. The sub-pixel electrode SAE and the replica pixel electrode CPE disposed in the first sub-display area SDA1 can be referred to as a first-type sub-pixel electrode SAE#1 (or "first sub-pixel electrode") and a first-type replica pixel electrode CPE#1 (or "first replica pixel electrode"), respectively.

[0127] On the other hand, the fourth to sixth sub-pixel electrodes SAE4, SAE5, and SAE6 disposed in the second sub-display area SDA2 may be connected to the fourth to sixth replica pixel electrodes CPE4, CPE5, and CPE6 by connection patterns disposed in the same layer (e.g., at) but distinguished. A plurality of connection patterns surrounding the fourth to sixth sub-pixel electrodes SAE4, SAE5, and SAE6 and the fourth to sixth replica pixel electrodes CPE4, CPE5, and CPE6 may be disposed in the second sub-display area SDA2, and the connection patterns may also be distinguished at the valley VA of the second pixel defining layer 132, so that different pairs of sub-pixel electrodes and replica pixel electrodes may be electrically insulated. The sub-pixel electrode SAE and the replica pixel electrode CPE disposed in the second sub-display area SDA2 may be referred to as a second type sub-pixel electrode SAE#2 (or "second sub-pixel electrode") and a second type replica pixel electrode CPE#2 (or "second replica pixel electrode"), respectively.

[0128] The first sub-pixel circuit SPC1 may be electrically connected to the first type sub-pixel electrode SAE#1 or the sub-pixel electrode SAE provided in the first sub-display pixel SDX1. Each of the plurality of first sub-pixel circuits SPC1 may be electrically connected to the first sub-pixel electrode SAE1, the second sub-pixel electrode SAE2, and the third sub-pixel electrode SAE3. Each of the first type replica pixel electrodes CPE#1 provided in the first sub-display pixel SDX1 may be electrically connected to the first type sub-pixel electrode SAE#1 through the bridging electrode BAE, and a plurality of light emitting elements including a pair of sub-pixel electrodes SAE and the replica pixel electrode CPE may emit light simultaneously (e.g., concurrently). Each of the sub-pixel electrodes SAE provided in the first sub-display pixel SDX1 may be provided to overlap with the first sub-pixel circuit SPC1.

[0129] The second sub-pixel circuit SPC2 may be electrically connected to the second-type sub-pixel electrode SAE#2 or the sub-pixel electrode SAE disposed in the second sub-display pixel SDX2. Each of the plurality of second sub-pixel circuits SPC2 may be electrically connected to the fourth sub-pixel electrode SAE4, the fifth sub-pixel electrode SAE5, and the sixth sub-pixel electrode SAE6. Each of the second-type replica pixel electrodes CPE#2 disposed in the second sub-display pixel SDX2 may be electrically connected to the fourth sub-pixel electrode SAE4, the fifth sub-pixel electrode SAE5, and the sixth sub-pixel electrode SAE6. Fig.11 ) is electrically connected to the second type sub-pixel electrode SAE#2, and a plurality of light emitting elements including a pair of sub-pixel electrodes SAE and a replica pixel electrode CPE may emit light simultaneously (e.g., concurrently). A connection pattern connecting the second sub-pixel circuit SPC2 and the second type sub-pixel electrode SAE#2 of the second sub-display pixel SDX2 may be provided in the sub-display area SDA. At least some of the first type replica pixel electrodes CPE#1 provided in the first sub-display pixel SDX1 may be provided to overlap with the second sub-pixel circuit SPC2. Others of the first type replica pixel electrodes CPE#1 provided in the first sub-display pixel SDX1 may be provided in an area where the sub-pixel circuits SPC1 and SPC2 are not provided.

[0130] According to one or more embodiments, the first type sub-pixel electrode SAE#1, the first type replica pixel electrode CPE#1 and the first type bridging electrode BAE#1 arranged in the first sub-display area SDA1 can be arranged in the same layer (for example, at) to form an integrated pattern. For example, the first bridging electrode to the third bridging electrode BAE1, BAE2 and BAE3 as the bridging electrode BAE arranged in the first sub-display area SDA1 can be a bridging portion that is integrated with the first sub-pixel electrode to the third sub-pixel electrode SAE1, SAE2 and SAE3 and the first replica pixel electrode to the third replica pixel electrode CPE1, CPE2 and CPE3. On the other hand, the second type sub-pixel electrode SAE#2 and the second type replica pixel electrode CPE#2 arranged in the second sub-display area SDA2 can be arranged in the same layer (for example, at) and have the same electrode structure, but the connecting pattern BAP (for example, see FIG. 2 ) arranged around them. Fig.11 ) may include different materials and have different structures. The connection pattern BAP disposed in the second sub-display area SDA2 may be disposed in the same layer (e.g., at) as the second type sub-pixel electrode SAE#2 and the second type replica pixel electrode CPE#2 disposed in the second sub-display area SDA2, and may be electrically connected to the second type sub-pixel electrode SAE#2 and the second type replica pixel electrode CPE#2 by contacting the second type sub-pixel electrode SAE#2 and the second type replica pixel electrode CPE#2.

[0131] The first type sub-pixel electrode SAE#1 disposed in the first sub-display area SDA1 may be disposed to overlap with the first sub-pixel circuit SPC1, and may be integrated with the first type replica pixel electrode CPE#1 through the first type bridging electrode BAE#1 at the same layer (e.g., at). The second type sub-pixel electrode SAE#2 disposed in the second sub-display area SDA2 may be electrically connected to the second sub-pixel circuit SPC2, but may be disposed not to overlap with the second sub-pixel circuit SPC2. The second type sub-pixel electrode SAE#2 disposed in the second sub-display area SDA2 may be electrically connected to the second sub-pixel circuit SPC2 through a bridging pattern disposed thereunder. A more detailed description thereof will be described later with reference to other drawings.

[0132] In the sub display area SDA, the sub pixel circuits SPC1 and SPC2 may be arranged only in the first sub display area SDA1 in consideration of transmittance. Because the number of sub pixel circuits SPC1 and SPC2 arranged per unit area in the sub display area SDA is smaller than the number of sub pixel circuits SPC1 and SPC2 arranged per unit area in the main display area MDA, in the case where the sub display pixels SDX1 and SDX2 are arranged in the sub display area SDA, the sub pixel electrode SAE and the replica pixel electrode CPE may form a pair to form a plurality of emission areas.

[0133] Fig. 9 is a cross-sectional view illustrating an example of a main display area of ​​a display device according to one or more embodiments.

[0134] Fig. 9 The cross sections of two light emitting elements EL and pixel circuits PXC1 and PXC2 provided in the main display area MDA are schematically shown. Fig. 9 A cross section of a portion of the first pixel circuit PXC1 and a portion of the second pixel circuit PXC2 adjacent to each other is shown.

[0135] Reference Fig. 9 The display panel 100 may include a substrate 110, a circuit layer 120 disposed on the substrate 110, a light emitting element layer 130, and an encapsulation layer 140. The circuit layer 120, the light emitting element layer 130, and the encapsulation layer 140 may be sequentially arranged or stacked on the substrate 110 in a thickness direction (eg, a third direction DR3).

[0136] The substrate 110 may be made of a material having a flexible property capable of being bent, folded, and / or rolled, etc. The substrate 110 may be formed of an insulating material such as a polymer resin. For example, the substrate 110 may be made of polyimide.

[0137] The circuit layer 120 may include pixel circuits PXC and wirings. For example, the circuit layer 120 may include circuit elements (e.g., pixel transistors T and capacitors Cst) constituting the pixel circuits PXC of each main display pixel MDX and wirings (e.g., various power lines and signal lines including power lines PL, scan lines SL, emission control lines ECL, and data lines DL) electrically connected to the pixel circuits PXC.

[0138] Among the elements that may be provided in the circuit layer 120, Fig. 9A first thin film transistor TFT1 (also referred to as a "first pixel transistor"), a second thin film transistor TFT2 (also referred to as a "second pixel transistor"), and a capacitor Cst included in the pixel circuit PXC of each main display pixel MDX are shown. The first thin film transistor TFT1 may be a first type transistor (e.g., a P-type transistor) including a first semiconductor material (e.g., polysilicon) among the pixel transistors T constituting each of the pixel circuits PXC. For example, the first thin film transistor TFT1 may be one of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. Fig. 9 1 and 2. One transistor (eg, a first connection electrode CNE1 and a second connection electrode CNE2) among the first type transistors is shown connected to the light emitting element EL through at least one connection electrode (eg, a first connection electrode CNE1 and a second connection electrode CNE2). Figure 5 The sixth transistor T6 of the pixel transistor T2 is used as the first thin film transistor TFT1. The second thin film transistor TFT2 may be a second type transistor (eg, an N-type transistor) including a second semiconductor material (eg, an oxide semiconductor) among the pixel transistors T. For example, the second thin film transistor TFT2 may be one of the third transistor T3 and the fourth transistor T4.

[0139] The circuit layer 120 may include a semiconductor layer for forming circuit elements, wirings, etc., a conductive layer, and an insulating layer disposed between the conductive layer and the semiconductor layer and / or disposed around the conductive layer and the semiconductor layer. For example, the circuit layer 120 may include a barrier layer 121, a lower conductive layer BCDL, a buffer layer 122, a first semiconductor layer SCL1 (e.g., a polycrystalline silicon semiconductor layer), a first insulating layer 123 (e.g., a first gate insulating layer), a first conductive layer CDL1 (e.g., a first gate conductive layer), a second insulating layer 124 (e.g., a second gate insulating layer), a second conductive layer CDL2 (e.g., a second gate conductive layer), a third insulating layer 125 (e.g., a first interlayer insulating layer), a second semiconductor layer SCL2 (e.g., an oxide semiconductor layer), a fourth insulating layer 126 (e.g., a third gate insulating layer), a third conductive layer CDL3 (e.g., a third gate insulating layer), a fifth insulating layer 127 (e.g., a second interlayer insulating layer), a fourth conductive layer CDL4 (e.g., a first source-drain conductive layer), and a sixth insulating layer 128 (e.g., a first via layer or a first planarizing layer) sequentially disposed on the substrate 110 with reference to a third direction DR3. In one or more embodiments, the circuit layer 120 may further include an interlayer insulating layer ILD (ILD1, ILD2) on the fifth insulating layer 127, and a fifth conductive layer CDL5 (e.g., a second source-drain conductive layer) and a seventh insulating layer 129 (e.g., a second via layer or a second planarization layer) sequentially disposed on the sixth insulating layer 128.

[0140] The barrier layer 121 may be disposed on the substrate 110. The barrier layer 121 may protect the elements disposed in the circuit layer 120 and the light emitting element layer 130 from moisture penetration through the substrate 110, which is susceptible to moisture penetration. The barrier layer 121 may include at least one inorganic layer containing an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, and / or other inorganic insulating materials). The material of the barrier layer 121 may be variously changed according to one or more embodiments.

[0141] The lower conductive layer BCDL may be disposed on the barrier layer 121. The lower conductive layer BCDL may include a lower metal layer BML overlapping an active layer (eg, first active layer ACT1 and / or second active layer ACT2) of at least one pixel transistor T and / or at least one wiring (or a portion of at least one wiring). Fig. 9 The lower metal layer BML is shown to be disposed to overlap only the first active layer ACT1 of the first thin film transistor TFT1 and the capacitor electrodes CAE1 and CAE2 of the capacitor Cst, but the present disclosure is not limited thereto. For example, the lower metal layer BML may be patterned into a suitable size and / or shape as needed and disposed on a portion of the pixel circuit PXC, or may be disposed on the entire surface of the pixel circuit PXC. For example, the lower metal layer BML may be disposed only in a portion of the pixel region to overlap with the capacitor electrodes CAE1 and CAE2 of the capacitor Cst. Figure 5 In one or more embodiments, the lower metal layer BML may also be used as a light shielding pattern and / or a back gate electrode of at least one pixel transistor T, etc.

[0142] The buffer layer 122 may be disposed on the lower conductive layer BCDL to cover the lower conductive layer BCDL. The buffer layer 122 may include at least one inorganic layer including an inorganic insulating material.

[0143] The first thin film transistor TFT1, the second thin film transistor TFT2, and the capacitor Cst may be disposed on one surface of the substrate 110 on which the buffer layer 122 is disposed. The first thin film transistor TFT1 may include a first active layer ACT1 and a first gate electrode G1. The second thin film transistor TFT2 may include a second active layer ACT2 and a second gate electrode G2. In one or more embodiments, the second thin film transistor TFT2 may include a back gate electrode BG. The capacitor Cst may include a first capacitor electrode CAE1 and a second capacitor electrode CAE2.

[0144] The first semiconductor layer SCL1 may be disposed on the buffer layer 122. The first semiconductor layer SCL1 may include a first active layer ACT1 of the first thin film transistor TFT1. For example, the first semiconductor layer SCL1 may include a first active layer ACT1 of each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7.

[0145] The first active layer ACT1 may be disposed on the buffer layer 122 and may include a first semiconductor material (e.g., polysilicon). The first active layer ACT1 may include a first channel region CH1, a first source region S1, and a first drain region D1. The first channel region CH1 may overlap with the first gate electrode G1 in the third direction DR3. The first source region S1 may be disposed on one side of the first channel region CH1, and the first drain region D1 may be disposed on the other side of the first channel region CH1. The first source region S1 and the first drain region D1 may be regions formed to have conductivity by doping ions or impurities into a semiconductor used to form the first active layer ACT1. In one or more embodiments, the first source region S1 may be a source electrode of the first thin film transistor TFT1. In one or more embodiments, the first thin film transistor TFT1 may include a separate source electrode connected to the first source region S1. In one or more embodiments, the first drain region D1 may be a drain electrode of the first thin film transistor TFT1. In one or more embodiments, the first thin film transistor TFT1 may include a separate drain electrode connected to the first drain region D1.

[0146] The first insulating layer 123 may be disposed on the first semiconductor layer SCL1 and the buffer layer 122 . The first insulating layer 123 may cover the first semiconductor layer SCL1 and the buffer layer 122 .

[0147] The first conductive layer CDL1 may be disposed on the first insulating layer 123. The first conductive layer CDL1 may include a first gate electrode G1 of the first thin film transistor TFT1. The first gate electrode G1 may be disposed to overlap a portion of the first active layer ACT1 (e.g., the first channel region CH1). In one or more embodiments, the first conductive layer CDL1 may further include at least one wiring (or a portion of at least one wiring), a conductive pattern (e.g., a bridge pattern), and / or a capacitor electrode. For example, the first conductive layer CDL1 may further include a first capacitor electrode CAE1 of a capacitor Cst.

[0148] In one or more embodiments, the first capacitor electrode CAE1 may be integrally formed with a gate electrode of at least one first thin film transistor TFT1. Figure 5 and Figure 6For example, the first capacitor electrode CAE1 and the gate electrode of the first transistor T1 may be formed as one conductive pattern, and the second capacitor electrode CAE2 may be disposed to overlap the conductive pattern.

[0149] The second insulating layer 124 may be disposed on the first conductive layer CDL1 and the first insulating layer 123. The second insulating layer 124 may cover the first conductive layer CDL1 and the first insulating layer 123.

[0150] The second conductive layer CDL2 may be disposed on the second insulating layer 124. The second conductive layer CDL2 may include one electrode of the capacitor Cst (e.g., the second capacitor electrode CAE2). In one or more embodiments, the second conductive layer CDL2 may further include at least one electrode, a wiring (or a portion of at least one wiring) and / or a conductive pattern (e.g., a bridge pattern). For example, the second conductive layer CDL2 may further include a back gate electrode BG connected to the second gate electrode G2 of the second thin film transistor TFT2.

[0151] The third insulating layer 125 may be disposed on the second conductive layer CDL2 and the second insulating layer 124. The third insulating layer 125 may cover the second conductive layer CDL2 and the second insulating layer 124.

[0152] The second semiconductor layer SCL2 may be disposed on the third insulating layer 125. The second semiconductor layer SCL2 may include a second active layer ACT2 of the second thin film transistor TFT2. For example, the second semiconductor layer SCL2 may include a second active layer ACT2 of each of the third transistor T3 and the fourth transistor T4.

[0153] The second active layer ACT2 may be disposed in the second semiconductor layer SCL2 and may include a second semiconductor material (eg, an oxide semiconductor) different from the first semiconductor material. For example, the second active layer ACT2 may include IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)), or IGTO (indium (In), gallium (Ga), tin (Sn), and / or oxygen (O)).

[0154] The second active layer ACT2 may include a second channel region CH2, a second source region S2, and a second drain region D2. The second channel region CH2 may overlap with the second gate electrode G2 in the third direction DR3. The second source region S2 may be disposed on one side of the second channel region CH2, and the second drain region D2 may be disposed on the other side of the second channel region CH2. The second source region S2 and the second drain region D2 may be conductive regions formed by doping ions or impurities into a semiconductor for forming the second active layer ACT2. In one or more embodiments, the second source region S2 may be a source electrode of the second thin film transistor TFT2. In one or more embodiments, the second thin film transistor TFT2 may include a separate source electrode connected to the second source region S2. In one or more embodiments, the second drain region D2 may be a drain electrode of the second thin film transistor TFT2. In one or more embodiments, the second thin film transistor TFT2 may include a separate drain electrode connected to the second drain region D2.

[0155] The fourth insulating layer 126 may be disposed on the second semiconductor layer SCL2 and the third insulating layer 125. The fourth insulating layer 126 may cover the second semiconductor layer SCL2 and the third insulating layer 125.

[0156] In one or more embodiments, the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, and the fourth insulating layer 126 may be inorganic insulating layers including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, and / or other inorganic insulating materials), and may each have a single layer structure or a multilayer structure. At least two insulating layers among the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, and the fourth insulating layer 126 may include the same material or may include different materials. The material of each of the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, and the fourth insulating layer 126 may be changed differently according to one or more embodiments.

[0157] The third conductive layer CDL3 may be disposed on the fourth insulating layer 126. The third conductive layer CDL3 may include a second gate electrode G2 of the second thin film transistor TFT2. The second gate electrode G2 may be disposed to overlap a portion of the second active layer ACT2 (e.g., the second channel region CH2). In one or more embodiments, the third conductive layer CDL3 may further include at least one wiring (or a portion of at least one wiring), a conductive pattern (e.g., a bridge pattern), and / or a capacitor electrode.

[0158] In one or more embodiments, each of the electrodes, conductive patterns and / or wirings disposed in the lower conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2 and the third conductive layer CDL3 may include a conductive material (e.g., at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and / or other metals, alloys thereof or other conductive materials), and may have a single layer structure or a multilayer structure. For example, each of the electrodes, conductive patterns and / or wirings disposed in the lower conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2 and the third conductive layer CDL3 may include molybdenum (Mo) or other metal materials. At least two conductive layers among the lower conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2 and the third conductive layer CDL3 may include the same material or may include different materials. The material of each of the lower conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2 and the third conductive layer CDL3 is not limited and may be changed differently according to one or more embodiments.

[0159] The fifth insulating layer 127 may be disposed on the third conductive layer CDL3 and the fourth insulating layer 126. The fifth insulating layer 127 may cover the third conductive layer CDL3 and the fourth insulating layer 126.

[0160] The fourth conductive layer CDL4 may be disposed on the fifth insulating layer 127. The fourth conductive layer CDL4 may include a first connection electrode CNE1 (or a drain electrode of the first thin film transistor TFT1), a first conductive pattern BE1 (or a source electrode of the second thin film transistor TFT2), and a second conductive pattern BE2 (or a drain electrode of the second thin film transistor TFT2). The first connection electrode CNE1 may be disposed in the fourth conductive layer CDL4 and may be connected to the first drain region D1 of the first active layer ACT1 through a first contact hole CT1 penetrating the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127. The first conductive pattern BE1 may be disposed in the fourth conductive layer CDL4 and may be connected to the second source region S2 of the second active layer ACT2 through a second contact hole CT2 penetrating the fourth insulating layer 126 and the fifth insulating layer 127. The second conductive pattern BE2 may be connected to the second drain region D2 of the second active layer ACT2 through a third contact hole CT3 penetrating the fourth insulating layer 126 and the fifth insulating layer 127. In one or more embodiments, the fourth conductive layer CDL4 may further include at least one wiring (or a portion of at least one wiring) and / or a conductive pattern (e.g., a bridge pattern). For example, the fourth conductive layer CDL4 may include a portion of a power line PL (e.g., a first pixel power line VDL and / or a second pixel power line VSL) disposed inside and / or outside the display area DA.

[0161] The first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 may be disposed on the fourth conductive layer CDL4 and the fifth insulating layer 127. The first interlayer insulating layer ILD1 may cover the fourth conductive layer CDL4 and the fifth insulating layer 127, and the second interlayer insulating layer ILD2 may be disposed on the first interlayer insulating layer ILD1. The first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 may also be disposed in the sub-display area SDA to form a layer on which a plurality of bridge patterns BRE1, BRE2, and BRE3 disposed in the sub-display area SDA are disposed. The first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 may include an inorganic insulating material, and may replace the sixth insulating layer 128 and the seventh insulating layer 129 not disposed in the second sub-display area SDA2 to cover a lower layer disposed in the second sub-display area SDA2.

[0162] The sixth insulating layer 128 may be disposed on the second interlayer insulating layer ILD2. The sixth insulating layer 128 may cover the second interlayer insulating layer ILD2.

[0163] The fifth conductive layer CDL5 may be disposed on the sixth insulating layer 128. The fifth conductive layer CDL5 may include a second connection electrode CNE2. The second connection electrode CNE2 may be disposed in the fifth conductive layer CDL5 and may be connected to the first connection electrode CNE1 through a fourth contact hole CT4 (or a first through hole) penetrating the sixth insulating layer 128, the second interlayer insulating layer ILD2, and the first interlayer insulating layer ILD1. In one or more embodiments, the fifth conductive layer CDL5 may further include at least one wiring (or a portion of at least one wiring) and / or a conductive pattern (e.g., a bridge pattern). For example, the fifth conductive layer CDL5 may include a portion of a power line PL (e.g., a first pixel power line VDL and / or a second pixel power line VSL) disposed inside and / or outside the display area DA.

[0164] In one or more embodiments, each of the electrodes, conductive patterns and / or wirings provided in the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may include a conductive material (e.g., at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and other metals, alloys thereof or other conductive materials), and may have a single layer structure or a multilayer structure. For example, each of the electrodes, conductive patterns and / or wirings provided in the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may be formed of a three-layer structure of titanium / aluminum / titanium (Ti / Al / Ti). The fourth conductive layer CDL4 and the fifth conductive layer CDL5 may include the same material or may include different materials. The material of each of the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may be changed differently according to one or more embodiments.

[0165] The seventh insulating layer 129 may be disposed on the fifth conductive layer CDL5 and the sixth insulating layer 128. The seventh insulating layer 129 may cover the fifth conductive layer CDL5 and the sixth insulating layer 128.

[0166] In one or more embodiments, the sixth insulating layer 128 and the seventh insulating layer 129 may be organic insulating layers including an organic insulating material (e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin and / or other organic insulating materials) to planarize the circuit layer 120, and may each have a single layer structure or a multilayer structure. The sixth insulating layer 128 and the seventh insulating layer 129 may include the same material or may include different materials. The material of each of the sixth insulating layer 128 and the seventh insulating layer 129 may be changed differently according to one or more embodiments.

[0167] The light emitting element layer 130 may include a first pixel defining layer 131 that separates the emission area EA of the pixel PX from the corresponding light emitting element EL located in the corresponding emission area EA. In one or more embodiments, the light emitting element layer 130 may further include a spacer SPC disposed on a portion of the first pixel defining layer 131.

[0168] Each light emitting element EL may include a pixel electrode AE ​​(e.g., an anode electrode) connected to at least one pixel transistor T (e.g., a first thin film transistor TFT1) included in the main display pixel MDX through a first connection electrode CNE1 and / or a second connection electrode CNE2, and a light emitting layer EML and a common electrode CE (e.g., a cathode electrode) sequentially disposed on the pixel electrodes AE (e.g., AE: AE1, AE2, AE3). In one or more embodiments, the light emitting element EL may further include a first intermediate layer (e.g., a hole layer including a hole transport layer) disposed between the pixel electrode AE ​​and the light emitting layer EML, and a second intermediate layer (e.g., an electron layer including an electron transport layer) disposed between the light emitting layer EML and the common electrode CE.

[0169] The pixel electrode AE ​​of the light emitting element EL may include a conductive material and may be disposed on the circuit layer 120. For example, the pixel electrode AE ​​may be disposed on the seventh insulating layer 129 to correspond to each emission area EA. The pixel electrode AE ​​may be connected to the second connection electrode CNE2 through a fifth contact hole CT5 (or a second through hole) penetrating the seventh insulating layer 129.

[0170] In one or more embodiments, the pixel electrode AE ​​may include a metal material having a high reflectivity. For example, the pixel electrode AE ​​may have a single layer structure of molybdenum (Mo), titanium (Ti), copper (Cu), and / or aluminum (Al), or may have a structure including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ) and multilayer structures of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au) and / or nickel (Ni) (e.g., ITO / Mg, ITO / MgF 2 , ITO / Ag and ITO / Ag / ITO).

[0171] The light emitting layer EML of the light emitting element EL may include a polymer material or a low molecular material. In one or more embodiments, the light emitting layer EML may be provided for each of the pixel electrodes AE1, AE2, and AE3 of each main display pixel MDX, and each light emitting layer EML may emit light of a color corresponding to the corresponding emission area EA. In one or more embodiments, the light emitting layer EML may be a common layer shared by emission areas EA of different colors, and a wavelength conversion layer and / or a color filter corresponding to the color (or wavelength band) of light desired to be emitted from each sub-pixel SPX may be arranged in the emission area EA of at least some of the sub-pixels SPX.

[0172] The common electrode CE of the light emitting element EL includes a conductive material and can be connected to the second pixel power line VSL. In one or more embodiments, the common electrode CE can be a common layer formed across the entire display area DA to cover the light emitting layer EML and the first pixel defining layer 131. The common electrode CE can be set across the entire main display area MDA and the entire sub-display area SDA. In one or more embodiments, the common electrode CE can be formed of a transparent conductive material (TCO) capable of transmitting light (such as ITO or IZO) or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag)). When the common electrode CE is made of a semi-transmissive conductive material, an improvement in light output efficiency due to the microcavity effect can be expected.

[0173] The first pixel defining layer 131 may have an opening corresponding to each of the emission areas EA, and may be around the emission area EA (e.g., may surround the emission area EA). For example, the first pixel defining layer 131 may be formed to cover the edge of the pixel electrode AE ​​of each of the light emitting elements EL, and may include an opening that exposes the remaining portion of the pixel electrode AE. The area where the exposed pixel electrode AE ​​overlaps the light emitting layer EML (or the area including the exposed pixel electrode AE ​​and the light emitting layer EML) may be defined as the emission area EA of each main display pixel MDX.

[0174] In one or more embodiments, the first pixel defining layer 131 may include at least one organic layer including an organic insulating material. For example, the first pixel defining layer 131 may include acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, benzocyclobutene (BCB) resin and / or other organic insulating materials.

[0175] The spacer SPC may be disposed on a portion of the first pixel defining layer 131. The spacer SPC may include at least one organic layer including an organic insulating material. The spacer SPC may include the same material as the first pixel defining layer 131 or may include a material different from the first pixel defining layer 131. In one or more embodiments, the first pixel defining layer 131 and the spacer SPC may be sequentially formed by separate mask processes. In one or more embodiments, the first pixel defining layer 131 and the spacer SPC may be formed simultaneously (e.g., concurrently) using a halftone mask. In this case, the first pixel defining layer 131 and the spacer SPC may be integrated with each other and be considered as a single insulating layer. The organic insulating material constituting the spacer SPC is not particularly limited and may be changed differently according to one or more embodiments.

[0176] The encapsulation layer 140 may be disposed on the light emitting element layer 130 in the main area MA. For example, the encapsulation layer 140 may be disposed in the display area DA and the non-display area NA to cover the light emitting element layer 130. The encapsulation layer 140 may block oxygen or moisture from penetrating into the light emitting element layer 130, and may reduce electrical or physical impact on the circuit layer 120 and the light emitting element layer 130.

[0177] In one or more embodiments, the encapsulation layer 140 may include a first inorganic encapsulation layer 141, an organic encapsulation layer 142, and a second inorganic encapsulation layer 143 sequentially disposed on the light emitting element layer 130. The first inorganic encapsulation layer 141 and the second inorganic encapsulation layer 143 may include an inorganic material, and the organic encapsulation layer 142 may include an organic material.

[0178] In one or more embodiments, the above reference Figure 3 The described touch sensing layer TSU and the color filter layer CFL may be disposed on the encapsulation layer 140 .

[0179] Fig.10 and Fig.11 is a cross-sectional view illustrating an example of a sub display region of a display device according to one or more embodiments. Fig.10 and Fig.11 The cross sections of the light emitting elements EL disposed in the first sub-display area SDA1 and the second sub-display area SDA2 and the electrical connection structures between the light emitting elements EL and the first sub-pixel circuit SPC1 and the second sub-pixel circuit SPC2 are respectively shown. Fig.10 The cross-sectional structure of the portion where the first sub-pixel electrode SAE1 and the first replica pixel electrode CPE1 are provided is shown. Fig.11 The structure of a portion where the fourth sub-pixel electrode SAE4 and the fourth replica pixel electrode CPE4 are provided is shown.

[0180] Reference Fig.10 and Fig.11 , the display device 10 may include a first sub-pixel circuit SPC1 and a second sub-pixel circuit SPC2 disposed in the first sub-display area SDA1. Each of the first sub-pixel circuit SPC1 and the second sub-pixel circuit SPC2 may include an element formed by wiring and patterns of first to fifth conductive layers CDL1, CDL2, CDL3, CDL4, and CDL5, a first semiconductor layer SCL1, and a second semiconductor layer SCL2 disposed on the substrate 110. The structures and connections of the first sub-pixel circuit SPC1 and the second sub-pixel circuit SPC2 may be the same as those described above with reference to Fig. 9 The structure and connection of the pixel circuit PXC described are the same. Therefore, the detailed description thereof is omitted hereinafter.

[0181] The display device 10 may include a third interlayer insulating layer ILD3 disposed in the second sub display area SDA2. The first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 may be disposed in the entire display area DA, and the third interlayer insulating layer ILD3 may be disposed on the second interlayer insulating layer ILD2 in the second sub display area SDA2. The third interlayer insulating layer ILD3 may be disposed throughout the entire second sub display area SDA2, and may be disposed to extend to the vicinity of a boundary between the first sub display area SDA1 and the second sub display area SDA2.

[0182] In the display device 10, the sixth insulating layer 128 and the seventh insulating layer 129 including an organic insulating material may be provided to improve transmittance in the second sub-display area SDA2. The sixth insulating layer 128 and the seventh insulating layer 129 are provided throughout the entire main display area MDA and the entire first sub-display area SDA1, but may be provided only partially in the second sub-display area SDA2 near the boundary with the first sub-display area SDA1. The sixth insulating layer 128 and the seventh insulating layer 129 may not be provided at least in the area of ​​the second sub-display area SDA2 where the light emitting element EL is provided or in the area where the sub-pixel electrode SAE and the replica pixel electrode CPE are provided. Since the sixth insulating layer 128 and the seventh insulating layer 129 including an organic insulating material are not provided in the second sub-display area SDA2, the second sub-display area SDA2 may have a high transmittance, and the amount of light incident on the components provided in the second sub-display area SDA2 or incident on the optical device 500 may be increased.

[0183] In the display device 10, in the main display area MDA and the first sub display area SDA1, the seventh insulating layer 129 including an organic insulating material may be disposed under the anode electrode of the light emitting element EL to serve as a via layer, but in the second sub display area SDA2, the first to third interlayer insulating layers ILD1, ILD2, and ILD3 including inorganic insulating materials may be disposed under the anode electrode of the light emitting element EL to serve as a via layer.

[0184] The first sub-pixel circuit SPC1 disposed in the first sub-display area SDA1 may be electrically connected to the first sub-pixel electrode SAE1. The first connection electrode CNE1 of the first sub-pixel circuit SPC1 may be connected to the second connection electrode CNE2 disposed on the sixth insulating layer 128, and the second connection electrode CNE2 of the first sub-pixel circuit SPC1 may be connected to the first sub-pixel electrode SAE1 disposed on the seventh insulating layer 129. The first sub-pixel electrode SAE1 may be disposed to overlap with the first sub-pixel circuit SPC1, and may be electrically connected to the first sub-pixel circuit SPC1 to become an anode electrode of the light emitting element EL. The first sub-pixel electrode SAE1 may overlap with the opening of the first pixel defining layer 131, and may constitute the light emitting element EL together with the light emitting layer EML disposed at the opening and the common electrode CE disposed on the light emitting layer EML.

[0185] The first replica pixel electrode CPE1 disposed in the first sub-display area SDA1 may be electrically connected to the first sub-pixel electrode SAE1. In one or more embodiments, the first replica pixel electrode CPE1 may be integrated with the first sub-pixel electrode SAE1 through a first bridging electrode BAE1 disposed in the same layer (e.g., at). Each of the first replica pixel electrode CPE1 and the first bridging electrode BAE1 may be directly disposed on the seventh insulating layer 129. The first replica pixel electrode CPE1 may be disposed to overlap with the second sub-pixel circuit SPC2, but may be electrically connected to the first sub-pixel circuit SPC1 through the first sub-pixel electrode SAE1. The first replica pixel electrode CPE1 may overlap with the opening of the first pixel defining layer 131, and may constitute a light emitting element EL together with a light emitting layer EML disposed at the opening and a common electrode CE disposed on the light emitting layer EML. An electrical signal for light emission of the light emitting element EL may be simultaneously (e.g., concurrently) applied to the first sub-pixel electrode SAE1 and the first replica pixel electrode CPE1, and the light emitting element EL including each of the first sub-pixel electrode SAE1 and the first replica pixel electrode CPE1 may simultaneously (e.g., concurrently) emit light. The light emitting layer EML disposed on the first sub-pixel electrode SAE1 and the first replica pixel electrode CPE1 may be a light emitting layer emitting light of the same color.

[0186] The second sub-pixel circuit SPC2 disposed in the first sub-display area SDA1 may be electrically connected to any one of the fourth to sixth sub-pixel electrodes SAE4, SAE5, and SAE6 disposed in the second sub-display area SDA2. The pixel circuit may not be disposed in the second sub-display area SDA2, and the second sub-display area SDA2 may include a plurality of patterns and electrodes capable of transmitting an electrical signal of the second sub-pixel circuit SPC2.

[0187] According to one or more embodiments, the display device 10 may include a plurality of bridge patterns BRE1, BRE2, and BRE3 disposed in the sub display areas SDA1 and SDA2. The bridge patterns BRE1, BRE2, and BRE3 may be disposed on the first interlayer insulating layer ILD1 or the second interlayer insulating layer ILD2 disposed throughout the entire display area DA. The bridge patterns BRE1, BRE2, and BRE3 may transmit an emission signal applied from the second sub pixel circuit SPC2 to the sub pixel electrode SAE disposed in the second sub display area SDA2.

[0188] For example, the bridge patterns BRE1, BRE2, and BRE3 may include a first bridge pattern BRE1, a second bridge pattern BRE2, and a third bridge pattern BRE3 disposed on the first interlayer insulating layer ILD1 or the second interlayer insulating layer ILD2. For example, the first bridge pattern BRE1 and the second bridge pattern BRE2 may be disposed on the second interlayer insulating layer ILD2, and the third bridge pattern BRE3 may be disposed on the first interlayer insulating layer ILD1. The third bridge pattern BRE3 may be disposed between the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2, and the first bridge pattern BRE1 and the second bridge pattern BRE2 may be disposed between the second interlayer insulating layer ILD2 and the third interlayer insulating layer ILD3. In one or more embodiments, each of the first to third bridge patterns BRE1, BRE2, and BRE3 may include a transparent conductive material (TCO) such as ITO and / or IZO.

[0189] The first and third bridge patterns BRE1 and BRE3 may be electrodes transmitting emission signals from the second sub-pixel circuit SPC2, and the second bridge pattern BRE2 may be an electrode connecting the third bridge pattern BRE3 disposed on another interlayer insulating layer and the sub-pixel electrode SAE disposed on the second bridge pattern BRE2.

[0190] For example, the first bridge pattern BRE1 may be disposed on the second interlayer insulating layer ILD2 and electrically connected to the second subpixel circuit SPC2 of the first sub-display area SDA1. The first bridge pattern BRE1 may be connected to the third connection electrode CNE3 through a sixth contact hole CT6 penetrating the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2. The first bridge pattern BRE1 may extend from the first sub-display area SDA1 to the second sub-display area SDA2 and may be connected to a subpixel electrode (e.g., a fourth subpixel electrode SAE4) in the second sub-display area SDA2. The fourth subpixel electrode SAE4 may be disposed on the third interlayer insulating layer ILD3 and may be connected to the first bridge pattern BRE1 through a seventh contact hole CT7 penetrating the third interlayer insulating layer ILD3.

[0191] The third bridge pattern BRE3 may be disposed on the first interlayer insulating layer ILD1 and electrically connected to the second sub-pixel circuit SPC2 of the first sub-display area SDA1. In one or more embodiments, the third bridge pattern BRE3 may be connected to the third connection electrode CNE3 of the second sub-pixel circuit SPC2 through a contact hole penetrating the first interlayer insulating layer ILD1. The third bridge pattern BRE3 may extend from the first sub-display area SDA1 to the second sub-display area SDA2 and may be connected to the second bridge pattern BRE2 disposed on the second interlayer insulating layer ILD2 in the second sub-display area SDA2. The second bridge pattern BRE2 may be disposed on the second interlayer insulating layer ILD2 and may be connected to the third bridge pattern BRE3 through an eighth contact hole CT8 penetrating the second interlayer insulating layer ILD2. The second bridge pattern BRE2 may be connected to a sub-pixel electrode (e.g., the fifth sub-pixel electrode SAE5) in the second sub-display area SDA2. The fifth sub-pixel electrode SAE5 may be disposed on the third interlayer insulating layer ILD3 and may be connected to the second bridge pattern BRE2 through a contact hole penetrating the third interlayer insulating layer ILD3. The second sub-pixel circuit SPC2 disposed in the first sub-display area SDA1 may be electrically connected to the sub-pixel electrodes SAE4, SAE5, and SAE6 of the second sub-display area SDA2 through the first to third bridge patterns BRE1, BRE2, and BRE3. The number and arrangement of the bridge patterns BRE1, BRE2, and BRE3 disposed in the sub-display areas SDA1 and SDA2 may be designed to correspond to the number and arrangement of the second sub-pixel circuit SPC2 and the number and arrangement of the sub-pixel electrodes SAE of the second sub-pixel area SDA2. The fourth to sixth subpixel electrodes SAE4, SAE5 and SAE6 arranged in the second sub-display area SDA2 can be electrically connected to the second subpixel circuit SPC2 through bridge patterns BRE1, BRE2 and BRE3 without overlapping the second subpixel circuit SPC2, and can become the anode electrodes of the light-emitting element EL arranged in the second sub-display area SDA2.

[0192] The fourth to sixth subpixel electrodes SAE4, SAE5, and SAE6 and the fourth to sixth replica pixel electrodes CPE4, CPE5, and CPE6 may all be disposed on the third interlayer insulating layer ILD3 in the second sub display area SDA2. The fourth to sixth subpixel electrodes SAE4, SAE5, and SAE6 may overlap with any one of the first bridge pattern BRE1 and the second bridge pattern BRE2 and may contact with any one of the first bridge pattern BRE1 and the second bridge pattern BRE2. The fourth to sixth replica pixel electrodes CPE4, CPE5, and CPE6 do not necessarily overlap with the first to third bridge patterns BRE1, BRE2, and BRE3, but may be disposed to overlap with them in some cases. The fourth to sixth replica pixel electrodes CPE4, CPE5 and CPE6 are not in direct contact with the first to third bridge patterns BRE1, BRE2 and BRE3, but can be electrically connected to the second subpixel circuit SPC2 through the connection pattern BAP described later and any one of the fourth to sixth subpixel electrodes SAE4, SAE5 and SAE6.

[0193] The fourth to sixth subpixel electrodes SAE4, SAE5, and SAE6 and the fourth to sixth replica pixel electrodes CPE4, CPE5, and CPE6 may perform the same functions as those of the subpixel electrodes and the replica pixel electrodes disposed in the first sub display area SDA1. For example, the fourth to sixth subpixel electrodes SAE4, SAE5, and SAE6 and the fourth to sixth replica pixel electrodes CPE4, CPE5, and CPE6 may be used as anode electrodes of the light emitting elements EL disposed in the second sub display area SDA2. The light emitting elements EL each including one of the fourth to sixth subpixel electrodes SAE4, SAE5, and SAE6 and the fourth to sixth replica pixel electrodes CPE4, CPE5, and CPE6 electrically connected to each other may emit light simultaneously (e.g., concurrently).

[0194] According to one or more embodiments, the display device 10 may include a second pixel defining layer 132 and a connection pattern BAP disposed in the second sub display area SDA2. The connection pattern BAP and the second pixel defining layer 132 may have a stacked structure on the third interlayer insulating layer ILD3 and may have substantially the same planar pattern. For example, the connection pattern BAP and the second pixel defining layer 132 may be disposed substantially throughout the entire second sub display area SDA2 except for some areas. The connection pattern BAP and the second pixel defining layer 132 may be disposed so that a plurality of sub pixel electrodes SAE4, SAE5, and SAE6 and a plurality of replica pixel electrodes CPE4, CPE5, and CPE6 of the second sub display area SDA2 are partially exposed.

[0195] The connection pattern BAP and the second pixel defining layer 132 may not be disposed in the valley VA formed around one of the pair of sub-pixel electrodes SAE4, SAE5, and SAE6 and one of the replica pixel electrodes CPE4, CPE5, and CPE6 (e.g., around one of the pair of sub-pixel electrodes SAE4, SAE5, and SAE6 and one of the replica pixel electrodes CPE4, CPE5, and CPE6). The valley VA may be an area where the connection pattern BAP and the second pixel defining layer 132 are substantially not disposed. For example, the valley VA may be around one fourth sub-pixel electrode SAE4 and one fourth replica pixel electrode CPE4 (e.g., around one fourth sub-pixel electrode SAE4 and one fourth replica pixel electrode CPE4). In addition, the valley VA may be around one fifth sub-pixel electrode SAE5 and one fifth replica pixel electrode CPE5 (e.g., around one fifth sub-pixel electrode SAE5 and one fifth replica pixel electrode CPE5), and may be around one sixth sub-pixel electrode SAE6 and one sixth replica pixel electrode CPE6. The valley VA may have an atypical pattern shape in the second sub-display area SDA2, and may have a partially closed loop shape around (for example, surrounding) one of a pair of sub-pixel electrodes SAE4, SAE5, and SAE6 and one of the replica pixel electrodes CPE4, CPE5, and CPE6.

[0196] In the second sub-display area SAD2, the connection pattern BAP and the second pixel defining layer 132 may be disposed in an area other than the area where the valley VA is located. In the area surrounded by the valley VA, the connection pattern BAP may be disposed in the same layer (e.g., at) as the sub-pixel electrodes SAE4, SAE5, and SAE6 and the replica pixel electrodes CPE4, CPE5, and CPE6, and one of a pair of sub-pixel electrodes SAE4, SAE5, and SAE6 and one of the replica pixel electrodes CPE4, CPE5, and CPE6 may be connected to each other through the connection pattern BAP. Hereinafter, the cross-sectional structure of the second pixel defining layer 132, the pixel electrode, and the connection pattern BAP disposed in the second sub-display area SDA2 will be described in more detail with reference to other drawings.

[0197] Fig.12 is a cross-sectional view illustrating connection between a pixel electrode and a connection pattern provided in a second sub display area of ​​a display device according to one or more embodiments. Fig.13 It is specifically shown that the setting Fig.12 A cross-sectional view of a connection between a pixel electrode and a connection pattern in a second sub-display area.

[0198] Apart from Fig. 9 and Fig.11 In addition, refer to Fig.12 and Fig.13 , the connection pattern BAP may be disposed on the third interlayer insulating layer ILD3. The connection pattern BAP may be disposed on the same layer (e.g., at) as the sub-pixel electrodes SAE4, SAE5, and SAE6 and the replica pixel electrodes CPE4, CPE5, and CPE6 of the second sub-display area SDA2, and may be partially disposed on the sub-pixel electrodes SAE4, SAE5, and SAE6 and the replica pixel electrodes CPE4, CPE5, and CPE6. For example, the connection pattern BAP may partially cover the side surfaces and top surfaces of the sub-pixel electrodes SAE4, SAE5, and SAE6 and the replica pixel electrodes CPE4, CPE5, and CPE6, and may be in contact with the side surfaces and top surfaces of the sub-pixel electrodes SAE4, SAE5, and SAE6 and the replica pixel electrodes CPE4, CPE5, and CPE6. The light-emitting layer EML may be disposed on a portion of the top surface of the sub-pixel electrodes SAE4, SAE5, and SAE6 and the replica pixel electrodes CPE4, CPE5, and CPE6 where the connection pattern BAP is not disposed.

[0199] In one or more embodiments, the connection pattern BAP may transmit light and may include a material having conductivity. For example, the connection pattern BAP may include at least one of IZO, IGZO, ITGZO, ITO, ITZO, ITGO, and IGO.

[0200] The second pixel defining layer 132 may be disposed on the connection pattern BAP. The second pixel defining layer 132 may be disposed on the entire connection pattern BAP, and may expose a portion of the top surface of the sub-pixel electrodes SAE4, SAE5, and SAE6 and the replica pixel electrodes CPE4, CPE5, and CPE6, while partially overlapping the top surfaces of the sub-pixel electrodes SAE4, SAE5, and SAE6 and the replica pixel electrodes CPE4, CPE5, and CPE6. For example, the second pixel defining layer 132 may include a plurality of openings to expose the sub-pixel electrodes SAE4, SAE5, and SAE6 and the replica pixel electrodes CPE4, CPE5, and CPE6, and the light emitting layer EML forming the light emitting element EL may be disposed on the sub-pixel electrodes SAE4, SAE5, and SAE6 and the replica pixel electrodes CPE4, CPE5, and CPE6 in the openings of the second pixel defining layer 132.

[0201] According to one or more embodiments, the second pixel defining layer 132 may include an inorganic insulating material. For example, the second pixel defining layer 132 may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride and / or silicon oxynitride. In the display device 10, the first pixel defining layer 131 including an organic insulating material may be disposed in the main display area MDA and the first sub-display area SDA1, and the second pixel defining layer 132 including an inorganic insulating material may be disposed in the second sub-display area SDA2. The thin second pixel defining layer 132 may be disposed in the second sub-display area SDA2 to ensure light transmittance.

[0202] According to one or more embodiments, the second pixel defining layer 132 may be spaced apart from the top surface of the sub-pixel electrodes SAE4, SAE5, and SAE6 and the replica pixel electrodes CPE4, CPE5, and CPE6. The second pixel defining layer 132 may not be in direct contact with the sub-pixel electrodes SAE4, SAE5, and SAE6 and the replica pixel electrodes CPE4, CPE5, and CPE6, while partially overlapping the sub-pixel electrodes SAE4, SAE5, and SAE6 and the replica pixel electrodes CPE4, CPE5, and CPE6, and the connection pattern BAP may be disposed between the second pixel defining layer 132 and the sub-pixel electrodes SAE4, SAE5, and SAE6 and the replica pixel electrodes CPE4, CPE5, and CPE6. The connection pattern BAP may be disposed under the second pixel defining layer 132 in a substantially identical pattern, and may be disposed to be recessed from the inner sidewall of the second pixel defining layer 132 at the opening of the second pixel defining layer 132. A space in which the connection pattern BAP is recessed inwardly may be formed between the bottom surface of the second pixel defining layer 132 and the top surfaces of the sub-pixel electrodes SAE4, SAE5, and SAE6 and the replica pixel electrodes CPE4, CPE5, and CPE6. The light emitting layer EML may be disposed in the opening of the second pixel defining layer 132, and the space formed by the second pixel defining layer 132, the connection pattern BAP, and the pixel electrode may be filled with the light emitting layer EML.

[0203] In the process of removing the layer formed to completely cover the third interlayer insulating layer ILD3 and the pixel electrode along the opening of the second pixel defining layer 132 , the shape of the connection pattern BAP may be formed by partially removing a portion disposed under the second pixel defining layer 132 .

[0204] According to one or more embodiments, the second pixel defining layer 132 may include a valley VA that does not overlap the pixel electrode of the second sub-display area SDA2 but exposes the layer therebelow, and the connection pattern BAP may not be disposed at the valley VA. The second pixel defining layer 132 and the connection pattern BAP disposed on both sides of the valley VA may be spaced apart from each other. Even at the valley VA of the second pixel defining layer 132, the connection pattern BAP may be recessed inward from the bottom surface of the second pixel defining layer 132, and the third interlayer insulating layer ILD3 may be exposed. The shape of the connection pattern BAP at the valley VA of the second pixel defining layer 132 may also be a structure formed by further etching a portion of the connection pattern BAP disposed below the second pixel defining layer 132.

[0205] Therefore, the connection pattern BAP may be completely separated from another connection pattern BAP disposed on the opposite side relative to the valley VA. The connection pattern BAP is partially removed at the opening of the valley VA and the second pixel defining layer 132, but may have a single pattern shape in the region surrounded by the valley VA in a closed loop shape. The connection pattern BAP disposed in the region surrounded by the valley VA may be connected to one of the sub-pixel electrodes SAE4, SAE5, and SAE6 and at least one of the replica pixel electrodes CPE4, CPE5, and CPE6. For example, the fourth sub-pixel electrode SAE4 and the fourth replica pixel electrode CPE4 may be disposed in the region surrounded by the valley VA, and may both be in contact with one connection pattern BAP disposed in the region surrounded by the valley VA. Each of the fifth sub-pixel electrode SAE5 and the fifth replica pixel electrode CPE5 may also be in contact with one connection pattern BAP disposed in the region surrounded by the valley VA. However, because the connection patterns BAP disposed in different regions surrounded by the valley VA are completely separated at the valley VA, the fourth sub-pixel electrode SAE4 may not be connected to the fifth sub-pixel electrode SAE5 and the fifth replica pixel electrode CPE5. One of a pair of sub-pixel electrodes SAE4, SAE5 and SAE6 disposed together in an area surrounded by the valley VA in the second sub-display area SDA2 and one of the duplicate pixel electrodes CPE4, CPE5 and CPE6 may be electrically connected to each other and driven simultaneously (e.g., concurrently). On the other hand, the sub-pixel electrodes SAE4, SAE5 and SAE6 disposed in different areas surrounded by the valley VA may be driven individually.

[0206] The second sub-pixel circuit SPC2 disposed in the first sub-display area SDA1 may be electrically connected to the fourth sub-pixel electrode SAE4. The third connection electrode CNE3 of the second sub-pixel circuit SPC2 may be connected to the first bridge pattern BRE1 disposed on the second interlayer insulating layer ILD2 through the sixth contact hole CT6, and the first bridge pattern BRE1 may contact the fourth sub-pixel electrode SAE4 through the seventh contact hole CT7 penetrating the third interlayer insulating layer ILD3. Optionally, the third connection electrode CNE3 may be connected to the third bridge pattern BRE3 disposed on the first interlayer insulating layer ILD1 through another contact hole, and the third bridge pattern BRE3 may be connected to the second bridge pattern BRE2 through the eighth contact hole CT8 penetrating the second interlayer insulating layer ILD2. The second bridge pattern BRE2 may contact the fifth sub-pixel electrode SAE5 disposed on the third interlayer insulating layer ILD3. Fig.11 A structure is shown in which the second sub-pixel circuit SPC2 is electrically connected to the fourth sub-pixel electrode SAE4, and the second sub-pixel circuit SPC2 not shown in the drawing may be connected to the fifth sub-pixel electrode SAE5.

[0207] The fourth replica pixel electrode CPE4 disposed in the second sub display area SDA2 may be electrically connected to the fourth sub pixel electrode SAE4. As described above, the fourth replica pixel electrode CPE4 may be electrically connected to the fourth sub pixel electrode SAE4 through the connection pattern BAP. The fourth sub pixel electrode SAE4 and the fourth replica pixel electrode CPE4 are disposed not to overlap with the second sub pixel circuit SPC2, but may be electrically connected to the second sub pixel circuit SPC2 through the bridge patterns BRE1, BRE2 and BRE3 and the connection pattern BAP.

[0208] In one or more embodiments, each of the first bridge pattern BRE1 and the third bridge pattern BRE3 may be arranged to extend from the first sub display area SDA1 to the second sub display area SDA2. One first bridge pattern BRE1 may be arranged to overlap at least one of the sub pixel electrodes SAE4, SAE5, and SAE6. On the other hand, the third bridge pattern BRE3 may not necessarily overlap the sub pixel electrodes SAE4, SAE5, and SAE6. However, the second bridge pattern BRE2 connecting the third bridge pattern BRE3 with one of the sub pixel electrodes SAE4, SAE5, and SAE6 may overlap at least one of the sub pixel electrodes SAE4, SAE5, and SAE6.

[0209] The fourth sub-pixel electrode SAE4 and the fourth replica pixel electrode CPE4 may overlap the opening of the second pixel defining layer 132, and may constitute a light emitting element EL together with a light emitting layer EML disposed at the opening and a common electrode CE disposed on the light emitting layer EML. An electrical signal for light emission of the light emitting element EL may be simultaneously (e.g., concurrently) applied to the fourth sub-pixel electrode SAE4 and the fourth replica pixel electrode CPE4, and the light emitting element EL including each of the fourth sub-pixel electrode SAE4 and the fourth replica pixel electrode CPE4 may simultaneously (e.g., concurrently) emit light. The light emitting layer EML disposed on the fourth sub-pixel electrode SAE4 and the fourth replica pixel electrode CPE4 may be a light emitting layer that emits light of the same color.

[0210] The connection pattern BAP may be in contact with the side surfaces and top surfaces of the sub-pixel electrodes SAE4, SAE5, and SAE6 and the replica pixel electrodes CPE4, CPE5, and CPE6 in the second sub-display area SDA2. In one or more embodiments, the pixel electrode AE, the sub-pixel electrode SAE, and the replica pixel electrode CPE of the display device 10 may have a structure in which one or more electrode layers ET1, ET2, and ET3 are stacked, and the connection pattern BAP may be in contact with the side surfaces or top surfaces of the electrode layers ET1, ET2, and ET3. For example, each of the pixel electrode AE, the sub-pixel electrode SAE, and the replica pixel electrode CPE may include a first electrode layer ET1, a second electrode layer ET2 disposed on the first electrode layer ET1, and a third electrode layer ET3 disposed on the second electrode layer ET2. The first electrode layer ET1 of each of the sub-pixel electrodes SAE4, SAE5, and SAE6 may be in contact with any one of the bridge patterns BRE1, BRE2, and BRE3. The connection pattern BAP may contact side surfaces of the first, second and third electrode layers ET1, ET2 and ET3 of each of the sub-pixel electrode SAE and the replica pixel electrode CPE. In addition, the connection pattern BAP may also contact a portion of the top surface of the third electrode layer ET3.

[0211] The common electrode CE may be disposed throughout the entire main display area MDA and the entire sub-display area SDA. In the second sub-display area SDA2, the common electrode CE may be disposed on the second pixel defining layer 132 and the plurality of light-emitting layers EML. The common electrode CE may also be disposed on the sidewall of the valley VA of the second pixel defining layer 132. Because the third interlayer insulating layer ILD3 is exposed at the valley VA of the second pixel defining layer 132, the common electrode CE may be in direct contact with the third interlayer insulating layer ILD3. In addition, the connection pattern BAP is recessed inwardly on the bottom surface of the second pixel defining layer 132 at the valley VA of the second pixel defining layer 132, so that the common electrode CE may be spaced apart from the connection pattern BAP.

[0212] In the display device 10 according to one or more embodiments, the interlayer insulating layers ILD1, ILD2, and ILD3 and the second pixel defining layer 132 are included in the second sub display area SDA2, so that the arrangement of the organic insulating material can be reduced or minimized. The first pixel defining layer 131, the sixth insulating layer 128, and the seventh insulating layer 129 including the organic insulating material may not be disposed in the second sub display area SDA2. That is, the first pixel defining layer 131, the sixth insulating layer 128, and the seventh insulating layer 129 may not overlap with the connection pattern BAP and the sub-pixel electrode SAE and the replica pixel electrode CPE disposed in the second sub display area SDA2.

[0213] The display device 10 can ensure sufficient light transmittance in the second sub-display area SDA2 by reducing or minimizing the arrangement of the organic insulating material. In addition, the display device 10 may include a connection pattern BAP having a pattern substantially the same as that of the second pixel defining layer 132 and spaced apart from each other relative to the valley VA, so that the sub-pixel electrode and the replica pixel electrode can be connected. In the display device 10, the connection patterns BAP distinguished from each other can be formed by a deposition process and an etching process without an additional mask process, so that the manufacturing process can be reduced.

[0214] Hereinafter, a manufacturing process of a structure provided in the second sub display area SDA2 of the display device 10 will be described with reference to other drawings.

[0215] Figures 14 to 28 are views sequentially illustrating a manufacturing process of a display device according to one or more embodiments. Figures 14 to 28 The processes of forming a plurality of sub-pixel electrodes and a replica pixel electrode, a connection pattern BAP, and a second pixel defining layer 132 in the second sub display area SDA2 of the display device 10 are sequentially illustrated.

[0216] Reference Fig.14 and Fig.15 , a plurality of sub-pixel electrodes SAE4, SAE5, and SAE6 and a plurality of replica pixel electrodes CPE4, CPE5, and CPE6 are formed on the third interlayer insulating layer ILD3 in the second sub display area SDA2 of the display device 10. In one or more embodiments, a layer disposed below the third interlayer insulating layer ILD3 may be formed by a typical deposition process, an etching process, and a mask process, and its structure is the same as described above, so that a detailed description thereof will be omitted. Fig.14 1 and 2 show a plurality of sub-pixel electrodes SAE4, SAE5 and SAE6 and a plurality of replica pixel electrodes CPE4, CPE5 and CPE6 disposed in the second sub-display pixel SDX2 of the second sub-display area SDA2. Fig.15 A fourth sub-pixel electrode SAE4, a fifth sub-pixel electrode SAE5 and a fourth replica pixel electrode CPE4 are shown.

[0217] The fourth sub-pixel electrode SAE4 may be connected to the first bridge pattern BRE1, and the fifth sub-pixel electrode SAE5 may be connected to the second bridge pattern BRE2 and the third bridge pattern BRE3. On the other hand, the fourth replica pixel electrode CPE4 may not be connected to the bridge patterns BRE1, BRE2, and BRE3. However, Fig.15 The sub-pixel electrodes SAE4, SAE5, and SAE6 and the bridge patterns BRE1, BRE2, and BRE3 shown in FIG. 1 are merely one example, and the display device 10 is not necessarily limited to this structure.

[0218] Next, refer to Figures 16 to 19 , a connection pattern layer BAL and an inorganic insulating layer 132_1 are sequentially formed on the third interlayer insulating layer ILD3, the plurality of sub-pixel electrodes SAE, and the plurality of replica pixel electrodes CPE. The connection pattern layer BAL may be disposed to cover all the sub-pixel electrodes SAE and the replica pixel electrodes CPE disposed on the third interlayer insulating layer ILD3, and the inorganic insulating layer 132_1 may be disposed on the connection pattern layer BAL. The connection pattern layer BAL may be patterned in a subsequent process to form a connection pattern BAP, and the inorganic insulating layer 132_1 may be patterned in a subsequent process to form a second pixel defining layer 132.

[0219] Next, refer to Fig. 20 and Fig.21 , a photoresist PR including a plurality of openings OP is formed on the inorganic insulating layer 132_1. The photoresist PR may include a plurality of openings OP overlapping the sub-pixel electrode SAE and the replica pixel electrode CPE. Some of the openings OP may be formed in a region that does not overlap the sub-pixel electrode SAE and the replica pixel electrode CPE. However, the openings OP that do not overlap the sub-pixel electrode SAE and the replica pixel electrode CPE may have a closed loop shape in a plan view and may be around one of a pair of sub-pixel electrodes SAE and one of the replica pixel electrodes CPE (e.g., may surround one of a pair of sub-pixel electrodes SAE and one of the replica pixel electrodes CPE).

[0220] Next, refer to Fig. 22 and Fig.23 , a first etching process (first etching) for forming the second pixel defining layer 132 by patterning the inorganic insulating layer 132_1 along the opening OP of the photoresist PR is performed. In this process, in the inorganic insulating layer 132_1, the area where the opening OP of the photoresist PR is located may be etched, and the portion overlapping the sub-pixel electrode SAE and the replica pixel electrode CPE may be removed. In addition, in the inorganic insulating layer 132_1, the portion of the opening OP in a closed loop shape around one of a pair of sub-pixel electrodes SAE and one of the replica pixel electrodes CPE (for example, around one of a pair of sub-pixel electrodes SAE and one of the replica pixel electrodes CPE) may also be removed. The connection pattern layer BAL may be exposed at the portion where the inorganic insulating layer 132_1 is etched and removed. The second pixel defining layer 132 may be formed in this process. In one or more embodiments, the first etching process (first etching) may be a dry etching process.

[0221] Next, refer to Figure 24 to Figure 27, after removing the photoresist PR, a second etching process (second etching) for etching the connection pattern layer BAL along the opening OP of the second pixel defining layer 132 is performed. For example, the photoresist PR may be removed by a stripping process, but the present disclosure is not limited thereto. In this process, the connection pattern layer BAL may be partially etched to form a connection pattern BAP. The connection pattern BAP remaining in the second etching process (second etching) may be used as a bridging electrode for one of a pair of sub-pixel electrodes SAE4, SAE5, and SAE6 and one of the duplicate pixel electrodes CPE4, CPE5, and CPE6 in the second sub-display area SDA2.

[0222] In one or more embodiments, the connection pattern layer BAL may include a material different from that of the inorganic insulating layer 132_1. As described above, the connection pattern BAP and the connection pattern layer BAL may include at least one of IZO, IGZO, ITGZO, ITO, ITZO, ITGO, and IGO, and may prevent the sub-pixel electrodes SAE4, SAE5, and SAE6 and the replica pixel electrodes CPE4, CPE5, and CPE6 disposed thereunder from being damaged in the first etching process (first etching) as the etching process of the inorganic insulating layer 132_1.

[0223] The area of ​​the connection pattern layer BAL exposed by the opening OP of the second pixel defining layer 132 may be removed, and the top surfaces of the sub-pixel electrode SAE and the replica pixel electrode CPE may be partially exposed at the portion where the connection pattern layer BAL is etched and removed. Here, the portion of the connection pattern layer BAL covered by the second pixel defining layer 132 may be further etched. Therefore, the connection pattern BAP may be recessed at the portion where the sub-pixel electrode SAE and the replica pixel electrode CPE are exposed by the opening of the second pixel defining layer 132 and located on the bottom surface of the second pixel defining layer 132.

[0224] In addition, in the region of the opening of the second pixel defining layer 132 having a closed loop shape and around (e.g., surrounding) a pair of sub-pixel electrodes SAE and the replica pixel electrode CPE, the connection pattern layer BAL may be partially removed to form a valley VA. A plurality of connection patterns BAP may be spaced apart and distinguished from each other relative to the valley VA. In one or more embodiments, the second etching process (second etching) may be a wet etching process.

[0225] Next, refer to Fig.28 , a light emitting layer EML may be formed on the sub-pixel electrode SAE and the replica pixel electrode CPE exposed through the opening of the second pixel defining layer 132 , and a common electrode CE, an encapsulation layer 140 , etc. may be formed on the light emitting layer EML, thereby manufacturing the display device 10 .

[0226] Fig.29 is a diagram illustrating one pixel of a second sub display area of ​​a display device according to one or more embodiments.

[0227] Reference Fig.29 In the display device 10 according to one or more embodiments, in the second sub display area SDA2, one fifth sub pixel electrode SAE5 may be electrically connected to three fifth replica pixel electrodes CPE5. Figure 8 The embodiment of is different in that some sub-pixel electrodes (eg, the fifth sub-pixel electrode SAE5 ) may be driven simultaneously (eg, concurrently) in groups with one or more replica pixel electrodes CPE.

[0228] The display device 10 can adjust the configuration of the light emitting element emitting light of a specific color by adjusting the number of pixel electrodes AE constituting one pixel PX. Similarly, the number of duplicate pixel electrodes CPE connected to one sub-pixel electrode SAE in the second sub-display area SDA2 can be adjusted to adjust the number of light emitting elements emitting light of a specific color in the corresponding sub-display pixel (e.g., the second sub-display pixel SDX2).

[0229] Because a greater number of replica pixel electrodes CPE are disposed in the second sub-display area SDA2, the planar shape of the valley VA or the connection pattern BAP may be changed. However, as described above, the shape of the valley VA may be changed differently depending on the number and arrangement of the sub-pixel electrodes SAE and the replica pixel electrodes CPE forming a group, and the shape of the connection pattern BAP may also be changed depending on the closed-loop shape of the valley VA. Because the pixel structure of the sub-display areas SDA1 and SDA2 is different from the pixel structure of the main display area MDA, the display device 10 may partially have a low resolution, but the resolution difference may be compensated by adjusting the number of the sub-pixel electrodes SAE and the replica pixel electrodes CPE forming a group.

[0230] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the embodiments without departing substantially from the spirit, scope and principles of the present disclosure. Therefore, the embodiments of the present disclosure are used only in a general and descriptive sense, and not for a limiting purpose.

Claims

1. A display device, comprising: a main display area and a first sub-display area and a second sub-display area, the first sub-display area and the second sub-display area being surrounded by the main display area and positioned adjacent to each other; A plurality of pixel electrodes, located in the main display area and spaced apart from each other; a plurality of first sub-pixel electrodes, located in the first sub-display area and spaced apart from each other; a plurality of first duplicate pixel electrodes, located in the first sub-display area and connected to the plurality of first sub-pixel electrodes via a first bridging electrode; a first pixel defining layer, located in the main display area and the first sub-display area, and having a plurality of openings therein respectively overlapping the plurality of pixel electrodes, the plurality of first sub-pixel electrodes, and the plurality of first replica pixel electrodes; a plurality of second sub-pixel electrodes and a plurality of second duplicate pixel electrodes, located in the second sub-display area and spaced apart from each other; a plurality of connection patterns, located in the second sub-display area and each connected to one of the plurality of second sub-pixel electrodes and one of the plurality of second replica pixel electrodes; as well as a second pixel defining layer, which is located on the plurality of connection patterns and has a plurality of openings therein respectively overlapping the plurality of second sub-pixel electrodes and the plurality of second replica pixel electrodes, The second pixel defining layer includes a valley around a second sub-pixel electrode among the plurality of second sub-pixel electrodes and a second replica pixel electrode among the plurality of second replica pixel electrodes, and the second sub-pixel electrode and the second replica pixel electrode are connected to each other through a connection pattern among the plurality of connection patterns.

2. The display device according to claim 1, wherein: The connection pattern is recessed inwardly from a sidewall of the valley and an opening among the plurality of openings of the second pixel defining layer.

3. The display device according to claim 1, wherein: The plurality of connection patterns are separated from each other with respect to the valley portion of the second pixel defining layer.

4. The display device according to claim 1, wherein: The connection pattern contacts a side surface of each of the second sub-pixel electrode and the second replica pixel electrode.

5. The display device according to claim 4, wherein: The connection pattern contacts a portion of a top surface of each of the second sub-pixel electrode and the second replica pixel electrode.

6. The display device according to claim 1, further comprising a common electrode, wherein the common electrode is located in the main display area, the first sub-display area, and the second sub-display area. in, The common electrode is located in the valley of the second pixel defining layer in the second sub-display area.

7. The display device according to claim 6, wherein: The common electrode does not contact the connection pattern.

8. The display device according to claim 1, wherein: The first pixel defining layer includes an organic insulating material, and the second pixel defining layer includes an inorganic insulating material. 9 . The display device of claim 1 , further comprising a first bridge pattern extending from the first sub display area to the second sub display area and connected to one second sub pixel electrode among the plurality of second sub pixel electrodes.

10. The display device according to claim 9, further comprising: a second bridge pattern overlapping another second sub-pixel electrode among the plurality of second sub-pixel electrodes; as well as A third bridge pattern connected to the second bridge pattern and extending from the first sub display area to the second sub display area.

11. The display device according to claim 10, further comprising a plurality of interlayer insulating layers, wherein the plurality of interlayer insulating layers are located in the second sub-display area. in, The first bridge pattern and the second bridge pattern are located on an interlayer insulation layer among the plurality of interlayer insulation layers, the interlayer insulation layer being different from another interlayer insulation layer among the plurality of interlayer insulation layers on which the third bridge pattern is located.

12. The display device according to claim 9, further comprising a plurality of first sub-pixel circuits and a plurality of second sub-pixel circuits, wherein the plurality of first sub-pixel circuits and the plurality of second sub-pixel circuits are located in the first sub-display area, in, The plurality of first sub-pixel electrodes overlap with at least one of the plurality of first sub-pixel circuits, at least some of the plurality of first replica pixel electrodes overlap with at least one of the plurality of second sub-pixel circuits, and the first bridge pattern is electrically connected to one of the plurality of second sub-pixel circuits.

13. The display device according to claim 1, further comprising: A first interlayer insulating layer is located in the main display area, the first sub-display area and the second sub-display area; as well as a first insulating layer, located on the first interlayer insulating layer and located in the main display area and the first sub-display area, The first insulating layer includes an organic insulating material, and the first interlayer insulating layer includes an inorganic insulating material.

14. The display device according to claim 13, wherein: The first insulating layer does not overlap the connection pattern, the second sub-pixel electrode, and the second replica pixel electrode.

15. The display device according to claim 1, wherein: The plurality of first sub-pixel electrodes, the plurality of first replica pixel electrodes and the first bridging electrode located in the first sub-display area are integrated into one.

16. A method for manufacturing a display device, the method comprising the following steps: preparing a substrate having a plurality of bridge patterns and an interlayer insulating layer on the plurality of bridge patterns, and forming a plurality of sub-pixel electrodes and a plurality of replica pixel electrodes spaced apart from each other on the interlayer insulating layer; forming a connection pattern layer on the interlayer insulating layer and covering the plurality of sub-pixel electrodes and the plurality of replica pixel electrodes, and forming an inorganic insulating layer on the connection pattern layer; forming a photoresist including a plurality of openings on the inorganic insulating layer, some of the plurality of openings surrounding a pair of sub-pixel electrodes and a replica pixel electrode without overlapping the plurality of sub-pixel electrodes and the plurality of replica pixel electrodes, and other of the plurality of openings overlapping at least one of the plurality of sub-pixel electrodes and the plurality of replica pixel electrodes; forming a pixel defining layer by etching the inorganic insulating layer along the opening of the photoresist, and etching the connection pattern layer along the opening formed in the pixel defining layer to partially expose top surfaces of the sub-pixel electrode and the replica pixel electrode; as well as A light emitting layer is formed on each of the sub-pixel electrode and the replica pixel electrode, and a common electrode is formed on the light emitting layer and the pixel defining layer.

17. The method according to claim 16, wherein: The pixel defining layer includes a valley formed by etching along an opening among the plurality of openings around the pair of sub-pixel electrodes and the replica pixel electrode, and in forming the connection pattern layer, the connection pattern layer is etched along the valley to form a plurality of connection patterns separated from each other relative to the valley.

18. The method according to claim 17, wherein: The connection pattern contacts each of the pair of sub-pixel electrodes and the replica pixel electrode.

19. The method according to claim 17, wherein: In forming the connection pattern layer, the connection pattern layer is etched along the opening of the pixel defining layer, and the connection pattern partially exposes the top surfaces of the sub-pixel electrode and the replica pixel electrode.

20. The method according to claim 17, wherein: The connection pattern is recessed inwardly from a sidewall of the valley and the opening of the pixel defining layer.

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