Frequency mixing

Abstract

An apparatus for mixing a signal is disclosed. In an example aspect, the apparatus includes a mixer circuit having a plurality of local oscillator nodes, a first node corresponding to a first frequency, and a plurality of second nodes corresponding to a second frequency. The mixer circuit includes a plurality of capacitors coupled between the plurality of local oscillator nodes and the plurality of second nodes. The mixer circuit has a plurality of switches including a first switch, a second switch, a third switch, and a fourth switch. The plurality of switches are coupled between the plurality of capacitors and the plurality of second nodes. The first switch and the second switch are coupled between the plurality of capacitors and the first node. The first switch and the second switch are arranged between the fourth switch and the third switch.

Description

Technical Field

[0001] The present disclosure relates generally to signal communication or signal processing using electronic devices, and more particularly, to mixer circuits that can be used for frequency conversion. Background Art

[0002] Electronic devices include traditional computing devices such as desktop computers, laptops, smart phones, wearable devices such as smart watches, Internet servers, etc. Electronic devices also include other types of computing devices such as personal voice assistants (e.g., smart speakers), wireless access points or routers, thermostats and other automation controllers, robots, automotive electronics, devices embedded in other machines such as refrigerators and industrial tools, Internet of Things (IoT) devices, medical devices, etc. These different electronic devices provide services related to productivity, communication, social interaction, security, health and safety, remote management, entertainment, transportation, and information dissemination. Therefore, electronic devices play a vital role in modern society.

[0003] In today's connected world, many services provided by electronic devices rely at least in part on electronic communications. Electronic communications may include, for example, the use of Electronic communications are those communications in which wireless signals or wired signals are exchanged between two or more electronic devices using a wireless network (such as a wireless or cellular network). Thus, electronic communications may include wireless transmission and reception or wired transmission and reception. To send and receive communications, electronic devices may use a transceiver, such as a wireless transceiver designed for wireless communications.

[0004] Thus, electronic communication may be achieved by propagating signals between two wireless transceivers at two different electronic devices. For example, using a wireless transmitter, a smartphone may send wireless signals to a base station over the air (as part of an uplink communication) to support mobile services. Using a wireless receiver, a smartphone may receive wireless signals sent from a base station via an air medium (as part of a downlink communication) to enable mobile services. In the case of a smartphone, mobile services may include making voice and video calls, engaging in social media interactions, transmitting messages, watching movies, sharing videos, performing searches, using map information or navigation instructions, finding friends, engaging in generally location-based services, transferring money, obtaining another service such as a car ride, and the like.

[0005] Many of these mobile services rely, at least in part, on the transmission or reception of wireless signals between two or more electronic devices. Accordingly, researchers, electrical engineers, and designers of electronic devices strive to develop wireless transceivers that can efficiently use wireless signals to provide these and other mobile services. Summary of the invention

[0006] In order to send or receive wireless signals, a wireless transceiver or radio frequency (RF) front end may include a transmission chain or a reception chain that processes propagated signals. A portion of the signal processing may include converting a signal from a first frequency to a second frequency. A mixer circuit may perform frequency conversion using a local oscillator signal from a local oscillator (LO). The mixer circuit uses a plurality of switches to combine a first signal at a first frequency with a local oscillator signal to generate a second signal at a second frequency. For differential signaling at the input and / or output of the mixer circuit, the number of the plurality of switches may be four. In order to counteract noise from a local oscillator, this document describes how a plurality of switches may be symmetrically arranged on a substrate. For example, a first switch and a second switch may be positioned on different sides of a symmetry line. Additionally or alternatively, a third switch and a fourth switch may be arranged on opposite sides of the first switch and the second switch, so that the first switch and the second switch are "sandwiched" between the third switch and the fourth switch along an axis located in the plane of the substrate, wherein the axis is perpendicular to the symmetry line. In addition, area reduction and layout simplification may be promoted by using coupling capacitors and / or bias resistors that are each shared between at least two of the plurality of switches. In such cases, the local oscillator signal or the bias signal may propagate through a given capacitor or resistor, respectively, to reach at least two switches that share the capacitor or resistor.These and other implementations are described herein.

[0007] In an example aspect, a device for frequency mixing is disclosed. The device includes a mixer circuit. The mixer circuit includes a plurality of local oscillator nodes, a first node corresponding to a first frequency, and a plurality of second nodes corresponding to a second frequency. The mixer circuit also includes a plurality of capacitors coupled between the plurality of local oscillator nodes and the plurality of second nodes. The mixer circuit also includes a plurality of switches, the plurality of switches including a first switch, a second switch, a third switch, and a fourth switch. The plurality of switches are coupled between the plurality of capacitors and the plurality of second nodes. The first switch and the second switch are coupled between the plurality of capacitors and the first node. The first switch and the second switch are arranged between the fourth switch and the third switch.

[0008] In an example aspect, a device for frequency mixing is disclosed. The device includes a mixer circuit. The mixer includes a plurality of local oscillator nodes, a first node corresponding to a first frequency, and a plurality of second nodes corresponding to a second frequency. The mixer circuit also includes a plurality of capacitors and a plurality of switches. The plurality of capacitors are coupled between the plurality of local oscillator nodes and the plurality of second nodes. The plurality of switches include a first switch, a second switch, a third switch, and a fourth switch. The plurality of switches are coupled between the plurality of capacitors and the plurality of second nodes. The first switch and the second switch are coupled between the plurality of capacitors and the first node, and the third switch and the fourth switch are coupled to each other via a floating node. The mixer circuit also includes a component for increasing symmetric related linearity.

[0009] In an example aspect, a device for frequency mixing is disclosed. The device includes a mixer circuit. The mixer circuit includes a first local oscillator node, a second local oscillator node, and a first node corresponding to a first frequency. The mixer circuit also includes a first capacitor, a second capacitor, and a second node and a third node each corresponding to a second frequency. The mixer circuit additionally includes a first switch, a second switch, a third switch, and a fourth switch. The first switch is coupled between the first capacitor and the second node, and the first switch is further coupled between the first capacitor and the first node. The second switch is coupled between the second capacitor and the third node, and the second switch is further coupled between the second capacitor and the first node. The third switch is coupled between the first capacitor and the third node. The fourth switch is coupled between the second capacitor and the second node. The first capacitor is coupled between the first local oscillator node and the first switch and the third switch, and the second capacitor is coupled between the second local oscillator node and the fourth switch and the second switch.

[0010] In an example aspect, a method for mixing a signal is disclosed. The method includes receiving a first signal at a first switch and a second switch via a first node, the first signal corresponding to a first frequency. The method also includes receiving a positive local oscillator signal at the first switch and the third switch via a first capacitor, and receiving a negative local oscillator signal at the second switch and the fourth switch via a second capacitor. The method additionally includes using a first switch, a second switch, a third switch, and a fourth switch to mix the first signal, the positive local oscillator signal, and the negative local oscillator signal to generate a second signal, wherein the second signal corresponds to a second frequency. The method also includes providing a second signal from the first switch, the second switch, the third switch, and the fourth switch via a plurality of second nodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 An environment is illustrated having an example electronic device with a wireless interface device including at least one example mixer circuit.

[0012] Figure 2 is a schematic diagram illustrating an example radio frequency (RF) front end and an example transceiver that may each include at least one mixer circuit.

[0013] Figure 3 is a schematic diagram illustrating an example of a plurality of receive chains that may each include at least one frequency converter as part of a wireless interface device.

[0014] Figure 4 is a schematic diagram illustrating an example frequency converter including a mixer circuit and a local oscillator.

[0015] Figure 5 is a schematic diagram illustrating an example mixer circuit including a plurality of nodes, a plurality of switches, and a plurality of capacitors.

[0016] Figure 6 is a schematic diagram illustrating an example implementation of a plurality of switches including two switches symmetrically coupled to a node with respect to a line of symmetry.

[0017] Figure 7 is a circuit diagram illustrating an example mixer circuit including a plurality of nodes, a plurality of switches, a plurality of capacitors, and a plurality of resistors.

[0018] Figure 8 is a flow chart illustrating an example process for mixing signals and / or operating a mixer circuit. DETAILED DESCRIPTION

[0019] Introduction and Overview

[0020] To facilitate the transmission and reception of wireless signals, electronic devices may use wireless interface devices including wireless transceivers and / or radio frequency (RF) front ends. Electronic devices communicate using wireless signals using EM signaling at various frequencies present on a portion of the electromagnetic (EM) spectrum. These wireless signals may travel between two electronic devices while oscillating at a specific frequency, such as a kilohertz (kHz) frequency, a megahertz (MHz) frequency, or a gigahertz (GHz) frequency. However, the EM spectrum is a limited resource that limits how many signals can be communicated simultaneously in any given spatial region. There are already billions of electronic devices using this limited resource. In order to achieve a greater number of simultaneous communications using EM signaling, a limited EM spectrum may be shared between electronic devices. The EM spectrum may be shared using, for example, frequency division multiplexing (FDM) techniques and / or time division multiplexing (TDM) techniques.

[0021] FDM or TDM techniques may require dividing the EM spectrum into different frequency bands and restricting communications to the designated frequency bands. EM signals in different frequency bands can be communicated simultaneously in the same area without significantly interfering with each other. To transmit a signal within a target frequency band, a transceiver may apply a mixer to the signal to up-convert a relatively lower frequency to the target frequency band. To recover information carried by a signal received within the target frequency band, a transceiver may apply a mixer to the received signal to down-convert from the target frequency band to a lower frequency.

[0022] In order to perform frequency conversion, the mixer circuit operates in conjunction with a local oscillator that generates a local oscillator signal. The mixer circuit "combines" (e.g., multiplies) the input signal with the local oscillator signal to generate an output signal. The mixer circuit can be configured so that the output signal has a higher frequency than the input signal for up-conversion as part of processing a signal to be sent in a transmit chain. Alternatively, the mixer circuit can be configured so that the output signal has a lower frequency than the input signal for down-conversion as part of processing a received signal in a receive chain. The frequency of the output signal depends at least in part on the frequency of the local oscillator signal provided by the local oscillator.

[0023] Although local oscillators facilitate the frequency conversion process, they may introduce noise into the process through the local oscillator signal. Local oscillators can be coupled to different types of mixers, such as double-balanced mixers or single-balanced mixers. Double-balanced mixers use balanced signals (e.g., differential signaling) for both input and output signals. In contrast, single-balanced mixers use at least one unbalanced signal (e.g., single-ended signaling) for either input or output signals.

[0024] In some frequency conversion situations, a double balanced mixer can perform better than a single balanced mixer, for example in dealing with noise injected by a local oscillator signal. The balanced signals at the input and output of the mixer can cancel the injected noise at least to some extent. However, compared to a single balanced mixer, a double balanced mixer may occupy a relatively large area to perform frequency conversion. In other words, a single balanced mixer can occupy a relatively smaller area than a double balanced mixer. The smaller area is partly derived from the ability to omit the transformer, which usually occupies a relatively large space, from the unbalanced side of a single balanced mixer.

[0025] Unfortunately, the unbalanced signal of a single balanced mixer may handle injected noise relatively poorly compared to the two balanced signals of a double balanced mixer. Thus, the poorer noise handling of a single balanced mixer conflicts with the smaller area occupied by a single balanced mixer, and the smaller area may be an important advantage in certain implementations. In addition, in the case of unbalanced signaling, layout and routing may be significantly simplified. Consuming less area on a substrate and achieving simplified signal routing may translate into smaller or lower cost devices, including smaller and less expensive devices.

[0026] In addition, as the number of frequency bands in which the wireless interface device is expected to operate increases, smaller areas and simplified routing layouts may become increasingly important. As described above, the frequency range in which the device is expected to communicate is increasing, so that faster communication can be performed with higher bandwidths, and more devices are allowed to share limited EM spectrum at the same time. In addition to different frequency bands, electronic devices may also be expected to handle different access protocols, including access protocols associated with various wireless standards, such as access protocols for licensed assisted access (LAA). These different frequency bands and access protocols cause electronic devices to have an increased number of transmission and / or receiving paths, such as a larger number of transmission chains and / or receiving chains. In the case where each such path potentially includes at least one mixer circuit, the area and layout differences between a double-balanced mixer and a single-balanced mixer may become even more influential.

[0027] Therefore, the size and / or cost of the wireless interface device can be significantly reduced by using a single balanced mixer, and the size and / or cost of the corresponding electronic device of the wireless interface device can be reduced accordingly. This document describes an example method using a single balanced mixer, which at least partially compensates for the noise injected by the local oscillator signal provided by the local oscillator of the frequency converter. For example, component symmetry can be enhanced to reduce the noise factor. Additionally or alternatively, components can be shared to further simplify layout and signal routing. Implementing one or more of these technologies can enable the use of a single balanced mixer with its size and cost advantages to replace a double balanced mixer.

[0028] In general, the mixer circuit uses a plurality of switches to combine a first signal at a first frequency with a local oscillator signal at a local oscillator frequency to generate a second signal at a second frequency. The second frequency is different from the first frequency. The plurality of switches may have a number greater than two, such as four switches. In some specific implementations, in order to counter the noise from the local oscillator signal, at least a portion of the plurality of switches may be symmetrically arranged on the substrate relative to each other. For example, the first switch and the second switch in the plurality of switches may be positioned on either side of the symmetry line. Additionally or alternatively, the third switch and the fourth switch in the plurality of switches may be arranged on opposite sides of the first switch and the second switch, so that the first switch and the second switch are "sandwiched" between the third switch and the fourth switch along an axis located in the plane of the substrate. The axis may be at least substantially perpendicular to the symmetry line. In addition, the first switch and the second switch "sandwiched" by the third switch and the fourth switch may be coupled to the same node. This same node may correspond to an input or output of the mixer circuit and is configured to propagate a single-ended unbalanced signal.

[0029] In other specific implementations, area reduction and layout simplification can be promoted by adopting coupling capacitors and / or bias resistors that are each shared between at least two switches in a plurality of switches. With respect to a local oscillator, a local oscillator signal can propagate through a given capacitor to reach at least two switches in a plurality of switches. With respect to a power distribution network, a bias signal (e.g., a direct current (DC) voltage) can propagate through a given resistor to reach at least two switches. In some cases, at least two switches are not adjacent to each other, such as the first switch and the third switch in some of the depicted examples. If a plurality of switches are implemented using field effect transistors (FETs), the local oscillator signal and the bias signal can be coupled to the gate terminal of the FET. These and other specific implementations are described herein.

[0030] Description Example

[0031] Figure 1 An example environment 100 is illustrated with an electronic device 102 having a wireless interface device 120 including at least one example mixer circuit 130. This document describes an example implementation of the mixer circuit 130, which can be part of a transceiver, a radio frequency front end (RFFE), etc. of a device. In the environment 100, the example electronic device 102 communicates with a base station 104 via a wireless link 106. Figure 1, the electronic device 102 is depicted as a smart phone. However, the electronic device 102 may be implemented as any suitable computing device or other electronic device. Examples of devices that may be implemented as the electronic device 102 include cellular base stations, broadband routers, access points, cellular or mobile phones, gaming devices, navigation devices, media devices, laptop computers, desktop computers, tablet computers, and server computers. Other examples of devices that may be implemented as the electronic device 102 include network attached storage (NAS) devices, smart appliances, transportation-based communication systems, Internet of Things (IoT) devices, sensors or security devices, asset trackers, fitness management devices, wearable devices (such as smart glasses or smart watches), wireless power devices (transmitters or receivers), medical devices, etc.

[0032] The base station 104 communicates with the electronic device 102 via a wireless link 106, which may be implemented as any suitable type of wireless link that carries communication signals. Although depicted as a base station tower of a cellular radio network, the base station 104 may represent or be implemented as another device, such as a satellite, a terrestrial broadcast tower, an access point, a peer device, a mesh network node, a fiber optic line interface, another electronic device substantially as described above, etc. Thus, the wireless link 106 may extend between the electronic device 102 and the base station 104 in any of a variety of ways.

[0033] Wireless link 106 may include a downlink of data or control information communicated from base station 104 to electronic device 102. Wireless link 106 may also include an uplink of other data or control information communicated from electronic device 102 to base station 104. Wireless link 106 may be implemented using any suitable wireless communication protocol or standard. Examples of such protocols and standards include 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) standards, such as 4th Generation (4G), 5th Generation (5G), or 6th Generation (6G) cellular standards; IEEE 802.11 standards, such as 802.11g, ac, ax, ad, aj, or ay standards (e.g., 6 or ); IEEE 802.16 standards (e.g., ); standard; ultra-wideband (UWB) standard (eg, IEEE 802.15.4); etc. In some implementations, the wireless link 106 can provide power wirelessly, and the electronic device 102 or the base station 104 can include a power source.

[0034] As shown for some specific implementations, the electronic device 102 may include at least one application processor 108 and at least one computer-readable storage medium 110 (CRM 110). The application processor 108 may include any type of processor, such as a central processing unit (CPU) or a multi-core processor, configured to execute processor-executable instructions (e.g., code) stored by the CRM 110. The CRM 110 may include any suitable type of data storage medium, such as volatile memory (e.g., random-access memory (RAM)), non-volatile memory (e.g., flash memory), optical media (e.g., optical disks), magnetic media (e.g., disks or tapes), etc. In the context of the present disclosure, the CRM 110 is implemented to store instructions 112, data 114, and other information for the electronic device 102, and therefore the CRM 110 does not include transient propagating signals or carrier waves.

[0035] The electronic device 102 may also include one or more input / output ports 116 (I / O ports 116) and at least one display 118. The I / O ports 116 enable data exchange or interaction with other devices, networks, or users. The I / O ports 116 may include serial ports (e.g., Universal Serial Bus port), parallel port, audio port, infrared (IR) port, camera or other sensor port, etc. The display 118 may be implemented as a display screen or projection that presents graphic images provided by other components of the electronic device 102, such as a user interface (UI) associated with an operating system, program, or application. Alternatively or additionally, the display 118 may be implemented as a display port or virtual interface through which the graphic content of the electronic device 102 is communicated or presented.

[0036] The electronic device 102 also includes at least one wireless interface device 120 and at least one antenna 122. The example wireless interface device 120 provides connectivity to corresponding networks and peer devices via a wireless link, which can be configured similarly or differently to the wireless link 106. The wireless interface device 120 can facilitate communication over any suitable type of wireless network, such as a wireless local area network (LAN) (WLAN), a wireless personal area network (PAN) (WPAN), a peer-to-peer (P2P) network, a mesh network, a cellular network, a wireless wide area network (WAN) (WWAN), and / or a navigation network (e.g., a global positioning system (GPS) or another satellite positioning system (SPS) or a global navigation satellite system (GNSS) in North America). In the context of the example environment 100, the electronic device 102 can communicate various data and control information bidirectionally with the base station 104 via the wireless interface device 120. However, the electronic device 102 can communicate directly with other peer devices, alternative wireless networks, etc. In addition, as described above, the electronic device 102 can alternatively be implemented as a base station 104 or another device as described herein.

[0037] like Figure 1 As shown in , the wireless interface device 120 may include at least one communication processor 124, at least one transceiver 126, and at least one radio frequency front end 128 (RFFE 128). These components process data information, control information, and signals associated with transmitting information for the electronic device 102 via the antenna 122. The communication processor 124 may be implemented as at least a portion of a system on a chip (SoC), a modem processor, or a baseband radio processor (BBP) that implements a digital communication interface for data, voice, messaging, or other applications of the electronic device 102. The communication processor 124 may include a digital signal processor (DSP) or one or more signal processing blocks (not shown) for encoding and modulating data for transmission and for demodulating and decoding received data. Additionally, the communication processor 124 may also manage (e.g., control or configure) aspects or operations of the transceiver 126, the RF front end 128, and other components of the wireless interface device 120 to implement various communication protocols or communication technologies.

[0038] In some cases, the application processor 108 and the communication processor 124 may be combined into one module or integrated circuit (IC), such as a SoC. In any case, the application processor 108, the communication processor 124, or the processor generally may be operably coupled to one or more other components (such as the CRM 110 or the display 118) to enable control of various components of the electronic device 102 or other interactions with various components. For example, at least one processor 108 or 124 may present one or more graphic images on a display screen implementation of the display 118 based on one or more wireless signals communicated (e.g., sent or received) via at least one antenna 122 using a component of the wireless interface device 120. In addition, the application processor 108 or the communication processor 124 (including combinations thereof) may be implemented using digital circuits that implement the logic or functionality described herein. Additionally, the communication processor 124 may also include a memory (not separately depicted) (such as the same CRM 110 or another CRM) or be associated with the memory for storing data and processor executable instructions (e.g., code).

[0039] As shown, the wireless interface device 120 may include at least one mixer circuit 130 described below. More specifically, the transceiver 126 may include at least one mixer circuit 130-1, or the RF front end 128 may include at least one mixer circuit 130-2 (according to the optional but permitted "inclusive or" interpretation of the word "or", both components may have at least one mixer circuit 130). The transceiver 126 may also include circuits and logic for filtering, switching, amplification, channelization, frequency transfer, etc.

[0040] The frequency transfer functionality may include up-conversion or down-conversion of a frequency performed by a single conversion operation (e.g., using a direct conversion architecture) or by multiple conversion operations (e.g., using a superheterodyne architecture). The transceiver 126 may perform the above steps by using the mixer circuit 130-1 and an associated local oscillator ( Figure 1 In general, the transceiver 126 may include filters, switches, amplifiers, mixers, etc., for routing and conditioning signals transmitted or received via the antenna 122.

[0041] In addition to the mixer circuit 130-1, the transceiver 126 may also include an analog-to-digital converter (ADC) or a digital-to-analog converter (DAC) ( Figure 1124, a portion of the transceiver 126, or separate from both (e.g., as another part of the SoC or as part of the application processor 108).

[0042] The components or circuits of transceiver 126 may be implemented in any suitable manner, such as using combined transceiver logic or separately as respective transmitter and receiver entities. In some cases, transceiver 126 may be implemented using multiple or different parts to perform respective transmit and receive operations (e.g., using a plurality of components such as a transmitter and a receiver). Figure 2 ) Although Figure 1 Not shown, transceiver 126 may also include logic for performing in-phase / quadrature (I / Q) operations such as synthesis, phase correction, modulation, demodulation, etc.

[0043] The RF front end 128 may also include one or more mixers (such as mixer circuit 130-2), one or more filters, one or more switches, or one or more amplifiers for conditioning signals received via antenna 122 or for conditioning signals to be transmitted via antenna 122. The RF front end 128 may also include a local oscillator, a phase shifter (PS), a peak detector, a power meter, a gain control block, an antenna tuning circuit, an N-way multiplexer, a balanced-unbalanced converter, etc. Configurable components of the RF front end 128 (such as some phase shifters, automatic gain controllers (AGCs), or reconfigurable versions of the mixer circuit 130) may be controlled by the communication processor 124 to achieve communication in various modes, using different frequency bands, or using beamforming. In some specific implementations, the antenna 122 is implemented as at least one antenna array including a plurality of antenna elements. Therefore, as used herein, "antenna" may refer to at least one discrete or independent antenna, to at least one antenna array including a plurality of antenna elements, or to a portion of an antenna array (e.g., an antenna element), depending on the context or specific implementation.

[0044] exist Figure 1, the example mixer circuit 130 is depicted as a mixer circuit 130-1 as part of the transceiver 126, as a mixer circuit 130-2 as part of the RF front end 128, and so on. However, the described specific implementation of the mixer circuit 130 may additionally or alternatively be used generally in other parts of the wireless interface device 120 or in other parts of the electronic device 102. As set forth above, the mixer circuit 130 may be included in electronic devices other than cellular telephones, such as the base station 104. Additionally, with a base station (or with a mobile phone using a superheterodyne architecture), a mixer circuit 130 as described herein may be used to implement, for example, a mixer for an intermediate frequency (IF) segment of the wireless interface device 120. Other electronic device devices that may employ the mixer circuit 130 include laptop computers as described herein, communication hardware for vehicles, wireless access points, wearable devices, and the like.

[0045] In an example implementation, mixer circuit 130 may include one or more switches 132-1 ... 132-S, one or more capacitors 134-1 ... 134-C, and one or more nodes 136-1 ... 136-N. Variables "S", "C", and "N" are positive integers that may be the same or different from each other. Although certain components are shown as Figure 1 1, but a given mixer circuit may have more, fewer, or different components. Figures 4 to 8 An example mixer and the operation of the example mixer are described below.

[0046] By using one or more aspects of the architecture and technology described herein, the mixer circuit 130 can increase linearity by a symmetrical arrangement of components. For example, in some implementations, a symmetric related linearity measurement result referred to as a second-order intercept point (IP2 or IIP2) can be improved by about 5 to 10 decibels (dB). This improvement can counter at least some of the noise introduced by the associated local oscillator. Noise handling enables the use of a single balanced mixer in some cases, thereby avoiding the use of a transformer, and thus reducing the area consumed by the frequency converter including the mixer. Example implementations can also share capacitors or resistors to reduce line count or simplify signal routing, including reducing line count and simplifying signal routing.

[0047] The number of transmit or receive chains using single balanced mixers as described herein rather than double balanced mixers multiplies these advantages. Figures 5 to 7 An example schematic diagram and circuit implementation for a mixer circuit that can be implemented according to the described implementation is depicted in . However, in the following, this document refers to Figure 2 to describe an example implementation of a transceiver and RF front end, and then refer to Figure 3 and Figure 4 to describe an example signal path and frequency converter.

[0048] Figure 2 is a schematic diagram 200 illustrating an example RF front end 128 and an example transceiver 126 that may each include at least one mixer circuit 130 . Figure 2 Also depicted is an antenna 122 and a communication processor 124. The communication processor 124 communicates one or more data signals to other components such as Figure 1 108) for further processing at 224 (e.g., for processing at the application level). As shown, circuit 200 may include mixer circuit 130-1, mixer circuit 130-2, mixer circuit 130-3, or mixer circuit 130-4, including one to four mixer circuits of such mixer circuits. However, circuit 200 may include a different number of mixers (e.g., more or fewer mixers), may include mixers coupled together in different ways, may include mixers in different locations, may include mixers implemented as part of a frequency converter, and so on.

[0049] As illustrated from left to right, in an example implementation, the antenna 122 is coupled to the RF front end 128, and the RF front end 128 is coupled to the transceiver 126. The transceiver 126 is coupled to the communication processor 124. The example RF front end 128 includes at least one signal propagation path 222. The at least one signal propagation path 222 may include at least one mixer circuit 130, such as mixer circuit 130-2 and mixer circuit 130-3. The example transceiver 126 includes at least one receive chain 202 (or receive path 202) and at least one transmit chain 252 (or transmit path 252). Although only one RF front end 128, one transceiver 126, and one communication processor 124 are shown at circuit 200, the electronic device 102 or the wireless interface device 120 of the electronic device may include multiple instances of any or all of such components. In addition, although Figure 2 Only certain components are explicitly depicted and shown as coupled together in a particular manner, but the transceiver 126 or RF front end 128 may include other components not illustrated (e.g., switches or duplexers), more or fewer components, arrangements of components coupled in a different manner, etc.

[0050] In some implementations, the RF front end 128 couples the antenna 122 to the transceiver 126 via a signal propagation path 222. In operation, the signal propagation path 222 carries a signal between the antenna 122 and the transceiver 126. During or as part of the signal propagation, the signal propagation path 222 conditions the propagated signal, such as using the mixer circuit 130-2 or the mixer circuit 130-3. This enables the RF front end 128 to couple the wireless signal 220 from the antenna 122 to the transceiver 126 as part of a receive operation. The RF front end 128 also enables a transmit signal to be coupled from the transceiver 126 to the antenna 122 as part of a transmit operation to send out the wireless signal 220. Although in Figure 2 Although not explicitly shown, the RF front end 128 or the signal propagation path 222 of the RF front end may include one or more other components, such as another mixer, a filter, an amplifier (e.g., a power amplifier (PA) or a low noise amplifier (LNA)), an N-way multiplexer, a phase shifter, a duplexer, one or more switches, etc.

[0051] In some implementations, the transceiver 126 may include at least one receive chain 202, at least one transmit chain 252, or at least one receive chain 202 and at least one transmit chain 252. From left to right, the receive chain 202 may include a low noise amplifier 204 (LNA 204), a filter circuit 206, a mixer circuit 130-1 for downconversion, and an ADC 210. The transmit chain 252 may include a power amplifier 254 (PA 254), a filter circuit 256, a mixer 130-4 for upconversion, and a DAC 260. However, the receive chain 202 or the transmit chain 252 may include other components—such as additional amplifiers or mixers, multiple filters, one or more buffers, or at least one local oscillator—that are electrically or electromagnetically coupled anywhere along the depicted receive and transmit chains.

[0052] The receive chain 202 is coupled between the signal propagation path 222 of the RF front end 128 and the communication processor 124, for example, via the low noise amplifier 204 and the ADC 210, respectively. The transmit chain 252 is coupled between the signal propagation path 222 and the communication processor 124, for example, via the power amplifier 254 and the DAC 260, respectively. The transceiver 126 may also include at least one phase-locked loop 232 (PLL 232) coupled to the mixer circuit 130-1 or the mixer circuit 130-4. For example, the transceiver 126 may include one PLL 232 for each transmit chain / receive chain pair, one PLL 232 for each transmit chain and one PLL 232 for each receive chain, multiple PLLs 232 for each chain, etc.

[0053] As shown along the signal propagation direction for certain example implementations of receive chain 202, antenna 122 is coupled to low noise amplifier 204 via signal propagation path 222 and mixer circuit 130-3 of the signal propagation path, and low noise amplifier 204 is coupled to filter circuit 206. Filter circuit 206 is coupled to mixer circuit 130-1, and mixer circuit 130-1 is coupled to ADC 210. ADC 210 is in turn coupled to communication processor 124. As shown along the signal propagation direction for certain example implementations of transmit chain 252, communication processor 124 is coupled to DAC 260, and DAC 260 is coupled to mixer circuit 130-4. Mixer circuit 130-4 is coupled to filter circuit 256, and filter circuit 256 is coupled to power amplifier 254. Power amplifier 254 is coupled to antenna 122 via the signal propagation path using mixer circuit 130-2 of signal propagation path 222. Although only one receive chain 202 and one transmit chain 252 are explicitly shown, the electronic device 102 or its transceiver 126 may include multiple instances of either or both components. Although the ADC 210 and DAC 260 are illustrated as being separately coupled to the communication processor 124, they may share a bus or other means for communicating with the processor 124.

[0054] As part of an example signal reception operation, the mixer circuit 130-3 (if present) of the signal propagation path 222 down-converts the received signal (e.g., down-converts to an intermediate frequency (IF)) and forwards the down-converted signal to the low noise amplifier 204. The low noise amplifier 204 accepts the down-converted signal from the RF front end 128 and provides an amplified signal to the filter circuit 206 based on the accepted signal. The filter circuit 206 filters the amplified signal and provides the filtered signal to the mixer circuit 130-1. The mixer circuit 130-1 performs a down-conversion operation on the filtered signal to down-convert from one frequency to a lower frequency (e.g., from IF to baseband frequency (BBF) in the presence of the mixer circuit 130-3, or from radio frequency (RF) to IF or BBF in the absence of the mixer circuit 130-3). The mixer circuit 130-1 can use at least one PLL 232 to perform the down-conversion in a single conversion step or through multiple conversion steps. Mixer circuit 130 - 1 may provide the down-converted analog signal to ADC 210 for ADC conversion and subsequently forwarded to communication processor 124 as a digital signal.

[0055] As part of the example signal transmission operation, the DAC 260 converts the digital signal received from the communication processor 124 into an analog signal. The mixer circuit 130-4 receives the analog signal at BBF or IF from the DAC 260. The mixer circuit 130-4 up-converts the analog signal to a higher frequency (such as up-converting to IF or RF) to generate the higher frequency signal to have a target synthesis frequency using the signal generated by the PLL 232. The mixer circuit 130-4 provides the RF or other up-converted signal to the filter circuit 256. The filter circuit 256 up-converts the IF or RF signal and provides the filtered signal to the power amplifier 254. Therefore, after filtering by the filter circuit 256, the power amplifier 254 amplifies the filtered signal and provides the amplified signal to the signal propagation path 222 for signal conditioning. For example, if the amplified signal is at IF, the RF front end 128 can use the mixer circuit 130-2 of the signal propagation path 222 to provide the RF signal to the antenna 122 to be sent as a wireless signal 220.

[0056] As described herein, example implementations of mixer circuit 130 may be used at any one or more of example mixer circuits 130-1, 130-2, 130-3, or 130-4 in transceiver 126 or RF front end 128 or at other mixers of electronic device 102. Figure 2 126). However, circuit 200 depicts only some examples for transceiver 126 and RF front end 128. In some cases, various components illustrated in the figures using separate schematic blocks or circuit elements may be manufactured or packaged in different discrete ways. For example, one physical module may include components of RF front end 128 and some components of transceiver 126, and another physical module may combine communication processor 124 with the remaining components of transceiver 126. In addition, in some cases, antenna 122 may be co-packaged with at least some components of RF front end 128 or transceiver 126.

[0057] In alternative implementations, one or more components may be physically or logically "shifted" to a different portion of the wireless interface device 120 and / or may be incorporated into a different module compared to the illustrated circuit 200. For example, the low noise amplifier 204 or the power amplifier 254 may alternatively or additionally be deployed in the RF front end 128. Similarly, the ADC 210 or the DAC 260 may alternatively be deployed in the communication processor 124.

[0058] Figure 3 3 is a diagram illustrating an example of multiple receive chains that may each include at least one frequency converter as part of a wireless interface device. As shown, the wireless interface device 120 (e.g., Figure 1 and Figure 2The wireless interface device may include a plurality of receiving chains 202-1, 202-2, ..., 202-R, where "R" represents a positive integer. Each receiving chain 202 includes at least one frequency converter 302. Figure 3 , "F" frequency converters 302-1, 302-2, ..., 302-F are depicted, where "F" represents a positive integer. For example, the first receiving chain 202-1 includes the first frequency converter 302-1, the second receiving chain 202-2 includes the second frequency converter 302-2, and the "Rth" receiving chain 202-R includes the "Fth" frequency converter 302-F.

[0059] In some implementations, each respective receive chain 202 corresponds to a respective frequency range 304, such as a first frequency range 304-1, a second frequency range 304-2, and an "Mth" frequency range 304-M. Additionally or alternatively, each respective receive chain 202 may correspond to a respective wireless standard or communication protocol. Examples include a receive chain 202 for a mid-high band (MHB) frequency range 304, a receive chain 202 for a millimeter wave (mmW) band 304, a receive chain 202 for a combined LAA and new radio unlicensed (NR-U) access scheme, and the like. The values ​​of the variables "R", "F", and "M" may be the same or different from one another.

[0060] Despite Figure 3 Only a receive chain is shown, but the wireless interface device 120 may additionally or alternatively include multiple transmit chains, such as ( Figure 2 Each receive chain 202 or transmit chain 252 may include a corresponding frequency converter or multiple frequency converters, or may share a frequency converter 202 with one or more other chains. Figure 3 1 and 2. Although illustrated as part of a receive chain and described above as part of a receive chain or a transmit chain (or part of both), the frequency converter 302 may also be implemented separately from any chain. Additionally or alternatively, the frequency converter 302 may be implemented as part of the RF front end 128. The RF front end 128 may also include at least a portion of the receive chain 202 or the transmit chain 252.

[0061] Figure 4 4 is a schematic diagram 400 illustrating an example frequency converter 302 including a mixer circuit 130 and a local oscillator 402. As shown, the mixer circuit 130 is coupled to the local oscillator 402 (LO 402). In an example implementation, the mixer circuit 130 includes an input interface 412, an output interface 414, and a control interface 416 (or LO interface 416). The local oscillator 402 generates a local oscillator signal 404 (LO signal 404). The local oscillator signal 404 may be implemented as follows: Figure 5 and Figure 6The local oscillator 402 sends or provides a local oscillator signal 404 to the mixer circuit 130 via at least one local oscillator node 410 (LO node 410). The mixer circuit 130 receives or accepts the local oscillator signal 404 through a control interface 416.

[0062] The mixer circuit 130 receives or accepts the first signal 406 through an input interface 412. The mixer circuit 130 can generate a second signal 408 based on the local oscillator signal 404 and the first signal 406 by performing a mixing operation (e.g., a multiplication operation). The mixer circuit 130 sends or provides the second signal 408 through an output interface 414. The first signal 406 corresponds to a first frequency 418-1, and the second signal 408 corresponds to a second frequency 418-2 that is different from the first frequency 418-1. Therefore, the frequency converter 302 (e.g., the mixer circuit 130 in combination with the local oscillator 402 or at least the local oscillator signal 404 from the local oscillator) converts the signal having the first frequency 418-1 to another signal having the second frequency 418-2.

[0063] The frequency converter 302 may perform up-conversion or down-conversion. In some cases, the first signal 406 corresponds to an input signal of the frequency converter 302 or the mixer circuit 130 of the frequency converter, and the second signal 408 corresponds to an output signal of the frequency converter 302 or the mixer circuit 130 of the frequency converter. For up-conversion, the second frequency 418-2 of the second signal 408 is greater than (e.g., higher than) the first frequency 418-1 of the first signal 406. For down-conversion, the second frequency 418-2 of the second signal 408 is less than (e.g., lower than) the first frequency 418-1 of the first signal 406. However, in other specific implementations, depending on the configuration of the unidirectional mixer circuit or the mode of the bidirectional mixer circuit, the second signal may correspond to the input signal and the first signal may correspond to the output signal.

[0064] Figure 5 is a schematic diagram illustrating an example mixer circuit 130 including a plurality of nodes, a plurality of switches, and a plurality of capacitors. Figure 1 , the mixer circuit 130 may include a plurality of switches 132-1 ... 132-S, a plurality of capacitors 134-1 ... 134-C, and a plurality of nodes 136-1 ... 136-N. Figure 5 In the example mixer circuit 130 shown, there are four (4) switches, so "S" may be equal to four. There are two (2) capacitors, so "C" may be equal to two. There are seven (7) identified nodes, so "N" may be equal to seven. However, each of these components may have more than Figure 5 Greater or fewer examples may be depicted or described herein.

[0065] In an example implementation, the plurality of switches 132-1 ... 132-S may include at least a first switch 132-1, a second switch 132-2, a third switch 132-3, and a fourth switch 132-4. The plurality of capacitors 134-1 ... 134-C may include a first capacitor 134-1 and a second capacitor 134-2. Figure 4 , at least one local oscillator node 410 can be implemented using multiple local oscillator nodes such as a first local oscillator node 410-1 and a second local oscillator node 410-2. Multiple local oscillator nodes can support differential signaling implementation of local oscillator signal 404. Therefore, the first local oscillator node 410-1 and the second local oscillator node 410-2 can include a positive local oscillator node and a negative local oscillator node. In addition, the local oscillator signal 404 can include a positive LO signal 404+ and a negative LO signal 404-. The positive LO signal 404+ and the negative LO signal 404- can also be referred to as a first local oscillator signal and a second local oscillator signal.

[0066] The mixer circuit 130 may also include a first node 506 and a plurality of second nodes 508-1 and 508-2. The first node 506 may correspond to the first frequency 418-1 based on, for example, the frequency of the signal passing through the first node 506. The plurality of second nodes 508-1 and 508-2 may correspond to the second frequency 418-2. The plurality of second nodes 508-1 and 508-2 may jointly carry a differential signal. Therefore, the plurality of second nodes 508-1 and 508-2 may also be referred to as a positive second node 508-1 and a negative second node 508-2. The mixer circuit 130 may also include at least one bias node 510 and at least one floating node 512. The bias node 510 may provide at least one bias signal (such as a gate bias voltage) to the plurality of switches 132-1 to 132-4. The floating node 512 enables the mixer circuit 130 to implement a single balanced mixer architecture. Although each of the specific nodes is depicted and described as having a specific number, each node may have more or fewer instances.

[0067] As illustrated, the plurality of capacitors 134-1 and 134-2 are coupled between the plurality of local oscillator nodes 410-1 and 410-2 and the plurality of second nodes 508-1 and 508-2. The plurality of switches 132-1 to 132-4 are coupled between the plurality of capacitors 134-1 and 134-2 and the plurality of second nodes 508-1 and 508-2. The first switch 132-1 and the second switch 132-2 are coupled between the plurality of capacitors 134-1 and 134-2 and the first node 506. In addition, the third switch 132-3 and the fourth switch 132-4 are coupled to each other via the floating node 512.

[0068] The first capacitor 134-1 may be coupled between the first local oscillator node 410-1 and the first switch 132-1 and the third switch 132-3. The second capacitor 134-2 may be coupled between the second local oscillator node 410-2 and the second switch 132-2 and the fourth switch 132-4. At least one bias node 510 may be coupled to the first switch 132-1 and the third switch 132-3 and to the second switch 132-2 and the fourth switch 132-4. Figure 7 The bias node example is further described.

[0069] In an example operation, the first node 506 may provide a first signal corresponding to the first frequency 418-1 to the mixer circuit 130, such as (also Figure 4 The plurality of second nodes 508-1 and 508-2 may receive a second signal corresponding to a second frequency 418-2 from the mixer circuit 130, such as (also Figure 4 Alternatively, the plurality of second nodes 508-1 and 508-2 can provide the second signal 408 to the mixer circuit 130, and the first node 506 can receive the first signal 406 from the mixer circuit 130. In some cases, the first signal 406 can be implemented as an unbalanced signal and the second signal 408 can be implemented as a balanced signal.

[0070] In some specific implementations, Figure 5 One or more of the components depicted in the drawings are disposed on a substrate 514 such as a semiconductor material (e.g., silicon). The substrate 514 defines a plane in which a plurality of axes may be located. As shown, a first axis 504-1 and a second axis 504-2 are located within a plane defined by the substrate 514. The first axis 504-1 and the second axis 504-2 are at least substantially perpendicular to each other. A line of symmetry 502 (LOS 502) may also be located within the plane 514. At least a portion of the illustrated components may be arranged substantially symmetrically about or relative to the line of symmetry 502. In some cases, the line of symmetry 502 may be at least substantially parallel to an axis 504, such as the second axis 504-2. This may include the line of symmetry 502 being colinear with the second axis 504-2 or being parallel to an angle achieved by a given process technology (e.g., within 10 degrees, within 5 degrees, or within 1 degree).

[0071] In an example aspect, the first switch 132-1 and the second switch 132-2 are disposed between the fourth switch 132-4 and the third switch 132-3. The first switch 132-1 and the second switch 132-2 are coupled to the first node 506 to convey information related signaling, such as the first signal 406. In contrast, the fourth switch 132-4 and the third switch 132-3 are coupled to the floating node 512. In this regard, the fourth switch 132-4 and the third switch 132-3 can operate as "dummy switches" with respect to the first node 506 or the first signal 406.

[0072] In other aspects, the first switch 132-1 can be disposed on the substrate 514 between the fourth switch 132-4 and the second switch 132-2. In addition, the second switch 132-2 can be disposed on the substrate 514 between the first switch 132-1 and the third switch 132-3. In certain symmetry-related aspects, the first switch 132-1 and the fourth switch 132-4 are symmetrically positioned on a first side of the symmetry line 502 (e.g., as shown in FIG. 5 ). Figure 5 ), and the second switch 132-2 and the third switch 132-3 are symmetrically positioned on a second side of the symmetry line 502 (eg, as depicted in FIG. 5 ). Figure 5 Similarly, the second capacitor 134 - 2 may be positioned on a first side of the symmetry line 502 , and the first capacitor 134 - 1 may be positioned on a second side of the symmetry line 502 .

[0073] Additionally or alternatively, the first switch 132-1, the second switch 132-2, the third switch 132-3, and the fourth switch 132-4 may be arranged along a line at least substantially parallel to the first axis 504-1 ( Figure 5 Not shown, but see Figure 7 ) is disposed on the substrate and lies in plane 514. This may include the line being collinear with the first axis 504-1 or parallel to an angle achieved by a given manufacturing technology. Figure 6 An example of this arrangement is described below.

[0074] exist( Figure 4In an example implementation in which a local oscillator 402 provides a differential local oscillator signal 404, the plurality of local oscillator nodes may include a positive local oscillator node 410-1 and a negative local oscillator node 410-2. The first capacitor 134-1 may be coupled between the positive local oscillator node 410-1 and the first switch 132-1, and the first capacitor 134-1 may also be coupled between the positive local oscillator node 410-1 and the third switch 132-3. The second capacitor 134-2 may be coupled between the negative local oscillator node 410-2 and the fourth switch 132-4, and the second capacitor 134-2 may also be coupled between the negative local oscillator node 410-2 and the second switch 132-2.

[0075] Figure 6 is a schematic diagram 600 illustrating an example implementation of a plurality of switches 132 - 1 through 132 - 4 including two switches symmetrically coupled to a node (eg, the first node 506 ). Figure 6 Also depicted is a substrate 514 and two axes that lie in a plane defined by the substrate 514. The two axes are a first axis 504-1 and a second axis 504-2. The line of symmetry 502 extends at least substantially parallel to the second axis 504-2 in the plane of the substrate 514.

[0076] In an example implementation, the plurality of switches 132-1 to 132-4 are disposed in the plane of the substrate 514 along a line 602. The line 602 is at least substantially parallel to the first axis 504-1 and at least substantially perpendicular to the symmetry line 502. As shown, the first switch 132-1 and the second switch 132-2 are symmetrically coupled to the first node 506 along or across the symmetry line 502. Each of the first switch 132-1 and the second switch 132-2 may include Figure 6 and Figure 7 Although eight transistors are shown for each of the first switch 132-1 and the second switch 132-2, each switch 132 may be formed of more or fewer transistors (including one transistor).

[0077] For the sake of clarity, from Figure 6 The plurality of second nodes 508-1 and 508-2 are omitted. Additionally, each of the third switch 132-3 and the fourth switch 132-4 may further include one or more transistors. Figure 6 5. A particular symmetrical arrangement of the first switch 132-1 and the second switch 132-2 with respect to the first node 506 and the symmetry line 502 is shown in FIG. 5, but the first switch 132-1 and the second switch 132-2 may be symmetrically positioned on the substrate in a different manner.

[0078] Figure 77 is a circuit diagram 700 illustrating an example mixer circuit including a plurality of nodes, a plurality of switches, a plurality of capacitors, and a plurality of resistors. The circuit diagram 700 provides Figure 5 An example circuit level implementation of the schematic diagram of FIG. Figure 5 In contrast, the plurality of switches 132-1 to 132-4 are each depicted as having at least one transistor M. As shown, the first switch 132-1 is implemented using at least one transistor M1, and the second switch 132-2 is implemented using at least one transistor M2. The third switch 132-3 is implemented using at least one transistor M3, and the fourth switch 132-4 is implemented using at least one transistor M4.

[0079] The second signal 408 is implemented using a differential signal including a first instance of the second signal 408-1 and a second instance of the second signal 408-2. These signals may also be referred to as a positive second signal 408-1 and a negative second signal 408-2. The differential signal may be implemented as, for example, two complementary signals or two signals with opposite polarities. In an example operation, the second signal 408-1 may propagate through a second node 508-1 (which may be referred to as a positive second node 508-1), and the second signal 408-2 may propagate on a second node 508-2 (which may be referred to as a negative second node 508-2).

[0080] and Figure 5 In further contrast, at least one bias node 510 is implemented as a first bias node 510-1 and a second bias node 510-2. In order to bias the transistors M1 to M4, a bias signal 704 is provided to each transistor M. The bias signal can be, for example, a DC voltage from a power distribution network node. Examples of power distribution network nodes include power supply nodes (such as power rails) and ground nodes (such as ground planes). In some cases, the bias signal 704 can be separated into a first bias signal 704-1 and a second bias signal 704-2.

[0081] Each respective bias signal 704 may be provided to at least one transistor M via at least one resistor 702 (e.g., a bias resistor). For separate bias signals, the at least one resistor 702 may be implemented using separate resistors from the plurality of resistors. For example, the mixer circuit 130 may bias the first transistor M1 and the third transistor M3 using the first bias signal 704-1 via the first resistor 702-1. Additionally, the mixer circuit 130 may bias the second transistor M2 and the fourth transistor M4 using the second bias signal 704-2 via the second resistor 702-2.

[0082] In general, each switch 132 can be implemented using at least one transistor. The transistor can be implemented using any one or more of a variety of transistor types. Example transistor types include field effect transistors (FETs), junction FETs (JFETs), metal oxide semiconductor FETs (MOSFETs), bipolar junction transistors (BJTs), insulated gate bipolar transistors (IGBTs), etc. Manufacturers can manufacture FETs as n-channel or p-channel transistor types and can manufacture BJTs as NPN or PNP transistor types.

[0083] Each transistor may include at least one control terminal and one or more channel terminals. For FET transistors, the control terminal may correspond to the gate terminal, and the channel terminal may correspond to the source terminal or the drain terminal. For BJT transistors, the control terminal may correspond to the base terminal, and the channel terminal may correspond to the emitter terminal or the controller terminal.

[0084] In order to bias each transistor M, a bias signal 704 is provided to the corresponding control terminal of each transistor M. Figure 7 In , each transistor M is implemented as an n-channel FET having a gate terminal, a drain terminal, and a source terminal. A plurality of bias signals 704-1 and 704-2 are coupled to the gate terminals of one or more transistors. For example, a first bias signal 704-1 can be coupled to the gate terminals of the first transistor M1 and the third transistor M3 through a first resistor 702-1. Similarly, a second bias signal 704-2 can be coupled to the gate terminals of the second transistor M2 and the fourth transistor M4 through a second resistor 702-2. Although in Figure 7 The transistors are depicted as n-channel FETs in FIG. 1 , but the mixer circuit can be implemented using p-channel FETs, any type of BJT, combinations thereof, etc.

[0085] As shown for some specific implementations, the plurality of bias nodes may include a first bias node 510-1 and a second bias node 510-2, and the plurality of bias resistors may include a first resistor 702-1 and a second resistor 702-2. The first resistor 702-1 may be coupled between the first bias node 510-1 and the first switch 132-1 (e.g., the first transistor M1), and the first resistor 702-1 may also be coupled between the first bias node 510-1 and the third switch 132-3 (e.g., the third transistor M3). The second resistor 702-2 may be coupled between the second bias node 510-2 and the fourth switch 132-4 (e.g., the fourth transistor M4), and the second resistor 702-2 may also be coupled between the second bias node 510-2 and the second switch 132-2 (e.g., the second transistor M2).

[0086] In an example implementation, each transistor M is coupled between two nodes via a corresponding channel terminal. For example, the first transistor M1 can be coupled between the first node 506 and the first instance of the second node 508-1 (e.g., the positive second node 508-1). The second transistor M2 can be coupled between the first node 506 and the second instance of the second node 508-2 (e.g., the negative second node 508-2). The third transistor M3 can be coupled between the floating node 512 and the second instance of the second node 508-2 (e.g., the negative second node 508-2). The fourth transistor M4 can be coupled between the floating node 512 and the first instance of the second node 508-1 (e.g., the positive second node 508-1).

[0087] Next, example couplings with different terminals of transistors forming the plurality of switches 132-1 to 132-4 are described. In some example couplings, a first capacitor 134-1 is coupled between a first local oscillator node 410-1 and respective control terminals (e.g., gate terminals for FET implementations) of the first and third switches 132-1, 132-3 (e.g., first and third transistors M1, M3). A second capacitor 134-2 is coupled between a second local oscillator node 410-2 and respective control terminals (e.g., gate terminals for FET implementations) of the fourth and second switches 132-4, 132-2 (e.g., transistors M4 and M2).

[0088] In other example couplings, a first resistor 702-1 of the plurality of resistors is coupled between the first bias node 510-1 and respective control terminals (e.g., gate terminals for FET implementations) of the first switch 132-1 and the third switch 132-3. A second resistor 702-2 of the plurality of resistors is coupled between the second bias node 510-2 and respective control terminals (e.g., gate terminals for FET implementations) of the fourth switch 132-4 and the second switch 132-2.

[0089] In yet other example couplings, the first switch 132-1 and the second switch 132-2 are coupled to the first node 506 via respective first terminals of the first terminal type of a given transistor type. The third switch 132-3 and the fourth switch 132-4 are coupled to each other via respective first terminals of the first terminal type (e.g., through the floating node 512). In addition, the second node 508-1 of the plurality of second nodes 508-1 and 508-2 is coupled to the fourth switch 132-4 and the first switch 132-1 via respective second terminals of the second terminal type. Another second node 508-2 of the plurality of second nodes 508-1 and 508-2 is coupled to the second switch 132-2 and the third switch 132-3 via respective second terminals of the second terminal type. These terminal types may correspond to channel terminals. As shown for the depicted FET, the first terminal type may correspond to the drain terminal of the transistor M, and the second terminal type may correspond to the source terminal of the transistor M.

[0090] In some specific implementations, the first switch 132-1 (e.g., including the first transistor M1) and the second switch 132-2 (e.g., including the second transistor M2) are disposed on the substrate, between the fourth switch 132-4 (e.g., including the fourth transistor M4) and the third switch 132-3 (e.g., including the third transistor M3). The first switch 132-1 (e.g., including the first transistor M1) and the second switch 132-2 (e.g., including the second transistor M2) are coupled to the same node (e.g., the first node 506) to communicate (e.g., receive / accept or send / provide) the same signal (e.g., the first signal 406) carrying user or application level information (e.g., in contrast to the oscillating signal 404 that may lack user or application level information).

[0091] This provides a mechanism for increasing the symmetry-related linearity of the mixer circuit 130. The mechanism for increasing the symmetry-related linearity can be further enhanced by symmetrically positioning multiple switches. For example, the first switch 132-1 and the fourth switch 132-4 can be positioned on a first side of the symmetry line 502, and the second switch 132-2 and the third switch 132-3 can be positioned on a second side of the symmetry line 502.

[0092] The area consumption of the mixer circuit 130 can be reduced by implementing a mechanism for sharing one or more components. For example, each capacitor 134 in the plurality of capacitors can be shared across two or more switches in the plurality of switches. For example, the first capacitor 134-1 in the plurality of capacitors 134-1 and 134-2 can be shared across the first switch 132-1 and the third switch 132-3 in the plurality of switches 132-1 to 132-4. As another example, each resistor 702 in the plurality of resistors can be shared across two or more switches in the plurality of switches. For example, the second resistor 702-2 in the plurality of resistors 702-1 and 702-2 can be shared across the second switch 132-2 and the fourth switch 132-4 in the plurality of switches 132-1 to 132-4. This sharing can also simplify layout or routing (including both) to further reduce consumption.

[0093] Figure 8 is a flow chart illustrating an example process 800 for mixing signals and / or operating a mixer circuit. The process 800 includes five blocks 802-810 that specify operations that may be performed for the method.

[0094] At block 802, a first signal is received at a first switch and a second switch via a first node, wherein the first signal corresponds to a first frequency. For example, the mixer circuit 130 may receive the first signal 406 at the first switch 132-1 and the second switch 132-2 via the first node 506, wherein the first signal 406 corresponds to the first frequency 418-1. For example, as part of the receive chain 202 or the transmit chain 252, the first transistor M1 and the second transistor M2 may receive the first signal 406 at their respective first channel terminals. Here, the first signal 406 may be a single-ended signal on the unbalanced side of a single balanced implementation of the mixer circuit 130.

[0095] At block 804, a positive local oscillator signal is received at the first switch and the third switch via the first capacitor. For example, the mixer circuit 130 may receive the positive local oscillator signal 404+ at the first switch 132-1 and the third switch 132-3 via the first capacitor 134-1. In some cases, the first transistor M1 and the third transistor M3 may receive the positive local oscillator signal 404+ at their respective gate terminals via the first capacitor 134-1. Thus, the first transistor M1 and the third transistor M3 may "share" the first capacitor 134-1 to reduce the area occupied by the mixer circuit 130, including by simplifying layout and routing. The first transistor M1 and the third transistor M3 may also share a bias resistor, rather than having two separate bias resistors.

[0096] At block 806, a negative local oscillator signal is received at the second switch and the fourth switch via the second capacitor. For example, the mixer circuit 130 may receive the negative local oscillator signal 404- at the second switch 132-2 and the fourth switch 132-4 via the second capacitor 134-2. In some cases, the second transistor M2 and the fourth transistor M4 may receive the negative local oscillator signal 404- at their respective gate terminals via the second capacitor 134-2. Therefore, the second transistor M2 and the fourth transistor M4 may "share" the second capacitor 134-2. The second transistor M2 and the fourth transistor M4 may also share a bias resistor. In order to support, for example, linearity-related performance parameters, the first transistor M1 and the second transistor M2 may be disposed on the substrate 514, between the third transistor M3 and the fourth transistor M4.

[0097] At block 808, the first signal, the positive local oscillator signal, and the negative local oscillator signal are mixed using the first switch, the second switch, the third switch, and the fourth switch to generate a second signal, wherein the second signal corresponds to the second frequency. For example, the mixer circuit 130 can use the first switch 132-1, the second switch 132-2, the third switch 132-3, and the fourth switch 132-4 to mix the first signal 406, the positive local oscillator signal 404+, and the negative local oscillator signal 404- to generate a second signal 408, wherein the second signal 408 corresponds to the second frequency 418-2. To this end, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 can be turned on and off by the positive oscillator signal 404+ or the negative oscillator signal 404- to combine the first signal 406 with the oscillator signal 404 using a mathematical operation, thereby generating a second signal 408 having a frequency different from the frequency of the first signal 406. In the case where the third switch 132 - 3 and the fourth switch 132 - 4 do not receive an input signal (and are coupled to each other), the third switch 132 - 3 and the fourth switch 132 - 4 may operate as dummy switches at least with respect to the first signal 406 .

[0098] At block 810, a second signal is provided from the first switch, the second switch, the third switch, and the fourth switch via a plurality of second nodes. For example, the mixer circuit 130 may provide the second signal 408 from the first switch 132-1, the second switch 132-2, the third switch 132-3, and the fourth switch 132-4 via a plurality of second nodes 508-1 and 508-2. Thus, as part of the frequency converter 302, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 may output the second signal 408 at their respective second channel terminals. Here, the second signal 408 may include a positive second signal 408-1 and a negative second signal 408-2 to implement a differential signal on the balanced side of a single balanced implementation of the mixer circuit 130.

[0099] Figure 8 The flowcharts of the present invention illustrate example processes or methods related to mixing signals and / or operating mixer circuits. The processes are described in the form of a set of blocks that specify operations that can be performed. However, the operations are not necessarily limited to the order shown in the figures or described herein, because the operations can be performed in an alternative order or in a completely or partially overlapping manner. In addition, more, fewer and / or different operations can be implemented to perform the corresponding process or alternative processes. The operations represented by the illustrated blocks of each process can be performed by an electronic device such as Figure 1 The electronic device 102 or the wireless interface device 120 of the electronic device is executed. More specifically, the operation of the corresponding process can be performed independently by the mixer circuit 130 of the transceiver 126 or the RF front end 128 or in combination with other components.

[0100] Specific implementation examples

[0101] This section describes some aspects of example implementations and / or example configurations related to the apparatus and / or processes presented above.

[0102] Example aspect 1: An apparatus, the apparatus comprising:

[0103] A mixer circuit, the mixer circuit comprising:

[0104] multiple local oscillator nodes;

[0105] a first node, the first node corresponding to a first frequency;

[0106] a plurality of second nodes, the plurality of second nodes corresponding to a second frequency;

[0107] a plurality of capacitors coupled between the plurality of local oscillator nodes and the plurality of second nodes; and

[0108] A plurality of switches, the plurality of switches comprising a first switch, a second switch, a third switch and a fourth switch; the plurality of switches are coupled between the plurality of capacitors and the plurality of second nodes; the first switch and the second switch are coupled between the plurality of capacitors and the first node; and the first switch and the second switch are arranged between the fourth switch and the third switch.

[0109] Example aspect 2: The apparatus according to example aspect 1, wherein:

[0110] The third switch and the fourth switch are coupled to each other via a floating node.

[0111] Example aspect 3: The apparatus according to example aspect 1 or 2, wherein:

[0112] The first node is configured to provide a first signal corresponding to the first frequency to the mixer circuit; and

[0113] and

[0114] The plurality of second nodes are configured to receive a second signal corresponding to the second frequency from the mixer circuit.

[0115] Example aspect 4: The apparatus of example aspect 3, wherein:

[0116] The first signal comprises an unbalanced signal; and

[0117] The second signal comprises a balanced signal.

[0118] Example aspect 5: The apparatus of any one of example aspects 2 to 4, wherein:

[0119] The first switch is disposed on the substrate and is located between the fourth switch and the second switch; and

[0120] The second switch is disposed on the substrate and located between the first switch and the third switch.

[0121] Example aspect 6: The apparatus of any one of example aspects 2 to 5, wherein:

[0122] The first switch and the fourth switch are symmetrically positioned on a first side of a symmetry line, and the second switch and the third switch are symmetrically positioned on a second side of the symmetry line.

[0123] Example aspect 7: The apparatus of example aspect 6, wherein:

[0124] The substrate defines a plane;

[0125] the plane includes a first axis and a second axis, the first axis being substantially perpendicular to the second axis, the second axis being at least substantially parallel to the line of symmetry; and

[0126] The first switch, the second switch, the third switch and the fourth switch are arranged on the substrate along a line at least substantially parallel to the first axis, lying in the plane.

[0127] Example aspect 8: The apparatus of example aspect 6 or 7, wherein:

[0128] The plurality of capacitors include a first capacitor and a second capacitor;

[0129] the first capacitor is positioned on the second side of the line of symmetry; and

[0130] The second capacitor is positioned on the first side of the line of symmetry.

[0131] Example aspect 9: The apparatus of example aspect 8, wherein:

[0132] The plurality of local oscillator nodes include a first local oscillator node and a second local oscillator node;

[0133] The first capacitor is coupled between the first local oscillator node and the first switch and the third switch; and

[0134] The second capacitor is coupled between the second local oscillator node and the second switch and the fourth switch. Example Aspect 10: The apparatus of any of the preceding example aspects, wherein:

[0135] The plurality of local oscillator nodes include a positive local oscillator node and a negative local oscillator node;

[0136] The plurality of capacitors include a first capacitor and a second capacitor;

[0137] the first capacitor coupled between the positive local oscillator node and the first switch;

[0138] the first capacitor coupled between the positive local oscillator node and the third switch;

[0139] the second capacitor is coupled between the negative local oscillator node and the fourth switch; and

[0140] The second capacitor is coupled between the negative local oscillator node and the second switch.

[0141] Example aspect 11: The apparatus of any of the preceding example aspects, wherein:

[0142] The mixer circuit comprises:

[0143] a plurality of bias nodes, the plurality of bias nodes comprising a first bias node and a second bias node; and

[0144] a plurality of bias resistors, the plurality of bias resistors comprising a first resistor and a second resistor;

[0145] The first resistor is coupled between the first bias node and the first switch;

[0146] The first resistor is coupled between the first bias node and the third switch;

[0147] The second resistor is coupled between the second bias node and the fourth switch; and

[0148] The second resistor is coupled between the second bias node and the second switch.

[0149] Example aspect 12: The apparatus according to any of the preceding example aspects, further comprising:

[0150] a local oscillator coupled to the plurality of local oscillator nodes,

[0151] Wherein the mixer circuit is configured to convert the frequency of a signal between the first frequency and the second frequency.

[0152] Example aspect 13: The apparatus according to any of the preceding example aspects, further comprising:

[0153] at least one transmission chain, the at least one transmission chain comprising the mixer circuit,

[0154] Wherein the mixer circuit is configured to perform frequency up-conversion.

[0155] Example aspect 14: The apparatus according to any of the preceding example aspects, further comprising:

[0156] at least one receive chain, the at least one receive chain comprising the mixer circuit,

[0157] Wherein the mixer circuit is configured to perform down conversion.

[0158] Example aspect 15: According to the apparatus of example aspect 14, the apparatus further comprises:

[0159] a wireless interface device, the wireless interface device comprising the at least one receive chain;

[0160] display screen; and

[0161] and at least one processor operatively coupled to the display screen and at least a portion of the wireless interface device, the at least one processor configured to present one or more graphical images on the display screen based on one or more wireless signals communicated using the mixer circuit of the wireless interface device.

[0162] Example Aspect 16: An apparatus, the apparatus comprising:

[0163] A mixer circuit, the mixer circuit comprising:

[0164] multiple local oscillator nodes;

[0165] a first node, the first node corresponding to a first frequency;

[0166] a plurality of second nodes, the plurality of second nodes corresponding to a second frequency;

[0167] a plurality of capacitors coupled between the plurality of local oscillator nodes and the plurality of second nodes;

[0168] a plurality of switches, the plurality of switches comprising a first switch, a second switch, a third switch and a fourth switch; the plurality of switches are coupled between the plurality of capacitors and the plurality of second nodes; the first switch and the second switch are coupled between the plurality of capacitors and the first node; the third switch and the fourth switch are coupled to each other via a floating node; and

[0169] Components used to increase symmetry-related linearity.

[0170] Example aspect 17: The apparatus of example aspect 16, wherein the means for increasing symmetry-related linearity comprises:

[0171] Means for symmetrically positioning the first switch and the fourth switch on a first side of a line of symmetry and symmetrically positioning the second switch and the third switch on a second side of the line of symmetry.

[0172] Example aspect 18: The apparatus according to example aspect 16 or 17, the apparatus further comprising:

[0173] Means for sharing each of the plurality of capacitors across two or more of the plurality of switches.

[0174] Example aspect 19: The apparatus according to any one of example aspects 16 to 18, the apparatus further comprising:

[0175] a plurality of resistors coupled to the plurality of switches; and

[0176] Means for sharing each resistor of the plurality of resistors across two or more switches of the plurality of switches.

[0177] Example Aspect 20: An apparatus, the apparatus comprising:

[0178] A mixer circuit, the mixer circuit comprising:

[0179] a first local oscillator node and a second local oscillator node;

[0180] a first node, the first node corresponding to a first frequency;

[0181] a second node and a third node, the second node and the third node each corresponding to a second frequency;

[0182] a first capacitor and a second capacitor;

[0183] a first switch, the first switch being coupled between the first capacitor and the second node, the first switch being further coupled between the first capacitor and the first node;

[0184] a second switch coupled between the second capacitor and the third node, the second switch further coupled between the second capacitor and the first node;

[0185] a third switch coupled between the first capacitor and the third node; and

[0186] a fourth switch coupled between the second capacitor and the second node,

[0187] The first capacitor is coupled between the first local oscillator node and the first and third switches, and the second capacitor is coupled between the second local oscillator node and the fourth and second switches.

[0188] Example aspect 21: According to the apparatus of example aspect 20, the apparatus further comprises:

[0189] Local Oscillator, where:

[0190] The first local oscillator node is coupled between the local oscillator and the first capacitor; and

[0191] The second local oscillator node is coupled between the local oscillator and the second capacitor.

[0192] Example aspect 22: The apparatus of example aspect 20 or 21, wherein:

[0193] The first capacitor is coupled between the first local oscillator node and respective control terminals of the first switch and the third switch; and

[0194] The second capacitor is coupled between the second local oscillator node and respective control terminals of the fourth switch and the second switch.

[0195] Example aspect 23: According to the apparatus of example aspect 22, the apparatus further includes:

[0196] a first resistor and a second resistor, wherein:

[0197] The first resistor is coupled between a first bias node and the respective control terminals of the first switch and the third switch; and

[0198] The second resistor is coupled between a second bias node and the respective control terminals of the fourth switch and the second switch.

[0199] Example aspect 24: The apparatus of example aspect 22 or 23, wherein:

[0200] the first switch and the second switch are coupled to the first node via respective first terminals of a first terminal type;

[0201] and

[0202] The third switch and the fourth switch are coupled to each other via respective first terminals of the first terminal type.

[0203] Example aspect 25: The apparatus of any one of example aspects 22 to 24, wherein:

[0204] the second node is coupled to the fourth switch and the first switch via respective second terminals of a second terminal type;

[0205] and

[0206] The third node is coupled to the second switch and the third switch via respective second terminals of the second terminal type.

[0207] Example aspect 26: The apparatus of example aspect 25, wherein:

[0208] The first terminal type comprises a drain terminal of a transistor; and

[0209] The second terminal type comprises source terminals of transistors.

[0210] Example aspect 27: The apparatus of any one of example aspects 20 to 26, wherein:

[0211] The first switch and the second switch are disposed between the fourth switch and the third switch.

[0212] Example aspect 28: The apparatus according to any one of example aspects 20 to 27, the apparatus further comprising:

[0213] A substrate, wherein:

[0214] The first switch is disposed on the substrate and is located between the fourth switch and the second switch;

[0215] The second switch is disposed on the substrate and is located between the first switch and the third switch; and

[0216] The first switch and the fourth switch are symmetrically positioned on a first side of a symmetry line located in a plane defined by the substrate, and the second switch and the third switch are symmetrically positioned on a second side of the symmetry line.

[0217] Example Aspect 29: A method for mixing a signal, the method comprising:

[0218] receiving a first signal at a first switch and a second switch via a first node, the first signal corresponding to a first frequency;

[0219] receiving a positive local oscillator signal at the first switch and a third switch via a first capacitor;

[0220] receiving a negative local oscillator signal at the second switch and a fourth switch via a second capacitor;

[0221] mixing the first signal, the positive local oscillator signal, and the negative local oscillator signal using the first switch, the second switch, the third switch, and the fourth switch to generate a second signal, the second signal corresponding to a second frequency; and

[0222] The second signals from the first switch, the second switch, the third switch, and the fourth switch are provided via a plurality of second nodes.

[0223] Example aspect 30: According to the method of example aspect 29, the apparatus further comprises:

[0224] The third switch and the fourth switch are operated as dummy switches with respect to the first signal.

[0225] in conclusion

[0226] As used herein, the term "coupling" refers to a relationship between two or more components that are in operable communication with each other to implement a feature described herein or to achieve a capability described herein. For example, coupling can be achieved using physical lines such as metal traces or wires or electromagnetic coupling such as transformers. Coupling can include direct coupling or indirect coupling. Direct coupling refers to connecting discrete circuit elements via the same node without intermediate elements. Indirect coupling refers to connecting discrete circuit elements via one or more other devices or other discrete circuit elements (including two or more different nodes).

[0227] The term "node" (including, for example, a "first node" or a "local oscillator node") at least refers to a point of electrical connection between two or more components (e.g., circuit elements). Although sometimes a node may be visually depicted as a single point in a diagram, the node may represent a connection portion of a physical circuit or network that has approximately the same voltage potential at or along the connection portion between two or more components. In other words, a node may represent at least one of a plurality of points along a conductive medium (e.g., a wire or trace) that exists between electrically connected components. Similarly, a "terminal" may represent one or more points that have at least approximately the same voltage potential relative to an input or output of a component (e.g., a transistor).

[0228] The terms "first", "second", "third" and other numerically related indicators are used herein to identify or distinguish items that are similar or similar to each other in a given context (such as a specific implementation, a single figure, a given component or a claim). Therefore, the first item in one context may be different from the first item in another context. For example, an item identified as a "first node" in one context may be identified as a "second node" in another context. Similarly, a "first capacitor" or a "first switch" in one claim may be described as a "second capacitor" or a "third switch" in different claims (e.g., in a separate set of claims), respectively.

[0229] Unless the context dictates otherwise, the use of the word "or" herein may be considered an "inclusive or" or use of a term that allows inclusion or application of one or more items linked by the word "or" (e.g., the phrase "A or B" may be interpreted as allowing only "A", only "B", or both "A" and "B"). In addition, as used herein, a phrase referring to "at least one of" a list of items refers to any combination of these items (including a single member). For example, "at least one of a, b, or c" may cover a, b, c, ab, ac, bc, and abc, as well as any combination with multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c). In addition, the items represented in the drawings and the terms discussed herein may indicate one or more items or terms, and thus the singular or plural forms of these items and terms may be interchangeably referred to in this written description.

[0230] Although the implementation of frequency mixing has been described in language specific to certain features and / or methods, the subject matter of the appended claims is not necessarily limited to the specific features or methods described. Rather, these specific features and methods are disclosed as example implementations of frequency mixing.

Claims

1. A device, comprising: A mixer circuit, the mixer circuit comprising: multiple local oscillator nodes; a first node, the first node corresponding to a first frequency; a plurality of second nodes, the plurality of second nodes corresponding to a second frequency; a plurality of capacitors coupled between the plurality of local oscillator nodes and the plurality of second nodes; and A plurality of switches, the plurality of switches comprising a first switch, a second switch, a third switch and a fourth switch; the plurality of switches are coupled between the plurality of capacitors and the plurality of second nodes; the first switch and the second switch are coupled between the plurality of capacitors and the first node; and the first switch and the second switch are arranged between the fourth switch and the third switch.

2. The device according to claim 1, wherein: The third switch and the fourth switch are coupled to each other via a floating node.

3. The device according to claim 2, wherein: The first node is configured to provide a first signal corresponding to the first frequency to the mixer circuit; and The plurality of second nodes are configured to receive a second signal corresponding to the second frequency from the mixer circuit.

4. The device according to claim 3, wherein: The first signal comprises an unbalanced signal; and The second signal comprises a balanced signal.

5. The device according to claim 2, wherein: The first switch is disposed on the substrate and is located between the fourth switch and the second switch; and The second switch is disposed on the substrate and located between the first switch and the third switch.

6. The device according to claim 5, wherein: The first switch and the fourth switch are symmetrically positioned on a first side of a symmetry line, and the second switch and the third switch are symmetrically positioned on a second side of the symmetry line.

7. The device according to claim 6, wherein: The substrate defines a plane; the plane includes a first axis and a second axis, the first axis being substantially perpendicular to the second axis, the second axis being at least substantially parallel to the line of symmetry; and The first switch, the second switch, the third switch and the fourth switch are arranged on the substrate along a line at least substantially parallel to the first axis, lying in the plane.

8. The device according to claim 6, wherein: The plurality of capacitors include a first capacitor and a second capacitor; the first capacitor is positioned on the second side of the line of symmetry; and The second capacitor is positioned on the first side of the line of symmetry.

9. The device according to claim 8, wherein: The plurality of local oscillator nodes include a first local oscillator node and a second local oscillator node; The first capacitor is coupled between the first local oscillator node and the first switch and the third switch; and The second capacitor is coupled between the second local oscillator node and the second switch and the fourth switch.

10. The device according to claim 1, wherein: The plurality of local oscillator nodes include a positive local oscillator node and a negative local oscillator node; The plurality of capacitors include a first capacitor and a second capacitor; the first capacitor coupled between the positive local oscillator node and the first switch; the first capacitor coupled between the positive local oscillator node and the third switch; the second capacitor is coupled between the negative local oscillator node and the fourth switch; and The second capacitor is coupled between the negative local oscillator node and the second switch.

11. The device according to claim 10, wherein: The mixer circuit comprises: a plurality of bias nodes, the plurality of bias nodes comprising a first bias node and a second bias node; and a plurality of bias resistors, the plurality of bias resistors comprising a first resistor and a second resistor; The first resistor is coupled between the first bias node and the first switch; The first resistor is coupled between the first bias node and the third switch; The second resistor is coupled between the second bias node and the fourth switch; and The second resistor is coupled between the second bias node and the second switch.

12. The device according to claim 1, further comprising: a local oscillator coupled to the plurality of local oscillator nodes, Wherein the mixer circuit is configured to convert the frequency of a signal between the first frequency and the second frequency.

13. The apparatus according to claim 1, further comprising: at least one transmission chain, the at least one transmission chain comprising the mixer circuit, Wherein the mixer circuit is configured to perform frequency up-conversion.

14. The apparatus according to claim 1, further comprising: at least one receive chain, the at least one receive chain comprising the mixer circuit, Wherein the mixer circuit is configured to perform down conversion.

15. The device according to claim 14, further comprising: a wireless interface device, the wireless interface device comprising the at least one receive chain; Display screen; and and at least one processor operatively coupled to the display screen and at least a portion of the wireless interface device, the at least one processor configured to present one or more graphical images on the display screen based on one or more wireless signals communicated using the mixer circuit of the wireless interface device.

16. A device, comprising: A mixer circuit, the mixer circuit comprising: multiple local oscillator nodes; a first node, the first node corresponding to a first frequency; a plurality of second nodes, the plurality of second nodes corresponding to a second frequency; a plurality of capacitors coupled between the plurality of local oscillator nodes and the plurality of second nodes; a plurality of switches, the plurality of switches comprising a first switch, a second switch, a third switch and a fourth switch; the plurality of switches are coupled between the plurality of capacitors and the plurality of second nodes; the first switch and the second switch are coupled between the plurality of capacitors and the first node; the third switch and the fourth switch are coupled to each other via a floating node; and Components used to increase symmetry-related linearity.

17. The apparatus of claim 16, wherein the means for increasing symmetry-related linearity comprises: Means for symmetrically positioning the first switch and the fourth switch on a first side of a line of symmetry and symmetrically positioning the second switch and the third switch on a second side of the line of symmetry.

18. The apparatus according to claim 16, further comprising: Means for sharing each of the plurality of capacitors across two or more of the plurality of switches.

19. The apparatus according to claim 18, further comprising: a plurality of resistors coupled to the plurality of switches; and Means for sharing each resistor of the plurality of resistors across two or more switches of the plurality of switches.

20. A device, comprising: A mixer circuit, the mixer circuit comprising: a first local oscillator node and a second local oscillator node; a first node, the first node corresponding to a first frequency; a second node and a third node, the second node and the third node each corresponding to a second frequency; a first capacitor and a second capacitor; a first switch, the first switch being coupled between the first capacitor and the second node, the A first switch is further coupled between the first capacitor and the first node; a second switch, the second switch being coupled between the second capacitor and the third node, the A second switch is further coupled between the second capacitor and the first node; a third switch coupled between the first capacitor and the third node; and a fourth switch coupled between the second capacitor and the second node, The first capacitor is coupled between the first local oscillator node and the first and third switches, and the second capacitor is coupled between the second local oscillator node and the fourth and second switches.

21. The apparatus according to claim 20, further comprising: Local Oscillator, where: The first local oscillator node is coupled between the local oscillator and the first capacitor; and The second local oscillator node is coupled between the local oscillator and the second capacitor.

22. The apparatus of claim 20, wherein: The first capacitor is coupled between the first local oscillator node and respective control terminals of the first switch and the third switch; and The second capacitor is coupled between the second local oscillator node and respective control terminals of the fourth switch and the second switch.

23. The apparatus according to claim 22, further comprising: a first resistor and a second resistor, wherein: The first resistor is coupled between a first bias node and the respective control terminals of the first switch and the third switch; and The second resistor is coupled between a second bias node and the respective control terminals of the fourth switch and the second switch.

24. The apparatus of claim 22, wherein: the first switch and the second switch are coupled to the first node via respective first terminals of a first terminal type; and The third switch and the fourth switch are coupled to each other via respective first terminals of the first terminal type.

25. The apparatus of claim 24, wherein: the second node is coupled to the fourth switch and the first switch via respective second terminals of a second terminal type; and The third node is coupled to the second switch and the third switch via respective second terminals of the second terminal type.

26. The apparatus of claim 25, wherein: The first terminal type comprises a drain terminal of a transistor; and The second terminal type comprises source terminals of transistors.

27. The apparatus of claim 20, wherein: The first switch and the second switch are disposed between the fourth switch and the third switch.

28. The apparatus according to claim 20, further comprising: A substrate, wherein: The first switch is disposed on the substrate and is located between the fourth switch and the second switch; The second switch is disposed on the substrate and is located between the first switch and the third switch; and The first switch and the fourth switch are symmetrically positioned on a first side of a symmetry line located in a plane defined by the substrate, and the second switch and the third switch are symmetrically positioned on a second side of the symmetry line.

29. A method for mixing a signal, the method comprising: receiving a first signal at a first switch and a second switch via a first node, the first signal corresponding to a first frequency; receiving a positive local oscillator signal at the first switch and a third switch via a first capacitor; receiving a negative local oscillator signal at the second switch and a fourth switch via a second capacitor; mixing the first signal, the positive local oscillator signal, and the negative local oscillator signal using the first switch, the second switch, the third switch, and the fourth switch to generate a second signal, the second signal corresponding to a second frequency; as well as The second signals from the first switch, the second switch, the third switch, and the fourth switch are provided via a plurality of second nodes.

30. The method according to claim 29, further comprising: The third switch and the fourth switch are operated as dummy switches with respect to the first signal.

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