Preparation method of MEMS device

Abstract

The invention provides a preparation method of an MEMS device, and the method comprises the steps: firstly forming an MEMS cavity in a first wafer, and then determining the actual position of a device region on a second wafer through the comparison of the preset relative offset of a first marking groove in the first wafer and a second marking groove in the second wafer and the actual relative offset. And forming a device region at the actual position of the device region. According to the method provided by the invention, the alignment precision of the MEMS cavity and the device region is greatly improved, so that the problem of low alignment precision of the device region and the MEMS cavity in the prior art is solved, and the product yield and reliability are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device preparation, and in particular to a method for preparing a MEMS device. Background Art

[0002] MEMS (Micro Electro Mechanical System) is a miniature device that can sense the physical world or act as a brake. Its main function is to use micromachining technology to produce micro-sensors, micro-actuators and other micro-mechanical basic parts and micro-electromechanical devices and devices based on silicon materials.

[0003] In the manufacturing process of MEMS devices, it is necessary to make corresponding MEMS cavities and device areas on the upper and lower sides. In the prior art, the device area is usually made in the top device layer on one side of the SOI wafer, and then the MEMS cavity is made on the other side of the SOI wafer opposite to the top device layer.

[0004] However, the alignment accuracy between the MEMS cavity and the device area in the MEMS device manufactured by this method is not high, which will lead to low yield and low reliability of MEMS products.

[0005] Therefore, how to improve the alignment accuracy between the MEMS cavity and the device area has become a technical problem that the industry urgently needs to solve. Summary of the invention

[0006] The present invention aims to provide a method for preparing a MEMS device, so as to solve the problem of low alignment accuracy between a MEMS cavity and a device area during the preparation process of the MEMS device.

[0007] In order to solve the above technical problems, according to a first aspect of the present invention, a method for preparing a MEMS device is provided, comprising:

[0008] Providing a first wafer, and forming a MEMS cavity and a first marking groove on one side of the first wafer;

[0009] Providing a second wafer, and forming a first oxide layer on one side of the second wafer;

[0010] Bonding a surface of the first wafer having the MEMS cavity formed thereon to a surface of the second wafer having the first oxide layer formed thereon, so as to seal the MEMS cavity and the first marking groove;

[0011] Thinning the side of the second wafer facing away from the bonding to a preset thickness;

[0012] forming a second oxide layer on the thinned surface of the second wafer;

[0013] A second marking groove is formed on a side of the second wafer where the second oxide layer is formed; the second marking groove penetrates the second oxide layer, the second wafer and the first oxide layer;

[0014] Obtaining an actual relative offset between the first mark groove and the second mark groove, and determining an actual position of a device area according to the actual relative offset and a preset relative offset; wherein the actual position of the device area is directly opposite to the MEMS cavity;

[0015] According to the actual position of the device area, the device area is manufactured on the second wafer to form a MEMS device.

[0016] Optionally, the first marking groove and the second marking groove are respectively located in cutting paths of the first wafer and the second wafer, the cutting paths are located outside the MEMS device body, and the second marking groove is located above the first marking groove.

[0017] Optionally, forming a MEMS cavity and a first marking groove on one side of the first wafer specifically includes:

[0018] Forming a first patterned mask layer on one side of the first wafer; wherein the first patterned mask layer includes a MEMS cavity pattern and a first marking groove pattern;

[0019] The first wafer is etched using the first patterned mask layer as a mask to form the MEMS cavity and the first marking groove.

[0020] Optionally, forming a second marking groove on a side of the second wafer on which the second oxide layer is formed specifically includes:

[0021] forming a second patterned mask layer on the second oxide layer; wherein the second patterned mask layer includes a second marking groove pattern;

[0022] Using the second patterned mask layer as a mask, etching the second oxide layer, the second wafer, and the first oxide layer, and stopping the etching at the first wafer to form a second marking groove;

[0023] The relative offset between the first mark groove pattern and the second mark groove pattern along the first direction is the preset offset; wherein the first direction is parallel to the channel direction of the MEMS device and points from the source region to the drain region.

[0024] Optionally, obtaining an actual relative offset between the first mark groove and the second mark groove, and determining an actual position of the device region according to the actual relative offset specifically includes:

[0025] Obtaining an actual relative offset between the first marking groove and the second marking groove;

[0026] Calculating a deviation between the actual relative offset and the preset relative offset;

[0027] The position of the preset device area pattern in the device area mask is adjusted according to the deviation value to determine the actual position of the device area.

[0028] Optionally, adjusting the position of a preset device area pattern in the device area mask according to the deviation value specifically includes:

[0029] coating a first photoresist layer on the second oxide layer;

[0030] Providing a first photomask, wherein the preset device region pattern is formed in the first photomask;

[0031] adjusting the exposure position of the first photomask according to the deviation value;

[0032] The first photoresist layer is exposed and developed using the adjusted first mask to form a device area pattern in the first photoresist layer to form a patterned first photoresist layer; wherein the position of the device area pattern is the actual position of the device area, corresponding to the MEMS cavity.

[0033] Optionally, adjusting the exposure position of the first mask according to the deviation value specifically includes:

[0034] If the deviation value is a positive number, the first mask is translated by the deviation value in a direction opposite to the first direction as the exposure position of the first mask;

[0035] If the deviation value is a negative number, the first mask is translated along the first direction by the deviation value as the exposure position of the first mask.

[0036] Optionally, the preset thickness is 5-20 microns.

[0037] Optionally, thinning the side of the second wafer facing away from the bonding to a preset thickness specifically includes:

[0038] Performing dry etching on the second wafer along a side of the second wafer facing away from the bonding so that the thickness of the second wafer reaches the preset thickness;

[0039] Performing chemical mechanical polishing on a side of the second wafer facing away from the bonding;

[0040] Wherein, the first wafer and the second wafer are both bare wafers.

[0041] Optionally, thinning the side of the second wafer facing away from the bonding to a preset thickness specifically includes:

[0042] Wet-etching the second wafer along a side of the second wafer facing away from the bonding so that the thickness of the second wafer reaches the preset thickness;

[0043] Performing chemical mechanical polishing on a side of the second wafer facing away from the bonding;

[0044] Among them, the first wafer is a highly doped bare wafer, and the second wafer is a bare wafer.

[0045] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0046] In a method for preparing a MEMS device provided in an embodiment of the present invention, a MEMS cavity is first formed on a first wafer, and then the actual position of a device area on the second wafer is determined by comparing the preset relative offset between a first mark groove on the first wafer and a second mark groove on the second wafer with the actual relative offset, and the device area is formed at the actual position of the device area. The method provided by the present invention greatly improves the alignment accuracy between the MEMS cavity and the device area, thereby solving the problem of low product yield and low reliability caused by low alignment accuracy between the device area and the MEMS cavity in the prior art.

[0047] Furthermore, by thinning the second wafer to different thicknesses, the sensitivity of the manufactured MEMS device can be different, so that the manufactured MEMS device can meet the film thickness requirements of different sensitivities within the expected range, thereby broadening the application scenarios.

[0048] Furthermore, in the conventional preparation process, a mechanical arm with a suction cup is required to suck the side of the second wafer facing away from the bonding to bond the side with the MEMS cavity formed with the side of the second wafer with the first oxide layer formed, so that the side of the second wafer facing away from the bonding will be scratched and metal contaminated in this process. Therefore, by thinning the side of the second wafer facing away from the bonding, the scratched and contaminated part can be removed, thereby reducing the probability of scratches and particle and metal contamination on the side of the second wafer facing away from the bonding in the finished product.

[0049] Furthermore, in an embodiment of the present invention, both the first wafer and the second wafer are bare wafers. Since bare wafers are thicker than SOI wafers used in the prior art, the risk of fragmentation is reduced to a certain extent during the preparation process.

[0050] Of course, the embodiments of the present invention do not necessarily satisfy all of the above beneficial effects at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 is a flow chart of a method for preparing a MEMS device provided in one embodiment of the present invention;

[0052] Figure 2-Figure 8 It is a schematic diagram of the device structure corresponding to each step of the method for preparing a MEMS device provided by an embodiment of the present invention.

[0053] Reference numerals:

[0054] 1-first wafer;

[0055] 2- second wafer;

[0056] 3- first oxide layer;

[0057] 4-MEMS cavity;

[0058] 5-first marking groove;

[0059] 6- second oxide layer;

[0060] 7- second marking groove;

[0061] 8-device area;

[0062] 9-a first doped region;

[0063] 10- a second doping region;

[0064] 11- Well region. DETAILED DESCRIPTION

[0065] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the embodiments in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present invention. The terms "first", "second", "third", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0066] As described in the background technology, in order to meet the requirements of manufacturing a MEMS cavity and a device area that are aligned vertically, the prior art usually manufactures the device area on the top device layer on one side of the SOI wafer, and then manufactures the MEMS cavity on the other side of the SOI wafer opposite to the top device layer. However, this method will cause the alignment accuracy of the MEMS cavity and the device area to be low.

[0067] In view of this, the present invention creatively proposes a method for preparing a MEMS device, comprising:

[0068] Providing a first wafer, and forming a MEMS cavity and a first marking groove on one side of the first wafer;

[0069] Providing a second wafer, and forming a first oxide layer on one side of the second wafer;

[0070] Bonding a surface of the first wafer having the MEMS cavity formed thereon to a surface of the second wafer having the first oxide layer formed thereon, so as to seal the MEMS cavity and the first marking groove;

[0071] Thinning the side of the second wafer facing away from the bonding to a preset thickness;

[0072] forming a second oxide layer on the thinned surface of the second wafer;

[0073] A second marking groove is formed on a side of the second wafer where the second oxide layer is formed; the second marking groove penetrates the second oxide layer, the second wafer and the first oxide layer;

[0074] Obtaining an actual relative offset between the first mark groove and the second mark groove, and determining an actual position of a device area according to the actual relative offset and a preset relative offset; wherein the actual position of the device area is directly opposite to the MEMS cavity;

[0075] According to the actual position of the device area, the device area is manufactured on the second wafer to form a MEMS device.

[0076] In the method for preparing a MEMS device provided by the technical solution of the present invention, a MEMS cavity is first formed on a first wafer, and then the actual position of a device area on the second wafer is determined by comparing the preset relative offset between a first mark groove on the first wafer and a second mark groove on the second wafer with the actual relative offset, and a device area is formed at the actual position of the device area. The method provided by the present invention greatly improves the alignment accuracy between the MEMS cavity and the device area, thereby solving the problem of low product yield and low reliability caused by low alignment accuracy between the device area and the MEMS cavity in the prior art.

[0077] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, the technical scheme of the present invention is described in detail below with reference to the accompanying drawings.

[0078] in, Figure 1 is a flow chart of a method for preparing a MEMS device provided in one embodiment of the present invention; Figure 2-Figure 8 It is a schematic diagram of the device structure corresponding to each step of the method for preparing a MEMS device provided in one embodiment of the present invention.

[0079] Please refer to Figure 1 Combined with Figure 2-Figure 8 , a method for preparing a MEMS device provided by an embodiment of the present invention comprises:

[0080] S1: providing a first wafer 1, forming a MEMS cavity 4 and a first marking groove 5 on one side of the first wafer 1; Figure 2 shown.

[0081] Specifically, the first marking groove 5 is located at the cutting path of the wafer, that is, outside the MEMS device body. The MEMS devices prepared on the wafer are packaged and cut through the cutting path. Therefore, the production of the first marking groove will not cause damage to the MEMS device, thereby not affecting the performance of the MEMS device.

[0082] As a specific implementation, S1 may specifically include:

[0083] S11: forming a second patterned mask layer on one side of the first wafer; wherein the second patterned mask layer includes a MEMS cavity pattern and a first marking groove pattern;

[0084] S12: using the second patterned mask layer as a mask, etching the first wafer to form the MEMS cavity and the first marking groove.

[0085] Of course, it should be appreciated that the present invention is not limited thereto, and any method that can form the MEMS cavity 4 and the first marking groove 5 in the first wafer 1 is within the protection scope of the present invention, such as a wet etching process.

[0086] As an example, the depth of the first marking groove 5 is the same as that of the MEMS cavity 4, which is 400-500 microns. Of course, the depth of the first marking groove 5 can also be other values, which is not limited in the present invention.

[0087] As a specific implementation, S1 may specifically include:

[0088] S111: spin coating a second photoresist layer on one side of the first wafer 1;

[0089] S112: using a second photomask to expose and develop the second photoresist layer to achieve patterning of the second photoresist layer, thereby forming a patterned second photoresist layer; the patterned second photoresist layer includes a MEMS cavity pattern and a first mark groove pattern;

[0090] S121 : using the patterned second photoresist layer as a mask, etching one side of the first wafer 1 to form a MEMS cavity 4 and a first marking groove 5 in the first wafer 1 .

[0091] Of course, in actual operation, after step S121 is completed, the remaining patterned second photoresist layer is removed.

[0092] In addition, it should be appreciated that the above example uses the material of the second patterned mask layer as photoresist. In actual applications, the second patterned mask layer may also be made of other materials and may also be formed in other ways, and the present invention is not limited thereto.

[0093] S2: providing a second wafer 2, and forming a first oxide layer 3 on one side of the second wafer 2, such as Figure 3 shown.

[0094] As an example, the first oxide layer 3 is silicon oxide, which is formed by thermal oxidation. Of course, it should be appreciated that the first oxide layer 3 can also be formed in other ways, and the present invention is not limited thereto, for example, the first oxide layer 3 is deposited on the other side of the first wafer 1 opposite to the MEMS cavity 4.

[0095] As an example, the thickness of the first oxide layer 3 is less than or equal to 2000 angstroms. Of course, the specific thickness of the first oxide layer 3 can be adjusted according to actual conditions, and it is not a factor that limits the protection scope of the present invention.

[0096] It should be noted that S1 and S2 are two steps for processing the first wafer 1 and the second wafer 2 respectively, that is, S1 and S2 are two steps that do not affect each other. Therefore, the present invention does not limit the order of S1 and S2. For example, S1 and S2 can be performed simultaneously or S2 can be performed first and then S1.

[0097] S3: bonding the surface of the first wafer 1 on which the MEMS cavity 4 is formed to the surface of the second wafer 2 on which the first oxide layer 3 is formed, so as to seal the MEMS cavity 4 and the first marking groove 5; Figure 4 shown.

[0098] The MEMS cavity 4 and the first marking groove 5 are sealed by the first oxide layer 3 on the second wafer 2 , so that the MEMS cavity 4 and the first marking groove 5 are closed.

[0099] In a specific implementation manner, bonding the side of the first wafer 1 forming the MEMS cavity 4 to the side of the second wafer 2 forming the first oxide layer 3 specifically includes:

[0100] S31: using a robot arm with a suction cup to suck the side of the second wafer 2 facing away from the bonding, and placing the second wafer 2 on the side of the first wafer 1 forming the MEMS cavity 4, so that the first oxide layer 3 on the side of the second wafer 2 facing away from the bonding is bonded to the side of the first wafer 1 forming the MEMS cavity 4;

[0101] S32: Using a bonding force application system, a surface of the first wafer 1 forming the MEMS cavity 4 is brought into close contact with a surface of the second wafer 2 facing away from the bonding;

[0102] S33 : With the assistance of a temperature system, the temperatures of the first wafer 1 and the second wafer 2 are adjusted to promote bonding between a side of the first wafer 1 forming the MEMS cavity 4 and a side of the second wafer 2 forming the first oxide layer 3 .

[0103] Of course, the above are all examples, and any method that can bond the side of the first wafer 1 that forms the MEMS cavity 4 to the side of the second wafer 2 that forms the first oxide layer 3 is within the protection scope of the present invention.

[0104] S4: Thinning the side of the second wafer 2 facing away from the bonding to a preset thickness; Figure 5 shown.

[0105] As an example, the preset thickness of the thinned second wafer 2 is 5-20 microns.

[0106] Among them, the thinner the thickness of the top silicon layer of the MEMS device, the faster the response speed of the MEMS device and the higher the sensitivity. Therefore, the second wafer is thinned, and the silicon substrate portion of the thinned second wafer is used as the top silicon layer of the MEMS device, and a device area is formed in this top silicon layer. The thickness of the top silicon can be adjusted by the thinning process of the second wafer to achieve arbitrary customization, so that the MEMS device involved in the present invention can be controlled within the expected range value, meet the film thickness requirements of different sensitivities, and broaden the application scenarios. Of course, the specific thickness of the second wafer 2 after thinning can be adjusted according to actual conditions, and it is not used as a factor to limit the scope of protection of the present invention.

[0107] Furthermore, in the conventional preparation process, a mechanical arm with a suction cup is required to suck the side of the second wafer 2 facing away from the bonding to bond the side with the MEMS cavity 4 to the side of the second wafer 2 with the first oxide layer 3, so that the side of the second wafer 2 facing away from the bonding will be scratched and metal contaminated in this process. Therefore, by thinning the side of the second wafer 2 facing away from the bonding, the scratched and contaminated part can be removed, thereby reducing the probability of scratches and particle and metal contamination on the side of the second wafer 2 facing away from the bonding in the finished product.

[0108] As an implementation manner, thinning the second wafer 2 specifically includes:

[0109] S411: performing dry etching on the second wafer 2 along a side of the second wafer 2 facing away from the bonding;

[0110] S412: performing chemical mechanical polishing on the side of the second wafer 2 facing away from the bonding.

[0111] Preferably, both the first wafer 1 and the second wafer 2 are bare wafers, and the thickness of the bare wafer is generally about 700 microns. Conventional SOI wafers (the thickness of the top silicon is generally 5-20 microns) perform ion implantation and other processes on the top silicon to form a device area, and then etch a MEMS cavity on the back of the SOI wafer. There is a risk of fragmentation during the SOI wafer preparation and transmission processes. Compared with conventional SOI wafers, in this embodiment, the first wafer is first cavity etched and then bonded to the second wafer, and the device area is produced after the second wafer is thinned, which reduces the use and operation of the thin slice and reduces the risk of fragmentation to a certain extent; further, after the thinning of the second wafer is completed, the surface of the second wafer is chemically mechanically polished to achieve flattening and maintain the flatness of the wafer surface.

[0112] As an example, the gas used for dry etching is carbon tetrafluoride, the etching temperature is room temperature, and the pressure of the carbon tetrafluoride is 170-190 mTorr. Of course, the specific dry etching conditions can be adjusted according to actual conditions, and they are not used as factors to limit the scope of protection of the present invention.

[0113] As another implementation manner, thinning the second wafer 2 specifically includes:

[0114] S421: wet-etching the second wafer 2 along a side of the second wafer 2 facing away from the bonding;

[0115] S422: performing chemical mechanical polishing on the side of the second wafer 2 facing away from the bonding.

[0116] The first wafer 1 is a highly doped bare wafer, and the second wafer 2 is a bare wafer. When the second wafer is thinned by wet etching, since the first wafer is a highly doped wafer, the damage to the surface of the first wafer during wet etching can be reduced.

[0117] As an example, the liquid used in the wet etching process is potassium hydroxide, the etching temperature is 60° C. to 100° C., and the etching rate is greater than 1000 nanometers per minute. Of course, the specific wet etching conditions can be adjusted according to actual conditions, and they are not used as factors to limit the scope of protection of the present invention.

[0118] In addition, those skilled in the art should be aware that there are many ways to thin the second wafer 2 and conditions corresponding to the thinning methods, and the present invention is not limited thereto.

[0119] S5: forming a second oxide layer 6 on the thinned surface of the second wafer 2; Figure 6 shown.

[0120] As an example, the second oxide layer 6 is silicon oxide, and is formed by thermal oxidation. Of course, it should be appreciated that the second oxide layer 6 can also be formed by other methods, and the present invention is not limited thereto.

[0121] As an example, the thickness of the second oxide layer 6 is less than or equal to 2000 angstroms. Of course, the specific thickness of the second oxide layer 6 can be adjusted according to actual conditions, and it is not a factor that limits the protection scope of the present invention.

[0122] The second oxide layer 6 serves as a barrier layer for subsequent ion implantation, which can effectively avoid the channel effect during ion implantation, thereby better controlling the depth of ion implantation.

[0123] S6: forming a second marking groove 7 on a side of the second wafer 2 where the second oxide layer 6 is formed; the second marking groove 7 penetrates the second oxide layer 6, the second wafer 2 and the first oxide layer 3; Figure 7 shown.

[0124] Specifically, the second marking groove 7 is located in the cutting path of the second wafer, and corresponds to the first marking groove, is located above the first marking groove, and is connected to the first marking groove. After the second wafer is bonded to the first wafer, the cutting paths of the two correspond to the cutting paths of the main body of the MEMS device chip, that is, the cutting paths are located outside the main body of the MEMS device, and the MEMS devices prepared on the wafer are packaged and cut through the cutting paths. Therefore, the production of the second marking groove will not cause damage to the MEMS device, and thus will not affect the performance of the MEMS device.

[0125] Among them, S6 specifically includes:

[0126] S61: forming a third patterned mask layer on the second oxide layer; wherein the third patterned mask layer includes a second mark groove pattern;

[0127] S62: using the third patterned mask layer as a mask to etch the second oxide layer, the second wafer, and the first oxide layer, and stopping the etching at the first wafer to form a second marking groove.

[0128] In one example, the etching method is dry etching. Of course, it should be appreciated that the present invention is not limited thereto, and any method that can form the second marking groove 7 in the second wafer 2 is within the protection scope of the present invention, such as wet etching process.

[0129] As a specific implementation, S6 may specifically include:

[0130] S611: spin coating a third photoresist layer on the second oxide layer 6;

[0131] S612: using a third photomask to expose and develop the third photoresist layer to achieve patterning of the third photoresist layer to form a patterned third photoresist layer, wherein the patterned third photoresist layer includes a second mark groove pattern;

[0132] S621 : using the patterned third photoresist layer as a mask, etching the second oxide layer 6 , and stopping the etching at a side of the first wafer 1 where the MEMS cavity 4 is formed, to form a second marking groove 7 .

[0133] Of course, in actual operation, after step S621 is completed, the remaining patterned third photoresist layer is removed.

[0134] In addition, it should be appreciated that the above example uses the material of the third patterned mask layer as photoresist. In actual applications, the third patterned mask layer may also be made of other materials and may also be formed in other ways, and the present invention is not limited thereto.

[0135] S7: Obtaining the actual relative offset between the first marking groove 5 and the second marking groove 7, and determining the actual position of the device area 8 according to the actual relative offset and a preset relative offset; wherein the actual position of the device area 8 is directly opposite to the MEMS cavity 4.

[0136] As an example, the preset relative offset is the relative offset of the first marking groove 5 pattern in the first patterned mask layer and the second marking groove pattern in the second patterned mask layer along the first direction. The first direction is parallel to the channel direction of the MEMS device and points from the source region to the drain region; of course, the present invention is not limited to this, and the first direction may also be a direction from the drain region to the source region.

[0137] Among them, S7 specifically includes:

[0138] S71: Obtaining an actual relative offset between the first marking groove 5 and the second marking groove 7;

[0139] S72: Calculating a deviation between the actual relative offset and the preset relative offset;

[0140] S73: adjusting the position of the preset device area pattern in the device area mask according to the deviation value to determine the actual position of the device area 8.

[0141] Among them, S73 further specifically includes:

[0142] S731: Spin-coating a first photoresist layer on the second oxide layer 6;

[0143] S732: providing a first photomask, wherein a pattern of the preset device area is formed in the first photomask;

[0144] S733: adjusting the exposure position of the first mask according to the deviation value;

[0145] S734: Use the adjusted first mask to expose and develop the first photoresist layer, and form a device area pattern in the first photoresist layer to form a patterned first photoresist layer; wherein the position of the device area pattern is the actual position of the device area, corresponding to the MEMS cavity 4.

[0146] Wherein, adjusting the exposure position of the first mask according to the deviation value specifically includes:

[0147] If the deviation value is a positive number, the first mask is translated by the deviation value in a direction opposite to the first direction as the exposure position of the first mask;

[0148] If the deviation value is a negative number, the first mask is translated along the first direction by the deviation value as the exposure position of the first mask.

[0149] It should be noted that the present invention has no specific requirements on the width of the first marking groove 5 and the second marking groove 7 and the depth of the first marking groove 5. As long as the method of determining the position of the device area 8 by comparing the actual relative offset of the first marking groove 5 and the second marking groove 7 with the preset relative offset is used, it is within the protection scope of the present invention.

[0150] S8: According to the determined actual position of the device area 8, the device area 8 is manufactured on the second wafer 2 to form a MEMS device; Figure 8 shown.

[0151] Among them, S8 may specifically include:

[0152] S81: performing a first ion implantation using the patterned first photoresist layer as a mask to form a well region 11 on the second wafer 2;

[0153] S82 : forming a first doping region 9 and a second doping region 10 in the well region 11 to form the MEMS device region 8 .

[0154] The first ions may be P-type ions or N-type ions; the first doping region 9 may include a P-type doping region or an N-type doping region, and the second doping region 10 may include a P-type doping region or an N-type doping region.

[0155] As an example, the first ions are N-type ions, the first doping region 9 is a high-concentration P-type doping region, and the second doping region 10 is a low-concentration P-type doping region.

[0156] In summary, the method for preparing a MEMS device provided by the technical solution of the present invention forms a MEMS cavity on a first wafer first, and then determines the actual position of a device area on a second wafer by comparing a preset relative offset between a first mark groove on the first wafer and a second mark groove on the second wafer with an actual relative offset, and forms a device area at the actual position of the device area. The method provided by the present invention greatly improves the alignment accuracy between the MEMS cavity and the device area, thereby solving the problem of low product yield and low reliability caused by low alignment accuracy between the device area and the MEMS cavity in the prior art.

[0157] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for preparing a MEMS device, characterized in that: include: Providing a first wafer, and forming a MEMS cavity and a first marking groove on one side of the first wafer; Providing a second wafer, and forming a first oxide layer on one side of the second wafer; Bonding a surface of the first wafer on which the MEMS cavity is formed to a surface of the second wafer on which the first oxide layer is formed, so as to seal the MEMS cavity and the first marking groove; Thinning the side of the second wafer facing away from the bonding to a preset thickness; forming a second oxide layer on the thinned surface of the second wafer; A second marking groove is formed on a side of the second wafer where the second oxide layer is formed; the second marking groove penetrates the second oxide layer, the second wafer and the first oxide layer; Obtaining an actual relative offset between the first mark groove and the second mark groove, and determining an actual position of a device area according to the actual relative offset and a preset relative offset; wherein the actual position of the device area is directly opposite to the MEMS cavity; According to the actual position of the device area, the device area is manufactured on the second wafer to form a MEMS device.

2. The method for preparing a MEMS device according to claim 1, characterized in that: The first marking groove and the second marking groove are respectively located in the cutting paths of the first wafer and the second wafer, the cutting paths are located outside the MEMS device body, and the second marking groove is located above the first marking groove.

3. The method for preparing a MEMS device according to claim 2, characterized in that: Forming a MEMS cavity and a first marking groove on one side of the first wafer specifically includes: Forming a first patterned mask layer on one side of the first wafer; wherein the first patterned mask layer includes a MEMS cavity pattern and a first marking groove pattern; The first wafer is etched using the first patterned mask layer as a mask to form the MEMS cavity and the first marking groove.

4. The method for preparing a MEMS device according to claim 3, characterized in that: Forming a second marking groove on a side of the second wafer where the second oxide layer is formed specifically includes: forming a second patterned mask layer on the second oxide layer; wherein the second patterned mask layer includes a second marking groove pattern; Using the second patterned mask layer as a mask, etching the second oxide layer, the second wafer, and the first oxide layer, and stopping the etching at the first wafer to form a second marking groove; The relative offset between the first mark groove pattern and the second mark groove pattern along the first direction is the preset offset; wherein the first direction is parallel to the channel direction of the MEMS device and points from the source region to the drain region.

5. The method for preparing a MEMS device according to claim 4, characterized in that: Obtaining an actual relative offset between the first mark groove and the second mark groove, and determining an actual position of the device area according to the actual relative offset and a preset relative offset, specifically includes: Obtaining an actual relative offset between the first marking groove and the second marking groove; Calculating a deviation between the actual relative offset and the preset relative offset; The position of the preset device area pattern in the device area mask is adjusted according to the deviation value to determine the actual position of the device area.

6. The method for preparing a MEMS device according to claim 5, characterized in that: Adjusting the position of a preset device area pattern in the device area mask according to the deviation value specifically includes: coating a first photoresist layer on the second oxide layer; Providing a first photomask, wherein the preset device area pattern is formed in the first photomask; adjusting the exposure position of the first mask according to the deviation value; The first photoresist layer is exposed and developed using the adjusted first mask to form a device area pattern in the first photoresist layer to form a patterned first photoresist layer; wherein the position of the device area pattern is the actual position of the device area, corresponding to the MEMS cavity.

7. The method for preparing a MEMS device according to claim 6, characterized in that: The step of adjusting the exposure position of the first mask according to the deviation value specifically includes: If the deviation value is a positive number, the first mask is translated by the deviation value in a direction opposite to the first direction as the exposure position of the first mask; If the deviation value is a negative number, the first mask is translated along the first direction by the deviation value as the exposure position of the first mask.

8. The method for preparing a MEMS device according to claim 1, characterized in that: The preset thickness is 5-20 microns.

9. The method for preparing a MEMS device according to claim 8, characterized in that: Thinning the side of the second wafer facing away from the bonding to a preset thickness, specifically comprising: Performing dry etching on the second wafer along a side of the second wafer facing away from the bonding so that the thickness of the second wafer reaches the preset thickness; Performing chemical mechanical polishing on a side of the second wafer facing away from the bonding; Wherein, the first wafer and the second wafer are both bare wafers.

10. The method for preparing a MEMS device according to claim 8, characterized in that: Thinning the side of the second wafer facing away from the bonding to a preset thickness, specifically comprising: Wet-etching the second wafer along a side of the second wafer facing away from the bonding so that the thickness of the second wafer reaches the preset thickness; Performing chemical mechanical polishing on a side of the second wafer facing away from the bonding; Among them, the first wafer is a highly doped bare wafer, and the second wafer is a bare wafer.

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